PGM.cpp revision 6dea6d87ed79bc0994d314fed1c90431091e8820
/* $Id$ */
/** @file
* PGM - Page Manager and Monitor. (Mixing stuff here, not good?)
*/
/*
* Copyright (C) 2006-2007 Sun Microsystems, Inc.
*
* This file is part of VirtualBox Open Source Edition (OSE), as
* available from http://www.virtualbox.org. This file is free software;
* General Public License (GPL) as published by the Free Software
* Foundation, in version 2 as it comes in the "COPYING" file of the
* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
*
* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
* Clara, CA 95054 USA or visit http://www.sun.com if you need
* additional information or have any questions.
*/
/** @page pg_pgm PGM - The Page Manager and Monitor
*
* @see grp_pgm,
* @ref pg_pgm_pool,
* @ref pg_pgm_phys.
*
*
* @section sec_pgm_modes Paging Modes
*
* There are three memory contexts: Host Context (HC), Guest Context (GC)
* and intermediate context. When talking about paging HC can also be refered to
* as "host paging", and GC refered to as "shadow paging".
*
* We define three basic paging modes: 32-bit, PAE and AMD64. The host paging mode
* is defined by the host operating system. The mode used in the shadow paging mode
* depends on the host paging mode and what the mode the guest is currently in. The
* following relation between the two is defined:
*
* @verbatim
Host > 32-bit | PAE | AMD64 |
Guest | | | |
==v================================
32-bit 32-bit PAE PAE
-------|--------|--------|--------|
PAE PAE PAE PAE
-------|--------|--------|--------|
AMD64 AMD64 AMD64 AMD64
-------|--------|--------|--------| @endverbatim
*
* All configuration except those in the diagonal (upper left) are expected to
* require special effort from the switcher (i.e. a bit slower).
*
*
*
*
* @section sec_pgm_shw The Shadow Memory Context
*
*
* [..]
*
* Because of guest context mappings requires PDPT and PML4 entries to allow
* writing on AMD64, the two upper levels will have fixed flags whatever the
* guest is thinking of using there. So, when shadowing the PD level we will
* calculate the effective flags of PD and all the higher levels. In legacy
* PAE mode this only applies to the PWT and PCD bits (the rest are
*
*
*
* @section sec_pgm_int The Intermediate Memory Context
*
* The world switch goes thru an intermediate memory context which purpose it is
* to provide different mappings of the switcher code. All guest mappings are also
* present in this context.
*
* The switcher code is mapped at the same location as on the host, at an
* identity mapped location (physical equals virtual address), and at the
* hypervisor location. The identity mapped location is for when the world
* switches that involves disabling paging.
*
* PGM maintain page tables for 32-bit, PAE and AMD64 paging modes. This
* simplifies switching guest CPU mode and consistency at the cost of more
* code to do the work. All memory use for those page tables is located below
* 4GB (this includes page tables for guest context mappings).
*
*
* @subsection subsec_pgm_int_gc Guest Context Mappings
*
* During assignment and relocation of a guest context mapping the intermediate
* memory context is used to verify the new location.
*
* Guest context mappings are currently restricted to below 4GB, for reasons
* of simplicity. This may change when we implement AMD64 support.
*
*
*
*
* @section sec_pgm_misc Misc
*
* @subsection subsec_pgm_misc_diff Differences Between Legacy PAE and Long Mode PAE
*
* The differences between legacy PAE and long mode PAE are:
* -# PDPE bits 1, 2, 5 and 6 are defined differently. In leagcy mode they are
* all marked down as must-be-zero, while in long mode 1, 2 and 5 have the
* usual meanings while 6 is ignored (AMD). This means that upon switching to
* legacy PAE mode we'll have to clear these bits and when going to long mode
* they must be set. This applies to both intermediate and shadow contexts,
* however we don't need to do it for the intermediate one since we're
* executing with CR0.WP at that time.
* -# CR3 allows a 32-byte aligned address in legacy mode, while in long mode
* a page aligned one is required.
*
*
* @section sec_pgm_handlers Access Handlers
*
* Placeholder.
*
*
* @subsection sec_pgm_handlers_virt Virtual Access Handlers
*
* Placeholder.
*
*
* @subsection sec_pgm_handlers_virt Virtual Access Handlers
*
* We currently implement three types of virtual access handlers: ALL, WRITE
* and HYPERVISOR (WRITE). See PGMVIRTHANDLERTYPE for some more details.
*
* The HYPERVISOR access handlers is kept in a separate tree since it doesn't apply
* to physical pages (PGMTREES::HyperVirtHandlers) and only needs to be consulted in
* a special \#PF case. The ALL and WRITE are in the PGMTREES::VirtHandlers tree, the
* rest of this section is going to be about these handlers.
*
* We'll go thru the life cycle of a handler and try make sense of it all, don't know
* how successfull this is gonna be...
*
* 1. A handler is registered thru the PGMR3HandlerVirtualRegister and
* PGMHandlerVirtualRegisterEx APIs. We check for conflicting virtual handlers
* and create a new node that is inserted into the AVL tree (range key). Then
* a full PGM resync is flagged (clear pool, sync cr3, update virtual bit of PGMPAGE).
*
* 2. The following PGMSyncCR3/SyncCR3 operation will first make invoke HandlerVirtualUpdate.
*
* 2a. HandlerVirtualUpdate will will lookup all the pages covered by virtual handlers
* via the current guest CR3 and update the physical page -> virtual handler
* translation. Needless to say, this doesn't exactly scale very well. If any changes
* are detected, it will flag a virtual bit update just like we did on registration.
* PGMPHYS pages with changes will have their virtual handler state reset to NONE.
*
* 2b. The virtual bit update process will iterate all the pages covered by all the
* virtual handlers and update the PGMPAGE virtual handler state to the max of all
* virtual handlers on that page.
*
* 2c. Back in SyncCR3 we will now flush the entire shadow page cache to make sure
* we don't miss any alias mappings of the monitored pages.
*
* 2d. SyncCR3 will then proceed with syncing the CR3 table.
*
* 3. \#PF(np,read) on a page in the range. This will cause it to be synced
* read-only and resumed if it's a WRITE handler. If it's an ALL handler we
* will call the handlers like in the next step. If the physical mapping has
* changed we will - some time in the future - perform a handler callback
* (optional) and update the physical -> virtual handler cache.
*
* 4. \#PF(,write) on a page in the range. This will cause the handler to
* be invoked.
*
* 5. The guest invalidates the page and changes the physical backing or
* unmaps it. This should cause the invalidation callback to be invoked
* (it might not yet be 100% perfect). Exactly what happens next... is
* this where we mess up and end up out of sync for a while?
*
* 6. The handler is deregistered by the client via PGMHandlerVirtualDeregister.
* We will then set all PGMPAGEs in the physical -> virtual handler cache for
* this handler to NONE and trigger a full PGM resync (basically the same
* as int step 1). Which means 2 is executed again.
*
*
* @subsubsection sub_sec_pgm_handler_virt_todo TODOs
*
* There is a bunch of things that needs to be done to make the virtual handlers
* work 100% correctly and work more efficiently.
*
* The first bit hasn't been implemented yet because it's going to slow the
* whole mess down even more, and besides it seems to be working reliably for
* our current uses. OTOH, some of the optimizations might end up more or less
* implementing the missing bits, so we'll see.
*
* On the optimization side, the first thing to do is to try avoid unnecessary
* cache flushing. Then try team up with the shadowing code to track changes
* in mappings by means of access to them (shadow in), updates to shadows pages,
* invlpg, and shadow PT discarding (perhaps).
*
* Some idea that have popped up for optimization for current and new features:
* - bitmap indicating where there are virtual handlers installed.
* (4KB => 2**20 pages, page 2**12 => covers 32-bit address space 1:1!)
* - Shadow page table entry bit (if any left)?
*
*/
/** @page pg_pgm_phys PGM Physical Guest Memory Management
*
*
* Objectives:
* - Guest RAM over-commitment using memory ballooning,
* zero pages and general page sharing.
* - Moving or mirroring a VM onto a different physical machine.
*
*
* @subsection subsec_pgmPhys_Definitions Definitions
*
* Allocation chunk - A RTR0MemObjAllocPhysNC object and the tracking
* machinery assoicated with it.
*
*
*
*
* @subsection subsec_pgmPhys_AllocPage Allocating a page.
*
* Initially we map *all* guest memory to the (per VM) zero page, which
* means that none of the read functions will cause pages to be allocated.
*
* Exception, access bit in page tables that have been shared. This must
* be handled, but we must also make sure PGMGst*Modify doesn't make
* unnecessary modifications.
*
* Allocation points:
* - PGMPhysSimpleWriteGCPhys and PGMPhysWrite.
* - Replacing a zero page mapping at \#PF.
* - Replacing a shared page mapping at \#PF.
* - ROM registration (currently MMR3RomRegister).
* - VM restore (pgmR3Load).
*
* For the first three it would make sense to keep a few pages handy
* until we've reached the max memory commitment for the VM.
*
* For the ROM registration, we know exactly how many pages we need
* and will request these from ring-0. For restore, we will save
* the number of non-zero pages in the saved state and allocate
* them up front. This would allow the ring-0 component to refuse
* the request if the isn't sufficient memory available for VM use.
*
* Btw. for both ROM and restore allocations we won't be requiring
* zeroed pages as they are going to be filled instantly.
*
*
* @subsection subsec_pgmPhys_FreePage Freeing a page
*
* There are a few points where a page can be freed:
* - After being replaced by the zero page.
* - After being replaced by a shared page.
* - After being ballooned by the guest additions.
* - At reset.
* - At restore.
*
* When freeing one or more pages they will be returned to the ring-0
* component and replaced by the zero page.
*
* The reasoning for clearing out all the pages on reset is that it will
* return us to the exact same state as on power on, and may thereby help
* us reduce the memory load on the system. Further it might have a
* (temporary) positive influence on memory fragmentation (@see subsec_pgmPhys_Fragmentation).
*
* On restore, as mention under the allocation topic, pages should be
* freed / allocated depending on how many is actually required by the
* new VM state. The simplest approach is to do like on reset, and free
* all non-ROM pages and then allocate what we need.
*
* A measure to prevent some fragmentation, would be to let each allocation
* chunk have some affinity towards the VM having allocated the most pages
* from it. Also, try make sure to allocate from allocation chunks that
* are almost full. Admittedly, both these measures might work counter to
* our intentions and its probably not worth putting a lot of effort,
* cpu time or memory into this.
*
*
* @subsection subsec_pgmPhys_SharePage Sharing a page
*
* The basic idea is that there there will be a idle priority kernel
* thread walking the non-shared VM pages hashing them and looking for
* pages with the same checksum. If such pages are found, it will compare
* them byte-by-byte to see if they actually are identical. If found to be
* identical it will allocate a shared page, copy the content, check that
* the page didn't change while doing this, and finally request both the
* VMs to use the shared page instead. If the page is all zeros (special
* checksum and byte-by-byte check) it will request the VM that owns it
* to replace it with the zero page.
*
* To make this efficient, we will have to make sure not to try share a page
* that will change its contents soon. This part requires the most work.
* A simple idea would be to request the VM to write monitor the page for
* a while to make sure it isn't modified any time soon. Also, it may
* make sense to skip pages that are being write monitored since this
* information is readily available to the thread if it works on the
* per-VM guest memory structures (presently called PGMRAMRANGE).
*
*
* @subsection subsec_pgmPhys_Fragmentation Fragmentation Concerns and Counter Measures
*
* The pages are organized in allocation chunks in ring-0, this is a necessity
* if we wish to have an OS agnostic approach to this whole thing. (On Linux we
* could easily work on a page-by-page basis if we liked. Whether this is possible
* or efficient on NT I don't quite know.) Fragmentation within these chunks may
* become a problem as part of the idea here is that we wish to return memory to
* the host system.
*
* For instance, starting two VMs at the same time, they will both allocate the
* guest memory on-demand and if permitted their page allocations will be
* intermixed. Shut down one of the two VMs and it will be difficult to return
* any memory to the host system because the page allocation for the two VMs are
* mixed up in the same allocation chunks.
*
* To further complicate matters, when pages are freed because they have been
* to be reused by another VM or returned to the host system. This will cause
* allocation chunks to contain pages belonging to different VMs and prevent
* returning memory to the host when one of those VM shuts down.
*
* The only way to really deal with this problem is to move pages. This can
* either be done at VM shutdown and or by the idle priority worker thread
* involved for coercing a VM to move a page (or to do it for it) will be
*
*
* @subsection subsec_pgmPhys_Tracking Tracking Structures And Their Cost
*
* There's a difficult balance between keeping the per-page tracking structures
* (global and guest page) easy to use and keeping them from eating too much
* memory. We have limited virtual memory resources available when operating in
* 32-bit kernel space (on 64-bit there'll it's quite a different story). The
* tracking structures will be attemted designed such that we can deal with up
* to 32GB of memory on a 32-bit system and essentially unlimited on 64-bit ones.
*
*
* @subsubsection subsubsec_pgmPhys_Tracking_Kernel Kernel Space
*
* @see pg_GMM
*
* @subsubsection subsubsec_pgmPhys_Tracking_PerVM Per-VM
*
* Fixed info is the physical address of the page (HCPhys) and the page id
* (described above). Theoretically we'll need 48(-12) bits for the HCPhys part.
* Today we've restricting ourselves to 40(-12) bits because this is the current
* restrictions of all AMD64 implementations (I think Barcelona will up this
* to 48(-12) bits, not that it really matters) and I needed the bits for
* tracking mappings of a page. 48-12 = 36. That leaves 28 bits, which means a
* decent range for the page id: 2^(28+12) = 1024TB.
*
* In additions to these, we'll have to keep maintaining the page flags as we
* currently do. Although it wouldn't harm to optimize these quite a bit, like
* for instance the ROM shouldn't depend on having a write handler installed
* that the page syncing code doesn't have to mess about checking multiple
* flag combinations (ROM || RW handler || write monitored) in order to
* figure out how to setup a shadow PTE. But this of course, is second
* priority at present. Current this requires 12 bits, but could probably
* be optimized to ~8.
*
* Then there's the 24 bits used to track which shadow page tables are
* currently mapping a page for the purpose of speeding up physical
* access handlers, and thereby the page pool cache. More bit for this
* purpose wouldn't hurt IIRC.
*
* Then there is a new bit in which we need to record what kind of page
* this is, shared, zero, normal or write-monitored-normal. This'll
* require 2 bits. One bit might be needed for indicating whether a
* write monitored page has been written to. And yet another one or
* two for tracking migration status. 3-4 bits total then.
*
* Whatever is left will can be used to record the sharabilitiy of a
* page. The page checksum will not be stored in the per-VM table as
* the idle thread will not be permitted to do modifications to it.
* It will instead have to keep its own working set of potentially
* shareable pages and their check sums and stuff.
*
* For the present we'll keep the current packing of the
* PGMRAMRANGE::aHCPhys to keep the changes simple, only of course,
* we'll have to change it to a struct with a total of 128-bits at
* our disposal.
*
* The initial layout will be like this:
* @verbatim
RTHCPHYS HCPhys; The current stuff.
63:40 Current shadow PT tracking stuff.
39:12 The physical page frame number.
11:0 The current flags.
uint32_t u28PageId : 28; The page id.
uint32_t u2State : 2; The page state { zero, shared, normal, write monitored }.
uint32_t fWrittenTo : 1; Whether a write monitored page was written to.
uint32_t u1Reserved : 1; Reserved for later.
uint32_t u32Reserved; Reserved for later, mostly sharing stats.
@endverbatim
*
* The final layout will be something like this:
* @verbatim
RTHCPHYS HCPhys; The current stuff.
63:48 High page id (12+).
47:12 The physical page frame number.
11:0 Low page id.
uint32_t fReadOnly : 1; Whether it's readonly page (rom or monitored in some way).
uint32_t u3Type : 3; The page type {RESERVED, MMIO, MMIO2, ROM, shadowed ROM, RAM}.
uint32_t u2PhysMon : 2; Physical access handler type {none, read, write, all}.
uint32_t u2VirtMon : 2; Virtual access handler type {none, read, write, all}..
uint32_t u2State : 2; The page state { zero, shared, normal, write monitored }.
uint32_t fWrittenTo : 1; Whether a write monitored page was written to.
uint32_t u20Reserved : 20; Reserved for later, mostly sharing stats.
uint32_t u32Tracking; The shadow PT tracking stuff, roughly.
@endverbatim
*
* Cost wise, this means we'll double the cost for guest memory. There isn't anyway
* around that I'm afraid. It means that the cost of dealing out 32GB of memory
* to one or more VMs is: (32GB >> PAGE_SHIFT) * 16 bytes, or 128MBs. Or another
* example, the VM heap cost when assigning 1GB to a VM will be: 4MB.
*
* A couple of cost examples for the total cost per-VM + kernel.
* 32-bit Windows and 32-bit linux:
* 1GB guest ram, 256K pages: 4MB + 2MB(+) = 6MB
* 4GB guest ram, 1M pages: 16MB + 8MB(+) = 24MB
* 32GB guest ram, 8M pages: 128MB + 64MB(+) = 192MB
* 64-bit Windows and 64-bit linux:
* 1GB guest ram, 256K pages: 4MB + 3MB(+) = 7MB
* 4GB guest ram, 1M pages: 16MB + 12MB(+) = 28MB
* 32GB guest ram, 8M pages: 128MB + 96MB(+) = 224MB
*
* UPDATE - 2007-09-27:
* trust the guest 100% and reporting the same page as ballooned more
* than once will put the GMM off balance.
*
*
* @subsection subsec_pgmPhys_Serializing Serializing Access
*
* Initially, we'll try a simple scheme:
*
* - The per-VM RAM tracking structures (PGMRAMRANGE) is only modified
* by the EMT thread of that VM while in the pgm critsect.
* - Other threads in the VM process that needs to make reliable use of
* the per-VM RAM tracking structures will enter the critsect.
* - No process external thread or kernel thread will ever try enter
* the pgm critical section, as that just won't work.
* - The idle thread (and similar threads) doesn't not need 100% reliable
* data when performing it tasks as the EMT thread will be the one to
* do the actual changes later anyway. So, as long as it only accesses
* the main ram range, it can do so by somehow preventing the VM from
* being destroyed while it works on it...
*
* - The over-commitment management, including the allocating/freeing
* chunks, is serialized by a ring-0 mutex lock (a fast one since the
* more mundane mutex implementation is broken on Linux).
* - A separeate mutex is protecting the set of allocation chunks so
* allocating more chunks. This mutex can be take from under the other
* one, but not the otherway around.
*
*
* @subsection subsec_pgmPhys_Request VM Request interface
*
* When in ring-0 it will become necessary to send requests to a VM so it can
* for instance move a page while defragmenting during VM destroy. The idle
* thread will make use of this interface to request VMs to setup shared
* pages and to perform write monitoring of pages.
*
* I would propose an interface similar to the current VMReq interface, similar
* in that it doesn't require locking and that the one sending the request may
* wait for completion if it wishes to. This shouldn't be very difficult to
* realize.
*
* The requests themselves are also pretty simple. They are basically:
* -# Check that some precondition is still true.
* -# Do the update.
* -# Update all shadow page tables involved with the page.
*
* The 3rd step is identical to what we're already doing when updating a
* physical handler, see pgmHandlerPhysicalSetRamFlagsAndFlushShadowPTs.
*
*
*
* @section sec_pgmPhys_MappingCaches Mapping Caches
*
* In order to be able to map in and out memory and to be able to support
* guest with more RAM than we've got virtual address space, we'll employing
* a mapping cache. There is already a tiny one for GC (see PGMGCDynMapGCPageEx)
* and we'll create a similar one for ring-0 unless we decide to setup a dedicate
* memory context for the HWACCM execution.
*
*
* @subsection subsec_pgmPhys_MappingCaches_R3 Ring-3
*
* We've considered implementing the ring-3 mapping cache page based but found
* that this was bother some when one had to take into account TLBs+SMP and
* portability (missing the necessary APIs on several platforms). There were
* also some performance concerns with this approach which hadn't quite been
* worked out.
*
* Instead, we'll be mapping allocation chunks into the VM process. This simplifies
* matters greatly quite a bit since we don't need to invent any new ring-0 stuff,
* only some minor RTR0MEMOBJ mapping stuff. The main concern here is that mapping
* compared to the previous idea is that mapping or unmapping a 1MB chunk is more
* costly than a single page, although how much more costly is uncertain. We'll
* try address this by using a very big cache, preferably bigger than the actual
* VM RAM size if possible. The current VM RAM sizes should give some idea for
* 32-bit boxes, while on 64-bit we can probably get away with employing an
* unlimited cache.
*
* The cache have to parts, as already indicated, the ring-3 side and the
* ring-0 side.
*
* The ring-0 will be tied to the page allocator since it will operate on the
* memory objects it contains. It will therefore require the first ring-0 mutex
* discussed in @ref subsec_pgmPhys_Serializing. We
* some double house keeping wrt to who has mapped what I think, since both
* VMMR0.r0 and RTR0MemObj will keep track of mapping relataions
*
* The ring-3 part will be protected by the pgm critsect. For simplicity, we'll
* require anyone that desires to do changes to the mapping cache to do that
* from within this critsect. Alternatively, we could employ a separate critsect
* for serializing changes to the mapping cache as this would reduce potential
* contention with other threads accessing mappings unrelated to the changes
* that are in process. We can see about this later, contention will show
* up in the statistics anyway, so it'll be simple to tell.
*
* The organization of the ring-3 part will be very much like how the allocation
* chunks are organized in ring-0, that is in an AVL tree by chunk id. To avoid
* having to walk the tree all the time, we'll have a couple of lookaside entries
* like in we do for I/O ports and MMIO in IOM.
*
* The simplified flow of a PGMPhysRead/Write function:
* -# Enter the PGM critsect.
* -# Lookup GCPhys in the ram ranges and get the Page ID.
* -# Calc the Allocation Chunk ID from the Page ID.
* -# Check the lookaside entries and then the AVL tree for the Chunk ID.
* If not found in cache:
* -# Call ring-0 and request it to be mapped and supply
* a chunk to be unmapped if the cache is maxed out already.
* -# Insert the new mapping into the AVL tree (id + R3 address).
* -# Update the relevant lookaside entry and return the mapping address.
* -# Leave the critsect.
*
*
* @section sec_pgmPhys_Fallback Fallback
*
* Current all the "second tier" hosts will not support the RTR0MemObjAllocPhysNC
* API and thus require a fallback.
*
* So, when RTR0MemObjAllocPhysNC returns VERR_NOT_SUPPORTED the page allocator
* will return to the ring-3 caller (and later ring-0) and asking it to seed
* the page allocator with some fresh pages (VERR_GMM_SEED_ME). Ring-3 will
* then perform an SUPR3PageAlloc(cbChunk >> PAGE_SHIFT) call and make a
* "SeededAllocPages" call to ring-0.
*
* The first time ring-0 sees the VERR_NOT_SUPPORTED failure it will disable
* all page sharing (zero page detection will continue). It will also force
* all allocations to come from the VM which seeded the page. Both these
* measures are taken to make sure that there will never be any need for
* mapping anything into ring-3 - everything will be mapped already.
*
* Whether we'll continue to use the current MM locked memory management
* for this I don't quite know (I'd prefer not to and just ditch that all
* togther), we'll see what's simplest to do.
*
*
*
* @section sec_pgmPhys_Changes Changes
*
* Breakdown of the changes involved?
*/
/*******************************************************************************
* Header Files *
*******************************************************************************/
#define LOG_GROUP LOG_GROUP_PGM
#include "PGMInternal.h"
/*******************************************************************************
* Defined Constants And Macros *
*******************************************************************************/
/** Saved state data unit version for 2.5.x and later. */
#define PGM_SAVED_STATE_VERSION 9
/** Saved state data unit version for 2.2.2 and later. */
#define PGM_SAVED_STATE_VERSION_2_2_2 8
/** Saved state data unit version for 2.2.0. */
#define PGM_SAVED_STATE_VERSION_RR_DESC 7
/** Saved state data unit version. */
#define PGM_SAVED_STATE_VERSION_OLD_PHYS_CODE 6
/*******************************************************************************
* Internal Functions *
*******************************************************************************/
#ifdef VBOX_STRICT
static DECLCALLBACK(void) pgmR3ResetNoMorePhysWritesFlag(PVM pVM, VMSTATE enmState, VMSTATE enmOldState, void *pvUser);
#endif
static PGMMODE pgmR3CalcShadowMode(PVM pVM, PGMMODE enmGuestMode, SUPPAGINGMODE enmHostMode, PGMMODE enmShadowMode, VMMSWITCHER *penmSwitcher);
#ifdef VBOX_WITH_DEBUGGER
/** @todo Convert the first two commands to 'info' items. */
static DECLCALLBACK(int) pgmR3CmdRam(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult);
static DECLCALLBACK(int) pgmR3CmdMap(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult);
static DECLCALLBACK(int) pgmR3CmdError(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult);
static DECLCALLBACK(int) pgmR3CmdSync(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult);
static DECLCALLBACK(int) pgmR3CmdSyncAlways(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult);
# ifdef VBOX_STRICT
static DECLCALLBACK(int) pgmR3CmdAssertCR3(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult);
# endif
static DECLCALLBACK(int) pgmR3CmdPhysToFile(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult);
#endif
/*******************************************************************************
* Global Variables *
*******************************************************************************/
#ifdef VBOX_WITH_DEBUGGER
/** Argument descriptors for '.pgmerror' and '.pgmerroroff'. */
static const DBGCVARDESC g_aPgmErrorArgs[] =
{
/* cTimesMin, cTimesMax, enmCategory, fFlags, pszName, pszDescription */
};
static const DBGCVARDESC g_aPgmPhysToFileArgs[] =
{
/* cTimesMin, cTimesMax, enmCategory, fFlags, pszName, pszDescription */
};
/** Command descriptors. */
{
/* pszCmd, cArgsMin, cArgsMax, paArgDesc, cArgDescs, pResultDesc, fFlags, pfnHandler pszSyntax, ....pszDescription */
{ "pgmerror", 0, 1, &g_aPgmErrorArgs[0], 1, NULL, 0, pgmR3CmdError, "", "Enables inject runtime of errors into parts of PGM." },
{ "pgmerroroff", 0, 1, &g_aPgmErrorArgs[0], 1, NULL, 0, pgmR3CmdError, "", "Disables inject runtime errors into parts of PGM." },
#ifdef VBOX_STRICT
#endif
{ "pgmsyncalways", 0, 0, NULL, 0, NULL, 0, pgmR3CmdSyncAlways, "", "Toggle permanent CR3 syncing." },
{ "pgmphystofile", 1, 2, &g_aPgmPhysToFileArgs[0], 2, NULL, 0, pgmR3CmdPhysToFile, "", "Save the physical memory to file." },
};
#endif
/*
* Shadow - 32-bit mode
*/
#define PGM_SHW_TYPE PGM_TYPE_32BIT
#include "PGMShw.h"
/* Guest - real mode */
#define PGM_GST_TYPE PGM_TYPE_REAL
#include "PGMBth.h"
#include "PGMGstDefs.h"
#include "PGMGst.h"
/* Guest - protected mode */
#define PGM_GST_TYPE PGM_TYPE_PROT
#include "PGMBth.h"
#include "PGMGstDefs.h"
#include "PGMGst.h"
/* Guest - 32-bit mode */
#define PGM_GST_TYPE PGM_TYPE_32BIT
#include "PGMBth.h"
#include "PGMGstDefs.h"
#include "PGMGst.h"
/*
* Shadow - PAE mode
*/
#define PGM_SHW_TYPE PGM_TYPE_PAE
#include "PGMShw.h"
/* Guest - real mode */
#define PGM_GST_TYPE PGM_TYPE_REAL
#include "PGMGstDefs.h"
#include "PGMBth.h"
/* Guest - protected mode */
#define PGM_GST_TYPE PGM_TYPE_PROT
#include "PGMGstDefs.h"
#include "PGMBth.h"
/* Guest - 32-bit mode */
#define PGM_GST_TYPE PGM_TYPE_32BIT
#include "PGMGstDefs.h"
#include "PGMBth.h"
/* Guest - PAE mode */
#define PGM_GST_TYPE PGM_TYPE_PAE
#include "PGMBth.h"
#include "PGMGstDefs.h"
#include "PGMGst.h"
/*
* Shadow - AMD64 mode
*/
#define PGM_SHW_TYPE PGM_TYPE_AMD64
#include "PGMShw.h"
#ifdef VBOX_WITH_64_BITS_GUESTS
/* Guest - AMD64 mode */
# define PGM_GST_TYPE PGM_TYPE_AMD64
# include "PGMBth.h"
# include "PGMGstDefs.h"
# include "PGMGst.h"
#endif /* VBOX_WITH_64_BITS_GUESTS */
/*
* Shadow - Nested paging mode
*/
#define PGM_SHW_TYPE PGM_TYPE_NESTED
#include "PGMShw.h"
/* Guest - real mode */
#define PGM_GST_TYPE PGM_TYPE_REAL
#include "PGMGstDefs.h"
#include "PGMBth.h"
/* Guest - protected mode */
#define PGM_GST_TYPE PGM_TYPE_PROT
#include "PGMGstDefs.h"
#include "PGMBth.h"
/* Guest - 32-bit mode */
#define PGM_GST_TYPE PGM_TYPE_32BIT
#include "PGMGstDefs.h"
#include "PGMBth.h"
/* Guest - PAE mode */
#define PGM_GST_TYPE PGM_TYPE_PAE
#include "PGMGstDefs.h"
#include "PGMBth.h"
#ifdef VBOX_WITH_64_BITS_GUESTS
/* Guest - AMD64 mode */
# define PGM_GST_TYPE PGM_TYPE_AMD64
# include "PGMGstDefs.h"
# include "PGMBth.h"
#endif /* VBOX_WITH_64_BITS_GUESTS */
/*
* Shadow - EPT
*/
#define PGM_SHW_TYPE PGM_TYPE_EPT
#include "PGMShw.h"
/* Guest - real mode */
#define PGM_GST_TYPE PGM_TYPE_REAL
#include "PGMGstDefs.h"
#include "PGMBth.h"
/* Guest - protected mode */
#define PGM_GST_TYPE PGM_TYPE_PROT
#include "PGMGstDefs.h"
#include "PGMBth.h"
/* Guest - 32-bit mode */
#define PGM_GST_TYPE PGM_TYPE_32BIT
#include "PGMGstDefs.h"
#include "PGMBth.h"
/* Guest - PAE mode */
#define PGM_GST_TYPE PGM_TYPE_PAE
#include "PGMGstDefs.h"
#include "PGMBth.h"
#ifdef VBOX_WITH_64_BITS_GUESTS
/* Guest - AMD64 mode */
# define PGM_GST_TYPE PGM_TYPE_AMD64
# include "PGMGstDefs.h"
# include "PGMBth.h"
#endif /* VBOX_WITH_64_BITS_GUESTS */
/**
* Initiates the paging of VM.
*
* @returns VBox status code.
* @param pVM Pointer to VM structure.
*/
{
LogFlow(("PGMR3Init:\n"));
int rc;
/*
* Assert alignment and sizes.
*/
/*
* Init the structure.
*/
/* Init the per-CPU part. */
{
#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
#endif
{
#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
#endif
}
pPGM->fA20Enabled = true;
}
true
#else
false
#endif
);
#else
rc = CFGMR3QueryU32Def(pCfgPGM, "MaxRing3Chunks", &pVM->pgm.s.ChunkR3Map.cMax, _1G / GMM_CHUNK_SIZE);
#endif
/*
* Get the configured RAM size - to estimate saved state size.
*/
if (rc == VERR_CFGM_VALUE_NOT_FOUND)
cbRam = 0;
else if (RT_SUCCESS(rc))
{
cbRam = 0;
}
else
{
return rc;
}
/*
* Register callbacks, string formatters and the saved state data unit.
*/
#ifdef VBOX_STRICT
#endif
if (RT_FAILURE(rc))
return rc;
/*
* Initialize the PGM critical section and flush the phys TLBs
*/
/*
* For the time being we sport a full set of handy pages in addition to the base
* memory to simplify things.
*/
rc = MMR3ReserveHandyPages(pVM, RT_ELEMENTS(pVM->pgm.s.aHandyPages)); /** @todo this should be changed to PGM_HANDY_PAGES_MIN but this needs proper testing... */
/*
* Trees
*/
if (RT_SUCCESS(rc))
{
/*
* Alocate the zero page.
*/
}
if (RT_SUCCESS(rc))
{
/*
* Init the paging.
*/
}
if (RT_SUCCESS(rc))
{
/*
* Init the page pool.
*/
}
if (RT_SUCCESS(rc))
{
{
if (RT_FAILURE(rc))
break;
}
}
if (RT_SUCCESS(rc))
{
/*
* Info & statistics
*/
"Shows the current paging mode. "
"Recognizes 'all', 'guest', 'shadow' and 'host' as arguments, defaulting to 'all' if nothing's given.",
"Dumps all the entries in the top level paging table. No arguments.",
"Dumps all the physical address ranges. No arguments.",
"Dumps physical, virtual and hyper virtual handlers. "
"Pass 'phys', 'virt', 'hyper' as argument if only one kind is wanted."
"Add 'nost' if the statistics are unwanted, use together with 'all' or explicit selection.",
"Dumps guest mappings.",
#ifdef VBOX_WITH_DEBUGGER
/*
* Debugger commands.
*/
static bool s_fRegisteredCmds = false;
if (!s_fRegisteredCmds)
{
if (RT_SUCCESS(rc))
s_fRegisteredCmds = true;
}
#endif
return VINF_SUCCESS;
}
/* Almost no cleanup necessary, MM frees all memory. */
return rc;
}
/**
* Initializes the per-VCPU PGM.
*
* @returns VBox status code.
* @param pVM The VM to operate on.
*/
{
LogFlow(("PGMR3InitCPU\n"));
return VINF_SUCCESS;
}
/**
* Init paging.
*
* Since we need to check what mode the host is operating in before we can choose
* the right paging functions for the host we have to delay this until R0 has
* been initialized.
*
* @returns VBox status code.
* @param pVM VM handle.
*/
{
/*
* Force a recalculation of modes and switcher so everyone gets notified.
*/
{
}
/*
* Allocate static mapping space for whatever the cr3 register
* points to and in the case of PAE mode to the 4 PDs.
*/
if (RT_FAILURE(rc))
{
return rc;
}
/*
* Allocate pages for the three possible intermediate contexts
* (AMD64, PAE and plain 32-Bit). We maintain all three contexts
* for the sake of simplicity. The AMD64 uses the PAE for the
* lower levels, making the total number of pages 11 (3 + 7 + 1).
*
* We assume that two page tables will be enought for the core code
* mappings (HC virtual and identity).
*/
pVM->pgm.s.pInterPD = (PX86PD)MMR3PageAllocLow(pVM); AssertReturn(pVM->pgm.s.pInterPD, VERR_NO_PAGE_MEMORY);
pVM->pgm.s.apInterPTs[0] = (PX86PT)MMR3PageAllocLow(pVM); AssertReturn(pVM->pgm.s.apInterPTs[0], VERR_NO_PAGE_MEMORY);
pVM->pgm.s.apInterPTs[1] = (PX86PT)MMR3PageAllocLow(pVM); AssertReturn(pVM->pgm.s.apInterPTs[1], VERR_NO_PAGE_MEMORY);
pVM->pgm.s.apInterPaePTs[0] = (PX86PTPAE)MMR3PageAlloc(pVM); AssertReturn(pVM->pgm.s.apInterPaePTs[0], VERR_NO_PAGE_MEMORY);
pVM->pgm.s.apInterPaePTs[1] = (PX86PTPAE)MMR3PageAlloc(pVM); AssertReturn(pVM->pgm.s.apInterPaePTs[1], VERR_NO_PAGE_MEMORY);
pVM->pgm.s.apInterPaePDs[0] = (PX86PDPAE)MMR3PageAlloc(pVM); AssertReturn(pVM->pgm.s.apInterPaePDs[0], VERR_NO_PAGE_MEMORY);
pVM->pgm.s.apInterPaePDs[1] = (PX86PDPAE)MMR3PageAlloc(pVM); AssertReturn(pVM->pgm.s.apInterPaePDs[1], VERR_NO_PAGE_MEMORY);
pVM->pgm.s.apInterPaePDs[2] = (PX86PDPAE)MMR3PageAlloc(pVM); AssertReturn(pVM->pgm.s.apInterPaePDs[2], VERR_NO_PAGE_MEMORY);
pVM->pgm.s.apInterPaePDs[3] = (PX86PDPAE)MMR3PageAlloc(pVM); AssertReturn(pVM->pgm.s.apInterPaePDs[3], VERR_NO_PAGE_MEMORY);
pVM->pgm.s.pInterPaePDPT = (PX86PDPT)MMR3PageAllocLow(pVM); AssertReturn(pVM->pgm.s.pInterPaePDPT, VERR_NO_PAGE_MEMORY);
pVM->pgm.s.pInterPaePDPT64 = (PX86PDPT)MMR3PageAllocLow(pVM); AssertReturn(pVM->pgm.s.pInterPaePDPT64, VERR_NO_PAGE_MEMORY);
pVM->pgm.s.pInterPaePML4 = (PX86PML4)MMR3PageAllocLow(pVM); AssertReturn(pVM->pgm.s.pInterPaePML4, VERR_NO_PAGE_MEMORY);
AssertRelease(pVM->pgm.s.HCPhysInterPD != NIL_RTHCPHYS && !(pVM->pgm.s.HCPhysInterPD & PAGE_OFFSET_MASK));
AssertRelease(pVM->pgm.s.HCPhysInterPaePDPT != NIL_RTHCPHYS && !(pVM->pgm.s.HCPhysInterPaePDPT & PAGE_OFFSET_MASK));
AssertRelease(pVM->pgm.s.HCPhysInterPaePML4 != NIL_RTHCPHYS && !(pVM->pgm.s.HCPhysInterPaePML4 & PAGE_OFFSET_MASK) && pVM->pgm.s.HCPhysInterPaePML4 < 0xffffffff);
/*
* Initialize the pages, setting up the PML4 and PDPT for repetitive 4GB action.
*/
{
}
{
pVM->pgm.s.pInterPaePDPT64->a[i].u = X86_PDPE_P | X86_PDPE_RW | X86_PDPE_US | X86_PDPE_A | PGM_PLXFLAGS_PERMANENT
}
pVM->pgm.s.pInterPaePML4->a[i].u = X86_PML4E_P | X86_PML4E_RW | X86_PML4E_US | X86_PML4E_A | PGM_PLXFLAGS_PERMANENT
/*
* Initialize paging workers and mode from current host mode
* and the guest running in real mode.
*/
{
case SUPPAGINGMODE_32_BIT:
case SUPPAGINGMODE_PAE:
case SUPPAGINGMODE_PAE_GLOBAL:
case SUPPAGINGMODE_PAE_NX:
break;
case SUPPAGINGMODE_AMD64:
case SUPPAGINGMODE_AMD64_NX:
#ifndef VBOX_WITH_HYBRID_32BIT_KERNEL
if (ARCH_BITS != 64)
{
AssertMsgFailed(("Host mode %d (64-bit) is not supported by non-64bit builds\n", pVM->pgm.s.enmHostMode));
}
#endif
break;
default:
}
if (RT_SUCCESS(rc))
{
LogFlow(("pgmR3InitPaging: returns successfully\n"));
#if HC_ARCH_BITS == 64
LogRel(("Debug: HCPhysInterPD=%RHp HCPhysInterPaePDPT=%RHp HCPhysInterPaePML4=%RHp\n",
LogRel(("Debug: apInterPTs={%RHp,%RHp} apInterPaePTs={%RHp,%RHp} apInterPaePDs={%RHp,%RHp,%RHp,%RHp} pInterPaePDPT64=%RHp\n",
MMPage2Phys(pVM, pVM->pgm.s.apInterPaePDs[0]), MMPage2Phys(pVM, pVM->pgm.s.apInterPaePDs[1]), MMPage2Phys(pVM, pVM->pgm.s.apInterPaePDs[2]), MMPage2Phys(pVM, pVM->pgm.s.apInterPaePDs[3]),
#endif
return VINF_SUCCESS;
}
return rc;
}
/**
* Init statistics
*/
{
int rc;
/* Common - misc variables */
STAM_REL_REG(pVM, &pPGM->cAllPages, STAMTYPE_U32, "/PGM/Page/cAllPages", STAMUNIT_OCCURENCES, "The total number of pages.");
STAM_REL_REG(pVM, &pPGM->cPrivatePages, STAMTYPE_U32, "/PGM/Page/cPrivatePages", STAMUNIT_OCCURENCES, "The number of private pages.");
STAM_REL_REG(pVM, &pPGM->cSharedPages, STAMTYPE_U32, "/PGM/Page/cSharedPages", STAMUNIT_OCCURENCES, "The number of shared pages.");
STAM_REL_REG(pVM, &pPGM->cZeroPages, STAMTYPE_U32, "/PGM/Page/cZeroPages", STAMUNIT_OCCURENCES, "The number of zero backed pages.");
STAM_REL_REG(pVM, &pPGM->cHandyPages, STAMTYPE_U32, "/PGM/Page/cHandyPages", STAMUNIT_OCCURENCES, "The number of handy pages (not included in cAllPages).");
STAM_REL_REG(pVM, &pPGM->cRelocations, STAMTYPE_COUNTER, "/PGM/cRelocations", STAMUNIT_OCCURENCES, "Number of hypervisor relocations.");
STAM_REL_REG(pVM, &pPGM->ChunkR3Map.c, STAMTYPE_U32, "/PGM/ChunkR3Map/c", STAMUNIT_OCCURENCES, "Number of mapped chunks.");
STAM_REL_REG(pVM, &pPGM->ChunkR3Map.cMax, STAMTYPE_U32, "/PGM/ChunkR3Map/cMax", STAMUNIT_OCCURENCES, "Maximum number of mapped chunks.");
#ifdef VBOX_WITH_STATISTICS
# define PGM_REG_COUNTER(a, b, c) \
# define PGM_REG_COUNTER_BYTES(a, b, c) \
# define PGM_REG_PROFILE(a, b, c) \
rc = STAMR3RegisterF(pVM, a, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_CALL, c, b); \
PGM_REG_COUNTER(&pPGM->StatR3DetectedConflicts, "/PGM/R3/DetectedConflicts", "The number of times PGMR3CheckMappingConflicts() detected a conflict.");
PGM_REG_PROFILE(&pPGM->StatR3ResolveConflict, "/PGM/R3/ResolveConflict", "pgmR3SyncPTResolveConflict() profiling (includes the entire relocation).");
PGM_REG_COUNTER(&pPGM->StatR3PhysRead, "/PGM/R3/Phys/Read", "The number of times PGMPhysRead was called.");
PGM_REG_COUNTER_BYTES(&pPGM->StatR3PhysReadBytes, "/PGM/R3/Phys/Read/Bytes", "The number of bytes read by PGMPhysRead.");
PGM_REG_COUNTER(&pPGM->StatR3PhysWrite, "/PGM/R3/Phys/Write", "The number of times PGMPhysWrite was called.");
PGM_REG_COUNTER_BYTES(&pPGM->StatR3PhysWriteBytes, "/PGM/R3/Phys/Write/Bytes", "The number of bytes written by PGMPhysWrite.");
PGM_REG_COUNTER(&pPGM->StatR3PhysSimpleRead, "/PGM/R3/Phys/Simple/Read", "The number of times PGMPhysSimpleReadGCPtr was called.");
PGM_REG_COUNTER_BYTES(&pPGM->StatR3PhysSimpleReadBytes, "/PGM/R3/Phys/Simple/Read/Bytes", "The number of bytes read by PGMPhysSimpleReadGCPtr.");
PGM_REG_COUNTER(&pPGM->StatR3PhysSimpleWrite, "/PGM/R3/Phys/Simple/Write", "The number of times PGMPhysSimpleWriteGCPtr was called.");
PGM_REG_COUNTER_BYTES(&pPGM->StatR3PhysSimpleWriteBytes, "/PGM/R3/Phys/Simple/Write/Bytes", "The number of bytes written by PGMPhysSimpleWriteGCPtr.");
PGM_REG_PROFILE(&pPGM->StatRZSyncCR3HandlerVirtualUpdate, "/PGM/RZ/SyncCR3/Handlers/VirtualUpdate", "Profiling of the virtual handler updates.");
PGM_REG_PROFILE(&pPGM->StatRZSyncCR3HandlerVirtualReset, "/PGM/RZ/SyncCR3/Handlers/VirtualReset", "Profiling of the virtual handler resets.");
PGM_REG_PROFILE(&pPGM->StatR3SyncCR3HandlerVirtualUpdate, "/PGM/R3/SyncCR3/Handlers/VirtualUpdate", "Profiling of the virtual handler updates.");
PGM_REG_PROFILE(&pPGM->StatR3SyncCR3HandlerVirtualReset, "/PGM/R3/SyncCR3/Handlers/VirtualReset", "Profiling of the virtual handler resets.");
PGM_REG_COUNTER(&pPGM->StatRZPhysHandlerReset, "/PGM/RZ/PhysHandlerReset", "The number of times PGMHandlerPhysicalReset is called.");
PGM_REG_COUNTER(&pPGM->StatR3PhysHandlerReset, "/PGM/R3/PhysHandlerReset", "The number of times PGMHandlerPhysicalReset is called.");
PGM_REG_PROFILE(&pPGM->StatRZVirtHandlerSearchByPhys, "/PGM/RZ/VirtHandlerSearchByPhys", "Profiling of pgmHandlerVirtualFindByPhysAddr.");
PGM_REG_PROFILE(&pPGM->StatR3VirtHandlerSearchByPhys, "/PGM/R3/VirtHandlerSearchByPhys", "Profiling of pgmHandlerVirtualFindByPhysAddr.");
PGM_REG_COUNTER(&pPGM->StatRZPageReplaceShared, "/PGM/RZ/Page/ReplacedShared", "Times a shared page was replaced.");
PGM_REG_COUNTER(&pPGM->StatRZPageReplaceZero, "/PGM/RZ/Page/ReplacedZero", "Times the zero page was replaced.");
/// @todo PGM_REG_COUNTER(&pPGM->StatRZPageHandyAllocs, "/PGM/RZ/Page/HandyAllocs", "Number of times we've allocated more handy pages.");
PGM_REG_COUNTER(&pPGM->StatR3PageReplaceShared, "/PGM/R3/Page/ReplacedShared", "Times a shared page was replaced.");
PGM_REG_COUNTER(&pPGM->StatR3PageReplaceZero, "/PGM/R3/Page/ReplacedZero", "Times the zero page was replaced.");
/// @todo PGM_REG_COUNTER(&pPGM->StatR3PageHandyAllocs, "/PGM/R3/Page/HandyAllocs", "Number of times we've allocated more handy pages.");
PGM_REG_COUNTER(&pPGM->StatRZPhysRead, "/PGM/RZ/Phys/Read", "The number of times PGMPhysRead was called.");
PGM_REG_COUNTER_BYTES(&pPGM->StatRZPhysReadBytes, "/PGM/RZ/Phys/Read/Bytes", "The number of bytes read by PGMPhysRead.");
PGM_REG_COUNTER(&pPGM->StatRZPhysWrite, "/PGM/RZ/Phys/Write", "The number of times PGMPhysWrite was called.");
PGM_REG_COUNTER_BYTES(&pPGM->StatRZPhysWriteBytes, "/PGM/RZ/Phys/Write/Bytes", "The number of bytes written by PGMPhysWrite.");
PGM_REG_COUNTER(&pPGM->StatRZPhysSimpleRead, "/PGM/RZ/Phys/Simple/Read", "The number of times PGMPhysSimpleReadGCPtr was called.");
PGM_REG_COUNTER_BYTES(&pPGM->StatRZPhysSimpleReadBytes, "/PGM/RZ/Phys/Simple/Read/Bytes", "The number of bytes read by PGMPhysSimpleReadGCPtr.");
PGM_REG_COUNTER(&pPGM->StatRZPhysSimpleWrite, "/PGM/RZ/Phys/Simple/Write", "The number of times PGMPhysSimpleWriteGCPtr was called.");
PGM_REG_COUNTER_BYTES(&pPGM->StatRZPhysSimpleWriteBytes, "/PGM/RZ/Phys/Simple/Write/Bytes", "The number of bytes written by PGMPhysSimpleWriteGCPtr.");
/* GC only: */
PGM_REG_COUNTER(&pPGM->StatRCDynMapCacheHits, "/PGM/RC/DynMapCache/Hits" , "Number of dynamic page mapping cache hits.");
PGM_REG_COUNTER(&pPGM->StatRCDynMapCacheMisses, "/PGM/RC/DynMapCache/Misses" , "Number of dynamic page mapping cache misses.");
PGM_REG_COUNTER(&pPGM->StatRCInvlPgConflict, "/PGM/RC/InvlPgConflict", "Number of times PGMInvalidatePage() detected a mapping conflict.");
PGM_REG_COUNTER(&pPGM->StatRCInvlPgSyncMonCR3, "/PGM/RC/InvlPgSyncMonitorCR3", "Number of times PGMInvalidatePage() ran into PGM_SYNC_MONITOR_CR3.");
PGM_REG_COUNTER(&pPGM->StatRCPhysRead, "/PGM/RC/Phys/Read", "The number of times PGMPhysRead was called.");
PGM_REG_COUNTER_BYTES(&pPGM->StatRCPhysReadBytes, "/PGM/RC/Phys/Read/Bytes", "The number of bytes read by PGMPhysRead.");
PGM_REG_COUNTER(&pPGM->StatRCPhysWrite, "/PGM/RC/Phys/Write", "The number of times PGMPhysWrite was called.");
PGM_REG_COUNTER_BYTES(&pPGM->StatRCPhysWriteBytes, "/PGM/RC/Phys/Write/Bytes", "The number of bytes written by PGMPhysWrite.");
PGM_REG_COUNTER(&pPGM->StatRCPhysSimpleRead, "/PGM/RC/Phys/Simple/Read", "The number of times PGMPhysSimpleReadGCPtr was called.");
PGM_REG_COUNTER_BYTES(&pPGM->StatRCPhysSimpleReadBytes, "/PGM/RC/Phys/Simple/Read/Bytes", "The number of bytes read by PGMPhysSimpleReadGCPtr.");
PGM_REG_COUNTER(&pPGM->StatRCPhysSimpleWrite, "/PGM/RC/Phys/Simple/Write", "The number of times PGMPhysSimpleWriteGCPtr was called.");
PGM_REG_COUNTER_BYTES(&pPGM->StatRCPhysSimpleWriteBytes, "/PGM/RC/Phys/Simple/Write/Bytes", "The number of bytes written by PGMPhysSimpleWriteGCPtr.");
# ifdef PGMPOOL_WITH_GCPHYS_TRACKING
PGM_REG_COUNTER(&pPGM->StatTrackVirgin, "/PGM/Track/Virgin", "The number of first time shadowings");
PGM_REG_COUNTER(&pPGM->StatTrackAliased, "/PGM/Track/Aliased", "The number of times switching to cRef2, i.e. the page is being shadowed by two PTs.");
PGM_REG_COUNTER(&pPGM->StatTrackAliasedMany, "/PGM/Track/AliasedMany", "The number of times we're tracking using cRef2.");
PGM_REG_COUNTER(&pPGM->StatTrackAliasedLots, "/PGM/Track/AliasedLots", "The number of times we're hitting pages which has overflowed cRef2");
PGM_REG_COUNTER(&pPGM->StatTrackOverflows, "/PGM/Track/Overflows", "The number of times the extent list grows too long.");
PGM_REG_PROFILE(&pPGM->StatTrackDeref, "/PGM/Track/Deref", "Profiling of SyncPageWorkerTrackDeref (expensive).");
# endif
#endif
/*
* Note! The layout below matches the member layout exactly!
*/
/*
* Common - stats
*/
{
#define PGM_REG_COUNTER(a, b, c) \
rc = STAMR3RegisterF(pVM, a, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, c, b, i); \
#define PGM_REG_PROFILE(a, b, c) \
rc = STAMR3RegisterF(pVM, a, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_CALL, c, b, i); \
PGM_REG_COUNTER(&pPGM->cGuestModeChanges, "/PGM/CPU%d/cGuestModeChanges", "Number of guest mode changes.");
#ifdef VBOX_WITH_STATISTICS
# if 0 /* rarely useful; leave for debugging. */
STAMR3RegisterF(pVM, &pPGM->StatSyncPtPD[i], STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES,
STAMR3RegisterF(pVM, &pPGM->StatSyncPagePD[i], STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES,
"The number of SyncPage per PD n.", "/PGM/CPU%d/PDSyncPage/%04X", i, j);
# endif
/* R0 only: */
PGM_REG_COUNTER(&pPGM->StatR0DynMapMigrateInvlPg, "/PGM/CPU%d/R0/DynMapMigrateInvlPg", "invlpg count in PGMDynMapMigrateAutoSet.");
PGM_REG_PROFILE(&pPGM->StatR0DynMapGCPageInl, "/PGM/CPU%d/R0/DynMapPageGCPageInl", "Calls to pgmR0DynMapGCPageInlined.");
PGM_REG_COUNTER(&pPGM->StatR0DynMapGCPageInlHits, "/PGM/CPU%d/R0/DynMapPageGCPageInl/Hits", "Hash table lookup hits.");
PGM_REG_COUNTER(&pPGM->StatR0DynMapGCPageInlMisses, "/PGM/CPU%d/R0/DynMapPageGCPageInl/Misses", "Misses that falls back to code common with PGMDynMapHCPage.");
PGM_REG_COUNTER(&pPGM->StatR0DynMapGCPageInlRamHits, "/PGM/CPU%d/R0/DynMapPageGCPageInl/RamHits", "1st ram range hits.");
PGM_REG_COUNTER(&pPGM->StatR0DynMapGCPageInlRamMisses, "/PGM/CPU%d/R0/DynMapPageGCPageInl/RamMisses", "1st ram range misses, takes slow path.");
PGM_REG_PROFILE(&pPGM->StatR0DynMapHCPageInl, "/PGM/CPU%d/R0/DynMapPageHCPageInl", "Calls to pgmR0DynMapHCPageInlined.");
PGM_REG_COUNTER(&pPGM->StatR0DynMapHCPageInlHits, "/PGM/CPU%d/R0/DynMapPageHCPageInl/Hits", "Hash table lookup hits.");
PGM_REG_COUNTER(&pPGM->StatR0DynMapHCPageInlMisses, "/PGM/CPU%d/R0/DynMapPageHCPageInl/Misses", "Misses that falls back to code common with PGMDynMapHCPage.");
PGM_REG_COUNTER(&pPGM->StatR0DynMapSetOptimize, "/PGM/CPU%d/R0/DynMapPage/SetOptimize", "Calls to pgmDynMapOptimizeAutoSet.");
PGM_REG_COUNTER(&pPGM->StatR0DynMapSetSearchFlushes, "/PGM/CPU%d/R0/DynMapPage/SetSearchFlushes","Set search restorting to subset flushes.");
PGM_REG_COUNTER(&pPGM->StatR0DynMapSetSearchHits, "/PGM/CPU%d/R0/DynMapPage/SetSearchHits", "Set search hits.");
PGM_REG_COUNTER(&pPGM->StatR0DynMapSetSearchMisses, "/PGM/CPU%d/R0/DynMapPage/SetSearchMisses", "Set search misses.");
PGM_REG_PROFILE(&pPGM->StatR0DynMapHCPage, "/PGM/CPU%d/R0/DynMapPage/HCPage", "Calls to PGMDynMapHCPage (ring-0).");
PGM_REG_COUNTER(&pPGM->StatR0DynMapPageInvlPg, "/PGM/CPU%d/R0/DynMapPage/InvlPg", "invlpg count in pgmR0DynMapPageSlow.");
PGM_REG_COUNTER(&pPGM->StatR0DynMapPageSlow, "/PGM/CPU%d/R0/DynMapPage/Slow", "Calls to pgmR0DynMapPageSlow - subtract this from pgmR0DynMapPage to get 1st level hits.");
PGM_REG_COUNTER(&pPGM->StatR0DynMapPageSlowLoopHits, "/PGM/CPU%d/R0/DynMapPage/SlowLoopHits" , "Hits in the loop path.");
PGM_REG_COUNTER(&pPGM->StatR0DynMapPageSlowLoopMisses, "/PGM/CPU%d/R0/DynMapPage/SlowLoopMisses", "Misses in the loop path. NonLoopMisses = Slow - SlowLoopHit - SlowLoopMisses");
//PGM_REG_COUNTER(&pPGM->StatR0DynMapPageSlowLostHits, "/PGM/CPU%d/R0/DynMapPage/SlowLostHits", "Lost hits.");
PGM_REG_COUNTER(&pPGM->StatR0DynMapSubsets, "/PGM/CPU%d/R0/Subsets", "Times PGMDynMapPushAutoSubset was called.");
PGM_REG_COUNTER(&pPGM->StatR0DynMapPopFlushes, "/PGM/CPU%d/R0/SubsetPopFlushes", "Times PGMDynMapPopAutoSubset flushes the subset.");
/* RZ only: */
PGM_REG_PROFILE(&pPGM->StatRZTrap0e, "/PGM/CPU%d/RZ/Trap0e", "Profiling of the PGMTrap0eHandler() body.");
PGM_REG_PROFILE(&pPGM->StatRZTrap0eTimeCheckPageFault, "/PGM/CPU%d/RZ/Trap0e/Time/CheckPageFault", "Profiling of checking for dirty/access emulation faults.");
PGM_REG_PROFILE(&pPGM->StatRZTrap0eTimeSyncPT, "/PGM/CPU%d/RZ/Trap0e/Time/SyncPT", "Profiling of lazy page table syncing.");
PGM_REG_PROFILE(&pPGM->StatRZTrap0eTimeMapping, "/PGM/CPU%d/RZ/Trap0e/Time/Mapping", "Profiling of checking virtual mappings.");
PGM_REG_PROFILE(&pPGM->StatRZTrap0eTimeOutOfSync, "/PGM/CPU%d/RZ/Trap0e/Time/OutOfSync", "Profiling of out of sync page handling.");
PGM_REG_PROFILE(&pPGM->StatRZTrap0eTimeHandlers, "/PGM/CPU%d/RZ/Trap0e/Time/Handlers", "Profiling of checking handlers.");
PGM_REG_PROFILE(&pPGM->StatRZTrap0eTime2CSAM, "/PGM/CPU%d/RZ/Trap0e/Time2/CSAM", "Profiling of the Trap0eHandler body when the cause is CSAM.");
PGM_REG_PROFILE(&pPGM->StatRZTrap0eTime2DirtyAndAccessed, "/PGM/CPU%d/RZ/Trap0e/Time2/DirtyAndAccessedBits", "Profiling of the Trap0eHandler body when the cause is dirty and/or accessed bit emulation.");
PGM_REG_PROFILE(&pPGM->StatRZTrap0eTime2GuestTrap, "/PGM/CPU%d/RZ/Trap0e/Time2/GuestTrap", "Profiling of the Trap0eHandler body when the cause is a guest trap.");
PGM_REG_PROFILE(&pPGM->StatRZTrap0eTime2HndPhys, "/PGM/CPU%d/RZ/Trap0e/Time2/HandlerPhysical", "Profiling of the Trap0eHandler body when the cause is a physical handler.");
PGM_REG_PROFILE(&pPGM->StatRZTrap0eTime2HndVirt, "/PGM/CPU%d/RZ/Trap0e/Time2/HandlerVirtual", "Profiling of the Trap0eHandler body when the cause is a virtual handler.");
PGM_REG_PROFILE(&pPGM->StatRZTrap0eTime2HndUnhandled, "/PGM/CPU%d/RZ/Trap0e/Time2/HandlerUnhandled", "Profiling of the Trap0eHandler body when the cause is access outside the monitored areas of a monitored page.");
PGM_REG_PROFILE(&pPGM->StatRZTrap0eTime2Misc, "/PGM/CPU%d/RZ/Trap0e/Time2/Misc", "Profiling of the Trap0eHandler body when the cause is not known.");
PGM_REG_PROFILE(&pPGM->StatRZTrap0eTime2OutOfSync, "/PGM/CPU%d/RZ/Trap0e/Time2/OutOfSync", "Profiling of the Trap0eHandler body when the cause is an out-of-sync page.");
PGM_REG_PROFILE(&pPGM->StatRZTrap0eTime2OutOfSyncHndPhys, "/PGM/CPU%d/RZ/Trap0e/Time2/OutOfSyncHndPhys", "Profiling of the Trap0eHandler body when the cause is an out-of-sync physical handler page.");
PGM_REG_PROFILE(&pPGM->StatRZTrap0eTime2OutOfSyncHndVirt, "/PGM/CPU%d/RZ/Trap0e/Time2/OutOfSyncHndVirt", "Profiling of the Trap0eHandler body when the cause is an out-of-sync virtual handler page.");
PGM_REG_PROFILE(&pPGM->StatRZTrap0eTime2OutOfSyncHndObs, "/PGM/CPU%d/RZ/Trap0e/Time2/OutOfSyncObsHnd", "Profiling of the Trap0eHandler body when the cause is an obsolete handler page.");
PGM_REG_PROFILE(&pPGM->StatRZTrap0eTime2SyncPT, "/PGM/CPU%d/RZ/Trap0e/Time2/SyncPT", "Profiling of the Trap0eHandler body when the cause is lazy syncing of a PT.");
PGM_REG_COUNTER(&pPGM->StatRZTrap0eConflicts, "/PGM/CPU%d/RZ/Trap0e/Conflicts", "The number of times #PF was caused by an undetected conflict.");
PGM_REG_COUNTER(&pPGM->StatRZTrap0eHandlersMapping, "/PGM/CPU%d/RZ/Trap0e/Handlers/Mapping", "Number of traps due to access handlers in mappings.");
PGM_REG_COUNTER(&pPGM->StatRZTrap0eHandlersOutOfSync, "/PGM/CPU%d/RZ/Trap0e/Handlers/OutOfSync", "Number of traps due to out-of-sync handled pages.");
PGM_REG_COUNTER(&pPGM->StatRZTrap0eHandlersPhysical, "/PGM/CPU%d/RZ/Trap0e/Handlers/Physical", "Number of traps due to physical access handlers.");
PGM_REG_COUNTER(&pPGM->StatRZTrap0eHandlersVirtual, "/PGM/CPU%d/RZ/Trap0e/Handlers/Virtual", "Number of traps due to virtual access handlers.");
PGM_REG_COUNTER(&pPGM->StatRZTrap0eHandlersVirtualByPhys, "/PGM/CPU%d/RZ/Trap0e/Handlers/VirtualByPhys", "Number of traps due to virtual access handlers by physical address.");
PGM_REG_COUNTER(&pPGM->StatRZTrap0eHandlersVirtualUnmarked,"/PGM/CPU%d/RZ/Trap0e/Handlers/VirtualUnmarked","Number of traps due to virtual access handlers by virtual address (without proper physical flags).");
PGM_REG_COUNTER(&pPGM->StatRZTrap0eHandlersUnhandled, "/PGM/CPU%d/RZ/Trap0e/Handlers/Unhandled", "Number of traps due to access outside range of monitored page(s).");
PGM_REG_COUNTER(&pPGM->StatRZTrap0eHandlersInvalid, "/PGM/CPU%d/RZ/Trap0e/Handlers/Invalid", "Number of traps due to access to invalid physical memory.");
PGM_REG_COUNTER(&pPGM->StatRZTrap0eUSNotPresentRead, "/PGM/CPU%d/RZ/Trap0e/Err/User/NPRead", "Number of user mode not present read page faults.");
PGM_REG_COUNTER(&pPGM->StatRZTrap0eUSNotPresentWrite, "/PGM/CPU%d/RZ/Trap0e/Err/User/NPWrite", "Number of user mode not present write page faults.");
PGM_REG_COUNTER(&pPGM->StatRZTrap0eUSWrite, "/PGM/CPU%d/RZ/Trap0e/Err/User/Write", "Number of user mode write page faults.");
PGM_REG_COUNTER(&pPGM->StatRZTrap0eUSReserved, "/PGM/CPU%d/RZ/Trap0e/Err/User/Reserved", "Number of user mode reserved bit page faults.");
PGM_REG_COUNTER(&pPGM->StatRZTrap0eUSNXE, "/PGM/CPU%d/RZ/Trap0e/Err/User/NXE", "Number of user mode NXE page faults.");
PGM_REG_COUNTER(&pPGM->StatRZTrap0eUSRead, "/PGM/CPU%d/RZ/Trap0e/Err/User/Read", "Number of user mode read page faults.");
PGM_REG_COUNTER(&pPGM->StatRZTrap0eSVNotPresentRead, "/PGM/CPU%d/RZ/Trap0e/Err/Supervisor/NPRead", "Number of supervisor mode not present read page faults.");
PGM_REG_COUNTER(&pPGM->StatRZTrap0eSVNotPresentWrite, "/PGM/CPU%d/RZ/Trap0e/Err/Supervisor/NPWrite", "Number of supervisor mode not present write page faults.");
PGM_REG_COUNTER(&pPGM->StatRZTrap0eSVWrite, "/PGM/CPU%d/RZ/Trap0e/Err/Supervisor/Write", "Number of supervisor mode write page faults.");
PGM_REG_COUNTER(&pPGM->StatRZTrap0eSVReserved, "/PGM/CPU%d/RZ/Trap0e/Err/Supervisor/Reserved", "Number of supervisor mode reserved bit page faults.");
PGM_REG_COUNTER(&pPGM->StatRZTrap0eSNXE, "/PGM/CPU%d/RZ/Trap0e/Err/Supervisor/NXE", "Number of supervisor mode NXE page faults.");
PGM_REG_COUNTER(&pPGM->StatRZTrap0eGuestPF, "/PGM/CPU%d/RZ/Trap0e/GuestPF", "Number of real guest page faults.");
PGM_REG_COUNTER(&pPGM->StatRZTrap0eGuestPFUnh, "/PGM/CPU%d/RZ/Trap0e/GuestPF/Unhandled", "Number of real guest page faults from the 'unhandled' case.");
PGM_REG_COUNTER(&pPGM->StatRZTrap0eGuestPFMapping, "/PGM/CPU%d/RZ/Trap0e/GuestPF/InMapping", "Number of real guest page faults in a mapping.");
PGM_REG_COUNTER(&pPGM->StatRZTrap0eWPEmulInRZ, "/PGM/CPU%d/RZ/Trap0e/WP/InRZ", "Number of guest page faults due to X86_CR0_WP emulation.");
PGM_REG_COUNTER(&pPGM->StatRZTrap0eWPEmulToR3, "/PGM/CPU%d/RZ/Trap0e/WP/ToR3", "Number of guest page faults due to X86_CR0_WP emulation (forward to R3 for emulation).");
#if 0 /* rarely useful; leave for debugging. */
STAMR3RegisterF(pVM, &pPGM->StatRZTrap0ePD[i], STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES,
#endif
PGM_REG_COUNTER(&pPGM->StatRZGuestCR3WriteHandled, "/PGM/CPU%d/RZ/CR3WriteHandled", "The number of times the Guest CR3 change was successfully handled.");
PGM_REG_COUNTER(&pPGM->StatRZGuestCR3WriteUnhandled, "/PGM/CPU%d/RZ/CR3WriteUnhandled", "The number of times the Guest CR3 change was passed back to the recompiler.");
PGM_REG_COUNTER(&pPGM->StatRZGuestCR3WriteConflict, "/PGM/CPU%d/RZ/CR3WriteConflict", "The number of times the Guest CR3 monitoring detected a conflict.");
PGM_REG_COUNTER(&pPGM->StatRZGuestROMWriteHandled, "/PGM/CPU%d/RZ/ROMWriteHandled", "The number of times the Guest ROM change was successfully handled.");
PGM_REG_COUNTER(&pPGM->StatRZGuestROMWriteUnhandled, "/PGM/CPU%d/RZ/ROMWriteUnhandled", "The number of times the Guest ROM change was passed back to the recompiler.");
/* HC only: */
/* RZ & R3: */
PGM_REG_PROFILE(&pPGM->StatRZSyncCR3, "/PGM/CPU%d/RZ/SyncCR3", "Profiling of the PGMSyncCR3() body.");
PGM_REG_PROFILE(&pPGM->StatRZSyncCR3Handlers, "/PGM/CPU%d/RZ/SyncCR3/Handlers", "Profiling of the PGMSyncCR3() update handler section.");
PGM_REG_COUNTER(&pPGM->StatRZSyncCR3Global, "/PGM/CPU%d/RZ/SyncCR3/Global", "The number of global CR3 syncs.");
PGM_REG_COUNTER(&pPGM->StatRZSyncCR3NotGlobal, "/PGM/CPU%d/RZ/SyncCR3/NotGlobal", "The number of non-global CR3 syncs.");
PGM_REG_COUNTER(&pPGM->StatRZSyncCR3DstCacheHit, "/PGM/CPU%d/RZ/SyncCR3/DstChacheHit", "The number of times we got some kind of a cache hit.");
PGM_REG_COUNTER(&pPGM->StatRZSyncCR3DstFreed, "/PGM/CPU%d/RZ/SyncCR3/DstFreed", "The number of times we've had to free a shadow entry.");
PGM_REG_COUNTER(&pPGM->StatRZSyncCR3DstFreedSrcNP, "/PGM/CPU%d/RZ/SyncCR3/DstFreedSrcNP", "The number of times we've had to free a shadow entry for which the source entry was not present.");
PGM_REG_COUNTER(&pPGM->StatRZSyncCR3DstNotPresent, "/PGM/CPU%d/RZ/SyncCR3/DstNotPresent", "The number of times we've encountered a not present shadow entry for a present guest entry.");
PGM_REG_COUNTER(&pPGM->StatRZSyncCR3DstSkippedGlobalPD, "/PGM/CPU%d/RZ/SyncCR3/DstSkippedGlobalPD", "The number of times a global page directory wasn't flushed.");
PGM_REG_COUNTER(&pPGM->StatRZSyncCR3DstSkippedGlobalPT, "/PGM/CPU%d/RZ/SyncCR3/DstSkippedGlobalPT", "The number of times a page table with only global entries wasn't flushed.");
PGM_REG_COUNTER(&pPGM->StatRZSyncPTFailed, "/PGM/CPU%d/RZ/SyncPT/Failed", "The number of times pfnSyncPT() failed.");
PGM_REG_COUNTER(&pPGM->StatRZSyncPagePDNAs, "/PGM/CPU%d/RZ/SyncPagePDNAs", "The number of time we've marked a PD not present from SyncPage to virtualize the accessed bit.");
PGM_REG_COUNTER(&pPGM->StatRZSyncPagePDOutOfSync, "/PGM/CPU%d/RZ/SyncPagePDOutOfSync", "The number of time we've encountered an out-of-sync PD in SyncPage.");
PGM_REG_COUNTER(&pPGM->StatRZAccessedPage, "/PGM/CPU%d/RZ/AccessedPage", "The number of pages marked not present for accessed bit emulation.");
PGM_REG_PROFILE(&pPGM->StatRZDirtyBitTracking, "/PGM/CPU%d/RZ/DirtyPage", "Profiling the dirty bit tracking in CheckPageFault().");
PGM_REG_COUNTER(&pPGM->StatRZDirtyPage, "/PGM/CPU%d/RZ/DirtyPage/Mark", "The number of pages marked read-only for dirty bit tracking.");
PGM_REG_COUNTER(&pPGM->StatRZDirtyPageBig, "/PGM/CPU%d/RZ/DirtyPage/MarkBig", "The number of 4MB pages marked read-only for dirty bit tracking.");
PGM_REG_COUNTER(&pPGM->StatRZDirtyPageSkipped, "/PGM/CPU%d/RZ/DirtyPage/Skipped", "The number of pages already dirty or readonly.");
PGM_REG_COUNTER(&pPGM->StatRZDirtyPageTrap, "/PGM/CPU%d/RZ/DirtyPage/Trap", "The number of traps generated for dirty bit tracking.");
PGM_REG_COUNTER(&pPGM->StatRZDirtyPageStale, "/PGM/CPU%d/RZ/DirtyPage/Stale", "The number of traps generated for dirty bit tracking (stale tlb entries).");
PGM_REG_COUNTER(&pPGM->StatRZDirtiedPage, "/PGM/CPU%d/RZ/DirtyPage/SetDirty", "The number of pages marked dirty because of write accesses.");
PGM_REG_COUNTER(&pPGM->StatRZDirtyTrackRealPF, "/PGM/CPU%d/RZ/DirtyPage/RealPF", "The number of real pages faults during dirty bit tracking.");
PGM_REG_COUNTER(&pPGM->StatRZPageAlreadyDirty, "/PGM/CPU%d/RZ/DirtyPage/AlreadySet", "The number of pages already marked dirty because of write accesses.");
PGM_REG_PROFILE(&pPGM->StatRZInvalidatePage, "/PGM/CPU%d/RZ/InvalidatePage", "PGMInvalidatePage() profiling.");
PGM_REG_COUNTER(&pPGM->StatRZInvalidatePage4KBPages, "/PGM/CPU%d/RZ/InvalidatePage/4KBPages", "The number of times PGMInvalidatePage() was called for a 4KB page.");
PGM_REG_COUNTER(&pPGM->StatRZInvalidatePage4MBPages, "/PGM/CPU%d/RZ/InvalidatePage/4MBPages", "The number of times PGMInvalidatePage() was called for a 4MB page.");
PGM_REG_COUNTER(&pPGM->StatRZInvalidatePage4MBPagesSkip, "/PGM/CPU%d/RZ/InvalidatePage/4MBPagesSkip","The number of times PGMInvalidatePage() skipped a 4MB page.");
PGM_REG_COUNTER(&pPGM->StatRZInvalidatePagePDMappings, "/PGM/CPU%d/RZ/InvalidatePage/PDMappings", "The number of times PGMInvalidatePage() was called for a page directory containing mappings (no conflict).");
PGM_REG_COUNTER(&pPGM->StatRZInvalidatePagePDNAs, "/PGM/CPU%d/RZ/InvalidatePage/PDNAs", "The number of times PGMInvalidatePage() was called for a not accessed page directory.");
PGM_REG_COUNTER(&pPGM->StatRZInvalidatePagePDNPs, "/PGM/CPU%d/RZ/InvalidatePage/PDNPs", "The number of times PGMInvalidatePage() was called for a not present page directory.");
PGM_REG_COUNTER(&pPGM->StatRZInvalidatePagePDOutOfSync, "/PGM/CPU%d/RZ/InvalidatePage/PDOutOfSync", "The number of times PGMInvalidatePage() was called for an out of sync page directory.");
PGM_REG_COUNTER(&pPGM->StatRZInvalidatePageSkipped, "/PGM/CPU%d/RZ/InvalidatePage/Skipped", "The number of times PGMInvalidatePage() was skipped due to not present shw or pending pending SyncCR3.");
PGM_REG_COUNTER(&pPGM->StatRZPageOutOfSyncSupervisor, "/PGM/CPU%d/RZ/OutOfSync/SuperVisor", "Number of traps due to pages out of sync and times VerifyAccessSyncPage calls SyncPage.");
PGM_REG_COUNTER(&pPGM->StatRZPageOutOfSyncUser, "/PGM/CPU%d/RZ/OutOfSync/User", "Number of traps due to pages out of sync and times VerifyAccessSyncPage calls SyncPage.");
PGM_REG_PROFILE(&pPGM->StatRZFlushTLB, "/PGM/CPU%d/RZ/FlushTLB", "Profiling of the PGMFlushTLB() body.");
PGM_REG_COUNTER(&pPGM->StatRZFlushTLBNewCR3, "/PGM/CPU%d/RZ/FlushTLB/NewCR3", "The number of times PGMFlushTLB was called with a new CR3, non-global. (switch)");
PGM_REG_COUNTER(&pPGM->StatRZFlushTLBNewCR3Global, "/PGM/CPU%d/RZ/FlushTLB/NewCR3Global", "The number of times PGMFlushTLB was called with a new CR3, global. (switch)");
PGM_REG_COUNTER(&pPGM->StatRZFlushTLBSameCR3, "/PGM/CPU%d/RZ/FlushTLB/SameCR3", "The number of times PGMFlushTLB was called with the same CR3, non-global. (flush)");
PGM_REG_COUNTER(&pPGM->StatRZFlushTLBSameCR3Global, "/PGM/CPU%d/RZ/FlushTLB/SameCR3Global", "The number of times PGMFlushTLB was called with the same CR3, global. (flush)");
PGM_REG_PROFILE(&pPGM->StatRZGstModifyPage, "/PGM/CPU%d/RZ/GstModifyPage", "Profiling of the PGMGstModifyPage() body.");
PGM_REG_PROFILE(&pPGM->StatR3SyncCR3, "/PGM/CPU%d/R3/SyncCR3", "Profiling of the PGMSyncCR3() body.");
PGM_REG_PROFILE(&pPGM->StatR3SyncCR3Handlers, "/PGM/CPU%d/R3/SyncCR3/Handlers", "Profiling of the PGMSyncCR3() update handler section.");
PGM_REG_COUNTER(&pPGM->StatR3SyncCR3Global, "/PGM/CPU%d/R3/SyncCR3/Global", "The number of global CR3 syncs.");
PGM_REG_COUNTER(&pPGM->StatR3SyncCR3NotGlobal, "/PGM/CPU%d/R3/SyncCR3/NotGlobal", "The number of non-global CR3 syncs.");
PGM_REG_COUNTER(&pPGM->StatR3SyncCR3DstCacheHit, "/PGM/CPU%d/R3/SyncCR3/DstChacheHit", "The number of times we got some kind of a cache hit.");
PGM_REG_COUNTER(&pPGM->StatR3SyncCR3DstFreed, "/PGM/CPU%d/R3/SyncCR3/DstFreed", "The number of times we've had to free a shadow entry.");
PGM_REG_COUNTER(&pPGM->StatR3SyncCR3DstFreedSrcNP, "/PGM/CPU%d/R3/SyncCR3/DstFreedSrcNP", "The number of times we've had to free a shadow entry for which the source entry was not present.");
PGM_REG_COUNTER(&pPGM->StatR3SyncCR3DstNotPresent, "/PGM/CPU%d/R3/SyncCR3/DstNotPresent", "The number of times we've encountered a not present shadow entry for a present guest entry.");
PGM_REG_COUNTER(&pPGM->StatR3SyncCR3DstSkippedGlobalPD, "/PGM/CPU%d/R3/SyncCR3/DstSkippedGlobalPD", "The number of times a global page directory wasn't flushed.");
PGM_REG_COUNTER(&pPGM->StatR3SyncCR3DstSkippedGlobalPT, "/PGM/CPU%d/R3/SyncCR3/DstSkippedGlobalPT", "The number of times a page table with only global entries wasn't flushed.");
PGM_REG_COUNTER(&pPGM->StatR3SyncPTFailed, "/PGM/CPU%d/R3/SyncPT/Failed", "The number of times pfnSyncPT() failed.");
PGM_REG_COUNTER(&pPGM->StatR3SyncPagePDNAs, "/PGM/CPU%d/R3/SyncPagePDNAs", "The number of time we've marked a PD not present from SyncPage to virtualize the accessed bit.");
PGM_REG_COUNTER(&pPGM->StatR3SyncPagePDOutOfSync, "/PGM/CPU%d/R3/SyncPagePDOutOfSync", "The number of time we've encountered an out-of-sync PD in SyncPage.");
PGM_REG_COUNTER(&pPGM->StatR3AccessedPage, "/PGM/CPU%d/R3/AccessedPage", "The number of pages marked not present for accessed bit emulation.");
PGM_REG_PROFILE(&pPGM->StatR3DirtyBitTracking, "/PGM/CPU%d/R3/DirtyPage", "Profiling the dirty bit tracking in CheckPageFault().");
PGM_REG_COUNTER(&pPGM->StatR3DirtyPage, "/PGM/CPU%d/R3/DirtyPage/Mark", "The number of pages marked read-only for dirty bit tracking.");
PGM_REG_COUNTER(&pPGM->StatR3DirtyPageBig, "/PGM/CPU%d/R3/DirtyPage/MarkBig", "The number of 4MB pages marked read-only for dirty bit tracking.");
PGM_REG_COUNTER(&pPGM->StatR3DirtyPageSkipped, "/PGM/CPU%d/R3/DirtyPage/Skipped", "The number of pages already dirty or readonly.");
PGM_REG_COUNTER(&pPGM->StatR3DirtyPageTrap, "/PGM/CPU%d/R3/DirtyPage/Trap", "The number of traps generated for dirty bit tracking.");
PGM_REG_COUNTER(&pPGM->StatR3DirtiedPage, "/PGM/CPU%d/R3/DirtyPage/SetDirty", "The number of pages marked dirty because of write accesses.");
PGM_REG_COUNTER(&pPGM->StatR3DirtyTrackRealPF, "/PGM/CPU%d/R3/DirtyPage/RealPF", "The number of real pages faults during dirty bit tracking.");
PGM_REG_COUNTER(&pPGM->StatR3PageAlreadyDirty, "/PGM/CPU%d/R3/DirtyPage/AlreadySet", "The number of pages already marked dirty because of write accesses.");
PGM_REG_PROFILE(&pPGM->StatR3InvalidatePage, "/PGM/CPU%d/R3/InvalidatePage", "PGMInvalidatePage() profiling.");
PGM_REG_COUNTER(&pPGM->StatR3InvalidatePage4KBPages, "/PGM/CPU%d/R3/InvalidatePage/4KBPages", "The number of times PGMInvalidatePage() was called for a 4KB page.");
PGM_REG_COUNTER(&pPGM->StatR3InvalidatePage4MBPages, "/PGM/CPU%d/R3/InvalidatePage/4MBPages", "The number of times PGMInvalidatePage() was called for a 4MB page.");
PGM_REG_COUNTER(&pPGM->StatR3InvalidatePage4MBPagesSkip, "/PGM/CPU%d/R3/InvalidatePage/4MBPagesSkip","The number of times PGMInvalidatePage() skipped a 4MB page.");
PGM_REG_COUNTER(&pPGM->StatR3InvalidatePagePDMappings, "/PGM/CPU%d/R3/InvalidatePage/PDMappings", "The number of times PGMInvalidatePage() was called for a page directory containing mappings (no conflict).");
PGM_REG_COUNTER(&pPGM->StatR3InvalidatePagePDNAs, "/PGM/CPU%d/R3/InvalidatePage/PDNAs", "The number of times PGMInvalidatePage() was called for a not accessed page directory.");
PGM_REG_COUNTER(&pPGM->StatR3InvalidatePagePDNPs, "/PGM/CPU%d/R3/InvalidatePage/PDNPs", "The number of times PGMInvalidatePage() was called for a not present page directory.");
PGM_REG_COUNTER(&pPGM->StatR3InvalidatePagePDOutOfSync, "/PGM/CPU%d/R3/InvalidatePage/PDOutOfSync", "The number of times PGMInvalidatePage() was called for an out of sync page directory.");
PGM_REG_COUNTER(&pPGM->StatR3InvalidatePageSkipped, "/PGM/CPU%d/R3/InvalidatePage/Skipped", "The number of times PGMInvalidatePage() was skipped due to not present shw or pending pending SyncCR3.");
PGM_REG_COUNTER(&pPGM->StatR3PageOutOfSyncSupervisor, "/PGM/CPU%d/R3/OutOfSync/SuperVisor", "Number of traps due to pages out of sync and times VerifyAccessSyncPage calls SyncPage.");
PGM_REG_COUNTER(&pPGM->StatR3PageOutOfSyncUser, "/PGM/CPU%d/R3/OutOfSync/User", "Number of traps due to pages out of sync and times VerifyAccessSyncPage calls SyncPage.");
PGM_REG_PROFILE(&pPGM->StatR3FlushTLB, "/PGM/CPU%d/R3/FlushTLB", "Profiling of the PGMFlushTLB() body.");
PGM_REG_COUNTER(&pPGM->StatR3FlushTLBNewCR3, "/PGM/CPU%d/R3/FlushTLB/NewCR3", "The number of times PGMFlushTLB was called with a new CR3, non-global. (switch)");
PGM_REG_COUNTER(&pPGM->StatR3FlushTLBNewCR3Global, "/PGM/CPU%d/R3/FlushTLB/NewCR3Global", "The number of times PGMFlushTLB was called with a new CR3, global. (switch)");
PGM_REG_COUNTER(&pPGM->StatR3FlushTLBSameCR3, "/PGM/CPU%d/R3/FlushTLB/SameCR3", "The number of times PGMFlushTLB was called with the same CR3, non-global. (flush)");
PGM_REG_COUNTER(&pPGM->StatR3FlushTLBSameCR3Global, "/PGM/CPU%d/R3/FlushTLB/SameCR3Global", "The number of times PGMFlushTLB was called with the same CR3, global. (flush)");
PGM_REG_PROFILE(&pPGM->StatR3GstModifyPage, "/PGM/CPU%d/R3/GstModifyPage", "Profiling of the PGMGstModifyPage() body.");
#endif /* VBOX_WITH_STATISTICS */
}
}
/**
* Init the PGM bits that rely on VMMR0 and MM to be fully initialized.
*
* The dynamic mapping area will also be allocated and initialized at this
* time. We could allocate it during PGMR3Init of course, but the mapping
* wouldn't be allocated at that time preventing us from setting up the
* page table entries with the dummy page.
*
* @returns VBox status code.
* @param pVM VM handle.
*/
{
int rc;
/*
* Reserve space for the dynamic mappings.
*/
if (RT_SUCCESS(rc))
if ( RT_SUCCESS(rc)
&& (pVM->pgm.s.pbDynPageMapBaseGC >> X86_PD_PAE_SHIFT) != ((pVM->pgm.s.pbDynPageMapBaseGC + MM_HYPER_DYNAMIC_SIZE - 1) >> X86_PD_PAE_SHIFT))
{
if (RT_SUCCESS(rc))
}
if (RT_SUCCESS(rc))
{
AssertRelease((pVM->pgm.s.pbDynPageMapBaseGC >> X86_PD_PAE_SHIFT) == ((pVM->pgm.s.pbDynPageMapBaseGC + MM_HYPER_DYNAMIC_SIZE - 1) >> X86_PD_PAE_SHIFT));
}
return rc;
}
/**
* Ring-3 init finalizing.
*
* @returns VBox status code.
* @param pVM The VM handle.
*/
{
int rc;
/*
* Reserve space for the dynamic mappings.
* Initialize the dynamic mapping pages with dummy pages to simply the cache.
*/
/* get the pointer to the page table entries. */
pVM->pgm.s.paDynPageMap32BitPTEsGC = pMapping->aPTs[iPT].pPTRC + iPG * sizeof(pMapping->aPTs[0].pPTR3->a[0]);
pVM->pgm.s.paDynPageMapPaePTEsGC = pMapping->aPTs[iPT].paPaePTsRC + iPG * sizeof(pMapping->aPTs[0].paPaePTsR3->a[0]);
/* init cache */
for (unsigned i = 0; i < MM_HYPER_DYNAMIC_SIZE; i += PAGE_SIZE)
{
}
/*
* Note that AMD uses all the 8 reserved bits for the address (so 40 bits in total);
* Intel only goes up to 36 bits, so we stick to 36 as well.
*/
/** @todo How to test for the 40 bits support? Long mode seems to be the test criterium. */
else
/*
* Allocate memory if we're supposed to do that.
*/
return rc;
}
/**
* Applies relocations to data and code managed by this component.
*
* This function will be called at init and whenever the VMM need to relocate it
* self inside the GC.
*
* @param pVM The VM.
* @param offDelta Relocation delta relative to old location.
*/
{
LogFlow(("PGMR3Relocate %RGv to %RGv\n", pVM->pgm.s.GCPtrCR3Mapping, pVM->pgm.s.GCPtrCR3Mapping + offDelta));
/*
* Paging stuff.
*/
/* Shadow, guest and both mode switch & relocation for each VCPU. */
{
}
/*
* Trees.
*/
/*
* Ram ranges.
*/
{
/* Update the pSelfRC pointers and relink them. */
}
/*
* Update the pSelfRC pointer of the MMIO2 ram ranges since they might not
* be mapped and thus not included in the above exercise.
*/
/*
* Update the two page directories with all page table mappings.
* (One or more of them have changed, that's why we're here.)
*/
/* Relocate GC addresses of Page Tables. */
{
{
}
}
/*
* Dynamic page mapping area.
*/
/*
* The Zero page.
*/
#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
#else
#endif
/*
* Physical and virtual handlers.
*/
RTAvlroGCPhysDoWithAll(&pVM->pgm.s.pTreesR3->PhysHandlers, true, pgmR3RelocatePhysHandler, &offDelta);
RTAvlroGCPtrDoWithAll(&pVM->pgm.s.pTreesR3->VirtHandlers, true, pgmR3RelocateVirtHandler, &offDelta);
RTAvlroGCPtrDoWithAll(&pVM->pgm.s.pTreesR3->HyperVirtHandlers, true, pgmR3RelocateHyperVirtHandler, &offDelta);
/*
* The page pool.
*/
}
/**
* Callback function for relocating a physical access handler.
*
* @returns 0 (continue enum)
* @param pNode Pointer to a PGMPHYSHANDLER node.
* @param pvUser Pointer to the offDelta. This is a pointer to the delta since we're
* not certain the delta will fit in a void pointer for all possible configs.
*/
{
if (pHandler->pfnHandlerRC)
return 0;
}
/**
* Callback function for relocating a virtual access handler.
*
* @returns 0 (continue enum)
* @param pNode Pointer to a PGMVIRTHANDLER node.
* @param pvUser Pointer to the offDelta. This is a pointer to the delta since we're
* not certain the delta will fit in a void pointer for all possible configs.
*/
{
return 0;
}
/**
* Callback function for relocating a virtual access handler for the hypervisor mapping.
*
* @returns 0 (continue enum)
* @param pNode Pointer to a PGMVIRTHANDLER node.
* @param pvUser Pointer to the offDelta. This is a pointer to the delta since we're
* not certain the delta will fit in a void pointer for all possible configs.
*/
{
return 0;
}
/**
* The VM is being reset.
*
* For the PGM component this means that any PD write monitors
* needs to be removed.
*
* @param pVM VM handle.
*/
{
int rc;
LogFlow(("PGMR3Reset:\n"));
/*
* Unfix any fixed mappings and disable CR3 monitoring.
*/
/* Exit the guest paging mode before the pgm pool gets reset.
* Important to clean up the amd64 case.
*/
{
}
#ifdef DEBUG
#endif
/*
* Switch mode back to real mode. (before resetting the pgm pool!)
*/
{
}
/*
* Reset the shadow page pool.
*/
{
/*
* Re-init other members.
*/
/*
* Clear the FFs PGM owns.
*/
}
/*
* Reset (zero) RAM pages.
*/
if (RT_SUCCESS(rc))
{
/*
* Reset (zero) shadow ROM pages.
*/
}
//return rc;
}
#ifdef VBOX_STRICT
/**
* VM state change callback for clearing fNoMorePhysWrites after
* a snapshot has been created.
*/
static DECLCALLBACK(void) pgmR3ResetNoMorePhysWritesFlag(PVM pVM, VMSTATE enmState, VMSTATE enmOldState, void *pvUser)
{
if (enmState == VMSTATE_RUNNING)
}
#endif
/**
* Terminates the PGM.
*
* @returns VBox status code.
* @param pVM Pointer to VM structure.
*/
{
}
/**
* Terminates the per-VCPU PGM.
*
* Termination means cleaning up and freeing all resources,
* the VM it self is at this point powered off or suspended.
*
* @returns VBox status code.
* @param pVM The VM to operate on.
*/
{
return 0;
}
/**
* Find the ROM tracking structure for the given page.
*
* @returns Pointer to the ROM page structure. NULL if the caller didn't check
* that it's a ROM page.
* @param pVM The VM handle.
* @param GCPhys The address of the ROM page.
*/
{
{
}
return NULL;
}
/**
* Save zero indicator + bits for the specified page.
*
* @param pVM The VM handle.
* @param pSSH The saved state handle.
* @param pPage The page to save.
* @param GCPhys The address of the page.
* @param pRam The ram range (for error logging).
*/
static int pgmR3SavePage(PVM pVM, PSSMHANDLE pSSM, PPGMPAGE pPage, RTGCPHYS GCPhys, PPGMRAMRANGE pRam)
{
int rc;
if (PGM_PAGE_IS_ZERO(pPage))
else
{
void const *pvPage;
AssertLogRelMsgRCReturn(rc, ("pPage=%R[pgmpage] GCPhys=%#x %s\n", pPage, GCPhys, pRam->pszDesc), rc);
}
return rc;
}
/**
* Save a shadowed ROM page.
*
* Format: Type, protection, and two pages with zero indicators.
*
* @param pVM The VM handle.
* @param pSSH The saved state handle.
* @param pPage The page to save.
* @param GCPhys The address of the page.
* @param pRam The ram range (for error logging).
*/
static int pgmR3SaveShadowedRomPage(PVM pVM, PSSMHANDLE pSSM, PPGMPAGE pPage, RTGCPHYS GCPhys, PPGMRAMRANGE pRam)
{
/* Need to save both pages and the current state. */
if (RT_SUCCESS(rc))
{
PPGMPAGE pPagePassive = PGMROMPROT_IS_ROM(pRomPage->enmProt) ? &pRomPage->Shadow : &pRomPage->Virgin;
}
return rc;
}
static const SSMFIELD s_aPGMFields[] =
{
};
static const SSMFIELD s_aPGMCpuFields[] =
{
};
/* For loading old saved states. (pre-smp) */
typedef struct
{
/** If set no conflict checks are required. (boolean) */
bool fMappingsFixed;
/** Size of fixed mapping */
/** Base address (GC) of fixed mapping */
/** A20 gate mask.
* Our current approach to A20 emulation is to let REM do it and don't bother
* anywhere else. The interesting Guests will be operating with it enabled anyway.
* But whould need arrise, we'll subject physical addresses to this mask. */
/** A20 gate state - boolean! */
bool fA20Enabled;
/** The guest paging mode. */
} PGMOLD;
static const SSMFIELD s_aPGMFields_Old[] =
{
};
/**
* Execute state save operation.
*
* @returns VBox status code.
* @param pVM VM Handle.
* @param pSSM SSM operation handle.
*/
{
int rc;
unsigned i;
/*
* Lock PGM and set the no-more-writes indicator.
*/
/*
* Save basic data (required / unaffected by relocation).
*/
{
}
/*
* The guest mappings.
*/
i = 0;
{
SSMR3PutU32( pSSM, i);
}
/*
* Ram ranges and the memory they describe.
*/
i = 0;
{
/*
* Save the ram range details.
*/
SSMR3PutU32(pSSM, i);
/*
* Iterate the pages, only two special case.
*/
{
if (uType == PGMPAGETYPE_ROM_SHADOW)
else if (uType == PGMPAGETYPE_MMIO2_ALIAS_MMIO)
{
/* MMIO2 alias -> MMIO; the device will just have to deal with this. */
}
else
{
}
if (RT_FAILURE(rc))
break;
}
if (RT_FAILURE(rc))
break;
}
}
/**
* Load an ignored page.
*
* @returns VBox status code.
* @param pSSM The saved state handle.
*/
{
}
/**
* Loads a page without any bits in the saved state, i.e. making sure it's
* really zero.
*
* @returns VBox status code.
* @param pVM The VM handle.
* @param uType The page type or PGMPAGETYPE_INVALID (old saved
* state).
* @param pPage The guest page tracking structure.
* @param GCPhys The page address.
* @param pRam The ram range (logging).
*/
static int pgmR3LoadPageZero(PVM pVM, uint8_t uType, PPGMPAGE pPage, RTGCPHYS GCPhys, PPGMRAMRANGE pRam)
{
&& uType != PGMPAGETYPE_INVALID)
return VERR_SSM_UNEXPECTED_DATA;
/* I think this should be sufficient. */
if (!PGM_PAGE_IS_ZERO(pPage))
return VERR_SSM_UNEXPECTED_DATA;
return VINF_SUCCESS;
}
/**
* Loads a page from the saved state.
*
* @returns VBox status code.
* @param pVM The VM handle.
* @param pSSM The SSM handle.
* @param uType The page type or PGMPAGETYEP_INVALID (old saved
* state).
* @param pPage The guest page tracking structure.
* @param GCPhys The page address.
* @param pRam The ram range (logging).
*/
static int pgmR3LoadPageBits(PVM pVM, PSSMHANDLE pSSM, uint8_t uType, PPGMPAGE pPage, RTGCPHYS GCPhys, PPGMRAMRANGE pRam)
{
int rc;
/*
* Match up the type, dealing with MMIO2 aliases (dropped).
*/
|| uType == PGMPAGETYPE_INVALID,
/*
* Load the page.
*/
void *pvPage;
if (RT_SUCCESS(rc))
return rc;
}
/**
* Loads a page (counter part to pgmR3SavePage).
*
* @returns VBox status code, fully bitched errors.
* @param pVM The VM handle.
* @param pSSM The SSM handle.
* @param uType The page type.
* @param pPage The page.
* @param GCPhys The page address.
* @param pRam The RAM range (for error messages).
*/
static int pgmR3LoadPage(PVM pVM, PSSMHANDLE pSSM, uint8_t uType, PPGMPAGE pPage, RTGCPHYS GCPhys, PPGMRAMRANGE pRam)
{
AssertLogRelMsgRCReturn(rc, ("pPage=%R[pgmpage] GCPhys=%#x %s rc=%Rrc\n", pPage, GCPhys, pRam->pszDesc, rc), rc);
if (uState == 0 /* zero */)
else if (uState == 1)
else
rc);
return VINF_SUCCESS;
}
/**
* Loads a shadowed ROM page.
*
* @returns VBox status code, errors are fully bitched.
* @param pVM The VM handle.
* @param pSSM The saved state handle.
* @param pPage The page.
* @param GCPhys The page address.
* @param pRam The RAM range (for error messages).
*/
static int pgmR3LoadShadowedRomPage(PVM pVM, PSSMHANDLE pSSM, PPGMPAGE pPage, RTGCPHYS GCPhys, PPGMRAMRANGE pRam)
{
/*
* Load and set the protection first, then load the two pages, the first
* one is the active the other is the passive.
*/
AssertLogRelMsgRCReturn(rc, ("pPage=%R[pgmpage] GCPhys=%#x %s\n", pPage, GCPhys, pRam->pszDesc), rc);
&& enmProt < PGMROMPROT_END,
{
}
if (RT_SUCCESS(rc))
{
*pPageActive = *pPage;
}
return rc;
}
/**
* Worker for pgmR3Load.
*
* @returns VBox status code.
*
* @param pVM The VM handle.
* @param pSSM The SSM handle.
* @param uVersion The saved state version.
*/
{
int rc;
/*
* Load basic data (required / unaffected by relocation).
*/
if (uVersion >= PGM_SAVED_STATE_VERSION)
{
{
}
}
else if (uVersion >= PGM_SAVED_STATE_VERSION_RR_DESC)
{
}
else
{
if (RT_FAILURE(rc))
return rc;
/* check separator. */
if (RT_FAILURE(rc))
return rc;
{
}
}
/*
* The guest mappings.
*/
uint32_t i = 0;
for (;; i++)
{
/* Check the seqence number / separator. */
if (RT_FAILURE(rc))
return rc;
if (u32Sep == ~0U)
break;
if (u32Sep != i)
{
}
/* get the mapping details. */
char szDesc[256];
szDesc[0] = '\0';
if (RT_FAILURE(rc))
return rc;
if (RT_FAILURE(rc))
return rc;
/* find matching range. */
break;
/* relocate it. */
{
}
else
}
/*
* Ram range flags and bits.
*/
i = 0;
{
/* Check the seqence number / separator. */
if (RT_FAILURE(rc))
return rc;
if (u32Sep == ~0U)
break;
if (u32Sep != i)
{
}
/* Get the range details. */
if (RT_FAILURE(rc))
return rc;
if (fHaveBits & ~1)
{
}
char szDesc[256];
szDesc[0] = '\0';
{
if (RT_FAILURE(rc))
return rc;
/* Since we've modified the description strings in r45878, only compare
them if the saved state is more recent. */
}
/*
* Match it up with the current range.
*
* Note there is a hack for dealing with the high BIOS mapping
* in the old saved state format, this means we might not have
* a 1:1 match on success.
*/
|| ( cchDesc
/* Hack for PDMDevHlpPhysReserve(pDevIns, 0xfff80000, 0x80000, "High ROM Region"); */
|| !fHaveBits)
)
{
LogRel(("Ram range: %RGp-%RGp %RGp bytes %s %s\n"
"State : %RGp-%RGp %RGp bytes %s %s\n",
/*
* If we're loading a state for debugging purpose, don't make a fuss if
* the MMIO and ROM stuff isn't 100% right, just skip the mismatches.
*/
AssertMsgFailed(("debug skipping not implemented, sorry\n"));
continue;
}
{
/*
* Load the pages one by one.
*/
{
AssertLogRelMsgRCReturn(rc, ("pPage=%R[pgmpage] iPage=%#x GCPhysPage=%#x %s\n", pPage, iPage, GCPhysPage, pRam->pszDesc), rc);
if (uType == PGMPAGETYPE_ROM_SHADOW)
else
AssertLogRelMsgRCReturn(rc, ("rc=%Rrc iPage=%#x GCPhysPage=%#x %s\n", rc, iPage, GCPhysPage, pRam->pszDesc), rc);
}
}
else
{
/*
* Old format.
*/
The rest is generally irrelevant and wrong since the stuff have to match registrations. */
{
AssertLogRelMsgRCReturn(rc, ("rc=%Rrc iPage=%#x GCPhys=%#x %s\n", rc, iPage, pRam->GCPhys, pRam->pszDesc), rc);
}
/* Load the bits */
if ( !fHaveBits
{
/*
* Dynamic chunks.
*/
{
AssertLogRelMsgRCReturn(rc, ("rc=%Rrc iPage=%#x GCPhys=%#x %s\n", rc, iPage, pRam->GCPhys, pRam->pszDesc), rc);
{
if (fPresent)
{
else
}
else
AssertLogRelMsgRCReturn(rc, ("rc=%Rrc iPage=%#x GCPhysPage=%#x %s\n", rc, iPage, GCPhysPage, pRam->pszDesc), rc);
}
}
}
{
/*
* MMIO2.
*/
}
{
/*
* PCI MMIO, no pages saved.
*/
}
else
{
/*
* Load the 0xfff80000..0xffffffff BIOS range.
* It starts with X reserved pages that we have to skip over since
* the RAMRANGE create by the new code won't include those.
*/
/* Skip wasted reserved pages before the ROM. */
{
}
/* Load the bios pages. */
{
AssertLogRelMsgRCReturn(rc, ("rc=%Rrc iPage=%#x GCPhys=%#x %s\n", rc, iPage, pRam->GCPhys, pRam->pszDesc), rc);
}
}
}
}
return rc;
}
/**
* Execute state load operation.
*
* @returns VBox status code.
* @param pVM VM Handle.
* @param pSSM SSM operation handle.
* @param uVersion Data layout version.
* @param uPass The data pass.
*/
{
int rc;
/*
* Validate version.
*/
if ( uVersion != PGM_SAVED_STATE_VERSION
{
AssertMsgFailed(("pgmR3Load: Invalid version uVersion=%d (current %d)!\n", uVersion, PGM_SAVED_STATE_VERSION));
}
/*
* Call the reset function to make sure all the memory is cleared.
*/
/*
* Do the loading while owning the lock because a bunch of the functions
* we're using requires this.
*/
if (RT_SUCCESS(rc))
{
/*
* We require a full resync now.
*/
{
}
{
/*
* Change the paging mode.
*/
/* Restore pVM->pgm.s.GCPhysCR3. */
else
}
}
return rc;
}
/**
* Show paging mode.
*
* @param pVM VM Handle.
* @param pHlp The info helpers.
* @param pszArgs "all" (default), "guest", "shadow" or "host".
*/
{
/* digest argument. */
if (pszArgs)
else
{
fGuest = true;
fShadow = true;
fHost = true;
}
/** @todo SMP support! */
/* print info. */
if (fGuest)
if (fShadow)
pHlp->pfnPrintf(pHlp, "Shadow paging mode: %s\n", PGMGetModeName(pVM->aCpus[0].pgm.s.enmShadowMode));
if (fHost)
{
const char *psz;
{
default: psz = "unknown"; break;
}
}
}
/**
* Dump registered MMIO ranges to the log.
*
* @param pVM VM Handle.
* @param pHlp The info helpers.
* @param pszArgs Arguments, ignored.
*/
{
"RAM ranges (pVM=%p)\n"
"%.*s %.*s\n",
pVM,
"%RGp-%RGp %RHv %s\n",
}
/**
* Dump the page directory to the log.
*
* @param pVM VM Handle.
* @param pHlp The info helpers.
* @param pszArgs Arguments, ignored.
*/
{
/** @todo SMP support!! */
/** @todo fix this! Convert the PGMR3DumpHierarchyHC functions to do guest stuff. */
/* Big pages supported? */
/* Global pages supported? */
/*
* Get page directory addresses.
*/
Assert(PGMPhysGCPhys2R3PtrAssert(pVM, (RTGCPHYS)(CPUMGetGuestCR3(pVCpu) & X86_CR3_PAGE_MASK), sizeof(*pPDSrc)) == pPDSrc);
/*
* Iterate the page directory.
*/
{
{
"%04X - %RGp P=%d U=%d RW=%d G=%d - BIG\n",
iPD,
else
"%04X - %RGp P=%d U=%d RW=%d [G=%d]\n",
iPD,
}
}
}
/**
* Service a VMMCALLRING3_PGM_LOCK call.
*
* @returns VBox status code.
* @param pVM The VM handle.
*/
{
return rc;
}
/**
* Converts a PGMMODE value to a PGM_TYPE_* \#define.
*
* @returns PGM_TYPE_*.
* @param pgmMode The mode value to convert.
*/
{
switch (pgmMode)
{
case PGMMODE_REAL: return PGM_TYPE_REAL;
case PGMMODE_PROTECTED: return PGM_TYPE_PROT;
case PGMMODE_32_BIT: return PGM_TYPE_32BIT;
case PGMMODE_PAE:
case PGMMODE_PAE_NX: return PGM_TYPE_PAE;
case PGMMODE_AMD64:
case PGMMODE_AMD64_NX: return PGM_TYPE_AMD64;
case PGMMODE_NESTED: return PGM_TYPE_NESTED;
case PGMMODE_EPT: return PGM_TYPE_EPT;
default:
}
}
/**
* Gets the index into the paging mode data array of a SHW+GST mode.
*
* @returns PGM::paPagingData index.
* @param uShwType The shadow paging mode type.
* @param uGstType The guest paging mode type.
*/
{
+ (uGstType - PGM_TYPE_REAL);
}
/**
* Gets the index into the paging mode data array of a SHW+GST mode.
*
* @returns PGM::paPagingData index.
* @param enmShw The shadow paging mode.
* @param enmGst The guest paging mode.
*/
{
}
/**
* Calculates the max data index.
* @returns The number of entries in the paging data array.
*/
DECLINLINE(unsigned) pgmModeDataMaxIndex(void)
{
}
/**
* Initializes the paging mode data kept in PGM::paModeData.
*
* @param pVM The VM handle.
* @param fResolveGCAndR0 Indicate whether or not GC and Ring-0 symbols can be resolved now.
* This is used early in the init process to avoid trouble with PDM
* not being initialized yet.
*/
{
int rc;
/*
* Allocate the array on the first call.
*/
{
pVM->pgm.s.paModeData = (PPGMMODEDATA)MMR3HeapAllocZ(pVM, MM_TAG_PGM, sizeof(PGMMODEDATA) * pgmModeDataMaxIndex());
}
/*
* Initialize the array entries.
*/
#ifdef VBOX_WITH_64_BITS_GUESTS
#endif
/* The nested paging mode. */
#ifdef VBOX_WITH_64_BITS_GUESTS
#endif
/* The shadow part of the nested callback mode depends on the host paging mode (AMD-V only). */
{
#if HC_ARCH_BITS == 32
case SUPPAGINGMODE_32_BIT:
for (unsigned i = PGM_TYPE_REAL; i <= PGM_TYPE_PAE; i++)
{
}
# ifdef VBOX_WITH_64_BITS_GUESTS
# endif
break;
case SUPPAGINGMODE_PAE:
case SUPPAGINGMODE_PAE_NX:
case SUPPAGINGMODE_PAE_GLOBAL:
for (unsigned i = PGM_TYPE_REAL; i <= PGM_TYPE_PAE; i++)
{
}
# ifdef VBOX_WITH_64_BITS_GUESTS
# endif
break;
#endif /* HC_ARCH_BITS == 32 */
case SUPPAGINGMODE_AMD64:
case SUPPAGINGMODE_AMD64_NX:
# ifdef VBOX_WITH_64_BITS_GUESTS
for (unsigned i = PGM_TYPE_REAL; i <= PGM_TYPE_AMD64; i++)
# else
for (unsigned i = PGM_TYPE_REAL; i <= PGM_TYPE_PAE; i++)
# endif
{
}
break;
#endif /* HC_ARCH_BITS == 64 || RT_OS_DARWIN */
default:
AssertFailed();
break;
}
/* Extended paging (EPT) / Intel VT-x */
#ifdef VBOX_WITH_64_BITS_GUESTS
#endif
return VINF_SUCCESS;
}
/**
* Switch to different (or relocated in the relocate case) mode data.
*
* @param pVM The VM handle.
* @param pVCpu The VMCPU to operate on.
* @param enmShw The the shadow paging mode.
* @param enmGst The the guest paging mode.
*/
{
/* shadow */
/* guest */
/* both */
#ifdef VBOX_STRICT
#endif
#ifdef VBOX_STRICT
#endif
#ifdef VBOX_STRICT
#endif
}
/**
* Calculates the shadow paging mode.
*
* @returns The shadow paging mode.
* @param pVM VM handle.
* @param enmGuestMode The guest mode.
* @param enmHostMode The host mode.
* @param enmShadowMode The current shadow mode.
* @param penmSwitcher Where to store the switcher to use.
* VMMSWITCHER_INVALID means no change.
*/
static PGMMODE pgmR3CalcShadowMode(PVM pVM, PGMMODE enmGuestMode, SUPPAGINGMODE enmHostMode, PGMMODE enmShadowMode, VMMSWITCHER *penmSwitcher)
{
switch (enmGuestMode)
{
/*
* When switching to real or protected mode we don't change
* anything since it's likely that we'll switch back pretty soon.
*
* During pgmR3InitPaging we'll end up here with PGMMODE_INVALID
* and is supposed to determine which shadow paging and switcher to
* use during init.
*/
case PGMMODE_REAL:
case PGMMODE_PROTECTED:
if ( enmShadowMode != PGMMODE_INVALID
break; /* (no change) */
switch (enmHostMode)
{
case SUPPAGINGMODE_32_BIT:
break;
case SUPPAGINGMODE_PAE:
case SUPPAGINGMODE_PAE_NX:
case SUPPAGINGMODE_PAE_GLOBAL:
#ifdef DEBUG_bird
if (RTEnvExist("VBOX_32BIT"))
{
}
#endif
break;
case SUPPAGINGMODE_AMD64:
case SUPPAGINGMODE_AMD64_NX:
#ifdef DEBUG_bird
if (RTEnvExist("VBOX_32BIT"))
{
}
#endif
break;
}
break;
case PGMMODE_32_BIT:
switch (enmHostMode)
{
case SUPPAGINGMODE_32_BIT:
break;
case SUPPAGINGMODE_PAE:
case SUPPAGINGMODE_PAE_NX:
case SUPPAGINGMODE_PAE_GLOBAL:
#ifdef DEBUG_bird
if (RTEnvExist("VBOX_32BIT"))
{
}
#endif
break;
case SUPPAGINGMODE_AMD64:
case SUPPAGINGMODE_AMD64_NX:
#ifdef DEBUG_bird
if (RTEnvExist("VBOX_32BIT"))
{
}
#endif
break;
}
break;
case PGMMODE_PAE:
case PGMMODE_PAE_NX: /** @todo This might require more switchers and guest+both modes. */
switch (enmHostMode)
{
case SUPPAGINGMODE_32_BIT:
break;
case SUPPAGINGMODE_PAE:
case SUPPAGINGMODE_PAE_NX:
case SUPPAGINGMODE_PAE_GLOBAL:
break;
case SUPPAGINGMODE_AMD64:
case SUPPAGINGMODE_AMD64_NX:
break;
}
break;
case PGMMODE_AMD64:
case PGMMODE_AMD64_NX:
switch (enmHostMode)
{
case SUPPAGINGMODE_32_BIT:
break;
case SUPPAGINGMODE_PAE:
case SUPPAGINGMODE_PAE_NX:
case SUPPAGINGMODE_PAE_GLOBAL:
break;
case SUPPAGINGMODE_AMD64:
case SUPPAGINGMODE_AMD64_NX:
break;
}
break;
default:
return PGMMODE_INVALID;
}
/* Override the shadow mode is nested paging is active. */
return enmShadowMode;
}
/**
* Performs the actual mode change.
* This is called by PGMChangeMode and pgmR3InitPaging().
*
* @returns VBox status code. May suspend or power off the VM on error, but this
* will trigger using FFs and not status codes.
*
* @param pVM VM handle.
* @param pVCpu The VMCPU to operate on.
* @param enmGuestMode The new guest mode. This is assumed to be different from
* the current mode.
*/
{
Log(("PGMR3ChangeMode: Guest mode: %s -> %s\n", PGMGetModeName(pVCpu->pgm.s.enmGuestMode), PGMGetModeName(enmGuestMode)));
/*
* Calc the shadow mode and switcher.
*/
PGMMODE enmShadowMode = pgmR3CalcShadowMode(pVM, enmGuestMode, pVM->pgm.s.enmHostMode, pVCpu->pgm.s.enmShadowMode, &enmSwitcher);
if (enmSwitcher != VMMSWITCHER_INVALID)
{
/*
* Select new switcher.
*/
if (RT_FAILURE(rc))
{
return rc;
}
}
/*
* Exit old mode(s).
*/
/* shadow */
{
LogFlow(("PGMR3ChangeMode: Shadow mode: %s -> %s\n", PGMGetModeName(pVCpu->pgm.s.enmShadowMode), PGMGetModeName(enmShadowMode)));
{
if (RT_FAILURE(rc))
{
return rc;
}
}
}
else
LogFlow(("PGMR3ChangeMode: Shadow mode remains: %s\n", PGMGetModeName(pVCpu->pgm.s.enmShadowMode)));
/* guest */
{
if (RT_FAILURE(rc))
{
return rc;
}
}
/*
* Load new paging mode data.
*/
/*
* Enter new shadow mode (if changed).
*/
{
int rc;
switch (enmShadowMode)
{
case PGMMODE_32_BIT:
break;
case PGMMODE_PAE:
case PGMMODE_PAE_NX:
break;
case PGMMODE_AMD64:
case PGMMODE_AMD64_NX:
break;
case PGMMODE_NESTED:
break;
case PGMMODE_EPT:
break;
case PGMMODE_REAL:
case PGMMODE_PROTECTED:
default:
return VERR_INTERNAL_ERROR;
}
if (RT_FAILURE(rc))
{
return rc;
}
}
/*
* Always flag the necessary updates
*/
/*
* Enter the new guest and shadow+guest modes.
*/
int rc = -1;
int rc2 = -1;
switch (enmGuestMode)
{
case PGMMODE_REAL:
{
case PGMMODE_32_BIT:
break;
case PGMMODE_PAE:
case PGMMODE_PAE_NX:
break;
case PGMMODE_NESTED:
break;
case PGMMODE_EPT:
break;
case PGMMODE_AMD64:
case PGMMODE_AMD64_NX:
AssertMsgFailed(("Should use PAE shadow mode!\n"));
default: AssertFailed(); break;
}
break;
case PGMMODE_PROTECTED:
{
case PGMMODE_32_BIT:
break;
case PGMMODE_PAE:
case PGMMODE_PAE_NX:
break;
case PGMMODE_NESTED:
break;
case PGMMODE_EPT:
break;
case PGMMODE_AMD64:
case PGMMODE_AMD64_NX:
AssertMsgFailed(("Should use PAE shadow mode!\n"));
default: AssertFailed(); break;
}
break;
case PGMMODE_32_BIT:
{
case PGMMODE_32_BIT:
break;
case PGMMODE_PAE:
case PGMMODE_PAE_NX:
break;
case PGMMODE_NESTED:
break;
case PGMMODE_EPT:
break;
case PGMMODE_AMD64:
case PGMMODE_AMD64_NX:
AssertMsgFailed(("Should use PAE shadow mode!\n"));
default: AssertFailed(); break;
}
break;
case PGMMODE_PAE_NX:
case PGMMODE_PAE:
{
if (!(u32Features & X86_CPUID_FEATURE_EDX_PAE))
N_("The guest is trying to switch to the PAE mode which is currently disabled by default in VirtualBox. PAE support can be enabled using the VM settings (General/Advanced)"));
{
case PGMMODE_PAE:
case PGMMODE_PAE_NX:
break;
case PGMMODE_NESTED:
break;
case PGMMODE_EPT:
break;
case PGMMODE_32_BIT:
case PGMMODE_AMD64:
case PGMMODE_AMD64_NX:
AssertMsgFailed(("Should use PAE shadow mode!\n"));
default: AssertFailed(); break;
}
break;
}
#ifdef VBOX_WITH_64_BITS_GUESTS
case PGMMODE_AMD64_NX:
case PGMMODE_AMD64:
{
case PGMMODE_AMD64:
case PGMMODE_AMD64_NX:
break;
case PGMMODE_NESTED:
break;
case PGMMODE_EPT:
break;
case PGMMODE_32_BIT:
case PGMMODE_PAE:
case PGMMODE_PAE_NX:
AssertMsgFailed(("Should use AMD64 shadow mode!\n"));
default: AssertFailed(); break;
}
break;
#endif
default:
break;
}
/* status codes. */
if (RT_SUCCESS(rc))
{
rc = VINF_SUCCESS;
}
/* Notify HWACCM as well. */
return rc;
}
/**
* Release the pgm lock if owned by the current VCPU
*
* @param pVM The VM to operate on.
*/
{
}
/**
* Called by pgmPoolFlushAllInt prior to flushing the pool.
*
* @returns VBox status code, fully asserted.
* @param pVM The VM handle.
* @param pVCpu The VMCPU to operate on.
*/
{
/* Unmap the old CR3 value before flushing everything. */
/* Exit the current shadow paging mode as well; nested paging and EPT use a root CR3 which will get flushed here. */
return rc;
}
/**
* Called by pgmPoolFlushAllInt after flushing the pool.
*
* @returns VBox status code, fully asserted.
* @param pVM The VM handle.
* @param pVCpu The VMCPU to operate on.
*/
{
("%RHp != %RHp %s\n", (RTHCPHYS)CPUMGetHyperCR3(pVCpu), PGMGetHyperCR3(pVCpu), PGMGetModeName(pVCpu->pgm.s.enmShadowMode)));
return rc;
}
/**
* Dumps a PAE shadow page table.
*
* @returns VBox status code (VINF_SUCCESS).
* @param pVM The VM handle.
* @param pPT Pointer to the page table.
* @param u64Address The virtual address of the page table starts.
* @param fLongMode Set if this a long mode table; clear if it's a legacy mode table.
* @param cMaxDepth The maxium depth.
* @param pHlp Pointer to the output functions.
*/
static int pgmR3DumpHierarchyHCPaePT(PVM pVM, PX86PTPAE pPT, uint64_t u64Address, bool fLongMode, unsigned cMaxDepth, PCDBGFINFOHLP pHlp)
{
for (unsigned i = 0; i < RT_ELEMENTS(pPT->a); i++)
{
{
fLongMode /*P R S A D G WT CD AT NX 4M a p ? */
? "%016llx 3 | P %c %c %c %c %c %s %s %s %s 4K %c%c%c %016llx\n"
: "%08llx 2 | P %c %c %c %c %c %s %s %s %s 4K %c%c%c %016llx\n",
Pte.u & X86_PTE_PAE_PG_MASK);
}
}
return VINF_SUCCESS;
}
/**
* Dumps a PAE shadow page directory table.
*
* @returns VBox status code (VINF_SUCCESS).
* @param pVM The VM handle.
* @param HCPhys The physical address of the page directory table.
* @param u64Address The virtual address of the page table starts.
* @param cr4 The CR4, PSE is currently used.
* @param fLongMode Set if this a long mode table; clear if it's a legacy mode table.
* @param cMaxDepth The maxium depth.
* @param pHlp Pointer to the output functions.
*/
static int pgmR3DumpHierarchyHCPaePD(PVM pVM, RTHCPHYS HCPhys, uint64_t u64Address, uint32_t cr4, bool fLongMode, unsigned cMaxDepth, PCDBGFINFOHLP pHlp)
{
if (!pPD)
{
pHlp->pfnPrintf(pHlp, "%0*llx error! Page directory at HCPhys=%RHp was not found in the page pool!\n",
return VERR_INVALID_PARAMETER;
}
int rc = VINF_SUCCESS;
for (unsigned i = 0; i < RT_ELEMENTS(pPD->a); i++)
{
{
fLongMode /*P R S A D G WT CD AT NX 4M a p ? */
? "%016llx 2 | P %c %c %c %c %c %s %s %s %s 4M %c%c%c %016llx\n"
: "%08llx 1 | P %c %c %c %c %c %s %s %s %s 4M %c%c%c %016llx\n",
Pde.u & X86_PDE_PAE_PG_MASK);
else
{
fLongMode /*P R S A D G WT CD AT NX 4M a p ? */
? "%016llx 2 | P %c %c %c %c %c %s %s .. %s 4K %c%c%c %016llx\n"
: "%08llx 1 | P %c %c %c %c %c %s %s .. %s 4K %c%c%c %016llx\n",
Pde.u & X86_PDE_PAE_PG_MASK);
if (cMaxDepth >= 1)
{
/** @todo what about using the page pool for mapping PTs? */
if (!(Pde.u & PGM_PDFLAGS_MAPPING))
else
{
{
{
pHlp->pfnPrintf(pHlp, "%0*llx error! Mapping error! PT %d has HCPhysPT=%RHp not %RHp is in the PD.\n",
}
}
}
int rc2 = VERR_INVALID_PARAMETER;
if (pPT)
else
}
}
}
}
return rc;
}
/**
* Dumps a PAE shadow page directory pointer table.
*
* @returns VBox status code (VINF_SUCCESS).
* @param pVM The VM handle.
* @param HCPhys The physical address of the page directory pointer table.
* @param u64Address The virtual address of the page table starts.
* @param cr4 The CR4, PSE is currently used.
* @param fLongMode Set if this a long mode table; clear if it's a legacy mode table.
* @param cMaxDepth The maxium depth.
* @param pHlp Pointer to the output functions.
*/
static int pgmR3DumpHierarchyHCPaePDPT(PVM pVM, RTHCPHYS HCPhys, uint64_t u64Address, uint32_t cr4, bool fLongMode, unsigned cMaxDepth, PCDBGFINFOHLP pHlp)
{
if (!pPDPT)
{
pHlp->pfnPrintf(pHlp, "%0*llx error! Page directory pointer table at HCPhys=%RHp was not found in the page pool!\n",
return VERR_INVALID_PARAMETER;
}
int rc = VINF_SUCCESS;
for (unsigned i = 0; i < c; i++)
{
{
if (fLongMode)
"%016llx 1 | P %c %c %c %c %c %s %s %s %s .. %c%c%c %016llx\n",
Pdpe.u & X86_PDPE_PG_MASK);
else
"%08x 0 | P %c %s %s %s %s .. %c%c%c %016llx\n",
i << X86_PDPT_SHIFT,
Pdpe.u & X86_PDPE_PG_MASK);
if (cMaxDepth >= 1)
{
int rc2 = pgmR3DumpHierarchyHCPaePD(pVM, Pdpe.u & X86_PDPE_PG_MASK, u64Address + ((uint64_t)i << X86_PDPT_SHIFT),
}
}
}
return rc;
}
/**
* Dumps a 32-bit shadow page table.
*
* @returns VBox status code (VINF_SUCCESS).
* @param pVM The VM handle.
* @param HCPhys The physical address of the table.
* @param cr4 The CR4, PSE is currently used.
* @param cMaxDepth The maxium depth.
* @param pHlp Pointer to the output functions.
*/
static int pgmR3DumpHierarchyHcPaePML4(PVM pVM, RTHCPHYS HCPhys, uint32_t cr4, unsigned cMaxDepth, PCDBGFINFOHLP pHlp)
{
if (!pPML4)
{
return VERR_INVALID_PARAMETER;
}
int rc = VINF_SUCCESS;
for (unsigned i = 0; i < RT_ELEMENTS(pPML4->a); i++)
{
{
uint64_t u64Address = ((uint64_t)i << X86_PML4_SHIFT) | (((uint64_t)i >> (X86_PML4_SHIFT - X86_PDPT_SHIFT - 1)) * 0xffff000000000000ULL);
"%016llx 0 | P %c %c %c %c %c %s %s %s %s .. %c%c%c %016llx\n",
Pml4e.u & X86_PML4E_PG_MASK);
if (cMaxDepth >= 1)
{
int rc2 = pgmR3DumpHierarchyHCPaePDPT(pVM, Pml4e.u & X86_PML4E_PG_MASK, u64Address, cr4, true, cMaxDepth - 1, pHlp);
}
}
}
return rc;
}
/**
* Dumps a 32-bit shadow page table.
*
* @returns VBox status code (VINF_SUCCESS).
* @param pVM The VM handle.
* @param pPT Pointer to the page table.
* @param u32Address The virtual address this table starts at.
* @param pHlp Pointer to the output functions.
*/
{
for (unsigned i = 0; i < RT_ELEMENTS(pPT->a); i++)
{
{
"%08x 1 | P %c %c %c %c %c %s %s %s .. 4K %c%c%c %08x\n",
u32Address + (i << X86_PT_SHIFT),
Pte.u & X86_PDE_PG_MASK);
}
}
return VINF_SUCCESS;
}
/**
* Dumps a 32-bit shadow page directory and page tables.
*
* @returns VBox status code (VINF_SUCCESS).
* @param pVM The VM handle.
* @param cr3 The root of the hierarchy.
* @param cr4 The CR4, PSE is currently used.
* @param cMaxDepth How deep into the hierarchy the dumper should go.
* @param pHlp Pointer to the output functions.
*/
int pgmR3DumpHierarchyHC32BitPD(PVM pVM, uint32_t cr3, uint32_t cr4, unsigned cMaxDepth, PCDBGFINFOHLP pHlp)
{
if (!pPD)
{
pHlp->pfnPrintf(pHlp, "Page directory at %#x was not found in the page pool!\n", cr3 & X86_CR3_PAGE_MASK);
return VERR_INVALID_PARAMETER;
}
int rc = VINF_SUCCESS;
for (unsigned i = 0; i < RT_ELEMENTS(pPD->a); i++)
{
{
"%08x 0 | P %c %c %c %c %c %s %s %s .. 4M %c%c%c %08x\n",
Pde.u & X86_PDE4M_PG_MASK);
else
{
"%08x 0 | P %c %c %c %c %c %s %s .. .. 4K %c%c%c %08x\n",
Pde.u & X86_PDE_PG_MASK);
if (cMaxDepth >= 1)
{
/** @todo what about using the page pool for mapping PTs? */
if (!(Pde.u & PGM_PDFLAGS_MAPPING))
else
{
{
pHlp->pfnPrintf(pHlp, "%08x error! Mapping error! PT %d has HCPhysPT=%RHp not %RHp is in the PD.\n",
}
}
int rc2 = VERR_INVALID_PARAMETER;
if (pPT)
else
pHlp->pfnPrintf(pHlp, "%08x error! Page table at %#x was not found in the page pool!\n", u32Address, HCPhys);
}
}
}
}
return rc;
}
/**
* Dumps a 32-bit shadow page table.
*
* @returns VBox status code (VINF_SUCCESS).
* @param pVM The VM handle.
* @param pPT Pointer to the page table.
* @param u32Address The virtual address this table starts at.
* @param PhysSearch Address to search for.
*/
{
for (unsigned i = 0; i < RT_ELEMENTS(pPT->a); i++)
{
{
Log(( /*P R S A D G WT CD AT NX 4M a m d */
"%08x 1 | P %c %c %c %c %c %s %s %s .. 4K %c%c%c %08x\n",
u32Address + (i << X86_PT_SHIFT),
Pte.u & X86_PDE_PG_MASK));
{
/** @todo SMP support!! */
Log(("Found %RGp at %RGv -> flags=%llx\n", PhysSearch, (RTGCPTR)(u32Address + (i << X86_PT_SHIFT)), fPageShw));
}
}
}
return VINF_SUCCESS;
}
/**
* Dumps a 32-bit guest page directory and page tables.
*
* @returns VBox status code (VINF_SUCCESS).
* @param pVM The VM handle.
* @param cr3 The root of the hierarchy.
* @param cr4 The CR4, PSE is currently used.
* @param PhysSearch Address to search for.
*/
{
bool fLongMode = false;
{
return VERR_INVALID_PARAMETER;
}
Log(("cr3=%08x cr4=%08x%s\n"
"%-*s P - Present\n"
"%-*s | R/W - Read (0) / Write (1)\n"
"%-*s | | U/S - User (1) / Supervisor (0)\n"
"%-*s | | | A - Accessed\n"
"%-*s | | | | D - Dirty\n"
"%-*s | | | | | G - Global\n"
"%-*s | | | | | | WT - Write thru\n"
"%-*s | | | | | | | CD - Cache disable\n"
"%-*s | | | | | | | | AT - Attribute table (PAT)\n"
"%-*s | | | | | | | | | NX - No execute (K8)\n"
"%-*s | | | | | | | | | | 4K/4M/2M - Page size.\n"
"%-*s | | | | | | | | | | | AVL - a=allocated; m=mapping; d=track dirty;\n"
"%-*s | | | | | | | | | | | | p=permanent; v=validated;\n"
"%-*s Level | | | | | | | | | | | | Page\n"
/* xxxx n **** P R S A D G WT CD AT NX 4M AVL xxxxxxxxxxxxx
- W U - - - -- -- -- -- -- 010 */
for (unsigned i = 0; i < RT_ELEMENTS(pPD->a); i++)
{
{
Log(( /*P R S A D G WT CD AT NX 4M a m d */
"%08x 0 | P %c %c %c %c %c %s %s %s .. 4M %c%c%c %08x\n",
/** @todo PhysSearch */
else
{
Log(( /*P R S A D G WT CD AT NX 4M a m d */
"%08x 0 | P %c %c %c %c %c %s %s .. .. 4K %c%c%c %08x\n",
Pde.u & X86_PDE_PG_MASK));
////if (cMaxDepth >= 1)
{
/** @todo what about using the page pool for mapping PTs? */
int rc2 = VERR_INVALID_PARAMETER;
if (pPT)
else
}
}
}
}
return rc;
}
/**
*
* @returns VBox status code (VINF_SUCCESS).
* @param pVM The VM handle.
* @param cr3 The root of the hierarchy.
* @param cr4 The cr4, only PAE and PSE is currently used.
* @param fLongMode Set if long mode, false if not long mode.
* @param cMaxDepth Number of levels to dump.
* @param pHlp Pointer to the output functions.
*/
VMMR3DECL(int) PGMR3DumpHierarchyHC(PVM pVM, uint64_t cr3, uint64_t cr4, bool fLongMode, unsigned cMaxDepth, PCDBGFINFOHLP pHlp)
{
if (!pHlp)
pHlp = DBGFR3InfoLogHlp();
if (!cMaxDepth)
return VINF_SUCCESS;
"cr3=%08x cr4=%08x%s\n"
"%-*s P - Present\n"
"%-*s | R/W - Read (0) / Write (1)\n"
"%-*s | | U/S - User (1) / Supervisor (0)\n"
"%-*s | | | A - Accessed\n"
"%-*s | | | | D - Dirty\n"
"%-*s | | | | | G - Global\n"
"%-*s | | | | | | WT - Write thru\n"
"%-*s | | | | | | | CD - Cache disable\n"
"%-*s | | | | | | | | AT - Attribute table (PAT)\n"
"%-*s | | | | | | | | | NX - No execute (K8)\n"
"%-*s | | | | | | | | | | 4K/4M/2M - Page size.\n"
"%-*s | | | | | | | | | | | AVL - a=allocated; m=mapping; d=track dirty;\n"
"%-*s | | | | | | | | | | | | p=permanent; v=validated;\n"
"%-*s Level | | | | | | | | | | | | Page\n"
/* xxxx n **** P R S A D G WT CD AT NX 4M AVL xxxxxxxxxxxxx
- W U - - - -- -- -- -- -- 010 */
if (cr4 & X86_CR4_PAE)
{
if (fLongMode)
return pgmR3DumpHierarchyHCPaePDPT(pVM, cr3 & X86_CR3_PAE_PAGE_MASK, 0, cr4, false, cMaxDepth, pHlp);
}
}
#ifdef VBOX_WITH_DEBUGGER
/**
* The '.pgmram' command.
*
* @returns VBox status.
* @param pCmd Pointer to the command descriptor (as registered).
* @param pCmdHlp Pointer to command helper functions.
* @param pVM Pointer to the current VM (if any).
* @param paArgs Pointer to (readonly) array of arguments.
* @param cArgs Number of arguments in the array.
*/
static DECLCALLBACK(int) pgmR3CmdRam(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult)
{
/*
* Validate input.
*/
if (!pVM)
/*
* Dump the ranges.
*/
{
"%RGp - %RGp %p\n",
if (RT_FAILURE(rc))
return rc;
}
return VINF_SUCCESS;
}
/**
* The '.pgmmap' command.
*
* @returns VBox status.
* @param pCmd Pointer to the command descriptor (as registered).
* @param pCmdHlp Pointer to command helper functions.
* @param pVM Pointer to the current VM (if any).
* @param paArgs Pointer to (readonly) array of arguments.
* @param cArgs Number of arguments in the array.
*/
static DECLCALLBACK(int) pgmR3CmdMap(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult)
{
/*
* Validate input.
*/
if (!pVM)
/*
* Print message about the fixedness of the mappings.
*/
int rc = pCmdHlp->pfnPrintf(pCmdHlp, NULL, pVM->pgm.s.fMappingsFixed ? "The mappings are FIXED.\n" : "The mappings are FLOATING.\n");
if (RT_FAILURE(rc))
return rc;
/*
* Dump the ranges.
*/
{
"%08x - %08x %s\n",
if (RT_FAILURE(rc))
return rc;
}
return VINF_SUCCESS;
}
/**
* The '.pgmerror' and '.pgmerroroff' commands.
*
* @returns VBox status.
* @param pCmd Pointer to the command descriptor (as registered).
* @param pCmdHlp Pointer to command helper functions.
* @param pVM Pointer to the current VM (if any).
* @param paArgs Pointer to (readonly) array of arguments.
* @param cArgs Number of arguments in the array.
*/
static DECLCALLBACK(int) pgmR3CmdError(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult)
{
/*
* Validate input.
*/
if (!pVM)
if (!cArgs)
{
/*
* Print the list of error injection locations with status.
*/
}
else
{
/*
* String switch on where to inject the error.
*/
else
}
return VINF_SUCCESS;
}
/**
* The '.pgmsync' command.
*
* @returns VBox status.
* @param pCmd Pointer to the command descriptor (as registered).
* @param pCmdHlp Pointer to command helper functions.
* @param pVM Pointer to the current VM (if any).
* @param paArgs Pointer to (readonly) array of arguments.
* @param cArgs Number of arguments in the array.
*/
static DECLCALLBACK(int) pgmR3CmdSync(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult)
{
/** @todo SMP support */
/*
* Validate input.
*/
if (!pVM)
/*
* Force page directory sync.
*/
if (RT_FAILURE(rc))
return rc;
return VINF_SUCCESS;
}
#ifdef VBOX_STRICT
/**
* The '.pgmassertcr3' command.
*
* @returns VBox status.
* @param pCmd Pointer to the command descriptor (as registered).
* @param pCmdHlp Pointer to command helper functions.
* @param pVM Pointer to the current VM (if any).
* @param paArgs Pointer to (readonly) array of arguments.
* @param cArgs Number of arguments in the array.
*/
static DECLCALLBACK(int) pgmR3CmdAssertCR3(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult)
{
/** @todo SMP support!! */
/*
* Validate input.
*/
if (!pVM)
if (RT_FAILURE(rc))
return rc;
return VINF_SUCCESS;
}
#endif /* VBOX_STRICT */
/**
* The '.pgmsyncalways' command.
*
* @returns VBox status.
* @param pCmd Pointer to the command descriptor (as registered).
* @param pCmdHlp Pointer to command helper functions.
* @param pVM Pointer to the current VM (if any).
* @param paArgs Pointer to (readonly) array of arguments.
* @param cArgs Number of arguments in the array.
*/
static DECLCALLBACK(int) pgmR3CmdSyncAlways(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult)
{
/** @todo SMP support!! */
/*
* Validate input.
*/
if (!pVM)
/*
* Force page directory sync.
*/
{
}
else
{
}
}
/**
* The '.pgmsyncalways' command.
*
* @returns VBox status.
* @param pCmd Pointer to the command descriptor (as registered).
* @param pCmdHlp Pointer to command helper functions.
* @param pVM Pointer to the current VM (if any).
* @param paArgs Pointer to (readonly) array of arguments.
* @param cArgs Number of arguments in the array.
*/
static DECLCALLBACK(int) pgmR3CmdPhysToFile(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult)
{
/*
* Validate input.
*/
if (!pVM)
if ( cArgs < 1
|| cArgs > 2
|| ( cArgs > 1
if ( cArgs >= 2
return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: Invalid 2nd argument '%s', must be 'nozero'.\n", paArgs[1].u.pszString);
/*
* Open the output file and get the ram parameters.
*/
int rc = RTFileOpen(&hFile, paArgs[0].u.pszString, RTFILE_O_WRITE | RTFILE_O_CREATE_REPLACE | RTFILE_O_DENY_WRITE);
if (RT_FAILURE(rc))
return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: RTFileOpen(,'%s',) -> %Rrc.\n", paArgs[0].u.pszString, rc);
/*
* Dump the physical memory, page by page.
*/
{
/* fill the gap */
{
{
}
}
{
if (PGM_PAGE_IS_ZERO(pPage))
{
if (fIncZeroPgs)
{
if (RT_FAILURE(rc))
}
}
else
{
switch (PGM_PAGE_GET_TYPE(pPage))
{
case PGMPAGETYPE_RAM:
case PGMPAGETYPE_ROM_SHADOW: /* trouble?? */
case PGMPAGETYPE_ROM:
case PGMPAGETYPE_MMIO2:
{
void const *pvPage;
if (RT_SUCCESS(rc))
{
if (RT_FAILURE(rc))
}
else
pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: PGMPhysGCPhys2CCPtrReadOnly -> %Rrc at GCPhys=%RGp.\n", rc, GCPhys);
break;
}
default:
AssertFailed();
case PGMPAGETYPE_MMIO:
if (fIncZeroPgs)
{
if (RT_FAILURE(rc))
}
break;
}
}
/* advance */
pPage++;
}
}
if (RT_SUCCESS(rc))
return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "Successfully saved physical memory to '%s'.\n", paArgs[0].u.pszString);
return VINF_SUCCESS;
}
#endif /* VBOX_WITH_DEBUGGER */
/**
* pvUser argument of the pgmR3CheckIntegrity*Node callbacks.
*/
typedef struct PGMCHECKINTARGS
{
bool fLeftToRight; /**< true: left-to-right; false: right-to-left. */
/**
* Validate a node in the physical handler tree.
*
* @returns 0 on if ok, other wise 1.
* @param pNode The handler node.
* @param pvUser pVM.
*/
static DECLCALLBACK(int) pgmR3CheckIntegrityPhysHandlerNode(PAVLROGCPHYSNODECORE pNode, void *pvUser)
{
AssertReleaseMsg(pCur->Core.Key <= pCur->Core.KeyLast,("pCur=%p %RGp-%RGp %s\n", pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->pszDesc));
|| (pArgs->fLeftToRight ? pArgs->pPrevPhys->Core.KeyLast < pCur->Core.Key : pArgs->pPrevPhys->Core.KeyLast > pCur->Core.Key),
("pPrevPhys=%p %RGp-%RGp %s\n"
" pCur=%p %RGp-%RGp %s\n",
pArgs->pPrevPhys, pArgs->pPrevPhys->Core.Key, pArgs->pPrevPhys->Core.KeyLast, pArgs->pPrevPhys->pszDesc,
return 0;
}
/**
* Validate a node in the virtual handler tree.
*
* @returns 0 on if ok, other wise 1.
* @param pNode The handler node.
* @param pvUser pVM.
*/
static DECLCALLBACK(int) pgmR3CheckIntegrityVirtHandlerNode(PAVLROGCPTRNODECORE pNode, void *pvUser)
{
AssertReleaseMsg(pCur->Core.Key <= pCur->Core.KeyLast,("pCur=%p %RGv-%RGv %s\n", pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->pszDesc));
|| (pArgs->fLeftToRight ? pArgs->pPrevVirt->Core.KeyLast < pCur->Core.Key : pArgs->pPrevVirt->Core.KeyLast > pCur->Core.Key),
("pPrevVirt=%p %RGv-%RGv %s\n"
" pCur=%p %RGv-%RGv %s\n",
pArgs->pPrevVirt, pArgs->pPrevVirt->Core.Key, pArgs->pPrevVirt->Core.KeyLast, pArgs->pPrevVirt->pszDesc,
{
AssertReleaseMsg(pCur->aPhysToVirt[iPage].offVirtHandler == -RT_OFFSETOF(PGMVIRTHANDLER, aPhysToVirt[iPage]),
("pCur=%p %RGv-%RGv %s\n"
"iPage=%d offVirtHandle=%#x expected %#x\n",
}
return 0;
}
/**
* Validate a node in the virtual handler tree.
*
* @returns 0 on if ok, other wise 1.
* @param pNode The handler node.
* @param pvUser pVM.
*/
static DECLCALLBACK(int) pgmR3CheckIntegrityPhysToVirtHandlerNode(PAVLROGCPHYSNODECORE pNode, void *pvUser)
{
AssertReleaseMsg(pCur->Core.Key <= pCur->Core.KeyLast,("pCur=%p %RGp-%RGp\n", pCur, pCur->Core.Key, pCur->Core.KeyLast));
|| (pArgs->fLeftToRight ? pArgs->pPrevPhys2Virt->Core.KeyLast < pCur->Core.Key : pArgs->pPrevPhys2Virt->Core.KeyLast > pCur->Core.Key),
("pPrevPhys2Virt=%p %RGp-%RGp\n"
" pCur=%p %RGp-%RGp\n",
|| (pArgs->fLeftToRight ? pArgs->pPrevPhys2Virt->Core.KeyLast < pCur->Core.Key : pArgs->pPrevPhys2Virt->Core.KeyLast > pCur->Core.Key),
("pPrevPhys2Virt=%p %RGp-%RGp\n"
" pCur=%p %RGp-%RGp\n",
AssertReleaseMsg((pCur->offNextAlias & (PGMPHYS2VIRTHANDLER_IN_TREE | PGMPHYS2VIRTHANDLER_IS_HEAD)) == (PGMPHYS2VIRTHANDLER_IN_TREE | PGMPHYS2VIRTHANDLER_IS_HEAD),
("pCur=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
{
for (;;)
{
pCur2 = (PPGMPHYS2VIRTHANDLER)((intptr_t)pCur + (pCur->offNextAlias & PGMPHYS2VIRTHANDLER_OFF_MASK));
(" pCur=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
AssertReleaseMsg((pCur2->offNextAlias & (PGMPHYS2VIRTHANDLER_IN_TREE | PGMPHYS2VIRTHANDLER_IS_HEAD)) == PGMPHYS2VIRTHANDLER_IN_TREE,
(" pCur=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n"
"pCur2=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
(" pCur=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n"
"pCur2=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
(" pCur=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n"
"pCur2=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
break;
}
}
return 0;
}
/**
* Perform an integrity check on the PGM component.
*
* @returns VINF_SUCCESS if everything is fine.
* @returns VBox error status after asserting on integrity breach.
* @param pVM The VM handle.
*/
{
/*
* Check the trees.
*/
int cErrors = 0;
cErrors += RTAvlroGCPhysDoWithAll(&pVM->pgm.s.pTreesR3->PhysHandlers, true, pgmR3CheckIntegrityPhysHandlerNode, &Args);
cErrors += RTAvlroGCPhysDoWithAll(&pVM->pgm.s.pTreesR3->PhysHandlers, false, pgmR3CheckIntegrityPhysHandlerNode, &Args);
cErrors += RTAvlroGCPtrDoWithAll( &pVM->pgm.s.pTreesR3->VirtHandlers, true, pgmR3CheckIntegrityVirtHandlerNode, &Args);
cErrors += RTAvlroGCPtrDoWithAll( &pVM->pgm.s.pTreesR3->VirtHandlers, false, pgmR3CheckIntegrityVirtHandlerNode, &Args);
cErrors += RTAvlroGCPtrDoWithAll( &pVM->pgm.s.pTreesR3->HyperVirtHandlers, true, pgmR3CheckIntegrityVirtHandlerNode, &Args);
cErrors += RTAvlroGCPtrDoWithAll( &pVM->pgm.s.pTreesR3->HyperVirtHandlers, false, pgmR3CheckIntegrityVirtHandlerNode, &Args);
cErrors += RTAvlroGCPhysDoWithAll(&pVM->pgm.s.pTreesR3->PhysToVirtHandlers, true, pgmR3CheckIntegrityPhysToVirtHandlerNode, &Args);
cErrors += RTAvlroGCPhysDoWithAll(&pVM->pgm.s.pTreesR3->PhysToVirtHandlers, false, pgmR3CheckIntegrityPhysToVirtHandlerNode, &Args);
}