HWACCMInternal.h revision c80185d78f848d437dc42cb143f32f3785ceaeca
/* $Id$ */
/** @file
* HWACCM - Internal header file.
*/
/*
* Copyright (C) 2006-2007 Oracle Corporation
*
* This file is part of VirtualBox Open Source Edition (OSE), as
* available from http://www.virtualbox.org. This file is free software;
* General Public License (GPL) as published by the Free Software
* Foundation, in version 2 as it comes in the "COPYING" file of the
* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
*/
#ifndef ___HWACCMInternal_h
#define ___HWACCMInternal_h
#if HC_ARCH_BITS == 64 || defined(VBOX_WITH_HYBRID_32BIT_KERNEL) || defined (VBOX_WITH_64_BITS_GUESTS)
/* Enable 64 bits guest support. */
# define VBOX_ENABLE_64_BITS_GUESTS
#endif
#define VMX_USE_CACHED_VMCS_ACCESSES
#define HWACCM_VMX_EMULATE_REALMODE
#define HWACCM_VTX_WITH_EPT
#define HWACCM_VTX_WITH_VPID
#if 0
/* Seeing somewhat random behaviour on my Nehalem system with auto-save of guest MSRs;
* for some strange reason the CPU doesn't save the MSRs during the VM-exit.
* Clearly visible with a dual VCPU configured OpenSolaris 200906 live cd VM.
*
*/
#define VBOX_WITH_AUTO_MSR_LOAD_RESTORE
#endif
/** @defgroup grp_hwaccm_int Internal
* @ingroup grp_hwaccm
* @internal
* @{
*/
/** Maximum number of exit reason statistics counters. */
#define MAX_EXITREASON_STAT 0x100
#define MASK_EXITREASON_STAT 0xff
#define MASK_INJECT_IRQ_STAT 0xff
/** @name Changed flags
* These flags are used to keep track of which important registers that
* have been changed since last they were reset.
* @{
*/
#define HWACCM_CHANGED_GUEST_FPU RT_BIT(0)
#define HWACCM_CHANGED_ALL ( HWACCM_CHANGED_GUEST_SEGMENT_REGS \
/** @} */
/** @name Intercepted traps
* Traps that need to be intercepted so we can correctly dispatch them to the guest if required.
* Currently #NM and #PF only
*/
#ifdef VBOX_STRICT
#define HWACCM_VMX_TRAP_MASK RT_BIT(X86_XCPT_BP) | RT_BIT(X86_XCPT_DB) | RT_BIT(X86_XCPT_DE) | RT_BIT(X86_XCPT_NM) | RT_BIT(X86_XCPT_PF) | RT_BIT(X86_XCPT_UD) | RT_BIT(X86_XCPT_NP) | RT_BIT(X86_XCPT_SS) | RT_BIT(X86_XCPT_GP) | RT_BIT(X86_XCPT_MF)
#else
#endif
/* All exceptions have to be intercept in emulated real-mode (minues NM & PF as they are always intercepted. */
#define HWACCM_VMX_TRAP_MASK_REALMODE RT_BIT(X86_XCPT_DE) | RT_BIT(X86_XCPT_DB) | RT_BIT(X86_XCPT_NMI) | RT_BIT(X86_XCPT_BP) | RT_BIT(X86_XCPT_OF) | RT_BIT(X86_XCPT_BR) | RT_BIT(X86_XCPT_UD) | RT_BIT(X86_XCPT_DF) | RT_BIT(X86_XCPT_CO_SEG_OVERRUN) | RT_BIT(X86_XCPT_TS) | RT_BIT(X86_XCPT_NP) | RT_BIT(X86_XCPT_SS) | RT_BIT(X86_XCPT_GP) | RT_BIT(X86_XCPT_MF) | RT_BIT(X86_XCPT_AC) | RT_BIT(X86_XCPT_MC) | RT_BIT(X86_XCPT_XF)
/** @} */
/** Maximum number of page flushes we are willing to remember before considering a full TLB flush. */
#define HWACCM_MAX_TLB_SHOOTDOWN_PAGES 8
/** Size for the EPT identity page table (1024 4 MB pages to cover the entire address space). */
/** Size of the TSS structure + 2 pages for the IO bitmap + end byte. */
/** Total guest mapped memory needed. */
/* Enable for TPR guest patching. */
#define VBOX_HWACCM_WITH_GUEST_PATCHING
/** HWACCM SSM version
*/
#define HWACCM_SSM_VERSION 5
#define HWACCM_SSM_VERSION_NO_PATCHING 4
#else
#define HWACCM_SSM_VERSION 4
#define HWACCM_SSM_VERSION_NO_PATCHING 4
#endif
#define HWACCM_SSM_VERSION_2_0_X 3
/* Per-cpu information. (host) */
typedef struct
{
/* Current ASID (AMD-V)/VPID (Intel) */
/* TLB flush count */
/* Set the first time a cpu is used to make sure we start with a clean TLB. */
bool fFlushTLB;
/** Configured for VT-x or AMD-V. */
bool fConfigured;
/** Set if the VBOX_HWVIRTEX_IGNORE_SVM_IN_USE hack is active. */
bool fIgnoreAMDVInUseError;
/** In use by our code. (for power suspend) */
volatile bool fInUse;
typedef HWACCM_CPUINFO *PHWACCM_CPUINFO;
typedef enum
{
/** The usual 32-bit paranoia. */
HWACCMPENDINGIO_32BIT_HACK = 0x7fffffff
typedef enum
{
/** The usual 32-bit paranoia. */
HWACCMTPRINSTR_32BIT_HACK = 0x7fffffff
typedef struct
{
/** The key is the address of patched instruction. (32 bits GC ptr) */
/** Original opcode. */
/** Instruction size. */
/** Replacement opcode. */
/** Replacement instruction size. */
/** Instruction type. */
/** Source operand. */
/** Destination operand. */
/** Number of times the instruction caused a fault. */
/** Patch address of the jump replacement. */
/** Pointer to HWACCMTPRPATCH. */
typedef HWACCMTPRPATCH *PHWACCMTPRPATCH;
/**
* Switcher function, HC to RC.
*
* @param pVM The VM handle.
* @param uOffsetVMCPU VMCPU offset from pVM
* @returns Return code indicating the action to take.
*/
/** Pointer to switcher function. */
typedef FNHWACCMSWITCHERHC *PFNHWACCMSWITCHERHC;
/**
* HWACCM VM Instance data.
* Changes to this must checked against the padding of the cfgm union in VM!
*/
typedef struct HWACCM
{
/** Set when we've initialized VMX or SVM. */
bool fInitialized;
/** Set when hardware acceleration is allowed. */
bool fAllowed;
/** Set if nested paging is enabled. */
bool fNestedPaging;
/** Set if nested paging is allowed. */
bool fAllowNestedPaging;
/** Set if large pages are enabled (requires nested paging). */
bool fLargePages;
/** Set if we can support 64-bit guests or not. */
bool fAllow64BitGuests;
/** Set if an IO-APIC is configured for this VM. */
bool fHasIoApic;
/** Set when TPR patching is allowed. */
bool fTRPPatchingAllowed;
/** Set when we initialize VT-x or AMD-V once for all CPUs. */
bool fGlobalInit;
/** Set when TPR patching is active. */
bool fTPRPatchingActive;
bool u8Alignment[6];
/** And mask for copying register contents. */
/** Maximum ASID allowed. */
/** The maximum number of resumes loops allowed in ring-0 (safety precaution).
* This number is set much higher when RTThreadPreemptIsPending is reliable. */
/** Guest allocated memory for patching purposes. */
/** Current free pointer inside the patch block. */
/** Size of the guest patch memory block. */
#if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS) && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
/** 32 to 64 bits switcher entrypoint. */
/* AMD-V 64 bits vmrun handler */
/* VT-x 64 bits vmlaunch handler */
/* RC handler to setup the 64 bits FPU state. */
/* RC handler to setup the 64 bits debug state. */
/* Test handler */
/*#elif defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
uint32_t u32Alignment[1]; */
#endif
struct
{
/** Set by the ring-0 driver to indicate VMX is supported by the CPU. */
bool fSupported;
/** Set when we've enabled VMX. */
bool fEnabled;
/** Set if VPID is supported. */
bool fVPID;
/** Set if VT-x VPID is allowed. */
bool fAllowVPID;
/** Set if unrestricted guest execution is allowed (real and protected mode without paging). */
bool fUnrestrictedGuest;
bool uAlignment[3];
/** Virtual address of the TSS page used for real mode emulation. */
/** Virtual address of the identity page table used for real mode and protected mode without paging emulation in EPT mode. */
/** R0 memory object for the APIC physical page (serves for filtering accesses). */
/** Physical address of the APIC physical page (serves for filtering accesses). */
/** Virtual address of the APIC physical page (serves for filtering accesses). */
/** R0 memory object for the MSR entry load page (guest MSRs). */
/** Physical address of the MSR entry load page (guest MSRs). */
/** Virtual address of the MSR entry load page (guest MSRs). */
#ifdef VBOX_WITH_CRASHDUMP_MAGIC
#endif
/** R0 memory object for the MSR exit store page (guest MSRs). */
/** Physical address of the MSR exit store page (guest MSRs). */
/** Virtual address of the MSR exit store page (guest MSRs). */
/** R0 memory object for the MSR exit load page (host MSRs). */
/** Physical address of the MSR exit load page (host MSRs). */
/** Virtual address of the MSR exit load page (host MSRs). */
/** Ring 0 handlers for VT-x. */
#endif
/** Host CR4 value (set by ring-0 VMX init) */
/** Host EFER value (set by ring-0 VMX init) */
/** VMX MSR values */
struct
{
} msr;
/** Flush types for invept & invvpid; they depend on capabilities. */
} vmx;
struct
{
/** Set by the ring-0 driver to indicate SVM is supported by the CPU. */
bool fSupported;
/** Set when we've enabled SVM. */
bool fEnabled;
/** Set if erratum 170 affects the AMD cpu. */
bool fAlwaysFlushTLB;
/** Set when the hack to ignore VERR_SVM_IN_USE is active. */
bool fIgnoreInUseError;
/** R0 memory object for the IO bitmap (12kb). */
/** Physical address of the IO bitmap (12kb). */
/** Virtual address of the IO bitmap. */
/* HWCR msr (for diagnostics) */
/** SVM revision. */
/** SVM feature bits from cpuid 0x8000000a */
} svm;
/**
* AVL tree with all patches (active or disabled) sorted by guest instruction address
*/
struct
{
} cpuid;
/** Saved error from detection */
/** HWACCMR0Init was run */
bool fHWACCMR0Init;
bool u8Alignment1[7];
} HWACCM;
/** Pointer to HWACCM VM instance data. */
/* Maximum number of cached entries. */
#define VMCSCACHE_MAX_ENTRY 128
/* Structure for storing read and write VMCS actions. */
typedef struct VMCSCACHE
{
#ifdef VBOX_WITH_CRASHDUMP_MAGIC
/* Magic marker for searching in crash dumps. */
#endif
/* CR2 is saved here for EPT syncing. */
struct
{
} Write;
struct
{
} Read;
#ifdef DEBUG
struct
{
} TestIn;
struct
{
} TestOut;
struct
{
} ScratchPad;
#endif
} VMCSCACHE;
/** Pointer to VMCSCACHE. */
typedef VMCSCACHE *PVMCSCACHE;
/** VMX StartVM function. */
typedef DECLCALLBACK(int) FNHWACCMVMXSTARTVM(RTHCUINT fResume, PCPUMCTX pCtx, PVMCSCACHE pCache, PVM pVM, PVMCPU pVCpu);
/** Pointer to a VMX StartVM function. */
/** SVM VMRun function. */
typedef DECLCALLBACK(int) FNHWACCMSVMVMRUN(RTHCPHYS pVMCBHostPhys, RTHCPHYS pVMCBPhys, PCPUMCTX pCtx, PVM pVM, PVMCPU pVCpu);
/** Pointer to a SVM VMRun function. */
/**
* HWACCM VMCPU Instance data.
*/
typedef struct HWACCMCPU
{
/** Old style FPU reporting trap mask override performed (optimization) */
bool fFPUOldStyleOverride;
/** Set if we don't have to flush the TLB on VM entry. */
bool fResumeVM;
/** Set if we need to flush the TLB during the world switch. */
bool fForceTLBFlush;
/** Set when we're using VT-x or AMD-V at that moment. */
bool fActive;
/** Set when the TLB has been checked until we return from the world switch. */
volatile uint8_t fCheckedTLBFlush;
/** HWACCM_CHANGED_* flags. */
/** Id of the last cpu we were executing code on (NIL_RTCPUID for the first time) */
/** TLB flush count */
/** Current ASID in use by the VM */
/** World switch exit counter. */
volatile uint32_t cWorldSwitchExit;
struct
{
/** Physical address of the VM control structure (VMCS). */
/** R0 memory object for the VM control structure (VMCS). */
/** Virtual address of the VM control structure (VMCS). */
/** Ring 0 handlers for VT-x. */
#if HC_ARCH_BITS == 32
#endif
/** Current VMX_VMCS_CTRL_PROC_EXEC_CONTROLS. */
/** Current VMX_VMCS_CTRL_PROC_EXEC2_CONTROLS. */
/** Physical address of the virtual APIC page for TPR caching. */
/** R0 memory object for the virtual APIC page for TPR caching. */
/** Virtual address of the virtual APIC page for TPR caching. */
/** Current CR0 mask. */
/** Current CR4 mask. */
/** Current EPTP. */
/** Physical address of the MSR bitmap (1 page). */
/** R0 memory object for the MSR bitmap (1 page). */
/** Virtual address of the MSR bitmap (1 page). */
/** Physical address of the guest MSR load area (1 page). */
/** R0 memory object for the guest MSR load area (1 page). */
/** Virtual address of the guest MSR load area (1 page). */
/** Physical address of the MSR load area (1 page). */
/** R0 memory object for the MSR load area (1 page). */
/** Virtual address of the MSR load area (1 page). */
#endif /* VBOX_WITH_AUTO_MSR_LOAD_RESTORE */
/* Last use TSC offset value. (cached) */
/** VMCS cache. */
/** Real-mode emulation state. */
struct
{
} RealMode;
struct
{
} lasterror;
/** The last seen guest paging mode (by VT-x). */
/** Current guest paging mode (as seen by HWACCMR3PagingModeChanged). */
/** Previous guest paging mode (as seen by HWACCMR3PagingModeChanged). */
} vmx;
struct
{
/** R0 memory object for the host VM control block (VMCB). */
/** Physical address of the host VM control block (VMCB). */
/** Virtual address of the host VM control block (VMCB). */
/** R0 memory object for the VM control block (VMCB). */
/** Physical address of the VM control block (VMCB). */
/** Virtual address of the VM control block (VMCB). */
/** Ring 0 handlers for VT-x. */
/** R0 memory object for the MSR bitmap (8kb). */
/** Physical address of the MSR bitmap (8kb). */
/** Virtual address of the MSR bitmap. */
R0PTRTYPE(void *) pMSRBitmap;
} svm;
/** Event injection state. */
struct
{
} Event;
/** IO Block emulation state. */
struct
{
bool fEnabled;
/** RIP at the start of the io code we wish to emulate in the recompiler. */
struct
{
/* Pending IO operation type. */
union
{
struct
{
unsigned uPort;
unsigned uAndVal;
unsigned cbSize;
} Port;
} s;
} PendingIO;
/** Currenty shadow paging mode. */
/** The CPU ID of the CPU currently owning the VMCS. Set in
* HWACCMR0Enter and cleared in HWACCMR0Leave. */
/** To keep track of pending TLB shootdown pages. (SMP guest only) */
struct
{
unsigned cPages;
} TlbShootdown;
/** For saving stack space, the disassembler state is allocated here instead of
* on the stack.
union
{
/** The disassembler scratch space. */
/** Padding. */
};
#if 1 /* temporary for tracking down darwin issues. */
#endif
#if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS) && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
#endif
#if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS) && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
#endif
#ifdef VBOX_WITH_STATISTICS
#endif
} HWACCMCPU;
/** Pointer to HWACCM VM instance data. */
typedef HWACCMCPU *PHWACCMCPU;
#ifdef IN_RING0
#ifdef VBOX_STRICT
#else
# define HWACCMDumpRegs(a, b ,c) do { } while (0)
# define HWACCMR0DumpDescriptor(a, b, c) do { } while (0)
#endif
/* Dummy callback handlers. */
VMMR0DECL(int) HWACCMR0DummyEnableCpu(PHWACCM_CPUINFO pCpu, PVM pVM, void *pvPageCpu, RTHCPHYS pPageCpuPhys);
VMMR0DECL(int) HWACCMR0DummyDisableCpu(PHWACCM_CPUINFO pCpu, void *pvPageCpu, RTHCPHYS pPageCpuPhys);
# ifdef VBOX_WITH_KERNEL_USING_XMM
DECLASM(int) hwaccmR0VMXStartVMWrapXMM(RTHCUINT fResume, PCPUMCTX pCtx, PVMCSCACHE pCache, PVM pVM, PVMCPU pVCpu, PFNHWACCMVMXSTARTVM pfnStartVM);
DECLASM(int) hwaccmR0SVMRunWrapXMM(RTHCPHYS pVMCBHostPhys, RTHCPHYS pVMCBPhys, PCPUMCTX pCtx, PVM pVM, PVMCPU pVCpu, PFNHWACCMSVMVMRUN pfnVMRun);
# endif
# ifdef VBOX_WITH_HYBRID_32BIT_KERNEL
/**
* Gets 64-bit GDTR and IDTR on darwin.
* @param pGdtr Where to store the 64-bit GDTR.
* @param pIdtr Where to store the 64-bit IDTR.
*/
/**
* Gets 64-bit CR3 on darwin.
* @returns CR3
*/
# endif
#endif /* IN_RING0 */
/** @} */
#endif