EM.cpp revision 3857503560316b1952243b559dec05f87c561404
/* $Id$ */
/** @file
* EM - Execution Monitor / Manager.
*/
/*
* Copyright (C) 2006-2007 Sun Microsystems, Inc.
*
* This file is part of VirtualBox Open Source Edition (OSE), as
* available from http://www.virtualbox.org. This file is free software;
* General Public License (GPL) as published by the Free Software
* Foundation, in version 2 as it comes in the "COPYING" file of the
* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
*
* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
* Clara, CA 95054 USA or visit http://www.sun.com if you need
* additional information or have any questions.
*/
/** @page pg_em EM - The Execution Monitor / Manager
*
* the right kind of execution (Raw-mode, Hardware Assisted, Recompiled or
* Interpreted), and keeping the CPU states in sync. The function
* EMR3ExecuteVM() is the 'main-loop' of the VM, while each of the execution
* modes has different inner loops (emR3RawExecute, emR3HwAccExecute, and
* emR3RemExecute).
*
* The interpreted execution is only used to avoid switching between
* The interpretation is thus implemented as part of EM.
*
* @see grp_em
*/
/*******************************************************************************
* Header Files *
*******************************************************************************/
#define LOG_GROUP LOG_GROUP_EM
#ifdef VBOX_WITH_VMI
#endif
#include <VBox/pdmcritsect.h>
#include <VBox/pdmqueue.h>
#include "EMInternal.h"
#include <VBox/disopcode.h>
#include <iprt/semaphore.h>
/*******************************************************************************
* Defined Constants And Macros *
*******************************************************************************/
#if 0 /* Disabled till after 2.1.0 when we've time to test it. */
#define EM_NOTIFY_HWACCM
#endif
/*******************************************************************************
* Internal Functions *
*******************************************************************************/
DECLINLINE(int) emR3RawExecuteInstruction(PVM pVM, PVMCPU pVCpu, const char *pszPrefix, int rcGC = VINF_SUCCESS);
/**
* Initializes the EM.
*
* @returns VBox status code.
* @param pVM The VM to operate on.
*/
{
LogFlow(("EMR3Init\n"));
/*
* Assert alignment and sizes.
*/
AssertCompile(sizeof(pVM->aCpus[0].em.s.u.FatalLongJump) <= sizeof(pVM->aCpus[0].em.s.u.achPaddingFatalLongJump));
/*
* Init the structure.
*/
if (RT_FAILURE(rc))
pVM->fRawR3Enabled = true;
if (RT_FAILURE(rc))
pVM->fRawR0Enabled = true;
/*
* Initialize the REM critical section.
*/
/*
* Saved state.
*/
if (RT_FAILURE(rc))
return rc;
{
# define EM_REG_COUNTER(a, b, c) \
rc = STAMR3RegisterF(pVM, a, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, c, b, i); \
# define EM_REG_COUNTER_USED(a, b, c) \
rc = STAMR3RegisterF(pVM, a, STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES, c, b, i); \
# define EM_REG_PROFILE(a, b, c) \
rc = STAMR3RegisterF(pVM, a, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_CALL, c, b, i); \
# define EM_REG_PROFILE_ADV(a, b, c) \
rc = STAMR3RegisterF(pVM, a, STAMTYPE_PROFILE_ADV, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_CALL, c, b, i); \
/*
* Statistics.
*/
#ifdef VBOX_WITH_STATISTICS
if (RT_FAILURE(rc))
return rc;
EM_REG_PROFILE(&pStats->StatRZEmulate, "/EM/CPU%d/RZ/Interpret", "Profiling of EMInterpretInstruction.");
EM_REG_PROFILE(&pStats->StatR3Emulate, "/EM/CPU%d/R3/Interpret", "Profiling of EMInterpretInstruction.");
EM_REG_PROFILE(&pStats->StatRZInterpretSucceeded, "/EM/CPU%d/RZ/Interpret/Success", "The number of times an instruction was successfully interpreted.");
EM_REG_PROFILE(&pStats->StatR3InterpretSucceeded, "/EM/CPU%d/R3/Interpret/Success", "The number of times an instruction was successfully interpreted.");
EM_REG_COUNTER_USED(&pStats->StatRZAnd, "/EM/CPU%d/RZ/Interpret/Success/And", "The number of times AND was successfully interpreted.");
EM_REG_COUNTER_USED(&pStats->StatR3And, "/EM/CPU%d/R3/Interpret/Success/And", "The number of times AND was successfully interpreted.");
EM_REG_COUNTER_USED(&pStats->StatRZAdd, "/EM/CPU%d/RZ/Interpret/Success/Add", "The number of times ADD was successfully interpreted.");
EM_REG_COUNTER_USED(&pStats->StatR3Add, "/EM/CPU%d/R3/Interpret/Success/Add", "The number of times ADD was successfully interpreted.");
EM_REG_COUNTER_USED(&pStats->StatRZAdc, "/EM/CPU%d/RZ/Interpret/Success/Adc", "The number of times ADC was successfully interpreted.");
EM_REG_COUNTER_USED(&pStats->StatR3Adc, "/EM/CPU%d/R3/Interpret/Success/Adc", "The number of times ADC was successfully interpreted.");
EM_REG_COUNTER_USED(&pStats->StatRZSub, "/EM/CPU%d/RZ/Interpret/Success/Sub", "The number of times SUB was successfully interpreted.");
EM_REG_COUNTER_USED(&pStats->StatR3Sub, "/EM/CPU%d/R3/Interpret/Success/Sub", "The number of times SUB was successfully interpreted.");
EM_REG_COUNTER_USED(&pStats->StatRZCpuId, "/EM/CPU%d/RZ/Interpret/Success/CpuId", "The number of times CPUID was successfully interpreted.");
EM_REG_COUNTER_USED(&pStats->StatR3CpuId, "/EM/CPU%d/R3/Interpret/Success/CpuId", "The number of times CPUID was successfully interpreted.");
EM_REG_COUNTER_USED(&pStats->StatRZDec, "/EM/CPU%d/RZ/Interpret/Success/Dec", "The number of times DEC was successfully interpreted.");
EM_REG_COUNTER_USED(&pStats->StatR3Dec, "/EM/CPU%d/R3/Interpret/Success/Dec", "The number of times DEC was successfully interpreted.");
EM_REG_COUNTER_USED(&pStats->StatRZHlt, "/EM/CPU%d/RZ/Interpret/Success/Hlt", "The number of times HLT was successfully interpreted.");
EM_REG_COUNTER_USED(&pStats->StatR3Hlt, "/EM/CPU%d/R3/Interpret/Success/Hlt", "The number of times HLT was successfully interpreted.");
EM_REG_COUNTER_USED(&pStats->StatRZInc, "/EM/CPU%d/RZ/Interpret/Success/Inc", "The number of times INC was successfully interpreted.");
EM_REG_COUNTER_USED(&pStats->StatR3Inc, "/EM/CPU%d/R3/Interpret/Success/Inc", "The number of times INC was successfully interpreted.");
EM_REG_COUNTER_USED(&pStats->StatRZInvlPg, "/EM/CPU%d/RZ/Interpret/Success/Invlpg", "The number of times INVLPG was successfully interpreted.");
EM_REG_COUNTER_USED(&pStats->StatR3InvlPg, "/EM/CPU%d/R3/Interpret/Success/Invlpg", "The number of times INVLPG was successfully interpreted.");
EM_REG_COUNTER_USED(&pStats->StatRZIret, "/EM/CPU%d/RZ/Interpret/Success/Iret", "The number of times IRET was successfully interpreted.");
EM_REG_COUNTER_USED(&pStats->StatR3Iret, "/EM/CPU%d/R3/Interpret/Success/Iret", "The number of times IRET was successfully interpreted.");
EM_REG_COUNTER_USED(&pStats->StatRZLLdt, "/EM/CPU%d/RZ/Interpret/Success/LLdt", "The number of times LLDT was successfully interpreted.");
EM_REG_COUNTER_USED(&pStats->StatR3LLdt, "/EM/CPU%d/R3/Interpret/Success/LLdt", "The number of times LLDT was successfully interpreted.");
EM_REG_COUNTER_USED(&pStats->StatRZLIdt, "/EM/CPU%d/RZ/Interpret/Success/LIdt", "The number of times LIDT was successfully interpreted.");
EM_REG_COUNTER_USED(&pStats->StatR3LIdt, "/EM/CPU%d/R3/Interpret/Success/LIdt", "The number of times LIDT was successfully interpreted.");
EM_REG_COUNTER_USED(&pStats->StatRZLGdt, "/EM/CPU%d/RZ/Interpret/Success/LGdt", "The number of times LGDT was successfully interpreted.");
EM_REG_COUNTER_USED(&pStats->StatR3LGdt, "/EM/CPU%d/R3/Interpret/Success/LGdt", "The number of times LGDT was successfully interpreted.");
EM_REG_COUNTER_USED(&pStats->StatRZMov, "/EM/CPU%d/RZ/Interpret/Success/Mov", "The number of times MOV was successfully interpreted.");
EM_REG_COUNTER_USED(&pStats->StatR3Mov, "/EM/CPU%d/R3/Interpret/Success/Mov", "The number of times MOV was successfully interpreted.");
EM_REG_COUNTER_USED(&pStats->StatRZMovCRx, "/EM/CPU%d/RZ/Interpret/Success/MovCRx", "The number of times MOV CRx was successfully interpreted.");
EM_REG_COUNTER_USED(&pStats->StatR3MovCRx, "/EM/CPU%d/R3/Interpret/Success/MovCRx", "The number of times MOV CRx was successfully interpreted.");
EM_REG_COUNTER_USED(&pStats->StatRZMovDRx, "/EM/CPU%d/RZ/Interpret/Success/MovDRx", "The number of times MOV DRx was successfully interpreted.");
EM_REG_COUNTER_USED(&pStats->StatR3MovDRx, "/EM/CPU%d/R3/Interpret/Success/MovDRx", "The number of times MOV DRx was successfully interpreted.");
EM_REG_COUNTER_USED(&pStats->StatRZOr, "/EM/CPU%d/RZ/Interpret/Success/Or", "The number of times OR was successfully interpreted.");
EM_REG_COUNTER_USED(&pStats->StatR3Or, "/EM/CPU%d/R3/Interpret/Success/Or", "The number of times OR was successfully interpreted.");
EM_REG_COUNTER_USED(&pStats->StatRZPop, "/EM/CPU%d/RZ/Interpret/Success/Pop", "The number of times POP was successfully interpreted.");
EM_REG_COUNTER_USED(&pStats->StatR3Pop, "/EM/CPU%d/R3/Interpret/Success/Pop", "The number of times POP was successfully interpreted.");
EM_REG_COUNTER_USED(&pStats->StatRZRdtsc, "/EM/CPU%d/RZ/Interpret/Success/Rdtsc", "The number of times RDTSC was successfully interpreted.");
EM_REG_COUNTER_USED(&pStats->StatR3Rdtsc, "/EM/CPU%d/R3/Interpret/Success/Rdtsc", "The number of times RDTSC was successfully interpreted.");
EM_REG_COUNTER_USED(&pStats->StatRZRdpmc, "/EM/CPU%d/RZ/Interpret/Success/Rdpmc", "The number of times RDPMC was successfully interpreted.");
EM_REG_COUNTER_USED(&pStats->StatR3Rdpmc, "/EM/CPU%d/R3/Interpret/Success/Rdpmc", "The number of times RDPMC was successfully interpreted.");
EM_REG_COUNTER_USED(&pStats->StatRZSti, "/EM/CPU%d/RZ/Interpret/Success/Sti", "The number of times STI was successfully interpreted.");
EM_REG_COUNTER_USED(&pStats->StatR3Sti, "/EM/CPU%d/R3/Interpret/Success/Sti", "The number of times STI was successfully interpreted.");
EM_REG_COUNTER_USED(&pStats->StatRZXchg, "/EM/CPU%d/RZ/Interpret/Success/Xchg", "The number of times XCHG was successfully interpreted.");
EM_REG_COUNTER_USED(&pStats->StatR3Xchg, "/EM/CPU%d/R3/Interpret/Success/Xchg", "The number of times XCHG was successfully interpreted.");
EM_REG_COUNTER_USED(&pStats->StatRZXor, "/EM/CPU%d/RZ/Interpret/Success/Xor", "The number of times XOR was successfully interpreted.");
EM_REG_COUNTER_USED(&pStats->StatR3Xor, "/EM/CPU%d/R3/Interpret/Success/Xor", "The number of times XOR was successfully interpreted.");
EM_REG_COUNTER_USED(&pStats->StatRZMonitor, "/EM/CPU%d/RZ/Interpret/Success/Monitor", "The number of times MONITOR was successfully interpreted.");
EM_REG_COUNTER_USED(&pStats->StatR3Monitor, "/EM/CPU%d/R3/Interpret/Success/Monitor", "The number of times MONITOR was successfully interpreted.");
EM_REG_COUNTER_USED(&pStats->StatRZMWait, "/EM/CPU%d/RZ/Interpret/Success/MWait", "The number of times MWAIT was successfully interpreted.");
EM_REG_COUNTER_USED(&pStats->StatR3MWait, "/EM/CPU%d/R3/Interpret/Success/MWait", "The number of times MWAIT was successfully interpreted.");
EM_REG_COUNTER_USED(&pStats->StatRZBtr, "/EM/CPU%d/RZ/Interpret/Success/Btr", "The number of times BTR was successfully interpreted.");
EM_REG_COUNTER_USED(&pStats->StatR3Btr, "/EM/CPU%d/R3/Interpret/Success/Btr", "The number of times BTR was successfully interpreted.");
EM_REG_COUNTER_USED(&pStats->StatRZBts, "/EM/CPU%d/RZ/Interpret/Success/Bts", "The number of times BTS was successfully interpreted.");
EM_REG_COUNTER_USED(&pStats->StatR3Bts, "/EM/CPU%d/R3/Interpret/Success/Bts", "The number of times BTS was successfully interpreted.");
EM_REG_COUNTER_USED(&pStats->StatRZBtc, "/EM/CPU%d/RZ/Interpret/Success/Btc", "The number of times BTC was successfully interpreted.");
EM_REG_COUNTER_USED(&pStats->StatR3Btc, "/EM/CPU%d/R3/Interpret/Success/Btc", "The number of times BTC was successfully interpreted.");
EM_REG_COUNTER_USED(&pStats->StatRZCmpXchg, "/EM/CPU%d/RZ/Interpret/Success/CmpXchg", "The number of times CMPXCHG was successfully interpreted.");
EM_REG_COUNTER_USED(&pStats->StatR3CmpXchg, "/EM/CPU%d/R3/Interpret/Success/CmpXchg", "The number of times CMPXCHG was successfully interpreted.");
EM_REG_COUNTER_USED(&pStats->StatRZCmpXchg8b, "/EM/CPU%d/RZ/Interpret/Success/CmpXchg8b", "The number of times CMPXCHG8B was successfully interpreted.");
EM_REG_COUNTER_USED(&pStats->StatR3CmpXchg8b, "/EM/CPU%d/R3/Interpret/Success/CmpXchg8b", "The number of times CMPXCHG8B was successfully interpreted.");
EM_REG_COUNTER_USED(&pStats->StatRZXAdd, "/EM/CPU%d/RZ/Interpret/Success/XAdd", "The number of times XADD was successfully interpreted.");
EM_REG_COUNTER_USED(&pStats->StatR3XAdd, "/EM/CPU%d/R3/Interpret/Success/XAdd", "The number of times XADD was successfully interpreted.");
EM_REG_COUNTER_USED(&pStats->StatR3Rdmsr, "/EM/CPU%d/R3/Interpret/Success/Rdmsr", "The number of times RDMSR was successfully interpreted.");
EM_REG_COUNTER_USED(&pStats->StatRZRdmsr, "/EM/CPU%d/RZ/Interpret/Success/Rdmsr", "The number of times RDMSR was successfully interpreted.");
EM_REG_COUNTER_USED(&pStats->StatR3Wrmsr, "/EM/CPU%d/R3/Interpret/Success/Wrmsr", "The number of times WRMSR was successfully interpreted.");
EM_REG_COUNTER_USED(&pStats->StatRZWrmsr, "/EM/CPU%d/RZ/Interpret/Success/Wrmsr", "The number of times WRMSR was successfully interpreted.");
EM_REG_COUNTER_USED(&pStats->StatR3StosWD, "/EM/CPU%d/R3/Interpret/Success/Stoswd", "The number of times STOSWD was successfully interpreted.");
EM_REG_COUNTER_USED(&pStats->StatRZStosWD, "/EM/CPU%d/RZ/Interpret/Success/Stoswd", "The number of times STOSWD was successfully interpreted.");
EM_REG_COUNTER_USED(&pStats->StatRZWbInvd, "/EM/CPU%d/RZ/Interpret/Success/WbInvd", "The number of times WBINVD was successfully interpreted.");
EM_REG_COUNTER_USED(&pStats->StatR3WbInvd, "/EM/CPU%d/R3/Interpret/Success/WbInvd", "The number of times WBINVD was successfully interpreted.");
EM_REG_COUNTER_USED(&pStats->StatRZLmsw, "/EM/CPU%d/RZ/Interpret/Success/Lmsw", "The number of times LMSW was successfully interpreted.");
EM_REG_COUNTER_USED(&pStats->StatR3Lmsw, "/EM/CPU%d/R3/Interpret/Success/Lmsw", "The number of times LMSW was successfully interpreted.");
EM_REG_COUNTER(&pStats->StatRZInterpretFailed, "/EM/CPU%d/RZ/Interpret/Failed", "The number of times an instruction was not interpreted.");
EM_REG_COUNTER(&pStats->StatR3InterpretFailed, "/EM/CPU%d/R3/Interpret/Failed", "The number of times an instruction was not interpreted.");
EM_REG_COUNTER_USED(&pStats->StatRZFailedAnd, "/EM/CPU%d/RZ/Interpret/Failed/And", "The number of times AND was not interpreted.");
EM_REG_COUNTER_USED(&pStats->StatR3FailedAnd, "/EM/CPU%d/R3/Interpret/Failed/And", "The number of times AND was not interpreted.");
EM_REG_COUNTER_USED(&pStats->StatRZFailedCpuId, "/EM/CPU%d/RZ/Interpret/Failed/CpuId", "The number of times CPUID was not interpreted.");
EM_REG_COUNTER_USED(&pStats->StatR3FailedCpuId, "/EM/CPU%d/R3/Interpret/Failed/CpuId", "The number of times CPUID was not interpreted.");
EM_REG_COUNTER_USED(&pStats->StatRZFailedDec, "/EM/CPU%d/RZ/Interpret/Failed/Dec", "The number of times DEC was not interpreted.");
EM_REG_COUNTER_USED(&pStats->StatR3FailedDec, "/EM/CPU%d/R3/Interpret/Failed/Dec", "The number of times DEC was not interpreted.");
EM_REG_COUNTER_USED(&pStats->StatRZFailedHlt, "/EM/CPU%d/RZ/Interpret/Failed/Hlt", "The number of times HLT was not interpreted.");
EM_REG_COUNTER_USED(&pStats->StatR3FailedHlt, "/EM/CPU%d/R3/Interpret/Failed/Hlt", "The number of times HLT was not interpreted.");
EM_REG_COUNTER_USED(&pStats->StatRZFailedInc, "/EM/CPU%d/RZ/Interpret/Failed/Inc", "The number of times INC was not interpreted.");
EM_REG_COUNTER_USED(&pStats->StatR3FailedInc, "/EM/CPU%d/R3/Interpret/Failed/Inc", "The number of times INC was not interpreted.");
EM_REG_COUNTER_USED(&pStats->StatRZFailedInvlPg, "/EM/CPU%d/RZ/Interpret/Failed/InvlPg", "The number of times INVLPG was not interpreted.");
EM_REG_COUNTER_USED(&pStats->StatR3FailedInvlPg, "/EM/CPU%d/R3/Interpret/Failed/InvlPg", "The number of times INVLPG was not interpreted.");
EM_REG_COUNTER_USED(&pStats->StatRZFailedIret, "/EM/CPU%d/RZ/Interpret/Failed/Iret", "The number of times IRET was not interpreted.");
EM_REG_COUNTER_USED(&pStats->StatR3FailedIret, "/EM/CPU%d/R3/Interpret/Failed/Iret", "The number of times IRET was not interpreted.");
EM_REG_COUNTER_USED(&pStats->StatRZFailedLLdt, "/EM/CPU%d/RZ/Interpret/Failed/LLdt", "The number of times LLDT was not interpreted.");
EM_REG_COUNTER_USED(&pStats->StatR3FailedLLdt, "/EM/CPU%d/R3/Interpret/Failed/LLdt", "The number of times LLDT was not interpreted.");
EM_REG_COUNTER_USED(&pStats->StatRZFailedLIdt, "/EM/CPU%d/RZ/Interpret/Failed/LIdt", "The number of times LIDT was not interpreted.");
EM_REG_COUNTER_USED(&pStats->StatR3FailedLIdt, "/EM/CPU%d/R3/Interpret/Failed/LIdt", "The number of times LIDT was not interpreted.");
EM_REG_COUNTER_USED(&pStats->StatRZFailedLGdt, "/EM/CPU%d/RZ/Interpret/Failed/LGdt", "The number of times LGDT was not interpreted.");
EM_REG_COUNTER_USED(&pStats->StatR3FailedLGdt, "/EM/CPU%d/R3/Interpret/Failed/LGdt", "The number of times LGDT was not interpreted.");
EM_REG_COUNTER_USED(&pStats->StatRZFailedMov, "/EM/CPU%d/RZ/Interpret/Failed/Mov", "The number of times MOV was not interpreted.");
EM_REG_COUNTER_USED(&pStats->StatR3FailedMov, "/EM/CPU%d/R3/Interpret/Failed/Mov", "The number of times MOV was not interpreted.");
EM_REG_COUNTER_USED(&pStats->StatRZFailedMovCRx, "/EM/CPU%d/RZ/Interpret/Failed/MovCRx", "The number of times MOV CRx was not interpreted.");
EM_REG_COUNTER_USED(&pStats->StatR3FailedMovCRx, "/EM/CPU%d/R3/Interpret/Failed/MovCRx", "The number of times MOV CRx was not interpreted.");
EM_REG_COUNTER_USED(&pStats->StatRZFailedMovDRx, "/EM/CPU%d/RZ/Interpret/Failed/MovDRx", "The number of times MOV DRx was not interpreted.");
EM_REG_COUNTER_USED(&pStats->StatR3FailedMovDRx, "/EM/CPU%d/R3/Interpret/Failed/MovDRx", "The number of times MOV DRx was not interpreted.");
EM_REG_COUNTER_USED(&pStats->StatRZFailedOr, "/EM/CPU%d/RZ/Interpret/Failed/Or", "The number of times OR was not interpreted.");
EM_REG_COUNTER_USED(&pStats->StatR3FailedOr, "/EM/CPU%d/R3/Interpret/Failed/Or", "The number of times OR was not interpreted.");
EM_REG_COUNTER_USED(&pStats->StatRZFailedPop, "/EM/CPU%d/RZ/Interpret/Failed/Pop", "The number of times POP was not interpreted.");
EM_REG_COUNTER_USED(&pStats->StatR3FailedPop, "/EM/CPU%d/R3/Interpret/Failed/Pop", "The number of times POP was not interpreted.");
EM_REG_COUNTER_USED(&pStats->StatRZFailedSti, "/EM/CPU%d/RZ/Interpret/Failed/Sti", "The number of times STI was not interpreted.");
EM_REG_COUNTER_USED(&pStats->StatR3FailedSti, "/EM/CPU%d/R3/Interpret/Failed/Sti", "The number of times STI was not interpreted.");
EM_REG_COUNTER_USED(&pStats->StatRZFailedXchg, "/EM/CPU%d/RZ/Interpret/Failed/Xchg", "The number of times XCHG was not interpreted.");
EM_REG_COUNTER_USED(&pStats->StatR3FailedXchg, "/EM/CPU%d/R3/Interpret/Failed/Xchg", "The number of times XCHG was not interpreted.");
EM_REG_COUNTER_USED(&pStats->StatRZFailedXor, "/EM/CPU%d/RZ/Interpret/Failed/Xor", "The number of times XOR was not interpreted.");
EM_REG_COUNTER_USED(&pStats->StatR3FailedXor, "/EM/CPU%d/R3/Interpret/Failed/Xor", "The number of times XOR was not interpreted.");
EM_REG_COUNTER_USED(&pStats->StatRZFailedMonitor, "/EM/CPU%d/RZ/Interpret/Failed/Monitor", "The number of times MONITOR was not interpreted.");
EM_REG_COUNTER_USED(&pStats->StatR3FailedMonitor, "/EM/CPU%d/R3/Interpret/Failed/Monitor", "The number of times MONITOR was not interpreted.");
EM_REG_COUNTER_USED(&pStats->StatRZFailedMWait, "/EM/CPU%d/RZ/Interpret/Failed/MWait", "The number of times MONITOR was not interpreted.");
EM_REG_COUNTER_USED(&pStats->StatR3FailedMWait, "/EM/CPU%d/R3/Interpret/Failed/MWait", "The number of times MONITOR was not interpreted.");
EM_REG_COUNTER_USED(&pStats->StatRZFailedRdtsc, "/EM/CPU%d/RZ/Interpret/Failed/Rdtsc", "The number of times RDTSC was not interpreted.");
EM_REG_COUNTER_USED(&pStats->StatR3FailedRdtsc, "/EM/CPU%d/R3/Interpret/Failed/Rdtsc", "The number of times RDTSC was not interpreted.");
EM_REG_COUNTER_USED(&pStats->StatRZFailedRdpmc, "/EM/CPU%d/RZ/Interpret/Failed/Rdpmc", "The number of times RDPMC was not interpreted.");
EM_REG_COUNTER_USED(&pStats->StatR3FailedRdpmc, "/EM/CPU%d/R3/Interpret/Failed/Rdpmc", "The number of times RDPMC was not interpreted.");
EM_REG_COUNTER_USED(&pStats->StatRZFailedRdmsr, "/EM/CPU%d/RZ/Interpret/Failed/Rdmsr", "The number of times RDMSR was not interpreted.");
EM_REG_COUNTER_USED(&pStats->StatR3FailedRdmsr, "/EM/CPU%d/R3/Interpret/Failed/Rdmsr", "The number of times RDMSR was not interpreted.");
EM_REG_COUNTER_USED(&pStats->StatRZFailedWrmsr, "/EM/CPU%d/RZ/Interpret/Failed/Wrmsr", "The number of times WRMSR was not interpreted.");
EM_REG_COUNTER_USED(&pStats->StatR3FailedWrmsr, "/EM/CPU%d/R3/Interpret/Failed/Wrmsr", "The number of times WRMSR was not interpreted.");
EM_REG_COUNTER_USED(&pStats->StatRZFailedLmsw, "/EM/CPU%d/RZ/Interpret/Failed/Lmsw", "The number of times LMSW was not interpreted.");
EM_REG_COUNTER_USED(&pStats->StatR3FailedLmsw, "/EM/CPU%d/R3/Interpret/Failed/Lmsw", "The number of times LMSW was not interpreted.");
EM_REG_COUNTER_USED(&pStats->StatRZFailedMisc, "/EM/CPU%d/RZ/Interpret/Failed/Misc", "The number of times some misc instruction was encountered.");
EM_REG_COUNTER_USED(&pStats->StatR3FailedMisc, "/EM/CPU%d/R3/Interpret/Failed/Misc", "The number of times some misc instruction was encountered.");
EM_REG_COUNTER_USED(&pStats->StatRZFailedAdd, "/EM/CPU%d/RZ/Interpret/Failed/Add", "The number of times ADD was not interpreted.");
EM_REG_COUNTER_USED(&pStats->StatR3FailedAdd, "/EM/CPU%d/R3/Interpret/Failed/Add", "The number of times ADD was not interpreted.");
EM_REG_COUNTER_USED(&pStats->StatRZFailedAdc, "/EM/CPU%d/RZ/Interpret/Failed/Adc", "The number of times ADC was not interpreted.");
EM_REG_COUNTER_USED(&pStats->StatR3FailedAdc, "/EM/CPU%d/R3/Interpret/Failed/Adc", "The number of times ADC was not interpreted.");
EM_REG_COUNTER_USED(&pStats->StatRZFailedBtr, "/EM/CPU%d/RZ/Interpret/Failed/Btr", "The number of times BTR was not interpreted.");
EM_REG_COUNTER_USED(&pStats->StatR3FailedBtr, "/EM/CPU%d/R3/Interpret/Failed/Btr", "The number of times BTR was not interpreted.");
EM_REG_COUNTER_USED(&pStats->StatRZFailedBts, "/EM/CPU%d/RZ/Interpret/Failed/Bts", "The number of times BTS was not interpreted.");
EM_REG_COUNTER_USED(&pStats->StatR3FailedBts, "/EM/CPU%d/R3/Interpret/Failed/Bts", "The number of times BTS was not interpreted.");
EM_REG_COUNTER_USED(&pStats->StatRZFailedBtc, "/EM/CPU%d/RZ/Interpret/Failed/Btc", "The number of times BTC was not interpreted.");
EM_REG_COUNTER_USED(&pStats->StatR3FailedBtc, "/EM/CPU%d/R3/Interpret/Failed/Btc", "The number of times BTC was not interpreted.");
EM_REG_COUNTER_USED(&pStats->StatRZFailedCli, "/EM/CPU%d/RZ/Interpret/Failed/Cli", "The number of times CLI was not interpreted.");
EM_REG_COUNTER_USED(&pStats->StatR3FailedCli, "/EM/CPU%d/R3/Interpret/Failed/Cli", "The number of times CLI was not interpreted.");
EM_REG_COUNTER_USED(&pStats->StatRZFailedCmpXchg, "/EM/CPU%d/RZ/Interpret/Failed/CmpXchg", "The number of times CMPXCHG was not interpreted.");
EM_REG_COUNTER_USED(&pStats->StatR3FailedCmpXchg, "/EM/CPU%d/R3/Interpret/Failed/CmpXchg", "The number of times CMPXCHG was not interpreted.");
EM_REG_COUNTER_USED(&pStats->StatRZFailedCmpXchg8b, "/EM/CPU%d/RZ/Interpret/Failed/CmpXchg8b", "The number of times CMPXCHG8B was not interpreted.");
EM_REG_COUNTER_USED(&pStats->StatR3FailedCmpXchg8b, "/EM/CPU%d/R3/Interpret/Failed/CmpXchg8b", "The number of times CMPXCHG8B was not interpreted.");
EM_REG_COUNTER_USED(&pStats->StatRZFailedXAdd, "/EM/CPU%d/RZ/Interpret/Failed/XAdd", "The number of times XADD was not interpreted.");
EM_REG_COUNTER_USED(&pStats->StatR3FailedXAdd, "/EM/CPU%d/R3/Interpret/Failed/XAdd", "The number of times XADD was not interpreted.");
EM_REG_COUNTER_USED(&pStats->StatRZFailedMovNTPS, "/EM/CPU%d/RZ/Interpret/Failed/MovNTPS", "The number of times MOVNTPS was not interpreted.");
EM_REG_COUNTER_USED(&pStats->StatR3FailedMovNTPS, "/EM/CPU%d/R3/Interpret/Failed/MovNTPS", "The number of times MOVNTPS was not interpreted.");
EM_REG_COUNTER_USED(&pStats->StatRZFailedStosWD, "/EM/CPU%d/RZ/Interpret/Failed/StosWD", "The number of times STOSWD was not interpreted.");
EM_REG_COUNTER_USED(&pStats->StatR3FailedStosWD, "/EM/CPU%d/R3/Interpret/Failed/StosWD", "The number of times STOSWD was not interpreted.");
EM_REG_COUNTER_USED(&pStats->StatRZFailedSub, "/EM/CPU%d/RZ/Interpret/Failed/Sub", "The number of times SUB was not interpreted.");
EM_REG_COUNTER_USED(&pStats->StatR3FailedSub, "/EM/CPU%d/R3/Interpret/Failed/Sub", "The number of times SUB was not interpreted.");
EM_REG_COUNTER_USED(&pStats->StatRZFailedWbInvd, "/EM/CPU%d/RZ/Interpret/Failed/WbInvd", "The number of times WBINVD was not interpreted.");
EM_REG_COUNTER_USED(&pStats->StatR3FailedWbInvd, "/EM/CPU%d/R3/Interpret/Failed/WbInvd", "The number of times WBINVD was not interpreted.");
EM_REG_COUNTER_USED(&pStats->StatRZFailedUserMode, "/EM/CPU%d/RZ/Interpret/Failed/UserMode", "The number of rejections because of CPL.");
EM_REG_COUNTER_USED(&pStats->StatR3FailedUserMode, "/EM/CPU%d/R3/Interpret/Failed/UserMode", "The number of rejections because of CPL.");
EM_REG_COUNTER_USED(&pStats->StatRZFailedPrefix, "/EM/CPU%d/RZ/Interpret/Failed/Prefix", "The number of rejections because of prefix .");
EM_REG_COUNTER_USED(&pStats->StatR3FailedPrefix, "/EM/CPU%d/R3/Interpret/Failed/Prefix", "The number of rejections because of prefix .");
EM_REG_COUNTER_USED(&pStats->StatHlt, "/EM/CPU%d/R3/PrivInst/Hlt", "Number of hlt instructions not handled in GC because of PATM.");
EM_REG_COUNTER_USED(&pStats->StatInvlpg, "/EM/CPU%d/R3/PrivInst/Invlpg", "Number of invlpg instructions.");
EM_REG_COUNTER_USED(&pStats->StatMisc, "/EM/CPU%d/R3/PrivInst/Misc", "Number of misc. instructions.");
EM_REG_COUNTER_USED(&pStats->StatMovWriteCR[0], "/EM/CPU%d/R3/PrivInst/Mov CR0, X", "Number of mov CR0 read instructions.");
EM_REG_COUNTER_USED(&pStats->StatMovWriteCR[1], "/EM/CPU%d/R3/PrivInst/Mov CR1, X", "Number of mov CR1 read instructions.");
EM_REG_COUNTER_USED(&pStats->StatMovWriteCR[2], "/EM/CPU%d/R3/PrivInst/Mov CR2, X", "Number of mov CR2 read instructions.");
EM_REG_COUNTER_USED(&pStats->StatMovWriteCR[3], "/EM/CPU%d/R3/PrivInst/Mov CR3, X", "Number of mov CR3 read instructions.");
EM_REG_COUNTER_USED(&pStats->StatMovWriteCR[4], "/EM/CPU%d/R3/PrivInst/Mov CR4, X", "Number of mov CR4 read instructions.");
EM_REG_COUNTER_USED(&pStats->StatMovReadCR[0], "/EM/CPU%d/R3/PrivInst/Mov X, CR0", "Number of mov CR0 write instructions.");
EM_REG_COUNTER_USED(&pStats->StatMovReadCR[1], "/EM/CPU%d/R3/PrivInst/Mov X, CR1", "Number of mov CR1 write instructions.");
EM_REG_COUNTER_USED(&pStats->StatMovReadCR[2], "/EM/CPU%d/R3/PrivInst/Mov X, CR2", "Number of mov CR2 write instructions.");
EM_REG_COUNTER_USED(&pStats->StatMovReadCR[3], "/EM/CPU%d/R3/PrivInst/Mov X, CR3", "Number of mov CR3 write instructions.");
EM_REG_COUNTER_USED(&pStats->StatMovReadCR[4], "/EM/CPU%d/R3/PrivInst/Mov X, CR4", "Number of mov CR4 write instructions.");
EM_REG_COUNTER_USED(&pStats->StatMovDRx, "/EM/CPU%d/R3/PrivInst/MovDRx", "Number of mov DRx instructions.");
EM_REG_COUNTER_USED(&pStats->StatIret, "/EM/CPU%d/R3/PrivInst/Iret", "Number of iret instructions.");
EM_REG_COUNTER_USED(&pStats->StatMovLgdt, "/EM/CPU%d/R3/PrivInst/Lgdt", "Number of lgdt instructions.");
EM_REG_COUNTER_USED(&pStats->StatMovLidt, "/EM/CPU%d/R3/PrivInst/Lidt", "Number of lidt instructions.");
EM_REG_COUNTER_USED(&pStats->StatMovLldt, "/EM/CPU%d/R3/PrivInst/Lldt", "Number of lldt instructions.");
EM_REG_COUNTER_USED(&pStats->StatSysEnter, "/EM/CPU%d/R3/PrivInst/Sysenter", "Number of sysenter instructions.");
EM_REG_COUNTER_USED(&pStats->StatSysExit, "/EM/CPU%d/R3/PrivInst/Sysexit", "Number of sysexit instructions.");
EM_REG_COUNTER_USED(&pStats->StatSysCall, "/EM/CPU%d/R3/PrivInst/Syscall", "Number of syscall instructions.");
EM_REG_COUNTER_USED(&pStats->StatSysRet, "/EM/CPU%d/R3/PrivInst/Sysret", "Number of sysret instructions.");
EM_REG_COUNTER(&pVCpu->em.s.StatTotalClis, "/EM/CPU%d/Cli/Total", "Total number of cli instructions executed.");
/* these should be considered for release statistics. */
EM_REG_COUNTER(&pVCpu->em.s.StatIOEmu, "/PROF/CPU%d/EM/Emulation/IO", "Profiling of emR3RawExecuteIOInstruction.");
EM_REG_COUNTER(&pVCpu->em.s.StatPrivEmu, "/PROF/CPU%d/EM/Emulation/Priv", "Profiling of emR3RawPrivileged.");
EM_REG_COUNTER(&pVCpu->em.s.StatMiscEmu, "/PROF/CPU%d/EM/Emulation/Misc", "Profiling of emR3RawExecuteInstruction.");
EM_REG_PROFILE(&pVCpu->em.s.StatHwAccEntry, "/PROF/CPU%d/EM/HwAccEnter", "Profiling Hardware Accelerated Mode entry overhead.");
EM_REG_PROFILE(&pVCpu->em.s.StatHwAccExec, "/PROF/CPU%d/EM/HwAccExec", "Profiling Hardware Accelerated Mode execution.");
EM_REG_PROFILE(&pVCpu->em.s.StatREMEmu, "/PROF/CPU%d/EM/REMEmuSingle", "Profiling single instruction REM execution.");
EM_REG_PROFILE(&pVCpu->em.s.StatREMSync, "/PROF/CPU%d/EM/REMSync", "Profiling REM context syncing.");
EM_REG_PROFILE(&pVCpu->em.s.StatRAWEntry, "/PROF/CPU%d/EM/RAWEnter", "Profiling Raw Mode entry overhead.");
EM_REG_PROFILE(&pVCpu->em.s.StatRAWExec, "/PROF/CPU%d/EM/RAWExec", "Profiling Raw Mode execution.");
EM_REG_PROFILE(&pVCpu->em.s.StatRAWTail, "/PROF/CPU%d/EM/RAWTail", "Profiling Raw Mode tail overhead.");
#endif /* VBOX_WITH_STATISTICS */
EM_REG_COUNTER(&pVCpu->em.s.StatForcedActions, "/PROF/CPU%d/EM/ForcedActions", "Profiling forced action execution.");
EM_REG_COUNTER(&pVCpu->em.s.StatHalted, "/PROF/CPU%d/EM/Halted", "Profiling halted state (VMR3WaitHalted).");
EM_REG_COUNTER(&pVCpu->em.s.StatREMTotal, "/PROF/CPU%d/EM/REMTotal", "Profiling emR3RemExecute (excluding FFs).");
EM_REG_COUNTER(&pVCpu->em.s.StatRAWTotal, "/PROF/CPU%d/EM/RAWTotal", "Profiling emR3RawExecute (excluding FFs).");
}
return VINF_SUCCESS;
}
/**
* Initializes the per-VCPU EM.
*
* @returns VBox status code.
* @param pVM The VM to operate on.
*/
{
LogFlow(("EMR3InitCPU\n"));
return VINF_SUCCESS;
}
/**
* Applies relocations to data and code managed by this
* component. This function will be called at init and
* whenever the VMM need to relocate it self inside the GC.
*
* @param pVM The VM.
*/
{
LogFlow(("EMR3Relocate\n"));
{
}
}
/**
* Reset notification.
*
* @param pVM
*/
{
LogFlow(("EMR3Reset: \n"));
{
}
}
/**
* Terminates the EM.
*
* Termination means cleaning up and freeing all resources,
* the VM it self is at this point powered off or suspended.
*
* @returns VBox status code.
* @param pVM The VM to operate on.
*/
{
return VINF_SUCCESS;
}
/**
* Terminates the per-VCPU EM.
*
* Termination means cleaning up and freeing all resources,
* the VM it self is at this point powered off or suspended.
*
* @returns VBox status code.
* @param pVM The VM to operate on.
*/
{
return 0;
}
/**
* Execute state save operation.
*
* @returns VBox status code.
* @param pVM VM Handle.
* @param pSSM SSM operation handle.
*/
{
{
}
return VINF_SUCCESS;
}
/**
* Execute state load operation.
*
* @returns VBox status code.
* @param pVM VM Handle.
* @param pSSM SSM operation handle.
* @param u32Version Data layout version.
*/
{
int rc = VINF_SUCCESS;
/*
* Validate version.
*/
if ( u32Version != EM_SAVED_STATE_VERSION
{
AssertMsgFailed(("emR3Load: Invalid version u32Version=%d (current %d)!\n", u32Version, EM_SAVED_STATE_VERSION));
}
/*
* Load the saved state.
*/
{
if (RT_FAILURE(rc))
{
}
}
return rc;
}
/**
* Enables or disables a set of raw-mode execution modes.
*
* @returns VINF_SUCCESS on success.
* @returns VINF_RESCHEDULE if a rescheduling might be required.
* @returns VERR_INVALID_PARAMETER on an invalid enmMode value.
*
* @param pVM The VM to operate on.
* @param enmMode The execution mode change.
* @thread The emulation thread.
*/
{
switch (enmMode)
{
case EMRAW_NONE:
pVM->fRawR3Enabled = false;
pVM->fRawR0Enabled = false;
break;
case EMRAW_RING3_ENABLE:
pVM->fRawR3Enabled = true;
break;
case EMRAW_RING3_DISABLE:
pVM->fRawR3Enabled = false;
break;
case EMRAW_RING0_ENABLE:
pVM->fRawR0Enabled = true;
break;
case EMRAW_RING0_DISABLE:
pVM->fRawR0Enabled = false;
break;
default:
return VERR_INVALID_PARAMETER;
}
Log(("EMR3SetRawMode: fRawR3Enabled=%RTbool fRawR0Enabled=%RTbool\n",
}
/**
* Raise a fatal error.
*
* Safely terminate the VM with full state report and stuff. This function
* will naturally never return.
*
* @param pVCpu VMCPU handle.
* @param rc VBox status code.
*/
{
AssertReleaseMsgFailed(("longjmp returned!\n"));
}
/**
* Gets the EM state name.
*
* @returns pointer to read only state name,
* @param enmState The state.
*/
{
switch (enmState)
{
case EMSTATE_NONE: return "EMSTATE_NONE";
case EMSTATE_RAW: return "EMSTATE_RAW";
case EMSTATE_HWACC: return "EMSTATE_HWACC";
case EMSTATE_REM: return "EMSTATE_REM";
case EMSTATE_PARAV: return "EMSTATE_PARAV";
case EMSTATE_HALTED: return "EMSTATE_HALTED";
case EMSTATE_WAIT_SIPI: return "EMSTATE_WAIT_SIPI";
case EMSTATE_SUSPENDED: return "EMSTATE_SUSPENDED";
case EMSTATE_TERMINATING: return "EMSTATE_TERMINATING";
case EMSTATE_DEBUG_GUEST_RAW: return "EMSTATE_DEBUG_GUEST_RAW";
case EMSTATE_DEBUG_GUEST_REM: return "EMSTATE_DEBUG_GUEST_REM";
case EMSTATE_DEBUG_HYPER: return "EMSTATE_DEBUG_HYPER";
case EMSTATE_GURU_MEDITATION: return "EMSTATE_GURU_MEDITATION";
default: return "Unknown!";
}
}
#ifdef VBOX_WITH_STATISTICS
/**
* Just a braindead function to keep track of cli addresses.
* @param pVM VM handle.
* @param pVMCPU VMCPU handle.
* @param GCPtrInstr The EIP of the cli instruction.
*/
{
if (!pRec)
{
/* New cli instruction; insert into the tree. */
if (!pRec)
return;
char szCliStatName[32];
STAM_REG(pVM, &pRec->Counter, STAMTYPE_COUNTER, szCliStatName, STAMUNIT_OCCURENCES, "Number of times cli was executed.");
}
}
#endif /* VBOX_WITH_STATISTICS */
/**
* Debug loop.
*
* @returns VBox status code for EM.
* @param pVM VM handle.
* @param pVCpu VMCPU handle.
* @param rc Current EM VBox status code..
*/
{
for (;;)
{
/*
* Debug related RC.
*/
switch (rc)
{
/*
* Single step an instruction.
*/
case VINF_EM_DBG_STEP:
else
{
}
break;
/*
*/
case VINF_EM_DBG_STEPPED:
break;
case VINF_EM_DBG_BREAKPOINT:
break;
case VINF_EM_DBG_STOP:
break;
break;
break;
RTPrintf("\nVINF_EM_DBG_HYPER_ASSERTION:\n%s%s\n", VMMR3GetRZAssertMsg1(pVM), VMMR3GetRZAssertMsg2(pVM));
rc = DBGFR3EventAssertion(pVM, DBGFEVENT_ASSERTION_HYPER, VMMR3GetRZAssertMsg1(pVM), VMMR3GetRZAssertMsg2(pVM));
break;
/*
* Guru meditation.
*/
case VERR_VMM_RING0_ASSERTION: /** @todo Make a guru meditation event! */
break;
case VERR_REM_TOO_MANY_TRAPS: /** @todo Make a guru meditation event! */
break;
default: /** @todo don't use default for guru, but make special errors code! */
break;
}
/*
* Process the result.
*/
do
{
switch (rc)
{
/*
* Continue the debugging loop.
*/
case VINF_EM_DBG_STEP:
case VINF_EM_DBG_STOP:
case VINF_EM_DBG_STEPPED:
case VINF_EM_DBG_BREAKPOINT:
break;
/*
* Resuming execution (in some form) has to be done here if we got
* a hypervisor debug event.
*/
case VINF_SUCCESS:
case VINF_EM_RESUME:
case VINF_EM_SUSPEND:
case VINF_EM_RESCHEDULE:
case VINF_EM_RESCHEDULE_RAW:
case VINF_EM_RESCHEDULE_REM:
case VINF_EM_HALT:
{
continue;
}
if (rc == VINF_SUCCESS)
return rc;
/*
* The debugger isn't attached.
* We'll simply turn the thing off since that's the easiest thing to do.
*/
case VERR_DBGF_NOT_ATTACHED:
switch (rcLast)
{
case VERR_TRPM_PANIC:
case VERR_TRPM_DONT_PANIC:
case VERR_VMM_RING0_ASSERTION:
return rcLast;
}
return VINF_EM_OFF;
/*
* Status codes terminating the VM in one or another sense.
*/
case VINF_EM_TERMINATE:
case VINF_EM_OFF:
case VINF_EM_RESET:
case VINF_EM_NO_MEMORY:
case VINF_EM_RAW_IRET_TRAP:
case VERR_TRPM_PANIC:
case VERR_TRPM_DONT_PANIC:
case VERR_VMM_RING0_ASSERTION:
case VERR_INTERNAL_ERROR:
case VERR_INTERNAL_ERROR_2:
case VERR_INTERNAL_ERROR_3:
case VERR_INTERNAL_ERROR_4:
case VERR_INTERNAL_ERROR_5:
return rc;
/*
* The rest is unexpected, and will keep us here.
*/
default:
break;
}
} while (false);
} /* debug for ever */
}
/**
* Locks REM execution to a single VCpu
*
* @param pVM VM handle.
*/
{
}
/**
* Unlocks REM execution
*
* @param pVM VM handle.
*/
{
}
/**
* Steps recompiled code.
*
* @returns VBox status code. The most important ones are: VINF_EM_STEP_EVENT,
* VINF_EM_RESCHEDULE, VINF_EM_SUSPEND, VINF_EM_RESET and VINF_EM_TERMINATE.
*
* @param pVM VM handle.
* @param pVCpu VMCPU handle.
*/
{
/*
* Switch to REM, step instruction, switch back.
*/
if (RT_SUCCESS(rc))
{
}
LogFlow(("emR3RemStep: returns %Rrc cs:eip=%04x:%08x\n", rc, CPUMGetGuestCS(pVCpu), CPUMGetGuestEIP(pVCpu)));
return rc;
}
/**
* Executes recompiled code.
*
* This function contains the recompiler version of the inner
* execution loop (the outer loop being in EMR3ExecuteVM()).
*
* @returns VBox status code. The most important ones are: VINF_EM_RESCHEDULE,
* VINF_EM_SUSPEND, VINF_EM_RESET and VINF_EM_TERMINATE.
*
* @param pVM VM handle.
* @param pVCpu VMCPU handle.
* @param pfFFDone Where to store an indicator telling wheter or not
* FFs were done before returning.
*
*/
{
#ifdef LOG_ENABLED
else
Log(("EMR%d: %04X:%08X ESP=%08X IF=%d CR0=%x\n", cpl, pCtx->cs, pCtx->eip, pCtx->esp, pCtx->eflags.Bits.u1IF, (uint32_t)pCtx->cr0));
#endif
#if defined(VBOX_STRICT) && defined(DEBUG_bird)
#endif
/* Big lock, but you are not supposed to own any lock when coming in here. */
/*
* Spin till we get a forced action which returns anything but VINF_SUCCESS
* or the REM suggests raw-mode execution.
*/
*pfFFDone = false;
bool fInREMState = false;
int rc = VINF_SUCCESS;
/* Flush the recompiler TLB if the VCPU has changed. */
{
/* Also sync the entire state. */
}
for (;;)
{
/*
* Update REM state if not already in sync.
*/
if (!fInREMState)
{
if (RT_FAILURE(rc))
break;
fInREMState = true;
/*
* We might have missed the raising of VMREQ, TIMER and some other
* imporant FFs while we were busy switching the state. So, check again.
*/
if ( VM_FF_ISPENDING(pVM, VM_FF_REQUEST | VM_FF_PDM_QUEUES | VM_FF_DBGF | VM_FF_TERMINATE | VM_FF_RESET)
{
goto l_REMDoForcedActions;
}
}
/*
* Execute REM.
*/
/*
* Deal with high priority post execution FFs before doing anything else.
*/
/*
* Process the returned status code.
* (Try keep this short! Call functions!)
*/
if (rc != VINF_SUCCESS)
{
break;
if (rc != VINF_REM_INTERRUPED_FF)
{
/*
* Anything which is not known to us means an internal error
* and the termination of the VM!
*/
break;
}
}
/*
* Check and execute forced actions.
* Sync back the VM state before calling any of these.
*/
#ifdef VBOX_HIGH_RES_TIMERS_HACK
#endif
AssertCompile((VMCPU_FF_ALL_BUT_RAW_MASK & ~(VMCPU_FF_CSAM_PENDING_ACTION | VMCPU_FF_CSAM_SCAN_PAGE)) & VMCPU_FF_TIMER);
|| VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_ALL_BUT_RAW_MASK & ~(VMCPU_FF_CSAM_PENDING_ACTION | VMCPU_FF_CSAM_SCAN_PAGE)))
{
if (fInREMState)
{
fInREMState = false;
}
if ( rc != VINF_SUCCESS
&& rc != VINF_EM_RESCHEDULE_REM)
{
*pfFFDone = true;
break;
}
}
} /* The Inner Loop, recompiled execution mode version. */
/*
* Returning. Sync back the VM state if required.
*/
if (fInREMState)
{
}
return rc;
}
/**
* Resumes executing hypervisor after a debug event.
*
* This is kind of special since our current guest state is
* potentially out of sync.
*
* @returns VBox status code.
* @param pVM The VM handle.
* @param pVCpu The VMCPU handle.
*/
{
int rc;
/*
* Resume execution.
*/
Log(("emR3RawStep: cs:eip=%RTsel:%RGr efl=%RGr - returned from GC with rc=%Rrc\n", pCtx->cs, pCtx->eip, pCtx->eflags, rc));
/*
* Deal with the return code.
*/
return rc;
}
/**
* Steps rawmode.
*
* @returns VBox status code.
* @param pVM The VM handle.
* @param pVCpu The VMCPU handle.
*/
{
int rc;
#ifndef DEBUG_sandervl
Log(("emR3RawStep: cs:eip=%RTsel:%RGr efl=%RGr\n", fGuest ? CPUMGetGuestCS(pVCpu) : CPUMGetHyperCS(pVCpu),
fGuest ? CPUMGetGuestEIP(pVCpu) : CPUMGetHyperEIP(pVCpu), fGuest ? CPUMGetGuestEFlags(pVCpu) : CPUMGetHyperEFlags(pVCpu)));
#endif
if (fGuest)
{
/*
* Check vital forced actions, but ignore pending interrupts and timers.
*/
{
if (rc != VINF_SUCCESS)
return rc;
}
/*
* Set flags for single stepping.
*/
}
else
/*
* Single step.
* We do not start time or anything, if anything we should just do a few nanoseconds.
*/
do
{
else
#ifndef DEBUG_sandervl
Log(("emR3RawStep: cs:eip=%RTsel:%RGr efl=%RGr - GC rc %Rrc\n", fGuest ? CPUMGetGuestCS(pVCpu) : CPUMGetHyperCS(pVCpu),
fGuest ? CPUMGetGuestEIP(pVCpu) : CPUMGetHyperEIP(pVCpu), fGuest ? CPUMGetGuestEFlags(pVCpu) : CPUMGetHyperEFlags(pVCpu), rc));
#endif
} while ( rc == VINF_SUCCESS
|| rc == VINF_EM_RAW_INTERRUPT);
/*
* Make sure the trap flag is cleared.
* (Too bad if the guest is trying to single step too.)
*/
if (fGuest)
else
/*
* Deal with the return codes.
*/
return rc;
}
#ifdef DEBUG
/**
* Steps hardware accelerated mode.
*
* @returns VBox status code.
* @param pVM The VM handle.
* @param pVCpu The VMCPU handle.
*/
{
int rc;
VMCPU_FF_CLEAR(pVCpu, (VMCPU_FF_SELM_SYNC_GDT | VMCPU_FF_SELM_SYNC_LDT | VMCPU_FF_TRPM_SYNC_IDT | VMCPU_FF_SELM_SYNC_TSS));
/*
* Check vital forced actions, but ignore pending interrupts and timers.
*/
{
if (rc != VINF_SUCCESS)
return rc;
}
/*
* Set flags for single stepping.
*/
/*
* Single step.
* We do not start time or anything, if anything we should just do a few nanoseconds.
*/
do
{
} while ( rc == VINF_SUCCESS
|| rc == VINF_EM_RAW_INTERRUPT);
/*
* Make sure the trap flag is cleared.
* (Too bad if the guest is trying to single step too.)
*/
/*
* Deal with the return codes.
*/
return rc;
}
{
int rc = VINF_SUCCESS;
Log(("Single step BEGIN:\n"));
for (uint32_t i = 0; i < cIterations; i++)
{
if (rc != VINF_SUCCESS)
break;
}
return rc;
}
{
int rc = VINF_SUCCESS;
Log(("Single step BEGIN:\n"));
for (uint32_t i = 0; i < cIterations; i++)
{
if ( rc != VINF_SUCCESS
break;
}
}
{
Log(("Single step BEGIN:\n"));
for (uint32_t i = 0; i < cIterations; i++)
{
break;
}
Log(("Single step END:\n"));
return VINF_EM_RESCHEDULE;
}
#endif /* DEBUG */
/**
* Executes one (or perhaps a few more) instruction(s).
*
* @returns VBox status code suitable for EM.
*
* @param pVM VM handle.
* @param pVCpu VMCPU handle
* @param rcGC GC return code
* @param pszPrefix Disassembly prefix. If not NULL we'll disassemble the
* instruction and prefix the log output with this text.
*/
#ifdef LOG_ENABLED
#else
#endif
{
int rc;
/*
*
* The simple solution is to use the recompiler.
* The better solution is to disassemble the current instruction and
* try handle as many as possible without using REM.
*
*/
#ifdef LOG_ENABLED
/*
* Disassemble the instruction if requested.
*/
if (pszPrefix)
{
}
#endif /* LOG_ENABLED */
/*
* PATM is making life more interesting.
* We cannot hand anything to REM which has an EIP inside patch code. So, we'll
* tell PATM there is a trap in this code and have it take the appropriate actions
* to allow us execute the code in REM.
*/
{
switch (rc)
{
/*
* It's not very useful to emulate a single instruction and then go back to raw
* mode; just execute the whole block until IF is set again.
*/
case VINF_SUCCESS:
Log(("emR3RawExecuteInstruction: Executing instruction starting at new address %RGv IF=%d VMIF=%x\n",
{
/*
*/
Log(("PATCH: IF=1 -> emulate last instruction as it can't be interrupted!!\n"));
}
else if (rcGC == VINF_PATM_PENDING_IRQ_AFTER_IRET)
{
}
return VINF_EM_RESCHEDULE_REM;
/*
* One instruction.
*/
case VINF_PATCH_EMULATE_INSTR:
Log(("emR3RawExecuteInstruction: Emulate patched instruction at %RGv IF=%d VMIF=%x\n",
/*
* The patch was disabled, hand it to the REM.
*/
case VERR_PATCH_DISABLED:
Log(("emR3RawExecuteInstruction: Disabled patch -> new eip %RGv IF=%d VMIF=%x\n",
{
/*
*/
Log(("PATCH: IF=1 -> emulate last instruction as it can't be interrupted!!\n"));
}
return VINF_EM_RESCHEDULE_REM;
/* Force continued patch exection; usually due to write monitored stack. */
case VINF_PATCH_CONTINUE:
return VINF_SUCCESS;
default:
return VERR_IPE_UNEXPECTED_STATUS;
}
}
#if 0
/* Try our own instruction emulator before falling back to the recompiler. */
if (RT_SUCCESS(rc))
{
{
/* @todo we can do more now */
case OP_MOV:
case OP_AND:
case OP_OR:
case OP_XOR:
case OP_POP:
case OP_INC:
case OP_DEC:
case OP_XCHG:
if (RT_SUCCESS(rc))
{
#ifdef EM_NOTIFY_HWACCM
#endif
return rc;
}
if (rc != VERR_EM_INTERPRETER)
break;
}
}
#endif /* 0 */
/* Flush the recompiler TLB if the VCPU has changed. */
#ifdef EM_NOTIFY_HWACCM
#endif
return rc;
}
/**
* Executes one (or perhaps a few more) instruction(s).
* This is just a wrapper for discarding pszPrefix in non-logging builds.
*
* @returns VBox status code suitable for EM.
* @param pVM VM handle.
* @param pVCpu VMCPU handle.
* @param pszPrefix Disassembly prefix. If not NULL we'll disassemble the
* instruction and prefix the log output with this text.
* @param rcGC GC return code
*/
{
#ifdef LOG_ENABLED
#else
#endif
}
/**
* Executes one (or perhaps a few more) IO instruction(s).
*
* @returns VBox status code suitable for EM.
* @param pVM VM handle.
* @param pVCpu VMCPU handle.
*/
{
int rc;
/** @todo probably we should fall back to the recompiler; otherwise we'll go back and forth between HC & GC
* as io instructions tend to come in packages of more than one
*/
if (RT_SUCCESS(rc))
{
{
{
case OP_IN:
{
break;
}
case OP_OUT:
{
break;
}
}
}
{
{
case OP_INSB:
case OP_INSWD:
{
break;
}
case OP_OUTSB:
case OP_OUTSWD:
{
break;
}
}
}
/*
* Handled the I/O return codes.
* (The unhandled cases end up with rc == VINF_EM_RAW_EMULATE_INSTR.)
*/
if (IOM_SUCCESS(rc))
{
return rc;
}
if (rc == VINF_EM_RAW_GUEST_TRAP)
{
return rc;
}
if (RT_FAILURE(rc))
{
return rc;
}
}
}
/**
* Handle a guest context trap.
*
* @returns VBox status code suitable for EM.
* @param pVM VM handle.
* @param pVCpu VMCPU handle.
*/
{
/*
* Get the trap info.
*/
if (RT_FAILURE(rc))
{
return rc;
}
/*
* Traps can be directly forwarded in hardware accelerated mode.
*/
if (HWACCMIsEnabled(pVM))
{
#ifdef LOGGING_ENABLED
#endif
return VINF_EM_RESCHEDULE_HWACC;
}
#if 1 /* Experimental: Review, disable if it causes trouble. */
/*
* Handle traps in patch code first.
*
* We catch a few of these cases in RC before returning to R3 (#PF, #GP, #BP)
* but several traps isn't handled specially by TRPM in RC and we end up here
* instead. One example is #DE.
*/
if ( uCpl == 0
{
}
#endif
/*
* If the guest gate is marked unpatched, then we will check again if we can patch it.
* (This assumes that we've already tried and failed to dispatch the trap in
* RC for the gates that already has been patched. Which is true for most high
* volume traps, because these are handled specially, but not for odd ones like #DE.)
*/
{
Log(("emR3RawHandleRC: recheck gate %x -> valid=%d\n", u8TrapNo, TRPMR3GetGuestTrapHandler(pVM, u8TrapNo) != TRPM_INVALID_HANDLER));
/* If it was successful, then we could go back to raw mode. */
{
/* Must check pending forced actions as our IDT or GDT might be out of sync. */
{
return VINF_EM_RESCHEDULE_RAW;
}
}
}
/*
* Scan kernel code that traps; we might not get another chance.
*/
/** @todo move this up before the dispatching? */
{
}
/*
* Trap specific handling.
*/
{
/*
* If MONITOR & MWAIT are supported, then interpret them here.
*/
if ( RT_SUCCESS(rc)
{
{
if (RT_SUCCESS(rc))
{
#ifdef EM_NOTIFY_HWACCM
#endif
return rc;
}
}
}
}
{
/*
* Handle I/O bitmap?
*/
/** @todo We're not supposed to be here with a false guest trap concerning
* I/O access. We can easily handle those in RC. */
if ( RT_SUCCESS(rc)
{
/*
* We should really check the TSS for the IO bitmap, but it's not like this
* lazy approach really makes things worse.
*/
}
}
#ifdef LOG_ENABLED
/* Get guest page information. */
Log(("emR3RawGuestTrap: cs:eip=%04x:%08x: trap=%02x err=%08x cr2=%08x cr0=%08x%s: Phys=%RGp fFlags=%08llx %s %s %s%s rc2=%d\n",
pCtx->cs, pCtx->eip, u8TrapNo, uErrorCode, uCR2, (uint32_t)pCtx->cr0, (enmType == TRPM_SOFTWARE_INT) ? " software" : "", GCPhys, fFlags,
#endif
/*
* #PG has CR2.
* (Because of stuff like above we must set CR2 in a delayed fashion.)
*/
return VINF_EM_RESCHEDULE_REM;
}
/**
* Handle a ring switch trap.
* Need to do statistics and to install patches. The result is going to REM.
*
* @returns VBox status code suitable for EM.
* @param pVM VM handle.
* @param pVCpu VMCPU handle.
*/
{
int rc;
/*
* sysenter, syscall & callgate
*/
if (RT_SUCCESS(rc))
{
{
{
(SELMGetCpuModeFromSelector(pVM, pCtx->eflags, pCtx->cs, &pCtx->csHid) == CPUMODE_32BIT) ? PATMFL_CODE32 : 0);
if (RT_SUCCESS(rc))
{
return VINF_EM_RESCHEDULE_RAW;
}
}
}
#ifdef VBOX_WITH_STATISTICS
{
case OP_SYSENTER:
break;
case OP_SYSEXIT:
break;
case OP_SYSCALL:
break;
case OP_SYSRET:
break;
}
#endif
}
else
/* go to the REM to emulate a single instruction */
}
/**
* Handle a trap (\#PF or \#GP) in patch code
*
* @returns VBox status code suitable for EM.
* @param pVM VM handle.
* @param pVCpu VMCPU handle.
* @param pCtx CPU context
* @param gcret GC return code
*/
{
int rc;
if (gcret == VINF_PATM_PATCH_INT3)
{
u8TrapNo = 3;
uCR2 = 0;
uErrorCode = 0;
}
else if (gcret == VINF_PATM_PATCH_TRAP_GP)
{
/* No active trap in this case. Kind of ugly. */
uCR2 = 0;
uErrorCode = 0;
}
else
{
if (RT_FAILURE(rc))
{
return rc;
}
/* Reset the trap as we'll execute the original instruction again. */
}
/*
* Deal with traps inside patch code.
* (This code won't run outside GC.)
*/
if (u8TrapNo != 1)
{
#ifdef LOG_ENABLED
int rc;
if ( RT_SUCCESS(rc)
{
/* Iret crashes are bad as we have already changed the flags on the stack */
if (rc == VINF_SUCCESS)
{
if ( (uEFlags & X86_EFL_VM)
{
if (uEFlags & X86_EFL_VM)
{
if (rc == VINF_SUCCESS)
{
Log(("Patch code: IRET->VM stack frame: return address %04X:%08RX32 eflags=%08x ss:esp=%04X:%08RX32\n", selCS, eip, uEFlags, selSS, esp));
Log(("Patch code: IRET->VM stack frame: DS=%04X ES=%04X FS=%04X GS=%04X\n", selDS, selES, selFS, selGS));
}
}
else
Log(("Patch code: IRET stack frame: return address %04X:%08RX32 eflags=%08x ss:esp=%04X:%08RX32\n", selCS, eip, uEFlags, selSS, esp));
}
else
Log(("Patch code: IRET stack frame: return address %04X:%08RX32 eflags=%08x\n", selCS, eip, uEFlags));
}
}
#endif /* LOG_ENABLED */
Log(("emR3PatchTrap: in patch: eip=%08x: trap=%02x err=%08x cr2=%08x cr0=%08x\n",
switch (rc)
{
/*
* Execute the faulting instruction.
*/
case VINF_SUCCESS:
{
/** @todo execute a whole block */
Log(("emR3PatchTrap: Virtual IF flag disabled!!\n"));
{
/* Windows XP lets irets fault intentionally and then takes action based on the opcode; an
* int3 patch overwrites it and leads to blue screens. Remove the patch in this case.
*/
if ( u8TrapNo == X86_XCPT_GP
{
/** @todo move to PATMR3HandleTrap */
}
/** @todo Knoppix 5 regression when returning VINF_SUCCESS here and going back to raw mode. */
/* Note: possibly because a reschedule is required (e.g. iret to V86 code) */
/* Interrupts are enabled; just go back to the original instruction.
return VINF_SUCCESS; */
}
return VINF_EM_RESCHEDULE_REM;
}
/*
* One instruction.
*/
case VINF_PATCH_EMULATE_INSTR:
Log(("emR3PatchTrap: Emulate patched instruction at %RGv IF=%d VMIF=%x\n",
/*
* The patch was disabled, hand it to the REM.
*/
case VERR_PATCH_DISABLED:
Log(("emR3PatchTrap: Virtual IF flag disabled!!\n"));
{
/*
*/
Log(("PATCH: IF=1 -> emulate last instruction as it can't be interrupted!!\n"));
}
return VINF_EM_RESCHEDULE_REM;
/* Force continued patch exection; usually due to write monitored stack. */
case VINF_PATCH_CONTINUE:
return VINF_SUCCESS;
/*
* Anything else is *fatal*.
*/
default:
return VERR_IPE_UNEXPECTED_STATUS;
}
}
return VINF_SUCCESS;
}
/**
* Handle a privileged instruction.
*
* @returns VBox status code suitable for EM.
* @param pVM VM handle.
* @param pVCpu VMCPU handle;
*/
{
if (PATMIsEnabled(pVM))
{
/*
* Check if in patch code.
*/
{
#ifdef LOG_ENABLED
#endif
AssertMsgFailed(("FATAL ERROR: executing random instruction inside generated patch jump %08X\n", pCtx->eip));
return VERR_EM_RAW_PATCH_CONFLICT;
}
{
(SELMGetCpuModeFromSelector(pVM, pCtx->eflags, pCtx->cs, &pCtx->csHid) == CPUMODE_32BIT) ? PATMFL_CODE32 : 0);
if (RT_SUCCESS(rc))
{
#ifdef LOG_ENABLED
#endif
return VINF_SUCCESS;
}
}
}
#ifdef LOG_ENABLED
{
}
#endif
/*
* Instruction statistics and logging.
*/
int rc;
if (RT_SUCCESS(rc))
{
#ifdef VBOX_WITH_STATISTICS
{
case OP_INVLPG:
break;
case OP_IRET:
break;
case OP_CLI:
break;
case OP_STI:
break;
case OP_INSB:
case OP_INSWD:
case OP_IN:
case OP_OUTSB:
case OP_OUTSWD:
case OP_OUT:
AssertMsgFailed(("Unexpected privileged exception due to port IO\n"));
break;
case OP_MOV_CR:
{
//read
}
else
{
//write
}
break;
case OP_MOV_DR:
break;
case OP_LLDT:
break;
case OP_LIDT:
break;
case OP_LGDT:
break;
case OP_SYSENTER:
break;
case OP_SYSEXIT:
break;
case OP_SYSCALL:
break;
case OP_SYSRET:
break;
case OP_HLT:
break;
default:
break;
}
#endif /* VBOX_WITH_STATISTICS */
{
{
case OP_CLI:
return VINF_EM_RESCHEDULE_REM; /* must go to the recompiler now! */
case OP_STI:
return VINF_SUCCESS;
case OP_HLT:
{
if (enmState == PATMTRANS_OVERWRITTEN)
{
/* Conflict detected, patch disabled */
}
/* The translation had better be successful. Otherwise we can't recover. */
AssertReleaseMsg(pOrgInstrGC && enmState != PATMTRANS_OVERWRITTEN, ("Unable to translate instruction address at %08RX32\n", pCtx->eip));
if (enmState != PATMTRANS_OVERWRITTEN)
}
/* no break; we could just return VINF_EM_HALT here */
case OP_MOV_CR:
case OP_MOV_DR:
#ifdef LOG_ENABLED
{
}
#endif
if (RT_SUCCESS(rc))
{
#ifdef EM_NOTIFY_HWACCM
#endif
)
{
/* Deal with CR0 updates inside patch code that force
* us to go to the recompiler.
*/
{
Log(("Force recompiler switch due to cr0 (%RGp) update rip=%RGv -> %RGv (enmState=%d)\n", pCtx->cr0, pCtx->rip, pOrgInstrGC, enmState));
if (enmState == PATMTRANS_OVERWRITTEN)
{
/* Conflict detected, patch disabled */
}
/* The translation had better be successful. Otherwise we can't recover. */
AssertReleaseMsg(pOrgInstrGC && enmState != PATMTRANS_OVERWRITTEN, ("Unable to translate instruction address at %RGv\n", (RTGCPTR)pCtx->rip));
if (enmState != PATMTRANS_OVERWRITTEN)
}
return VINF_EM_RESCHEDULE;
}
return rc; /* can return VINF_EM_HALT as well. */
}
break; /* fall back to the recompiler */
}
}
}
}
/**
* Update the forced rawmode execution modifier.
*
* This function is called when we're returning from the raw-mode loop(s). If we're
* in patch code, it will set a flag forcing execution to be resumed in raw-mode,
* if not in patch code, the flag will be cleared.
*
* We should never interrupt patch code while it's being executed. Cli patches can
* contain big code blocks, but they are always executed with IF=0. Other patches
* replace single instructions and should be atomic.
*
* @returns Updated rc.
*
* @param pVM The VM handle.
* @param pVCpu The VMCPU handle.
* @param pCtx The guest CPU context.
* @param rc The result code.
*/
{
{
/* ignore reschedule attempts. */
switch (rc)
{
case VINF_EM_RESCHEDULE:
case VINF_EM_RESCHEDULE_REM:
LogFlow(("emR3RawUpdateForceFlag: patch address -> force raw reschedule\n"));
rc = VINF_SUCCESS;
break;
}
}
else
return rc;
}
/**
* Process a subset of the raw-mode return code.
*
* Since we have to share this with raw-mode single stepping, this inline
* function has been created to avoid code duplication.
*
* @returns VINF_SUCCESS if it's ok to continue raw mode.
* @returns VBox status code to return to the EM main loop.
*
* @param pVM The VM handle
* @param pVCpu The VMCPU handle
* @param rc The return code.
* @param pCtx The guest cpu context.
*/
{
switch (rc)
{
/*
* Common & simple ones.
*/
case VINF_SUCCESS:
break;
case VINF_EM_RESCHEDULE_RAW:
case VINF_EM_RESCHEDULE_HWACC:
case VINF_EM_RAW_INTERRUPT:
case VINF_EM_RAW_TO_R3:
case VINF_EM_PENDING_REQUEST:
rc = VINF_SUCCESS;
break;
/*
* Privileged instruction.
*/
case VINF_PATM_PATCH_TRAP_GP:
break;
/*
* Got a trap which needs dispatching.
*/
case VINF_EM_RAW_GUEST_TRAP:
{
AssertReleaseMsgFailed(("FATAL ERROR: executing random instruction inside generated patch jump %08X\n", CPUMGetGuestEIP(pVCpu)));
break;
}
break;
/*
* Trap in patch code.
*/
case VINF_PATM_PATCH_TRAP_PF:
case VINF_PATM_PATCH_INT3:
break;
rc = VINF_SUCCESS;
break;
rc = VINF_SUCCESS;
break;
/*
* Patch manager.
*/
break;
#ifdef VBOX_WITH_VMI
/*
* PARAV function.
*/
case VINF_EM_RESCHEDULE_PARAV:
break;
#endif
/*
* Memory mapped I/O access - attempt to patch the instruction
*/
PATMFL_MMIO_ACCESS | ((SELMGetCpuModeFromSelector(pVM, pCtx->eflags, pCtx->cs, &pCtx->csHid) == CPUMODE_32BIT) ? PATMFL_CODE32 : 0));
if (RT_FAILURE(rc))
break;
AssertFailed(); /* not yet implemented. */
break;
/*
* Conflict or out of page tables.
*
* VM_FF_PGM_SYNC_CR3 is set by the hypervisor and all we need to
* do here is to execute the pending forced actions.
*/
case VINF_PGM_SYNC_CR3:
("VINF_PGM_SYNC_CR3 and no VMCPU_FF_PGM_SYNC_CR3*!\n"));
rc = VINF_SUCCESS;
break;
/*
* Paging mode change.
*/
case VINF_PGM_CHANGE_MODE:
if (rc == VINF_SUCCESS)
break;
/*
* CSAM wants to perform a task in ring-3. It has set an FF action flag.
*/
case VINF_CSAM_PENDING_ACTION:
rc = VINF_SUCCESS;
break;
/*
* Invoked Interrupt gate - must directly (!) go to the recompiler.
*/
if (TRPMHasTrap(pVCpu))
{
/* If the guest gate is marked unpatched, then we will check again if we can patch it. */
{
Log(("emR3RawHandleRC: recheck gate %x -> valid=%d\n", u8Interrupt, TRPMR3GetGuestTrapHandler(pVM, u8Interrupt) != TRPM_INVALID_HANDLER));
/* Note: If it was successful, then we could go back to raw mode, but let's keep things simple for now. */
}
}
break;
/*
* Other ring switch types.
*/
case VINF_EM_RAW_RING_SWITCH:
break;
/*
* REMGCNotifyInvalidatePage() failed because of overflow.
*/
rc = VINF_SUCCESS;
break;
/*
* I/O Port access - emulate the instruction.
*/
case VINF_IOM_HC_IOPORT_READ:
case VINF_IOM_HC_IOPORT_WRITE:
break;
/*
* Memory mapped I/O access - emulate the instruction.
*/
case VINF_IOM_HC_MMIO_READ:
case VINF_IOM_HC_MMIO_WRITE:
break;
/*
* (MM)IO intensive code block detected; fall back to the recompiler for better performance
*/
break;
/*
* Execute instruction.
*/
break;
break;
break;
break;
break;
/** @todo skip instruction and go directly to the halt state. (see REM for implementation details) */
break;
break;
case VINF_PATCH_EMULATE_INSTR:
break;
/*
* Stale selector and iret traps => REM.
*/
case VINF_EM_RAW_IRET_TRAP:
/* We will not go to the recompiler if EIP points to patch code. */
{
}
break;
/*
* Up a level.
*/
case VINF_EM_TERMINATE:
case VINF_EM_OFF:
case VINF_EM_RESET:
case VINF_EM_SUSPEND:
case VINF_EM_HALT:
case VINF_EM_RESUME:
case VINF_EM_NO_MEMORY:
case VINF_EM_RESCHEDULE:
case VINF_EM_RESCHEDULE_REM:
case VINF_EM_WAIT_SIPI:
break;
/*
* Up a level and invoke the debugger.
*/
case VINF_EM_DBG_STEPPED:
case VINF_EM_DBG_BREAKPOINT:
case VINF_EM_DBG_STEP:
case VINF_EM_DBG_STOP:
break;
/*
* Up a level, dump and debug.
*/
case VERR_TRPM_DONT_PANIC:
case VERR_TRPM_PANIC:
case VERR_VMM_RING0_ASSERTION:
break;
/*
* Up a level, after HwAccM have done some release logging.
*/
break;
/*
* Anything which is not known to us means an internal error
* and the termination of the VM!
*/
default:
break;
}
return rc;
}
/**
* Check for pending raw actions
*
* @returns VBox status code. May return VINF_EM_NO_MEMORY but none of the other
* EM statuses.
* @param pVM The VM to operate on.
* @param pVCpu The VMCPU handle.
*/
{
}
/**
* Process raw-mode specific forced actions.
*
* This function is called when any FFs in the VM_FF_HIGH_PRIORITY_PRE_RAW_MASK is pending.
*
* @returns VBox status code. May return VINF_EM_NO_MEMORY but none of the other
* EM statuses.
* @param pVM The VM handle.
* @param pVCpu The VMCPU handle.
* @param pCtx The guest CPUM register context.
*/
{
/*
* Note that the order is *vitally* important!
* Also note that SELMR3UpdateFromCPUM may trigger VM_FF_SELM_SYNC_TSS.
*/
/*
* Sync selector tables.
*/
{
if (RT_FAILURE(rc))
return rc;
}
/*
* Sync IDT.
*
* The CSAMR3CheckGates call in TRPMR3SyncIDT may call PGMPrefetchPage
* and PGMShwModifyPage, so we're in for trouble if for instance a
* PGMSyncCR3+pgmPoolClearAll is pending.
*/
{
&& CSAMIsEnabled(pVM))
{
int rc = PGMSyncCR3(pVCpu, pCtx->cr0, pCtx->cr3, pCtx->cr4, VMCPU_FF_ISSET(pVCpu, VMCPU_FF_PGM_SYNC_CR3));
if (RT_FAILURE(rc))
return rc;
}
if (RT_FAILURE(rc))
return rc;
}
/*
* Sync TSS.
*/
{
if (RT_FAILURE(rc))
return rc;
}
/*
* Sync page directory.
*/
{
int rc = PGMSyncCR3(pVCpu, pCtx->cr0, pCtx->cr3, pCtx->cr4, VMCPU_FF_ISSET(pVCpu, VMCPU_FF_PGM_SYNC_CR3));
if (RT_FAILURE(rc))
return rc;
/* Prefetch pages for EIP and ESP. */
/** @todo This is rather expensive. Should investigate if it really helps at all. */
if (rc == VINF_SUCCESS)
if (rc != VINF_SUCCESS)
{
if (rc != VINF_PGM_SYNC_CR3)
{
return rc;
}
rc = PGMSyncCR3(pVCpu, pCtx->cr0, pCtx->cr3, pCtx->cr4, VMCPU_FF_ISSET(pVCpu, VMCPU_FF_PGM_SYNC_CR3));
if (RT_FAILURE(rc))
return rc;
}
/** @todo maybe prefetch the supervisor stack page as well */
}
/*
* Allocate handy pages (just in case the above actions have consumed some pages).
*/
{
if (RT_FAILURE(rc))
return rc;
}
/*
* Check whether we're out of memory now.
*
* This may stem from some of the above actions or operations that has been executed
* since we ran FFs. The allocate handy pages must for instance always be followed by
* this check.
*/
return VINF_EM_NO_MEMORY;
return VINF_SUCCESS;
}
/**
* Executes raw code.
*
* This function contains the raw-mode version of the inner
* execution loop (the outer loop being in EMR3ExecuteVM()).
*
* @returns VBox status code. The most important ones are: VINF_EM_RESCHEDULE,
* VINF_EM_RESCHEDULE_REM, VINF_EM_SUSPEND, VINF_EM_RESET and VINF_EM_TERMINATE.
*
* @param pVM VM handle.
* @param pVCpu VMCPU handle.
* @param pfFFDone Where to store an indicator telling whether or not
* FFs were done before returning.
*/
{
int rc = VERR_INTERNAL_ERROR;
*pfFFDone = false;
/*
*
* Spin till we get a forced action or raw mode status code resulting in
* in anything but VINF_SUCCESS or VINF_EM_RESCHEDULE_RAW.
*
*/
for (;;)
{
/*
* Check various preconditions.
*/
#ifdef VBOX_STRICT
&& PGMMapHasConflicts(pVM))
{
AssertMsgFailed(("We should not get conflicts any longer!!!\n"));
return VERR_INTERNAL_ERROR;
}
#endif /* VBOX_STRICT */
/*
* Process high priority pre-execution raw-mode FFs.
*/
{
if (rc != VINF_SUCCESS)
break;
}
/*
* If we're going to execute ring-0 code, the guest state needs to
* and perhaps EIP) needs to be stored with PATM.
*/
if (rc != VINF_SUCCESS)
{
break;
}
/*
* Scan code before executing it. Don't bother with user mode or V86 code
*/
{
{
if (rc != VINF_SUCCESS)
{
break;
}
}
}
#ifdef LOG_ENABLED
/*
* Log important stuff before entering GC.
*/
Log(("RV86: %04X:%08X IF=%d VMFlags=%x\n", pCtx->cs, pCtx->eip, pCtx->eflags.Bits.u1IF, pGCState->uVMFlags));
{
Log(("RR0: %08X ESP=%08X IF=%d VMFlags=%x PIF=%d CPL=%d (Scanned=%d)\n", pCtx->eip, pCtx->esp, pCtx->eflags.Bits.u1IF, pGCState->uVMFlags, pGCState->fPIF, (pCtx->ss & X86_SEL_RPL), fCSAMScanned));
}
Log(("RR3: %08X ESP=%08X IF=%d VMFlags=%x\n", pCtx->eip, pCtx->esp, pCtx->eflags.Bits.u1IF, pGCState->uVMFlags));
#endif /* LOG_ENABLED */
/*
* Execute the code.
*/
LogFlow(("RR0-E: %08X ESP=%08X IF=%d VMFlags=%x PIF=%d CPL=%d\n", pCtx->eip, pCtx->esp, pCtx->eflags.Bits.u1IF, pGCState->uVMFlags, pGCState->fPIF, (pCtx->ss & X86_SEL_RPL)));
/*
* Restore the real CPU state and deal with high priority post
* execution FFs before doing anything else.
*/
#ifdef VBOX_STRICT
/*
* Assert TSS consistency & rc vs patch code.
*/
if ( !VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_SELM_SYNC_TSS | VMCPU_FF_SELM_SYNC_GDT) /* GDT implies TSS at the moment. */
&& EMIsRawRing0Enabled(pVM))
switch (rc)
{
case VINF_SUCCESS:
case VINF_EM_RAW_INTERRUPT:
case VINF_PATM_PATCH_TRAP_PF:
case VINF_PATM_PATCH_TRAP_GP:
case VINF_PATM_PATCH_INT3:
case VINF_EM_RAW_GUEST_TRAP:
case VINF_EM_RESCHEDULE_RAW:
break;
default:
LogIt(NULL, 0, LOG_GROUP_PATM, ("Patch code interrupted at %RRv for reason %Rrc\n", (RTRCPTR)CPUMGetGuestEIP(pVCpu), rc));
break;
}
/*
* Let's go paranoid!
*/
&& PGMMapHasConflicts(pVM))
{
return VERR_INTERNAL_ERROR;
}
#endif /* VBOX_STRICT */
/*
* Process the returned status code.
*/
{
break;
}
if (rc != VINF_SUCCESS)
{
if (rc != VINF_SUCCESS)
{
break;
}
}
/*
* Check and execute forced actions.
*/
#ifdef VBOX_HIGH_RES_TIMERS_HACK
#endif
{
if ( rc != VINF_SUCCESS
&& rc != VINF_EM_RESCHEDULE_RAW)
{
if (rc != VINF_SUCCESS)
{
*pfFFDone = true;
break;
}
}
}
}
/*
* Return to outer loop.
*/
#if defined(LOG_ENABLED) && defined(DEBUG)
#endif
return rc;
}
/**
* Executes hardware accelerated raw code. (Intel VMX & AMD SVM)
*
* This function contains the raw-mode version of the inner
* execution loop (the outer loop being in EMR3ExecuteVM()).
*
* @returns VBox status code. The most important ones are: VINF_EM_RESCHEDULE, VINF_EM_RESCHEDULE_RAW,
* VINF_EM_RESCHEDULE_REM, VINF_EM_SUSPEND, VINF_EM_RESET and VINF_EM_TERMINATE.
*
* @param pVM VM handle.
* @param pVCpu VMCPU handle.
* @param pfFFDone Where to store an indicator telling whether or not
* FFs were done before returning.
*/
{
int rc = VERR_INTERNAL_ERROR;
*pfFFDone = false;
#ifdef EM_NOTIFY_HWACCM
#endif
/*
* Spin till we get a forced action which returns anything but VINF_SUCCESS.
*/
for (;;)
{
/*
* Process high priority pre-execution raw-mode FFs.
*/
VMCPU_FF_CLEAR(pVCpu, (VMCPU_FF_SELM_SYNC_GDT | VMCPU_FF_SELM_SYNC_LDT | VMCPU_FF_TRPM_SYNC_IDT | VMCPU_FF_SELM_SYNC_TSS)); /* not relevant in HWACCM mode; shouldn't be set really. */
{
if (rc != VINF_SUCCESS)
break;
}
#ifdef LOG_ENABLED
/*
* Log important stuff before entering GC.
*/
if (TRPMHasTrap(pVCpu))
Log(("CPU%d: Pending hardware interrupt=0x%x cs:rip=%04X:%RGv\n", pVCpu->idCpu, TRPMGetTrapNo(pVCpu), pCtx->cs, (RTGCPTR)pCtx->rip));
{
else if (CPUMIsGuestIn64BitCodeEx(pCtx))
Log(("HWR%d: %04X:%RGv ESP=%RGv IF=%d IOPL=%d CR0=%x CR4=%x EFER=%x\n", cpl, pCtx->cs, (RTGCPTR)pCtx->rip, pCtx->rsp, pCtx->eflags.Bits.u1IF, pCtx->eflags.Bits.u2IOPL, (uint32_t)pCtx->cr0, (uint32_t)pCtx->cr4, (uint32_t)pCtx->msrEFER));
else
Log(("HWR%d: %04X:%08X ESP=%08X IF=%d IOPL=%d CR0=%x CR4=%x EFER=%x\n", cpl, pCtx->cs, pCtx->eip, pCtx->esp, pCtx->eflags.Bits.u1IF, pCtx->eflags.Bits.u2IOPL, (uint32_t)pCtx->cr0, (uint32_t)pCtx->cr4, (uint32_t)pCtx->msrEFER));
}
else
{
else if (CPUMIsGuestIn64BitCodeEx(pCtx))
Log(("HWR%d-CPU%d: %04X:%RGv ESP=%RGv IF=%d IOPL=%d CR0=%x CR4=%x EFER=%x\n", cpl, pVCpu->idCpu, pCtx->cs, (RTGCPTR)pCtx->rip, pCtx->rsp, pCtx->eflags.Bits.u1IF, pCtx->eflags.Bits.u2IOPL, (uint32_t)pCtx->cr0, (uint32_t)pCtx->cr4, (uint32_t)pCtx->msrEFER));
else
Log(("HWR%d-CPU%d: %04X:%08X ESP=%08X IF=%d IOPL=%d CR0=%x CR4=%x EFER=%x\n", cpl, pVCpu->idCpu, pCtx->cs, pCtx->eip, pCtx->esp, pCtx->eflags.Bits.u1IF, pCtx->eflags.Bits.u2IOPL, (uint32_t)pCtx->cr0, (uint32_t)pCtx->cr4, (uint32_t)pCtx->msrEFER));
}
#endif /* LOG_ENABLED */
/*
* Execute the code.
*/
/*
* Deal with high priority post execution FFs before doing anything else.
*/
/*
* Process the returned status code.
*/
break;
if (rc != VINF_SUCCESS)
break;
/*
* Check and execute forced actions.
*/
#ifdef VBOX_HIGH_RES_TIMERS_HACK
#endif
{
if ( rc != VINF_SUCCESS
&& rc != VINF_EM_RESCHEDULE_HWACC)
{
*pfFFDone = true;
break;
}
}
}
/*
* Return to outer loop.
*/
#if defined(LOG_ENABLED) && defined(DEBUG)
#endif
return rc;
}
/**
* Decides whether to execute RAW, HWACC or REM.
*
* @returns new EM state
* @param pVM The VM.
* @param pVCpu The VMCPU handle.
* @param pCtx The CPU context.
*/
{
/*
* When forcing raw-mode execution, things are simple.
*/
return EMSTATE_RAW;
/*
* We stay in the wait for SIPI state unless explicitly told otherwise.
*/
return EMSTATE_WAIT_SIPI;
/* !!! THIS MUST BE IN SYNC WITH remR3CanExecuteRaw !!! */
/* !!! THIS MUST BE IN SYNC WITH remR3CanExecuteRaw !!! */
/* !!! THIS MUST BE IN SYNC WITH remR3CanExecuteRaw !!! */
if (HWACCMIsEnabled(pVM))
{
/* Hardware accelerated raw-mode:
*
* Typically only 32-bits protected mode, with paging enabled, code is allowed here.
*/
return EMSTATE_HWACC;
/* Note: Raw mode and hw accelerated mode are incompatible. The latter turns
* off monitoring features essential for raw mode! */
return EMSTATE_REM;
}
/*
* Standard raw-mode:
*
* Here we only support 16 & 32 bits protected mode ring 3 code that has no IO privileges
* or 32 bits protected mode ring 0 code
*
* The tests are ordered by the likelyhood of being true during normal execution.
*/
{
return EMSTATE_REM;
}
#ifndef VBOX_RAW_V86
Log2(("raw mode refused: VM_MASK\n"));
return EMSTATE_REM;
}
#endif
/** @todo check up the X86_CR0_AM flag in respect to raw mode!!! We're probably not emulating it right! */
{
//Log2(("raw mode refused: %s%s%s\n", (u32CR0 & X86_CR0_PG) ? "" : " !PG", (u32CR0 & X86_CR0_PE) ? "" : " !PE", (u32CR0 & X86_CR0_AM) ? "" : " !AM"));
return EMSTATE_REM;
}
{
if (!(u32Features & X86_CPUID_FEATURE_EDX_PAE))
return EMSTATE_REM;
}
{
if (!EMIsRawRing3Enabled(pVM))
return EMSTATE_REM;
{
Log2(("raw mode refused: IF (RawR3)\n"));
return EMSTATE_REM;
}
{
Log2(("raw mode refused: CR0.WP + RawR0\n"));
return EMSTATE_REM;
}
}
else
{
if (!EMIsRawRing0Enabled(pVM))
return EMSTATE_REM;
/* Only ring 0 supervisor code. */
if ((uSS & X86_SEL_RPL) != 0)
{
return EMSTATE_REM;
}
// Let's start with pure 32 bits ring 0 code first
/** @todo What's pure 32-bit mode? flat? */
{
return EMSTATE_REM;
}
/* Write protection must be turned on, or else the guest can overwrite our hypervisor code and data. */
if (!(u32CR0 & X86_CR0_WP))
{
Log2(("raw r0 mode refused: CR0.WP=0!\n"));
return EMSTATE_REM;
}
{
Log2(("raw r0 mode forced: patch code\n"));
return EMSTATE_RAW;
}
#if !defined(VBOX_ALLOW_IF0) && !defined(VBOX_RUN_INTERRUPT_GATE_HANDLERS)
{
////Log2(("R0: IF=0 VIF=%d %08X\n", eip, pVMeflags));
//Log2(("RR0: Interrupts turned off; fall back to emulation\n"));
return EMSTATE_REM;
}
#endif
/** @todo still necessary??? */
{
return EMSTATE_REM;
}
}
return EMSTATE_RAW;
}
/**
* Executes all high priority post execution force actions.
*
* @returns rc or a fatal status code.
*
* @param pVM VM handle.
* @param pVCpu VMCPU handle.
* @param rc The current rc.
*/
{
{
if ( rc > VINF_EM_NO_MEMORY
&& rc <= VINF_EM_LAST)
}
return rc;
}
/**
* Executes all pending forced actions.
*
* Forced actions can cause execution delays and execution
* rescheduling. The first we deal with using action priority, so
* that for instance pending timers aren't scheduled and ran until
* right before execution. The rescheduling we deal with using
* return codes. The same goes for VM termination, only in that case
* we exit everything.
*
* @returns VBox status code of equal or greater importance/severity than rc.
* The most important ones are: VINF_EM_RESCHEDULE,
* VINF_EM_SUSPEND, VINF_EM_RESET and VINF_EM_TERMINATE.
*
* @param pVM VM handle.
* @param pVCpu VMCPU handle.
* @param rc The current rc.
*
*/
{
#ifdef VBOX_STRICT
int rcIrq = VINF_SUCCESS;
#endif
int rc2;
#define UPDATE_RC() \
do { \
AssertMsg(rc2 <= 0 || (rc2 >= VINF_EM_FIRST && rc2 <= VINF_EM_LAST), ("Invalid FF return code: %Rra\n", rc2)); \
break; \
} while (0)
/*
* Post execution chunk first.
*/
{
/*
* Termination request.
*/
{
Log2(("emR3ForcedActions: returns VINF_EM_TERMINATE\n"));
return VINF_EM_TERMINATE;
}
/*
* Debugger Facility polling.
*/
{
UPDATE_RC();
}
/*
* Postponed reset request.
*/
{
UPDATE_RC();
}
/*
* CSAM page scanning.
*/
{
/** @todo: check for 16 or 32 bits code! (D bit in the code selector) */
Log(("Forced action VMCPU_FF_CSAM_SCAN_PAGE\n"));
}
/*
* Out of memory? Putting this after CSAM as it may in theory cause us to run out of memory.
*/
{
UPDATE_RC();
if (rc == VINF_EM_NO_MEMORY)
return rc;
}
/* check that we got them all */
AssertCompile(VM_FF_NORMAL_PRIORITY_POST_MASK == (VM_FF_TERMINATE | VM_FF_DBGF | VM_FF_RESET | VM_FF_PGM_NO_MEMORY));
}
/*
* Normal priority then.
* (Executed in no particular order.)
*/
{
/*
* PDM Queues are pending.
*/
/*
* PDM DMA transfers are pending.
*/
/*
* Requests from other threads.
*/
{
{
return rc2;
}
UPDATE_RC();
}
/* Replay the handler notification changes. */
{
}
/* check that we got them all */
AssertCompile(VM_FF_NORMAL_PRIORITY_MASK == (VM_FF_REQUEST | VM_FF_PDM_QUEUES | VM_FF_PDM_DMA | VM_FF_REM_HANDLER_NOTIFY));
}
/*
* Normal priority then. (per-VCPU)
* (Executed in no particular order.)
*/
{
/*
* Requests from other threads.
*/
{
{
return rc2;
}
UPDATE_RC();
}
/* check that we got them all */
}
/*
* High priority pre execution chunk last.
* (Executed in ascending priority order.)
*/
{
/*
* Timers before interrupts.
*/
/*
* The instruction following an emulated STI should *always* be executed!
*/
{
Log(("VM_FF_EMULATED_STI at %RGv successor %RGv\n", (RTGCPTR)CPUMGetGuestRIP(pVCpu), EMGetInhibitInterruptsPC(pVCpu)));
{
/* Note: we intentionally don't clear VM_FF_INHIBIT_INTERRUPTS here if the eip is the same as the inhibited instr address.
* Before we are able to execute this instruction in raw mode (iret to guest code) an external interrupt might
* force a world switch again. Possibly allowing a guest interrupt to be dispatched in the process. This could
* break the guest. Sounds very unlikely, but such timing sensitive problem are not as rare as you might think.
*/
}
if (HWACCMR3IsActive(pVCpu))
else
UPDATE_RC();
}
/*
* Interrupts.
*/
&& !TRPMHasTrap(pVCpu) /* an interrupt could already be scheduled for dispatching in the recompiler. */
&& !HWACCMR3IsEventPending(pVM))
{
{
/* Note: it's important to make sure the return code from TRPMR3InjectEvent isn't ignored! */
/** @todo this really isn't nice, should properly handle this */
#ifdef VBOX_STRICT
#endif
UPDATE_RC();
}
/** @todo really ugly; if we entered the hlt state when exiting the recompiler and an interrupt was pending, we previously got stuck in the halted state. */
{
UPDATE_RC();
}
}
/*
* Allocate handy pages.
*/
{
UPDATE_RC();
}
/*
* Debugger Facility request.
*/
{
UPDATE_RC();
}
/*
* Termination request.
*/
{
Log2(("emR3ForcedActions: returns VINF_EM_TERMINATE\n"));
return VINF_EM_TERMINATE;
}
/*
* Out of memory? Since most of our fellow high priority actions may cause us
* to run out of memory, we're employing VM_FF_IS_PENDING_EXCEPT and putting this
* at the end rather than the start. Also, VM_FF_TERMINATE has higher priority
* than us since we can terminate without allocating more memory.
*/
{
UPDATE_RC();
if (rc == VINF_EM_NO_MEMORY)
return rc;
}
/*
* If the virtual sync clock is still stopped, make TM restart it.
*/
#ifdef DEBUG
/*
* Debug, pause the VM.
*/
{
Log(("emR3ForcedActions: returns VINF_EM_SUSPEND\n"));
return VINF_EM_SUSPEND;
}
#endif
/* check that we got them all */
AssertCompile(VM_FF_HIGH_PRIORITY_PRE_MASK == (VM_FF_TM_VIRTUAL_SYNC | VM_FF_DBGF | VM_FF_TERMINATE | VM_FF_DEBUG_SUSPEND | VM_FF_PGM_NEED_HANDY_PAGES | VM_FF_PGM_NO_MEMORY));
AssertCompile(VMCPU_FF_HIGH_PRIORITY_PRE_MASK == (VMCPU_FF_TIMER | VMCPU_FF_INTERRUPT_APIC | VMCPU_FF_INTERRUPT_PIC | VMCPU_FF_PGM_SYNC_CR3 | VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL | VMCPU_FF_SELM_SYNC_TSS | VMCPU_FF_TRPM_SYNC_IDT | VMCPU_FF_SELM_SYNC_GDT | VMCPU_FF_SELM_SYNC_LDT | VMCPU_FF_INHIBIT_INTERRUPTS));
}
return rc;
}
/**
* Release the IOM lock if owned by the current VCPU
*
* @param pVM The VM to operate on.
*/
{
}
/**
* Execute VM.
*
* This function is the main loop of the VM. The emulation thread
* calls this function when the VM has been successfully constructed
* and we're ready for executing the VM.
*
* Returning from this function means that the VM is turned off or
* suspended (state already saved) and deconstruction in next in line.
*
* All interaction from other thread are done using forced actions
* and signaling of the wait object.
*
* @returns VBox status code, informational status codes may indicate failure.
* @param pVM The VM to operate on.
* @param pVCpu The VMCPU to operate on.
*/
{
LogFlow(("EMR3ExecuteVM: pVM=%p enmVMState=%d enmState=%d (%s) fForceRAW=%d\n", pVM, pVM->enmVMState,
Assert(pVCpu->em.s.enmState == EMSTATE_NONE || pVCpu->em.s.enmState == EMSTATE_WAIT_SIPI || pVCpu->em.s.enmState == EMSTATE_SUSPENDED);
if (rc == 0)
{
/*
* Start the virtual time.
*/
/*
* The Outer Main Loop.
*/
bool fFFDone = false;
/* Reschedule right away to start in the right state. */
rc = VINF_SUCCESS;
{
/* Pause->Resume: Restore the old wait state or else we'll start executing code. */
}
else
for (;;)
{
/*
* Before we can schedule anything (we're here because
* scheduling is required) we must service any pending
* forced actions to avoid any pending action causing
* immediate rescheduling upon entering an inner loop
*
* Do forced actions.
*/
if ( !fFFDone
&& rc != VINF_EM_TERMINATE
&& rc != VINF_EM_OFF
{
if ( ( rc == VINF_EM_RESCHEDULE_REM
|| rc == VINF_EM_RESCHEDULE_HWACC)
}
else if (fFFDone)
fFFDone = false;
/*
* Now what to do?
*/
switch (rc)
{
/*
* Keep doing what we're currently doing.
*/
case VINF_SUCCESS:
break;
/*
* Reschedule - to raw-mode execution.
*/
case VINF_EM_RESCHEDULE_RAW:
Log2(("EMR3ExecuteVM: VINF_EM_RESCHEDULE_RAW: %d -> %d (EMSTATE_RAW)\n", pVCpu->em.s.enmState, EMSTATE_RAW));
break;
/*
* Reschedule - to hardware accelerated raw-mode execution.
*/
case VINF_EM_RESCHEDULE_HWACC:
Log2(("EMR3ExecuteVM: VINF_EM_RESCHEDULE_HWACC: %d -> %d (EMSTATE_HWACC)\n", pVCpu->em.s.enmState, EMSTATE_HWACC));
break;
/*
* Reschedule - to recompiled execution.
*/
case VINF_EM_RESCHEDULE_REM:
Log2(("EMR3ExecuteVM: VINF_EM_RESCHEDULE_REM: %d -> %d (EMSTATE_REM)\n", pVCpu->em.s.enmState, EMSTATE_REM));
break;
#ifdef VBOX_WITH_VMI
/*
* Reschedule - parav call.
*/
case VINF_EM_RESCHEDULE_PARAV:
Log2(("EMR3ExecuteVM: VINF_EM_RESCHEDULE_PARAV: %d -> %d (EMSTATE_PARAV)\n", pVCpu->em.s.enmState, EMSTATE_PARAV));
break;
#endif
/*
* Resume.
*/
case VINF_EM_RESUME:
/* Don't reschedule in the halted or wait for SIPI case. */
break;
/* fall through and get scheduled. */
/*
* Reschedule.
*/
case VINF_EM_RESCHEDULE:
{
Log2(("EMR3ExecuteVM: VINF_EM_RESCHEDULE: %d -> %d (%s)\n", pVCpu->em.s.enmState, enmState, EMR3GetStateName(enmState)));
break;
}
/*
* Halted.
*/
case VINF_EM_HALT:
break;
/*
* Switch to the wait for SIPI state (application processor only)
*/
case VINF_EM_WAIT_SIPI:
break;
/*
* Suspend.
*/
case VINF_EM_SUSPEND:
break;
/*
* Reset.
* We might end up doing a double reset for now, we'll have to clean up the mess later.
*/
case VINF_EM_RESET:
{
{
Log2(("EMR3ExecuteVM: VINF_EM_RESET: %d -> %d (%s)\n", pVCpu->em.s.enmState, enmState, EMR3GetStateName(enmState)));
}
else
{
/* All other VCPUs go into the wait for SIPI state. */
}
break;
}
/*
* Power Off.
*/
case VINF_EM_OFF:
Log2(("EMR3ExecuteVM: returns VINF_EM_OFF (%d -> %d)\n", pVCpu->em.s.enmState, EMSTATE_TERMINATING));
return rc;
/*
* Terminate the VM.
*/
case VINF_EM_TERMINATE:
Log(("EMR3ExecuteVM returns VINF_EM_TERMINATE (%d -> %d)\n", pVCpu->em.s.enmState, EMSTATE_TERMINATING));
return rc;
/*
* Out of memory, suspend the VM and stuff.
*/
case VINF_EM_NO_MEMORY:
N_("Unable to allocate and lock memory. The virtual machine will be paused. Please close applications to free up memory or close the VM"));
if (rc != VINF_EM_SUSPEND)
{
if (RT_SUCCESS_NP(rc))
{
}
}
return rc;
/*
* Guest debug events.
*/
case VINF_EM_DBG_STEPPED:
AssertMsgFailed(("VINF_EM_DBG_STEPPED cannot be here!"));
case VINF_EM_DBG_STOP:
case VINF_EM_DBG_BREAKPOINT:
case VINF_EM_DBG_STEP:
{
}
else
{
}
break;
/*
* Hypervisor debug events.
*/
break;
/*
* Guru mediations.
*/
case VERR_VMM_RING0_ASSERTION:
Log(("EMR3ExecuteVM: %Rrc: %d -> %d (EMSTATE_GURU_MEDITATION)\n", rc, pVCpu->em.s.enmState, EMSTATE_GURU_MEDITATION));
break;
/*
* Any error code showing up here other than the ones we
* know and process above are considered to be FATAL.
*
* Unknown warnings and informational status codes are also
* included in this.
*/
default:
if (RT_SUCCESS_NP(rc))
{
}
break;
}
/*
* Act on the state.
*/
{
/*
* Execute raw.
*/
case EMSTATE_RAW:
break;
/*
* Execute hardware accelerated raw.
*/
case EMSTATE_HWACC:
break;
/*
* Execute recompiled.
*/
case EMSTATE_REM:
break;
#ifdef VBOX_WITH_VMI
/*
* Execute PARAV function.
*/
case EMSTATE_PARAV:
break;
#endif
/*
* Application processor execution halted until SIPI.
*/
case EMSTATE_WAIT_SIPI:
/* no break */
/*
* hlt - execution halted until interrupt.
*/
case EMSTATE_HALTED:
{
break;
}
/*
* Suspended - return to VM.cpp.
*/
case EMSTATE_SUSPENDED:
return VINF_EM_SUSPEND;
/*
* Debugging in the guest.
*/
case EMSTATE_DEBUG_GUEST_REM:
case EMSTATE_DEBUG_GUEST_RAW:
break;
/*
* Debugging in the hypervisor.
*/
case EMSTATE_DEBUG_HYPER:
{
if (rc != VINF_SUCCESS)
{
/* switch to guru meditation mode */
return rc;
}
break;
}
/*
* Guru meditation takes place in the debugger.
*/
case EMSTATE_GURU_MEDITATION:
{
return rc;
}
/*
* The states we don't expect here.
*/
case EMSTATE_NONE:
case EMSTATE_TERMINATING:
default:
return VERR_EM_INTERNAL_ERROR;
}
} /* The Outer Main Loop */
}
else
{
/*
* Fatal error.
*/
/** @todo change the VM state! */
return rc;
}
/* (won't ever get here). */
AssertFailed();
}