CPUMInternal.h revision 409950536f73e7c9a387f7d548122ae6bffae950
/* $Id$ */
/** @file
* CPUM - Internal header file.
*/
/*
* Copyright (C) 2006-2007 Sun Microsystems, Inc.
*
* This file is part of VirtualBox Open Source Edition (OSE), as
* available from http://www.virtualbox.org. This file is free software;
* General Public License (GPL) as published by the Free Software
* Foundation, in version 2 as it comes in the "COPYING" file of the
* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
*
* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
* Clara, CA 95054 USA or visit http://www.sun.com if you need
* additional information or have any questions.
*/
#ifndef ___CPUMInternal_h
#define ___CPUMInternal_h
/** @defgroup grp_cpum_int Internals
* @ingroup grp_cpum
* @internal
* @{
*/
/** Flags and types for CPUM fault handlers
* @{ */
/** Type: Load DS */
#define CPUM_HANDLER_DS 1
/** Type: Load ES */
#define CPUM_HANDLER_ES 2
/** Type: Load FS */
#define CPUM_HANDLER_FS 3
/** Type: Load GS */
#define CPUM_HANDLER_GS 4
/** Type: IRET */
#define CPUM_HANDLER_IRET 5
/** Type mask. */
#define CPUM_HANDLER_TYPEMASK 0xff
/** If set EBP points to the CPUMCTXCORE that's being used. */
/** @} */
/** Use flags (CPUM::fUseFlags).
* (Don't forget to sync this with CPUMInternal.mac!)
* @{ */
/** Used the FPU, SSE or such stuff. */
#define CPUM_USED_FPU RT_BIT(0)
/** Used the FPU, SSE or such stuff since last we were in REM.
* REM syncing is clearing this, lazy FPU is setting it. */
/** Host OS is using SYSENTER and we must NULL the CS. */
/** Host OS is using SYSENTER and we must NULL the CS. */
/** Debug registers are used by host and must be disabled. */
/** Enabled use of debug registers in guest context. */
/** The XMM state was manually restored. (AMD only) */
/** Sync the FPU state on entry (32->64 switcher only). */
/** Sync the debug state on entry (32->64 switcher only). */
/** @} */
/* Sanity check. */
# error "VBOX_WITH_HYBRID_32BIT_KERNEL is only for 32 bit builds."
#endif
/**
* The saved host CPU state.
*
* @remark The special VBOX_WITH_HYBRID_32BIT_KERNEL checks here are for the 10.4.x series
* of Mac OS X where the OS is essentially 32-bit but the cpu mode can be 64-bit.
*/
typedef struct CPUMHOSTCTX
{
/** FPU state. (16-byte alignment)
* @remark On x86, the format isn't necessarily X86FXSTATE (not important). */
/** General purpose register, selectors, flags and more
* @{ */
/** General purpose register ++
* { */
//uint64_t rax; - scratch
//uint64_t rcx; - scratch
//uint64_t rdx; - scratch
//uint64_t r8; - scratch
//uint64_t r9; - scratch
//uint64_t rip; - scratch
#endif
#if HC_ARCH_BITS == 32
//uint32_t eax; - scratch
//uint32_t ecx; - scratch
//uint32_t edx; - scratch
//uint32_t eip; - scratch
/* lss pair! */
#endif
/** @} */
/** Selector registers
* @{ */
/** @} */
/** Control registers.
* @{ */
//uint32_t cr2; - scratch
/** @} */
/** Debug registers.
* @{ */
/** @} */
/** Global Descriptor Table register. */
/** Interrupt Descriptor Table register. */
/** The task register. */
/** The task register. */
/** The sysenter msr registers.
* This member is not used by the hypervisor context. */
/* padding to get 64byte aligned size */
/** Control registers.
* @{ */
//uint64_t cr2; - scratch
/** @} */
/** Debug registers.
* @{ */
/** @} */
/** Global Descriptor Table register. */
/** Interrupt Descriptor Table register. */
/** The task register. */
/** The task register. */
/** MSRs
* @{ */
/** @} */
/* padding to get 32byte aligned size */
# ifdef VBOX_WITH_HYBRID_32BIT_KERNEL
# else
# endif
#else
#endif
} CPUMHOSTCTX;
/** Pointer to the saved host CPU state. */
typedef CPUMHOSTCTX *PCPUMHOSTCTX;
/**
* CPUM Data (part of VM)
*/
typedef struct CPUM
{
/**
* Hypervisor context.
* Aligned on a 64-byte boundrary.
*/
/** Pointer to the current hypervisor core context - R3Ptr. */
/** Pointer to the current hypervisor core context - R0Ptr. */
/** Pointer to the current hypervisor core context - RCPtr. */
/* Offset from CPUM to CPUMCPU for the first CPU. */
/** Hidden selector registers state.
* Valid (hw accelerated raw mode) or not (normal raw mode)
*/
/** Host CPU Features - ECX */
struct
{
/** edx part */
/** ecx part */
} CPUFeatures;
/** Host extended CPU features. */
struct
{
/** edx part */
/** ecx part */
/* CPU manufacturer. */
/** CR4 mask */
struct
{
} CR4;
/** Have we entered rawmode? */
bool fRawEntered;
/** The standard set of CpuId leafs. */
/** The extended set of CpuId leafs. */
/** The centaur set of CpuId leafs. */
/** The default set of CpuId leafs. */
/** Align the next member, and thereby the structure, on a 64-byte boundrary. */
/**
* Guest context on raw mode entry.
* This a debug feature, see CPUMR3SaveEntryCtx.
*/
} CPUM;
/** Pointer to the CPUM instance data residing in the shared VM structure. */
/**
* CPUM Data (part of VMCPU)
*/
typedef struct CPUMCPU
{
/**
* Saved host context. Only valid while inside GC.
* Aligned on a 64-byte boundrary.
*/
/**
* Guest context.
* Aligned on a 64-byte boundrary.
*/
/**
* Guest context - misc MSRs
* Aligned on a 64-byte boundrary.
*/
/** Use flags.
* These flags indicates both what is to be used and what has been used.
*/
/** Changed flags.
* These flags indicates to REM (and others) which important guest
* registers which has been changed since last time the flags were cleared.
* See the CPUM_CHANGED_* defines for what we keep track of.
*/
/* Offset to CPUM. (subtract from the pointer to get to CPUM) */
/* Temporary storage for the return code of the function called in the 32-64 switcher. */
/* Round to 16 byte size.
uint32_t uPadding;
*/
/** Pointer to the CPUMCPU instance data residing in the shared VMCPU structure. */
#ifdef IN_RING0
#endif
/** @} */
#endif