CPUM.cpp revision b5d837811bf21f30a31748bbbcb28ee562bb2355
/* $Id$ */
/** @file
* CPUM - CPU Monitor / Manager.
*/
/*
* Copyright (C) 2006-2007 Sun Microsystems, Inc.
*
* This file is part of VirtualBox Open Source Edition (OSE), as
* available from http://www.virtualbox.org. This file is free software;
* General Public License (GPL) as published by the Free Software
* Foundation, in version 2 as it comes in the "COPYING" file of the
* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
*
* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
* Clara, CA 95054 USA or visit http://www.sun.com if you need
* additional information or have any questions.
*/
/** @page pg_cpum CPUM - CPU Monitor / Manager
*
* The CPU Monitor / Manager keeps track of all the CPU registers. It is
* also responsible for lazy FPU handling and some of the context loading
* in raw mode.
*
* There are three CPU contexts, the most important one is the guest one (GC).
* When running in raw-mode (RC) there is a special hyper context for the VMM
* part that floats around inside the guest address space. When running in
* raw-mode, CPUM also maintains a host context for saving and restoring
* registers accross world switches. This latter is done in cooperation with the
* world switcher (@see pg_vmm).
*
* @see grp_cpum
*/
/*******************************************************************************
* Header Files *
*******************************************************************************/
#define LOG_GROUP LOG_GROUP_CPUM
#include "CPUMInternal.h"
/*******************************************************************************
* Defined Constants And Macros *
*******************************************************************************/
/** The saved state version. */
#define CPUM_SAVED_STATE_VERSION 10
/** The saved state version for the 2.1 trunk before the MSR changes. */
#define CPUM_SAVED_STATE_VERSION_VER2_1_NOMSR 9
/** The saved state version of 2.0, used for backwards compatibility. */
#define CPUM_SAVED_STATE_VERSION_VER2_0 8
/** The saved state version of 1.6, used for backwards compatability. */
#define CPUM_SAVED_STATE_VERSION_VER1_6 6
/*******************************************************************************
* Structures and Typedefs *
*******************************************************************************/
/**
* What kind of cpu info dump to perform.
*/
typedef enum CPUMDUMPTYPE
{
} CPUMDUMPTYPE;
/** Pointer to a cpu info dump type. */
typedef CPUMDUMPTYPE *PCPUMDUMPTYPE;
/*******************************************************************************
* Internal Functions *
*******************************************************************************/
/**
* Initializes the CPUM.
*
* @returns VBox status code.
* @param pVM The VM to operate on.
*/
{
LogFlow(("CPUMR3Init\n"));
/*
* Assert alignment and sizes.
*/
/* Calculate the offset from CPUM to CPUMCPU for the first CPU. */
/* Calculate the offset from CPUMCPU to CPUM. */
{
/*
* Setup any fixed pointers and offsets.
*/
}
/*
* Check that the CPU supports the minimum features we require.
*/
if (!ASMHasCpuId())
{
Log(("The CPU doesn't support CPUID!\n"));
return VERR_UNSUPPORTED_CPU;
}
/* Setup the CR4 AND and OR masks used in the switcher */
/* Depends on the presence of FXSAVE(SSE) support on the host CPU */
{
/* No FXSAVE implies no SSE */
}
else
{
}
{
Log(("The CPU doesn't support MMX!\n"));
return VERR_UNSUPPORTED_CPU;
}
{
Log(("The CPU doesn't support TSC!\n"));
return VERR_UNSUPPORTED_CPU;
}
/* Bogus on AMD? */
/*
* Setup hypervisor startup values.
*/
/*
* Register saved state data item.
*/
if (RT_FAILURE(rc))
return rc;
/* Query the CPU manufacturer. */
if ( uEAX >= 1
&& uEBX == X86_CPUID_VENDOR_AMD_EBX
&& uECX == X86_CPUID_VENDOR_AMD_ECX
&& uEDX == X86_CPUID_VENDOR_AMD_EDX)
else if ( uEAX >= 1
&& uEDX == X86_CPUID_VENDOR_INTEL_EDX)
else /** @todo Via */
/*
* Register info handlers.
*/
DBGFR3InfoRegisterInternal(pVM, "cpumhyper", "Displays the hypervisor cpu state.", &cpumR3InfoHyper);
DBGFR3InfoRegisterInternal(pVM, "cpumguestinstr", "Displays the current guest instruction.", &cpumR3InfoGuestInstr);
/*
* Initialize the Guest CPU state.
*/
if (RT_FAILURE(rc))
return rc;
return VINF_SUCCESS;
}
/**
* Initializes the per-VCPU CPUM.
*
* @returns VBox status code.
* @param pVM The VM to operate on.
*/
{
LogFlow(("CPUMR3InitCPU\n"));
return VINF_SUCCESS;
}
/**
* Initializes the emulated CPU's cpuid information.
*
* @returns VBox status code.
* @param pVM The VM to operate on.
*/
{
uint32_t i;
/*
* Get the host CPUIDs.
*/
ASMCpuId_Idx_ECX(i, 0,
ASMCpuId(0x80000000 + i,
ASMCpuId(0xc0000000 + i,
/*
* Only report features we can support.
*/
//| X86_CPUID_FEATURE_EDX_PAE - not implemented yet.
//| X86_CPUID_FEATURE_EDX_APIC - set by the APIC device if present.
/** @note we don't report sysenter/sysexit support due to our inability to keep the IOPL part of eflags in sync while in ring 1 (see #1757) */
//| X86_CPUID_FEATURE_EDX_SEP
//| X86_CPUID_FEATURE_EDX_PSN - no serial number.
//| X86_CPUID_FEATURE_EDX_DS - no debug store.
//| X86_CPUID_FEATURE_EDX_ACPI - not virtualized yet.
//| X86_CPUID_FEATURE_EDX_SS - no self snoop.
//| X86_CPUID_FEATURE_EDX_HTT - no hyperthreading.
//| X86_CPUID_FEATURE_EDX_TM - no thermal monitor.
//| X86_CPUID_FEATURE_EDX_PBE - no pneding break enabled.
| 0;
/* Can't properly emulate monitor & mwait with guest SMP; force the guest to use hlt for idling VCPUs. */
//| X86_CPUID_FEATURE_ECX_CPLDS - no CPL qualified debug store.
//| X86_CPUID_FEATURE_ECX_VMX - not virtualized.
//| X86_CPUID_FEATURE_ECX_EST - no extended speed step.
//| X86_CPUID_FEATURE_ECX_TM2 - no thermal monitor 2.
//| X86_CPUID_FEATURE_ECX_SSSE3 - no SSSE3 support
//| X86_CPUID_FEATURE_ECX_CNTXID - no L1 context id (MSR++).
//| X86_CPUID_FEATURE_ECX_CX16 - no cmpxchg16b
/* ECX Bit 14 - xTPR Update Control. Processor supports changing IA32_MISC_ENABLES[bit 23]. */
//| X86_CPUID_FEATURE_ECX_TPRUPDATE
/* ECX Bit 21 - x2APIC support - not yet. */
// | X86_CPUID_FEATURE_ECX_X2APIC
/* ECX Bit 23 - POPCOUNT instruction. */
//| X86_CPUID_FEATURE_ECX_POPCOUNT
| 0;
/* ASSUMES that this is ALWAYS the AMD define feature set if present. */
| X86_CPUID_AMD_FEATURE_EDX_MSR //?? this means AMD MSRs..
//| X86_CPUID_AMD_FEATURE_EDX_PAE - not implemented yet.
//| X86_CPUID_AMD_FEATURE_EDX_MCE - not virtualized yet.
//| X86_CPUID_AMD_FEATURE_EDX_APIC - set by the APIC device if present.
/** @note we don't report sysenter/sysexit support due to our inability to keep the IOPL part of eflags in sync while in ring 1 (see #1757) */
//| X86_CPUID_AMD_FEATURE_EDX_SEP
//| X86_CPUID_AMD_FEATURE_EDX_NX - not virtualized, requires PAE.
//| X86_CPUID_AMD_FEATURE_EDX_AXMMX
//| X86_CPUID_AMD_FEATURE_EDX_PAGE1GB
//| X86_CPUID_AMD_FEATURE_EDX_RDTSCP - AMD only; turned on when necessary
//| X86_CPUID_AMD_FEATURE_EDX_LONG_MODE - turned on when necessary
| 0;
//| X86_CPUID_AMD_FEATURE_ECX_LAHF_SAHF
//| X86_CPUID_AMD_FEATURE_ECX_CMPL
//| X86_CPUID_AMD_FEATURE_ECX_SVM - not virtualized.
//| X86_CPUID_AMD_FEATURE_ECX_EXT_APIC
/** Note: This could prevent migration from AMD to Intel CPUs! */
| X86_CPUID_AMD_FEATURE_ECX_CR8L /* expose lock mov cr0 = mov cr8 hack for guests that can use this feature to access the TPR. */
//| X86_CPUID_AMD_FEATURE_ECX_ABM
//| X86_CPUID_AMD_FEATURE_ECX_SSE4A
//| X86_CPUID_AMD_FEATURE_ECX_MISALNSSE
//| X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF
//| X86_CPUID_AMD_FEATURE_ECX_OSVW
//| X86_CPUID_AMD_FEATURE_ECX_SKINIT
//| X86_CPUID_AMD_FEATURE_ECX_WDT
| 0;
/*
* Hide HTT, multicode, SMP, whatever.
* (APIC-ID := 0 and #LogCpus := 0)
*/
#ifdef VBOX_WITH_MULTI_CORE
{
/* If CPUID Fn0000_0001_EDX[HTT] = 1 then LogicalProcessorCount is the number of threads per CPU core times the number of CPU cores per processor */
pCPUM->aGuestCpuIdStd[1].edx |= X86_CPUID_FEATURE_EDX_HTT; /* necessary for hyper-threading *or* multi-core CPUs */
}
#endif
/* Cpuid 2:
* Intel: Cache and TLB information
* AMD: Reserved
* Safe to expose
*/
/* Cpuid 3:
* Intel: EAX, EBX - reserved
* ECX, EDX - Processor Serial Number if available, otherwise reserved
* AMD: Reserved
* Safe to expose
*/
/* Cpuid 4:
* Intel: Deterministic Cache Parameters Leaf
* Note: Depends on the ECX input! -> Feeling rather lazy now, so we just return 0
* AMD: Reserved
* Safe to expose, except for EAX:
* Bits 25-14: Maximum number of addressable IDs for logical processors sharing this cache (see note)**
* Bits 31-26: Maximum number of processor cores in this physical package**
* @Note These SMP values are constant regardless of ECX
*/
#ifdef VBOX_WITH_MULTI_CORE
{
/* One logical processor with possibly multiple cores. */
/* See http://www.intel.com/Assets/PDF/appnote/241618.pdf p. 29 */
}
#endif
* Intel: ECX, EDX - reserved
* EAX, EBX - Smallest and largest monitor line size
* AMD: EDX - reserved
* EAX, EBX - Smallest and largest monitor line size
* ECX - extensions (ignored for now)
* Safe to expose
*/
/*
* Determine the default.
*
* Intel returns values of the highest standard function, while AMD
* returns zeros. VIA on the other hand seems to returning nothing or
* perhaps some random garbage, we don't try to duplicate this behavior.
*/
/* Cpuid 0x800000005 & 0x800000006 contain information about L1, L2 & L3 cache and TLB identifiers.
* Safe to pass on to the guest.
*
* Intel: 0x800000005 reserved
* 0x800000006 L2 cache information
* AMD: 0x800000005 L1 cache information
*/
/* Cpuid 0x800000007:
* AMD: EAX, EBX, ECX - reserved
* EDX: Advanced Power Management Information
* Intel: Reserved
*/
{
{
/* Only expose the TSC invariant capability bit to the guest. */
//| X86_CPUID_AMD_ADVPOWER_EDX_TS
//| X86_CPUID_AMD_ADVPOWER_EDX_FID
//| X86_CPUID_AMD_ADVPOWER_EDX_VID
//| X86_CPUID_AMD_ADVPOWER_EDX_TTP
//| X86_CPUID_AMD_ADVPOWER_EDX_TM
//| X86_CPUID_AMD_ADVPOWER_EDX_STC
//| X86_CPUID_AMD_ADVPOWER_EDX_MC
//| X86_CPUID_AMD_ADVPOWER_EDX_HWPSTATE
#if 1
/* We don't expose X86_CPUID_AMD_ADVPOWER_EDX_TSCINVAR, because newer Linux kernels blindly assume
* that the AMD performance counters work if this is set for 64 bits guests. (can't really find a CPUID feature bit for them though)
*/
#else
#endif
| 0;
}
else
}
/* Cpuid 0x800000008:
* AMD: EBX, EDX - reserved
* ECX: Number of cores + APICIdCoreIdSize
* EBX, ECX, EDX - reserved
*/
{
/* Only expose the virtual and physical address sizes to the guest. (EAX completely) */
/* Set APICIdCoreIdSize to zero (use legacy method to determine the number of cores per cpu)
* NC (0-7) Number of cores; 0 equals 1 core */
#ifdef VBOX_WITH_MULTI_CORE
{
/* Legacy method to determine the number of cores. */
}
#endif
}
/** @cfgm{/CPUM/NT4LeafLimit, boolean, false}
* Limit the number of standard CPUID leafs to 0..2 to prevent NT4 from
* bugchecking with MULTIPROCESSOR_CONFIGURATION_NOT_SUPPORTED (0x3e).
* This option corrsponds somewhat to IA32_MISC_ENABLES.BOOT_NT4[bit 22].
* @todo r=bird: The intel docs states that leafs 3 is included, why don't we?
*/
bool fNt4LeafLimit;
CFGMR3QueryBoolDef(CFGMR3GetChild(CFGMR3GetRoot(pVM), "CPUM"), "NT4LeafLimit", &fNt4LeafLimit, false);
if (fNt4LeafLimit)
/*
* Limit it the number of entries and fill the remaining with the defaults.
*
* The limits are masking off stuff about power saving and similar, this
* is perhaps a bit crudely done as there is probably some relatively harmless
* info too in these leaves (like words about having a constant TSC).
*/
: 0;
/*
* Workaround for missing cpuid(0) patches when leaf 4 returns GuestCpuIdDef:
* If we miss to patch a cpuid(0).eax then Linux tries to determine the number
* of processors from (cpuid(4).eax >> 26) + 1.
*/
/*
* Centaur stuff (VIA).
*
* The important part here (we think) is to make sure the 0xc0000000
* function returns 0xc0000001. As for the features, we don't currently
* let on about any of those... 0xc0000002 seems to be some
* temperature/hz/++ stuff, include it as well (static).
*/
{
i++)
}
else
/*
* Load CPUID overrides from configuration.
*/
* Overloads the CPUID leaf values. */
for (i=0;; )
{
while (cElements-- > 0)
{
if (pNode)
{
if (RT_SUCCESS(rc))
else
if (RT_SUCCESS(rc))
else
if (RT_SUCCESS(rc))
else
if (RT_SUCCESS(rc))
else
}
pCpuId++;
i++;
}
/* next */
if ((i & UINT32_C(0xc0000000)) == 0)
{
i = UINT32_C(0x80000000);
}
{
i = UINT32_C(0xc0000000);
}
else
break;
}
/* Check if PAE was explicitely enabled by the user. */
bool fEnable = false;
/*
* Log the cpuid and we're good.
*/
LogRel(("Logical host processors: %d, processor active mask: %016RX64\n",
LogRel(("************************* CPUID dump ************************\n"));
LogRel(("\n"));
LogRel(("******************** End of CPUID dump **********************\n"));
return VINF_SUCCESS;
}
/**
* Applies relocations to data and code managed by this
* component. This function will be called at init and
* whenever the VMM need to relocate it self inside the GC.
*
* The CPUM will update the addresses used by the switcher.
*
* @param pVM The VM.
*/
{
LogFlow(("CPUMR3Relocate\n"));
{
/*
* Switcher pointers.
*/
}
}
/**
* Terminates the CPUM.
*
* Termination means cleaning up and freeing all resources,
* the VM it self is at this point powered off or suspended.
*
* @returns VBox status code.
* @param pVM The VM to operate on.
*/
{
return 0;
}
/**
* Terminates the per-VCPU CPUM.
*
* Termination means cleaning up and freeing all resources,
* the VM it self is at this point powered off or suspended.
*
* @returns VBox status code.
* @param pVM The VM to operate on.
*/
{
#ifdef VBOX_WITH_CRASHDUMP_MAGIC
{
}
#endif
return 0;
}
{
/* @todo anything different for VCPU > 0? */
/*
* Initialize everything to ZERO first.
*/
/* Intel 64 and IA-32 Architectures Software Developer's Manual Volume 3A, Table 8-1. IA-32 Processor States Following Power-up, Reset, or INIT */
/* Init PAT MSR */
/* Reset EFER; see AMD64 Architecture Programmer's Manual Volume 2: Table 14-1. Initial Processor State
* The Intel docs don't mention it.
*/
}
/**
* Resets the CPU.
*
* @returns VINF_SUCCESS.
* @param pVM The VM handle.
*/
{
{
#ifdef VBOX_WITH_CRASHDUMP_MAGIC
/* Magic marker for searching in crash dumps. */
#endif
}
}
/**
* Execute state save operation.
*
* @returns VBox status code.
* @param pVM VM Handle.
* @param pSSM SSM operation handle.
*/
{
/*
* Save.
*/
{
}
{
}
/* Add the cpuid for checking that the cpu is unchanged. */
}
/**
* Load a version 1.6 CPUMCTX structure.
*
* @returns VBox status code.
* @param pVM VM Handle.
* @param pCpumctx16 Version 1.6 CPUMCTX
*/
{
#define CPUMCTX16_LOADREG(RegName) \
#define CPUMCTX16_LOADDRXREG(RegName) \
#define CPUMCTX16_LOADHIDREG(RegName) \
#define CPUMCTX16_LOADSEGREG(RegName) \
}
/**
* Execute state load operation.
*
* @returns VBox status code.
* @param pVM VM Handle.
* @param pSSM SSM operation handle.
* @param uVersion Data layout version.
*/
{
/*
* Validate version.
*/
if ( uVersion != CPUM_SAVED_STATE_VERSION
{
}
/* Set the size of RTGCPTR for SSMR3GetGCPtr. */
else if (uVersion <= CPUM_SAVED_STATE_VERSION)
/*
* Restore.
*/
{
}
{
/* Save the old cpumctx state into the new one. */
}
else
{
{
}
{
return VERR_SSM_UNEXPECTED_DATA;
}
{
if (uVersion == CPUM_SAVED_STATE_VERSION)
}
}
/* Support old saved states with a smaller standard cpuid array. */
/*
* Check that the basic cpuid id information is unchanged.
* @todo we should check the 64 bits capabilities too!
*/
if (RT_SUCCESS(rc))
{
/* Ignore CPU stepping. */
/* Ignore APIC ID (AMD specs). */
/* Ignore the number of Logical CPUs (AMD specs). */
/* Ignore some advanced capability bits, that we don't expose to the guest. */
);
);
/* Make sure we don't forget to update the masks when enabling
* features in the future.
*/
)));
/* do the compare */
{
LogRel(("cpumR3Load: CpuId mismatch! (ignored due to SSMAFTER_DEBUG_IT)\n"
"Saved=%.*Rhxs\n"
"Real =%.*Rhxs\n",
sizeof(au32CpuIdSaved), au32CpuIdSaved,
else
{
LogRel(("cpumR3Load: CpuId mismatch!\n"
"Saved=%.*Rhxs\n"
"Real =%.*Rhxs\n",
sizeof(au32CpuIdSaved), au32CpuIdSaved,
}
}
}
return rc;
}
/**
* Formats the EFLAGS value into mnemonics.
*
* @param pszEFlags Where to write the mnemonics. (Assumes sufficient buffer space.)
* @param efl The EFLAGS value.
*/
{
/*
* Format the flags.
*/
static const struct
{
} s_aFlags[] =
{
};
for (unsigned i = 0; i < RT_ELEMENTS(s_aFlags); i++)
{
if (pszAdd)
{
*psz++ = ' ';
}
}
}
/**
* Formats a full register dump.
*
* @param pVM VM Handle.
* @param pCtx The context to format.
* @param pCtxCore The context core to format.
* @param pHlp Output functions.
* @param enmType The dump type.
* @param pszPrefix Register name prefix.
*/
static void cpumR3InfoOne(PVM pVM, PCPUMCTX pCtx, PCCPUMCTXCORE pCtxCore, PCDBGFINFOHLP pHlp, CPUMDUMPTYPE enmType, const char *pszPrefix)
{
/*
* Format the EFLAGS.
*/
char szEFlags[80];
/*
* Format the registers.
*/
switch (enmType)
{
case CPUMDUMPTYPE_TERSE:
if (CPUMIsGuestIn64BitCodeEx(pCtx))
"%srax=%016RX64 %srbx=%016RX64 %srcx=%016RX64 %srdx=%016RX64\n"
"%srsi=%016RX64 %srdi=%016RX64 %sr8 =%016RX64 %sr9 =%016RX64\n"
"%sr10=%016RX64 %sr11=%016RX64 %sr12=%016RX64 %sr13=%016RX64\n"
"%sr14=%016RX64 %sr15=%016RX64\n"
"%srip=%016RX64 %srsp=%016RX64 %srbp=%016RX64 %siopl=%d %*s\n"
"%scs=%04x %sss=%04x %sds=%04x %ses=%04x %sfs=%04x %sgs=%04x %seflags=%08x\n",
pszPrefix, pCtxCore->rax, pszPrefix, pCtxCore->rbx, pszPrefix, pCtxCore->rcx, pszPrefix, pCtxCore->rdx, pszPrefix, pCtxCore->rsi, pszPrefix, pCtxCore->rdi,
pszPrefix, pCtxCore->r8, pszPrefix, pCtxCore->r9, pszPrefix, pCtxCore->r10, pszPrefix, pCtxCore->r11, pszPrefix, pCtxCore->r12, pszPrefix, pCtxCore->r13,
pszPrefix, pCtxCore->rip, pszPrefix, pCtxCore->rsp, pszPrefix, pCtxCore->rbp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
pszPrefix, (RTSEL)pCtxCore->cs, pszPrefix, (RTSEL)pCtxCore->ss, pszPrefix, (RTSEL)pCtxCore->ds, pszPrefix, (RTSEL)pCtxCore->es,
else
"%seax=%08x %sebx=%08x %secx=%08x %sedx=%08x %sesi=%08x %sedi=%08x\n"
"%seip=%08x %sesp=%08x %sebp=%08x %siopl=%d %*s\n"
"%scs=%04x %sss=%04x %sds=%04x %ses=%04x %sfs=%04x %sgs=%04x %seflags=%08x\n",
pszPrefix, pCtxCore->eax, pszPrefix, pCtxCore->ebx, pszPrefix, pCtxCore->ecx, pszPrefix, pCtxCore->edx, pszPrefix, pCtxCore->esi, pszPrefix, pCtxCore->edi,
pszPrefix, pCtxCore->eip, pszPrefix, pCtxCore->esp, pszPrefix, pCtxCore->ebp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
pszPrefix, (RTSEL)pCtxCore->cs, pszPrefix, (RTSEL)pCtxCore->ss, pszPrefix, (RTSEL)pCtxCore->ds, pszPrefix, (RTSEL)pCtxCore->es,
break;
case CPUMDUMPTYPE_DEFAULT:
if (CPUMIsGuestIn64BitCodeEx(pCtx))
"%srax=%016RX64 %srbx=%016RX64 %srcx=%016RX64 %srdx=%016RX64\n"
"%srsi=%016RX64 %srdi=%016RX64 %sr8 =%016RX64 %sr9 =%016RX64\n"
"%sr10=%016RX64 %sr11=%016RX64 %sr12=%016RX64 %sr13=%016RX64\n"
"%sr14=%016RX64 %sr15=%016RX64\n"
"%srip=%016RX64 %srsp=%016RX64 %srbp=%016RX64 %siopl=%d %*s\n"
"%scs=%04x %sss=%04x %sds=%04x %ses=%04x %sfs=%04x %sgs=%04x %str=%04x %seflags=%08x\n"
"%scr0=%08RX64 %scr2=%08RX64 %scr3=%08RX64 %scr4=%08RX64 %sgdtr=%016RX64:%04x %sldtr=%04x\n"
,
pszPrefix, pCtxCore->rax, pszPrefix, pCtxCore->rbx, pszPrefix, pCtxCore->rcx, pszPrefix, pCtxCore->rdx, pszPrefix, pCtxCore->rsi, pszPrefix, pCtxCore->rdi,
pszPrefix, pCtxCore->r8, pszPrefix, pCtxCore->r9, pszPrefix, pCtxCore->r10, pszPrefix, pCtxCore->r11, pszPrefix, pCtxCore->r12, pszPrefix, pCtxCore->r13,
pszPrefix, pCtxCore->rip, pszPrefix, pCtxCore->rsp, pszPrefix, pCtxCore->rbp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
pszPrefix, (RTSEL)pCtxCore->cs, pszPrefix, (RTSEL)pCtxCore->ss, pszPrefix, (RTSEL)pCtxCore->ds, pszPrefix, (RTSEL)pCtxCore->es,
pszPrefix, (RTSEL)pCtxCore->fs, pszPrefix, (RTSEL)pCtxCore->gs, pszPrefix, (RTSEL)pCtx->tr, pszPrefix, efl,
else
"%seax=%08x %sebx=%08x %secx=%08x %sedx=%08x %sesi=%08x %sedi=%08x\n"
"%seip=%08x %sesp=%08x %sebp=%08x %siopl=%d %*s\n"
"%scs=%04x %sss=%04x %sds=%04x %ses=%04x %sfs=%04x %sgs=%04x %str=%04x %seflags=%08x\n"
"%scr0=%08RX64 %scr2=%08RX64 %scr3=%08RX64 %scr4=%08RX64 %sgdtr=%08RX64:%04x %sldtr=%04x\n"
,
pszPrefix, pCtxCore->eax, pszPrefix, pCtxCore->ebx, pszPrefix, pCtxCore->ecx, pszPrefix, pCtxCore->edx, pszPrefix, pCtxCore->esi, pszPrefix, pCtxCore->edi,
pszPrefix, pCtxCore->eip, pszPrefix, pCtxCore->esp, pszPrefix, pCtxCore->ebp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
pszPrefix, (RTSEL)pCtxCore->cs, pszPrefix, (RTSEL)pCtxCore->ss, pszPrefix, (RTSEL)pCtxCore->ds, pszPrefix, (RTSEL)pCtxCore->es,
pszPrefix, (RTSEL)pCtxCore->fs, pszPrefix, (RTSEL)pCtxCore->gs, pszPrefix, (RTSEL)pCtx->tr, pszPrefix, efl,
break;
case CPUMDUMPTYPE_VERBOSE:
if (CPUMIsGuestIn64BitCodeEx(pCtx))
"%srax=%016RX64 %srbx=%016RX64 %srcx=%016RX64 %srdx=%016RX64\n"
"%srsi=%016RX64 %srdi=%016RX64 %sr8 =%016RX64 %sr9 =%016RX64\n"
"%sr10=%016RX64 %sr11=%016RX64 %sr12=%016RX64 %sr13=%016RX64\n"
"%sr14=%016RX64 %sr15=%016RX64\n"
"%srip=%016RX64 %srsp=%016RX64 %srbp=%016RX64 %siopl=%d %*s\n"
"%scs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
"%sds={%04x base=%016RX64 limit=%08x flags=%08x}\n"
"%ses={%04x base=%016RX64 limit=%08x flags=%08x}\n"
"%sfs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
"%sgs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
"%sss={%04x base=%016RX64 limit=%08x flags=%08x}\n"
"%scr0=%016RX64 %scr2=%016RX64 %scr3=%016RX64 %scr4=%016RX64\n"
"%sdr0=%016RX64 %sdr1=%016RX64 %sdr2=%016RX64 %sdr3=%016RX64\n"
"%sdr4=%016RX64 %sdr5=%016RX64 %sdr6=%016RX64 %sdr7=%016RX64\n"
"%sgdtr=%016RX64:%04x %sidtr=%016RX64:%04x %seflags=%08x\n"
"%sldtr={%04x base=%08RX64 limit=%08x flags=%08x}\n"
"%str ={%04x base=%08RX64 limit=%08x flags=%08x}\n"
"%sSysEnter={cs=%04llx eip=%016RX64 esp=%016RX64}\n"
,
pszPrefix, pCtxCore->rax, pszPrefix, pCtxCore->rbx, pszPrefix, pCtxCore->rcx, pszPrefix, pCtxCore->rdx, pszPrefix, pCtxCore->rsi, pszPrefix, pCtxCore->rdi,
pszPrefix, pCtxCore->r8, pszPrefix, pCtxCore->r9, pszPrefix, pCtxCore->r10, pszPrefix, pCtxCore->r11, pszPrefix, pCtxCore->r12, pszPrefix, pCtxCore->r13,
pszPrefix, pCtxCore->rip, pszPrefix, pCtxCore->rsp, pszPrefix, pCtxCore->rbp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
pszPrefix, pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pszPrefix, pCtx->idtr.pIdt, pCtx->idtr.cbIdt, pszPrefix, efl,
else
"%seax=%08x %sebx=%08x %secx=%08x %sedx=%08x %sesi=%08x %sedi=%08x\n"
"%seip=%08x %sesp=%08x %sebp=%08x %siopl=%d %*s\n"
"%scs={%04x base=%016RX64 limit=%08x flags=%08x} %sdr0=%08RX64 %sdr1=%08RX64\n"
"%sds={%04x base=%016RX64 limit=%08x flags=%08x} %sdr2=%08RX64 %sdr3=%08RX64\n"
"%ses={%04x base=%016RX64 limit=%08x flags=%08x} %sdr4=%08RX64 %sdr5=%08RX64\n"
"%sfs={%04x base=%016RX64 limit=%08x flags=%08x} %sdr6=%08RX64 %sdr7=%08RX64\n"
"%sgs={%04x base=%016RX64 limit=%08x flags=%08x} %scr0=%08RX64 %scr2=%08RX64\n"
"%sss={%04x base=%016RX64 limit=%08x flags=%08x} %scr3=%08RX64 %scr4=%08RX64\n"
"%sgdtr=%016RX64:%04x %sidtr=%016RX64:%04x %seflags=%08x\n"
"%sldtr={%04x base=%08RX64 limit=%08x flags=%08x}\n"
"%str ={%04x base=%08RX64 limit=%08x flags=%08x}\n"
"%sSysEnter={cs=%04llx eip=%08llx esp=%08llx}\n"
,
pszPrefix, pCtxCore->eax, pszPrefix, pCtxCore->ebx, pszPrefix, pCtxCore->ecx, pszPrefix, pCtxCore->edx, pszPrefix, pCtxCore->esi, pszPrefix, pCtxCore->edi,
pszPrefix, pCtxCore->eip, pszPrefix, pCtxCore->esp, pszPrefix, pCtxCore->ebp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
pszPrefix, (RTSEL)pCtxCore->cs, pCtx->csHid.u64Base, pCtx->csHid.u32Limit, pCtx->csHid.Attr.u, pszPrefix, pCtx->dr[0], pszPrefix, pCtx->dr[1],
pszPrefix, (RTSEL)pCtxCore->ds, pCtx->dsHid.u64Base, pCtx->dsHid.u32Limit, pCtx->dsHid.Attr.u, pszPrefix, pCtx->dr[2], pszPrefix, pCtx->dr[3],
pszPrefix, (RTSEL)pCtxCore->es, pCtx->esHid.u64Base, pCtx->esHid.u32Limit, pCtx->esHid.Attr.u, pszPrefix, pCtx->dr[4], pszPrefix, pCtx->dr[5],
pszPrefix, (RTSEL)pCtxCore->fs, pCtx->fsHid.u64Base, pCtx->fsHid.u32Limit, pCtx->fsHid.Attr.u, pszPrefix, pCtx->dr[6], pszPrefix, pCtx->dr[7],
pszPrefix, (RTSEL)pCtxCore->gs, pCtx->gsHid.u64Base, pCtx->gsHid.u32Limit, pCtx->gsHid.Attr.u, pszPrefix, pCtx->cr0, pszPrefix, pCtx->cr2,
pszPrefix, (RTSEL)pCtxCore->ss, pCtx->ssHid.u64Base, pCtx->ssHid.u32Limit, pCtx->ssHid.Attr.u, pszPrefix, pCtx->cr3, pszPrefix, pCtx->cr4,
pszPrefix, pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pszPrefix, pCtx->idtr.pIdt, pCtx->idtr.cbIdt, pszPrefix, efl,
"FPU:\n"
"%sFCW=%04x %sFSW=%04x %sFTW=%02x\n"
"%sres1=%02x %sFOP=%04x %sFPUIP=%08x %sCS=%04x %sRsvrd1=%04x\n"
"%sFPUDP=%04x %sDS=%04x %sRsvrd2=%04x %sMXCSR=%08x %sMXCSR_MASK=%08x\n"
,
pszPrefix, pCtx->fpu.huh1, pszPrefix, pCtx->fpu.FOP, pszPrefix, pCtx->fpu.FPUIP, pszPrefix, pCtx->fpu.CS, pszPrefix, pCtx->fpu.Rsvrd1,
"MSR:\n"
"%sEFER =%016RX64\n"
"%sPAT =%016RX64\n"
"%sSTAR =%016RX64\n"
"%sCSTAR =%016RX64\n"
"%sLSTAR =%016RX64\n"
"%sSFMASK =%016RX64\n"
"%sKERNELGSBASE =%016RX64\n",
break;
}
}
/**
* Display all cpu states and any other cpum info.
*
* @param pVM VM Handle.
* @param pHlp The info helper functions.
* @param pszArgs Arguments, ignored.
*/
{
}
/**
* Parses the info argument.
*
* The argument starts with 'verbose', 'terse' or 'default' and then
* continues with the comment string.
*
* @param pszArgs The pointer to the argument string.
* @param penmType Where to store the dump type request.
* @param ppszComment Where to store the pointer to the comment string.
*/
static void cpumR3InfoParseArg(const char *pszArgs, CPUMDUMPTYPE *penmType, const char **ppszComment)
{
if (!pszArgs)
{
*ppszComment = "";
}
else
{
{
pszArgs += 5;
}
{
pszArgs += 5;
}
{
pszArgs += 7;
}
else
}
}
/**
* Display the guest cpu state.
*
* @param pVM VM Handle.
* @param pHlp The info helper functions.
* @param pszArgs Arguments, ignored.
*/
{
const char *pszComment;
/* @todo SMP support! */
if (!pVCpu)
}
/**
* Display the current guest instruction
*
* @param pVM VM Handle.
* @param pHlp The info helper functions.
* @param pszArgs Arguments, ignored.
*/
{
char szInstruction[256];
/* @todo SMP support! */
if (!pVCpu)
if (RT_SUCCESS(rc))
}
/**
* Display the hypervisor cpu state.
*
* @param pVM VM Handle.
* @param pHlp The info helper functions.
* @param pszArgs Arguments, ignored.
*/
{
const char *pszComment;
/* @todo SMP */
pHlp->pfnPrintf(pHlp, "CR4OrMask=%#x CR4AndMask=%#x\n", pVM->cpum.s.CR4.OrMask, pVM->cpum.s.CR4.AndMask);
}
/**
* Display the host cpu state.
*
* @param pVM VM Handle.
* @param pHlp The info helper functions.
* @param pszArgs Arguments, ignored.
*/
{
const char *pszComment;
/*
* Format the EFLAGS.
*/
/* @todo SMP */
#if HC_ARCH_BITS == 32
#else
#endif
char szEFlags[80];
/*
* Format the registers.
*/
#if HC_ARCH_BITS == 32
# ifdef VBOX_WITH_HYBRID_32BIT_KERNEL
# endif
{
"eax=xxxxxxxx ebx=%08x ecx=xxxxxxxx edx=xxxxxxxx esi=%08x edi=%08x\n"
"eip=xxxxxxxx esp=%08x ebp=%08x iopl=%d %31s\n"
"cs=%04x ds=%04x es=%04x fs=%04x gs=%04x eflags=%08x\n"
"cr0=%08RX64 cr2=xxxxxxxx cr3=%08RX64 cr4=%08RX64 gdtr=%08x:%04x ldtr=%04x\n"
"dr[0]=%08RX64 dr[1]=%08RX64x dr[2]=%08RX64 dr[3]=%08RX64x dr[6]=%08RX64 dr[7]=%08RX64\n"
"SysEnter={cs=%04x eip=%08x esp=%08x}\n"
,
}
# ifdef VBOX_WITH_HYBRID_32BIT_KERNEL
else
# endif
#endif
{
"rax=xxxxxxxxxxxxxxxx rbx=%016RX64 rcx=xxxxxxxxxxxxxxxx\n"
"rdx=xxxxxxxxxxxxxxxx rsi=%016RX64 rdi=%016RX64\n"
"rip=xxxxxxxxxxxxxxxx rsp=%016RX64 rbp=%016RX64\n"
" r8=xxxxxxxxxxxxxxxx r9=xxxxxxxxxxxxxxxx r10=%016RX64\n"
"r11=%016RX64 r12=%016RX64 r13=%016RX64\n"
"r14=%016RX64 r15=%016RX64\n"
"iopl=%d %31s\n"
"cs=%04x ds=%04x es=%04x fs=%04x gs=%04x eflags=%08RX64\n"
"cr0=%016RX64 cr2=xxxxxxxxxxxxxxxx cr3=%016RX64\n"
"cr4=%016RX64 ldtr=%04x tr=%04x\n"
"dr[0]=%016RX64 dr[1]=%016RX64 dr[2]=%016RX64\n"
"dr[3]=%016RX64 dr[6]=%016RX64 dr[7]=%016RX64\n"
"gdtr=%016RX64:%04x idtr=%016RX64:%04x\n"
"SysEnter={cs=%04x eip=%08x esp=%08x}\n"
"FSbase=%016RX64 GSbase=%016RX64 efer=%08RX64\n"
,
}
#endif
}
/**
* Get L1 cache / TLS associativity.
*/
static const char *getCacheAss(unsigned u, char *pszBuf)
{
if (u == 0)
return "res0 ";
if (u == 1)
return "direct";
if (u >= 256)
return "???";
return pszBuf;
}
/**
* Get L2 cache soociativity.
*/
const char *getL2CacheAss(unsigned u)
{
switch (u)
{
case 0: return "off ";
case 1: return "direct";
case 2: return "2 way ";
case 3: return "res3 ";
case 4: return "4 way ";
case 5: return "res5 ";
case 6: return "8 way "; case 7: return "res7 ";
case 8: return "16 way";
case 9: return "res9 ";
case 10: return "res10 ";
case 11: return "res11 ";
case 12: return "res12 ";
case 13: return "res13 ";
case 14: return "res14 ";
case 15: return "fully ";
default:
return "????";
}
}
/**
* Display the guest CpuId leaves.
*
* @param pVM VM Handle.
* @param pHlp The info helper functions.
* @param pszArgs "terse", "default" or "verbose".
*/
{
/*
* Parse the argument.
*/
unsigned iVerbosity = 1;
if (pszArgs)
{
iVerbosity--;
iVerbosity++;
}
/*
* Start cracking.
*/
" RAW Standard CPUIDs\n"
" Function eax ebx ecx edx\n");
{
"Gst: %08x %08x %08x %08x %08x%s\n"
"Hst: %08x %08x %08x %08x\n",
}
/*
* If verbose, decode it.
*/
if (iVerbosity)
{
"Name: %.04s%.04s%.04s\n"
"Supports: 0-%x\n",
}
/*
* Get Features.
*/
{
"Family: %d \tExtended: %d \tEffective: %d\n"
"Model: %d \tExtended: %d \tEffective: %d\n"
"Stepping: %d\n"
"APIC ID: %#04x\n"
"Logical CPUs: %d\n"
"CLFLUSH Size: %d\n"
"Brand ID: %#04x\n",
if (iVerbosity == 1)
{
}
else
{
pHlp->pfnPrintf(pHlp, "VME - Virtual 8086 Mode Enhancements = %d (%d)\n", EdxGuest.u1VME, EdxHost.u1VME);
pHlp->pfnPrintf(pHlp, "PAE - Physical Address Extension = %d (%d)\n", EdxGuest.u1PAE, EdxHost.u1PAE);
pHlp->pfnPrintf(pHlp, "MTRR - Memory Type Range Registers = %d (%d)\n", EdxGuest.u1MTRR, EdxHost.u1MTRR);
pHlp->pfnPrintf(pHlp, "MCA - Machine Check Architecture = %d (%d)\n", EdxGuest.u1MCA, EdxHost.u1MCA);
pHlp->pfnPrintf(pHlp, "CMOV - Conditional Move Instructions = %d (%d)\n", EdxGuest.u1CMOV, EdxHost.u1CMOV);
pHlp->pfnPrintf(pHlp, "PSE-36 - 36-bit Page Size Extention = %d (%d)\n", EdxGuest.u1PSE36, EdxHost.u1PSE36);
pHlp->pfnPrintf(pHlp, "CLFSH - CLFLUSH Instruction. = %d (%d)\n", EdxGuest.u1CLFSH, EdxHost.u1CLFSH);
pHlp->pfnPrintf(pHlp, "ACPI - Thermal Mon. & Soft. Clock Ctrl.= %d (%d)\n", EdxGuest.u1ACPI, EdxHost.u1ACPI);
pHlp->pfnPrintf(pHlp, "FXSR - FXSAVE and FXRSTOR Instructions = %d (%d)\n", EdxGuest.u1FXSR, EdxHost.u1FXSR);
pHlp->pfnPrintf(pHlp, "HTT - Hyper-Threading Technolog = %d (%d)\n", EdxGuest.u1HTT, EdxHost.u1HTT);
pHlp->pfnPrintf(pHlp, "CPL-DS - CPL Qualified Debug Store = %d (%d)\n", EcxGuest.u1CPLDS, EcxHost.u1CPLDS);
pHlp->pfnPrintf(pHlp, "VMX - Virtual Machine Technology = %d (%d)\n", EcxGuest.u1VMX, EcxHost.u1VMX);
pHlp->pfnPrintf(pHlp, "Supports Supplemental SSE3 or not = %d (%d)\n", EcxGuest.u1SSSE3, EcxHost.u1SSSE3);
pHlp->pfnPrintf(pHlp, "xTPR Update Control = %d (%d)\n", EcxGuest.u1TPRUpdate, EcxHost.u1TPRUpdate);
pHlp->pfnPrintf(pHlp, "Supports the x2APIC extensions = %d (%d)\n", EcxGuest.u1x2APIC, EcxHost.u1x2APIC);
}
}
{
/** @todo */
}
/*
* Extended.
* Implemented after AMD specs.
*/
"\n"
" RAW Extended CPUIDs\n"
" Function eax ebx ecx edx\n");
{
"Gst: %08x %08x %08x %08x %08x%s\n"
"Hst: %08x %08x %08x %08x\n",
}
/*
* Understandable output
*/
if (iVerbosity)
{
"Ext Name: %.4s%.4s%.4s\n"
"Ext Supports: 0x80000000-%#010x\n",
}
{
"Family: %d \tExtended: %d \tEffective: %d\n"
"Model: %d \tExtended: %d \tEffective: %d\n"
"Stepping: %d\n"
"Brand ID: %#05x\n",
if (iVerbosity == 1)
{
}
else
{
pHlp->pfnPrintf(pHlp, "FPU - x87 FPU on Chip = %d (%d)\n", !!(uEdxGst & RT_BIT( 0)), !!(uEdxHst & RT_BIT( 0)));
pHlp->pfnPrintf(pHlp, "VME - Virtual 8086 Mode Enhancements = %d (%d)\n", !!(uEdxGst & RT_BIT( 1)), !!(uEdxHst & RT_BIT( 1)));
pHlp->pfnPrintf(pHlp, "DE - Debugging extensions = %d (%d)\n", !!(uEdxGst & RT_BIT( 2)), !!(uEdxHst & RT_BIT( 2)));
pHlp->pfnPrintf(pHlp, "PSE - Page Size Extension = %d (%d)\n", !!(uEdxGst & RT_BIT( 3)), !!(uEdxHst & RT_BIT( 3)));
pHlp->pfnPrintf(pHlp, "TSC - Time Stamp Counter = %d (%d)\n", !!(uEdxGst & RT_BIT( 4)), !!(uEdxHst & RT_BIT( 4)));
pHlp->pfnPrintf(pHlp, "MSR - K86 Model Specific Registers = %d (%d)\n", !!(uEdxGst & RT_BIT( 5)), !!(uEdxHst & RT_BIT( 5)));
pHlp->pfnPrintf(pHlp, "PAE - Physical Address Extension = %d (%d)\n", !!(uEdxGst & RT_BIT( 6)), !!(uEdxHst & RT_BIT( 6)));
pHlp->pfnPrintf(pHlp, "MCE - Machine Check Exception = %d (%d)\n", !!(uEdxGst & RT_BIT( 7)), !!(uEdxHst & RT_BIT( 7)));
pHlp->pfnPrintf(pHlp, "CX8 - CMPXCHG8B instruction = %d (%d)\n", !!(uEdxGst & RT_BIT( 8)), !!(uEdxHst & RT_BIT( 8)));
pHlp->pfnPrintf(pHlp, "APIC - APIC On-Chip = %d (%d)\n", !!(uEdxGst & RT_BIT( 9)), !!(uEdxHst & RT_BIT( 9)));
pHlp->pfnPrintf(pHlp, "10 - Reserved = %d (%d)\n", !!(uEdxGst & RT_BIT(10)), !!(uEdxHst & RT_BIT(10)));
pHlp->pfnPrintf(pHlp, "SEP - SYSCALL and SYSRET = %d (%d)\n", !!(uEdxGst & RT_BIT(11)), !!(uEdxHst & RT_BIT(11)));
pHlp->pfnPrintf(pHlp, "MTRR - Memory Type Range Registers = %d (%d)\n", !!(uEdxGst & RT_BIT(12)), !!(uEdxHst & RT_BIT(12)));
pHlp->pfnPrintf(pHlp, "PGE - PTE Global Bit = %d (%d)\n", !!(uEdxGst & RT_BIT(13)), !!(uEdxHst & RT_BIT(13)));
pHlp->pfnPrintf(pHlp, "MCA - Machine Check Architecture = %d (%d)\n", !!(uEdxGst & RT_BIT(14)), !!(uEdxHst & RT_BIT(14)));
pHlp->pfnPrintf(pHlp, "CMOV - Conditional Move Instructions = %d (%d)\n", !!(uEdxGst & RT_BIT(15)), !!(uEdxHst & RT_BIT(15)));
pHlp->pfnPrintf(pHlp, "PAT - Page Attribute Table = %d (%d)\n", !!(uEdxGst & RT_BIT(16)), !!(uEdxHst & RT_BIT(16)));
pHlp->pfnPrintf(pHlp, "PSE-36 - 36-bit Page Size Extention = %d (%d)\n", !!(uEdxGst & RT_BIT(17)), !!(uEdxHst & RT_BIT(17)));
pHlp->pfnPrintf(pHlp, "18 - Reserved = %d (%d)\n", !!(uEdxGst & RT_BIT(18)), !!(uEdxHst & RT_BIT(18)));
pHlp->pfnPrintf(pHlp, "19 - Reserved = %d (%d)\n", !!(uEdxGst & RT_BIT(19)), !!(uEdxHst & RT_BIT(19)));
pHlp->pfnPrintf(pHlp, "NX - No-Execute Page Protection = %d (%d)\n", !!(uEdxGst & RT_BIT(20)), !!(uEdxHst & RT_BIT(20)));
pHlp->pfnPrintf(pHlp, "DS - Debug Store = %d (%d)\n", !!(uEdxGst & RT_BIT(21)), !!(uEdxHst & RT_BIT(21)));
pHlp->pfnPrintf(pHlp, "AXMMX - AMD Extensions to MMX Instr. = %d (%d)\n", !!(uEdxGst & RT_BIT(22)), !!(uEdxHst & RT_BIT(22)));
pHlp->pfnPrintf(pHlp, "MMX - Intel MMX Technology = %d (%d)\n", !!(uEdxGst & RT_BIT(23)), !!(uEdxHst & RT_BIT(23)));
pHlp->pfnPrintf(pHlp, "FXSR - FXSAVE and FXRSTOR Instructions = %d (%d)\n", !!(uEdxGst & RT_BIT(24)), !!(uEdxHst & RT_BIT(24)));
pHlp->pfnPrintf(pHlp, "25 - AMD fast FXSAVE and FXRSTOR Instr.= %d (%d)\n", !!(uEdxGst & RT_BIT(25)), !!(uEdxHst & RT_BIT(25)));
pHlp->pfnPrintf(pHlp, "26 - 1 GB large page support = %d (%d)\n", !!(uEdxGst & RT_BIT(26)), !!(uEdxHst & RT_BIT(26)));
pHlp->pfnPrintf(pHlp, "27 - RDTSCP instruction = %d (%d)\n", !!(uEdxGst & RT_BIT(27)), !!(uEdxHst & RT_BIT(27)));
pHlp->pfnPrintf(pHlp, "28 - Reserved = %d (%d)\n", !!(uEdxGst & RT_BIT(28)), !!(uEdxHst & RT_BIT(28)));
pHlp->pfnPrintf(pHlp, "29 - AMD Long Mode = %d (%d)\n", !!(uEdxGst & RT_BIT(29)), !!(uEdxHst & RT_BIT(29)));
pHlp->pfnPrintf(pHlp, "30 - AMD Extensions to 3DNow = %d (%d)\n", !!(uEdxGst & RT_BIT(30)), !!(uEdxHst & RT_BIT(30)));
pHlp->pfnPrintf(pHlp, "31 - AMD 3DNow = %d (%d)\n", !!(uEdxGst & RT_BIT(31)), !!(uEdxHst & RT_BIT(31)));
pHlp->pfnPrintf(pHlp, "LahfSahf - LAHF/SAHF in 64-bit mode = %d (%d)\n", !!(uEcxGst & RT_BIT( 0)), !!(uEcxHst & RT_BIT( 0)));
pHlp->pfnPrintf(pHlp, "CmpLegacy - Core MP legacy mode (depr) = %d (%d)\n", !!(uEcxGst & RT_BIT( 1)), !!(uEcxHst & RT_BIT( 1)));
pHlp->pfnPrintf(pHlp, "SVM - AMD VM Extensions = %d (%d)\n", !!(uEcxGst & RT_BIT( 2)), !!(uEcxHst & RT_BIT( 2)));
pHlp->pfnPrintf(pHlp, "APIC registers starting at 0x400 = %d (%d)\n", !!(uEcxGst & RT_BIT( 3)), !!(uEcxHst & RT_BIT( 3)));
pHlp->pfnPrintf(pHlp, "AltMovCR8 - LOCK MOV CR0 means MOV CR8 = %d (%d)\n", !!(uEcxGst & RT_BIT( 4)), !!(uEcxHst & RT_BIT( 4)));
pHlp->pfnPrintf(pHlp, "Advanced bit manipulation = %d (%d)\n", !!(uEcxGst & RT_BIT( 5)), !!(uEcxHst & RT_BIT( 5)));
pHlp->pfnPrintf(pHlp, "SSE4A instruction support = %d (%d)\n", !!(uEcxGst & RT_BIT( 6)), !!(uEcxHst & RT_BIT( 6)));
pHlp->pfnPrintf(pHlp, "Misaligned SSE mode = %d (%d)\n", !!(uEcxGst & RT_BIT( 7)), !!(uEcxHst & RT_BIT( 7)));
pHlp->pfnPrintf(pHlp, "PREFETCH and PREFETCHW instruction = %d (%d)\n", !!(uEcxGst & RT_BIT( 8)), !!(uEcxHst & RT_BIT( 8)));
pHlp->pfnPrintf(pHlp, "OS visible workaround = %d (%d)\n", !!(uEcxGst & RT_BIT( 9)), !!(uEcxHst & RT_BIT( 9)));
pHlp->pfnPrintf(pHlp, "Instruction based sampling = %d (%d)\n", !!(uEcxGst & RT_BIT(10)), !!(uEcxHst & RT_BIT(10)));
pHlp->pfnPrintf(pHlp, "SSE5 support = %d (%d)\n", !!(uEcxGst & RT_BIT(11)), !!(uEcxHst & RT_BIT(11)));
pHlp->pfnPrintf(pHlp, "SKINIT, STGI, and DEV support = %d (%d)\n", !!(uEcxGst & RT_BIT(12)), !!(uEcxHst & RT_BIT(12)));
pHlp->pfnPrintf(pHlp, "Watchdog timer support. = %d (%d)\n", !!(uEcxGst & RT_BIT(13)), !!(uEcxHst & RT_BIT(13)));
}
}
{
if (cExtMax >= 3)
{
}
if (cExtMax >= 4)
{
}
}
{
char sz1[32];
char sz2[32];
"TLB 2/4M Data: %s %3d entries\n",
"TLB 4K Data: %s %3d entries\n",
"L1 Instr Cache Lines Per Tag: %d\n"
"L1 Instr Cache Associativity: %s\n"
"L1 Instr Cache Size: %d KB\n",
(uEDX >> 0) & 0xff,
"L1 Data Cache Line Size: %d bytes\n"
"L1 Data Cache Lines Per Tag: %d\n"
"L1 Data Cache Associativity: %s\n"
"L1 Data Cache Size: %d KB\n",
(uECX >> 0) & 0xff,
}
{
"L2 TLB 2/4M Data: %s %4d entries\n",
"L2 TLB 4K Data: %s %4d entries\n",
"L2 Cache Line Size: %d bytes\n"
"L2 Cache Lines Per Tag: %d\n"
"L2 Cache Associativity: %s\n"
"L2 Cache Size: %d KB\n",
(uEDX >> 0) & 0xff,
}
{
}
{
"Physical Address Width: %d bits\n"
"Virtual Address Width: %d bits\n",
(uEAX >> 0) & 0xff,
"Physical Core Count: %d\n",
(uECX >> 0) & 0xff);
}
/*
* Centaur.
*/
"\n"
" RAW Centaur CPUIDs\n"
" Function eax ebx ecx edx\n");
{
"Gst: %08x %08x %08x %08x %08x%s\n"
"Hst: %08x %08x %08x %08x\n",
}
/*
* Understandable output
*/
if (iVerbosity)
{
"Centaur Supports: 0xc0000000-%#010x\n",
}
{
if (iVerbosity == 1)
{
}
else
{
pHlp->pfnPrintf(pHlp, "AIS - Alternate Instruction Set = %d (%d)\n", !!(uEdxGst & RT_BIT( 0)), !!(uEdxHst & RT_BIT( 0)));
pHlp->pfnPrintf(pHlp, "AIS-E - AIS enabled = %d (%d)\n", !!(uEdxGst & RT_BIT( 1)), !!(uEdxHst & RT_BIT( 1)));
pHlp->pfnPrintf(pHlp, "RNG - Random Number Generator = %d (%d)\n", !!(uEdxGst & RT_BIT( 2)), !!(uEdxHst & RT_BIT( 2)));
pHlp->pfnPrintf(pHlp, "RNG-E - RNG enabled = %d (%d)\n", !!(uEdxGst & RT_BIT( 3)), !!(uEdxHst & RT_BIT( 3)));
pHlp->pfnPrintf(pHlp, "LH - LongHaul MSR 0000_110Ah = %d (%d)\n", !!(uEdxGst & RT_BIT( 4)), !!(uEdxHst & RT_BIT( 4)));
pHlp->pfnPrintf(pHlp, "FEMMS - FEMMS = %d (%d)\n", !!(uEdxGst & RT_BIT( 5)), !!(uEdxHst & RT_BIT( 5)));
pHlp->pfnPrintf(pHlp, "ACE - Advanced Cryptography Engine = %d (%d)\n", !!(uEdxGst & RT_BIT( 6)), !!(uEdxHst & RT_BIT( 6)));
pHlp->pfnPrintf(pHlp, "ACE-E - ACE enabled = %d (%d)\n", !!(uEdxGst & RT_BIT( 7)), !!(uEdxHst & RT_BIT( 7)));
pHlp->pfnPrintf(pHlp, "ACE2 - Advanced Cryptography Engine 2 = %d (%d)\n", !!(uEdxGst & RT_BIT( 8)), !!(uEdxHst & RT_BIT( 8)));
pHlp->pfnPrintf(pHlp, "ACE2-E - ACE enabled = %d (%d)\n", !!(uEdxGst & RT_BIT( 9)), !!(uEdxHst & RT_BIT( 9)));
pHlp->pfnPrintf(pHlp, "PHE - Hash Engine = %d (%d)\n", !!(uEdxGst & RT_BIT(10)), !!(uEdxHst & RT_BIT(10)));
pHlp->pfnPrintf(pHlp, "PHE-E - PHE enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(11)), !!(uEdxHst & RT_BIT(11)));
pHlp->pfnPrintf(pHlp, "PMM - Montgomery Multiplier = %d (%d)\n", !!(uEdxGst & RT_BIT(12)), !!(uEdxHst & RT_BIT(12)));
pHlp->pfnPrintf(pHlp, "PMM-E - PMM enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(13)), !!(uEdxHst & RT_BIT(13)));
pHlp->pfnPrintf(pHlp, "Bit %d = %d (%d)\n", !!(uEdxGst & RT_BIT(iBit)), !!(uEdxHst & RT_BIT(iBit)));
}
}
}
/**
* Structure used when disassembling and instructions in DBGF.
* This is used so the reader function can get the stuff it needs.
*/
typedef struct CPUMDISASSTATE
{
/** Pointer to the CPU structure. */
/** The VM handle. */
/** The VMCPU handle. */
/** Pointer to the first byte in the segemnt. */
/** Pointer to the byte after the end of the segment. (might have wrapped!) */
/** The size of the segment minus 1. */
/** Pointer to the current page - R3 Ptr. */
void const *pvPageR3;
/** Pointer to the current page - GC Ptr. */
/** The lock information that PGMPhysReleasePageMappingLock needs. */
/** Whether the PageMapLock is valid or not. */
bool fLocked;
/** 64 bits mode or not. */
bool f64Bits;
/**
* Instruction reader.
*
* @returns VBox status code.
* @param PtrSrc Address to read from.
* In our case this is relative to the selector pointed to by the 2nd user argument of uDisCpu.
* @param pu8Dst Where to store the bytes.
* @param cbRead Number of bytes to read.
* @param uDisCpu Pointer to the disassembler cpu state.
* In this context it's always pointer to the Core of a DBGFDISASSTATE.
*/
static DECLCALLBACK(int) cpumR3DisasInstrRead(RTUINTPTR PtrSrc, uint8_t *pu8Dst, unsigned cbRead, void *uDisCpu)
{
for (;;)
{
/* Need to update the page translation? */
{
int rc = VINF_SUCCESS;
/* translate the address */
{
}
else
{
/* Release mapping lock previously acquired. */
rc = PGMPhysGCPtr2CCPtrReadOnly(pState->pVCpu, pState->pvPageGC, &pState->pvPageR3, &pState->PageMapLock);
}
if (RT_FAILURE(rc))
{
return rc;
}
}
/* check the segemnt limit */
return VERR_OUT_OF_SELECTOR_BOUNDS;
/* calc how much we can read */
{
}
/* read and advance */
if (!cbRead)
return VINF_SUCCESS;
}
}
/**
* Disassemble an instruction and return the information in the provided structure.
*
* @returns VBox status code.
* @param pVM VM Handle
* @param pVCpu VMCPU Handle
* @param pCtx CPU context
* @param GCPtrPC Program counter (relative to CS) to disassemble from.
* @param pCpu Disassembly state
* @param pszPrefix String prefix for logging (debug only)
*
*/
VMMR3DECL(int) CPUMR3DisasmInstrCPU(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, RTGCPTR GCPtrPC, PDISCPUSTATE pCpu, const char *pszPrefix)
{
int rc;
/*
* Get selector information.
*/
{
if (CPUMAreHiddenSelRegsValid(pVM))
{
}
else
{
if (RT_FAILURE(rc))
{
AssertMsgFailed(("SELMR3GetShadowSelectorInfo failed for %04X:%RGv rc=%d\n", pCtx->cs, GCPtrPC, rc));
return rc;
}
/*
* Validate the selector.
*/
if (RT_FAILURE(rc))
{
return rc;
}
}
}
else
{
/* real or V86 mode */
}
/*
* Disassemble the instruction.
*/
#ifndef LOG_ENABLED
if (RT_SUCCESS(rc))
{
#else
char szOutput[160];
if (RT_SUCCESS(rc))
{
/* log it */
if (pszPrefix)
else
#endif
rc = VINF_SUCCESS;
}
else
/* Release mapping lock acquired in cpumR3DisasInstrRead. */
return rc;
}
#ifdef DEBUG
/**
* Disassemble an instruction and dump it to the log
*
* @returns VBox status code.
* @param pVM VM Handle
* @param pVCpu VMCPU Handle
* @param pCtx CPU context
* @param pc GC instruction pointer
* @param pszPrefix String prefix for logging
*
* @deprecated Use DBGFR3DisasInstrCurrentLog().
*/
VMMR3DECL(void) CPUMR3DisasmInstr(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, RTGCPTR pc, const char *pszPrefix)
{
}
/**
* Debug helper - Saves guest context on raw mode entry (for fatal dump)
*
* @internal
*/
{
/* @todo SMP support!! */
}
#endif /* DEBUG */
/**
* API for controlling a few of the CPU features found in CR4.
*
* Currently only X86_CR4_TSD is accepted as input.
*
* @returns VBox status code.
*
* @param pVM The VM handle.
* @param fOr The CR4 OR mask.
* @param fAnd The CR4 AND mask.
*/
{
AssertMsgReturn((fAnd & ~(X86_CR4_TSD)) == ~(X86_CR4_TSD), ("%#x\n", fAnd), VERR_INVALID_PARAMETER);
return VINF_SUCCESS;
}
/**
* Gets a pointer to the array of standard CPUID leafs.
*
* CPUMR3GetGuestCpuIdStdMax() give the size of the array.
*
* @returns Pointer to the standard CPUID leafs (read-only).
* @param pVM The VM handle.
* @remark Intended for PATM.
*/
{
}
/**
* Gets a pointer to the array of extended CPUID leafs.
*
* CPUMGetGuestCpuIdExtMax() give the size of the array.
*
* @returns Pointer to the extended CPUID leafs (read-only).
* @param pVM The VM handle.
* @remark Intended for PATM.
*/
{
}
/**
* Gets a pointer to the array of centaur CPUID leafs.
*
* CPUMGetGuestCpuIdCentaurMax() give the size of the array.
*
* @returns Pointer to the centaur CPUID leafs (read-only).
* @param pVM The VM handle.
* @remark Intended for PATM.
*/
{
}
/**
* Gets a pointer to the default CPUID leaf.
*
* @returns Pointer to the default CPUID leaf (read-only).
* @param pVM The VM handle.
* @remark Intended for PATM.
*/
{
}