CPUM.cpp revision 224509fa8d22e75b8db1b6a8b6e2d26cbc1e13e0
/* $Id$ */
/** @file
* CPUM - CPU Monitor(/Manager)
*/
/*
* Copyright (C) 2006 InnoTek Systemberatung GmbH
*
* This file is part of VirtualBox Open Source Edition (OSE), as
* available from http://www.virtualbox.org. This file is free software;
* General Public License as published by the Free Software Foundation,
* in version 2 as it comes in the "COPYING" file of the VirtualBox OSE
* distribution. VirtualBox OSE is distributed in the hope that it will
* be useful, but WITHOUT ANY WARRANTY of any kind.
*
* If you received this file as part of a commercial VirtualBox
* distribution, then only the terms of your commercial VirtualBox
* license agreement apply instead of the previous paragraph.
*/
/*******************************************************************************
* Header Files *
*******************************************************************************/
#define LOG_GROUP LOG_GROUP_CPUM
#include "CPUMInternal.h"
#include "x86context.h"
/*******************************************************************************
* Defined Constants And Macros *
*******************************************************************************/
/** The saved state version. */
#define CPUM_SAVED_STATE_VERSION 3
/*******************************************************************************
* Structures and Typedefs *
*******************************************************************************/
/**
* What kind of cpu info dump to performe.
*/
typedef enum CPUMDUMPTYPE
{
/*******************************************************************************
* Internal Functions *
*******************************************************************************/
/**
* Initializes the CPUM.
*
* @returns VBox status code.
* @param pVM The VM to operate on.
*/
{
LogFlow(("CPUMR3Init\n"));
/*
* Assert alignment and sizes.
*/
/*
* Setup any fixed pointers and offsets.
*/
/* Hidden selector registers are invalid by default. */
/*
* Check that the CPU supports the minimum features we require.
*/
/** @todo check the contract! */
if (!ASMHasCpuId())
{
Log(("The CPU doesn't support CPUID!\n"));
return VERR_UNSUPPORTED_CPU;
}
/* Setup the CR4 AND and OR masks used in the switcher */
/* Depends on the presence of FXSAVE(SSE) support on the host CPU */
{
/* No FXSAVE implies no SSE */
}
else
{
}
{
Log(("The CPU doesn't support MMX!\n"));
return VERR_UNSUPPORTED_CPU;
}
{
Log(("The CPU doesn't support TSC!\n"));
return VERR_UNSUPPORTED_CPU;
}
/* Bogus on AMD? */
{
}
/*
* Setup hypervisor startup values.
*/
/*
* Register saved state data item.
*/
if (VBOX_FAILURE(rc))
return rc;
/*
* Register info handlers.
*/
DBGFR3InfoRegisterInternal(pVM, "cpumhyper", "Displays the hypervisor cpu state.", &cpumR3InfoHyper);
/*
* Initialize the Guest CPU state.
*/
if (VBOX_FAILURE(rc))
return rc;
return VINF_SUCCESS;
}
/**
* Initializes the emulated CPU's cpuid information.
*
* @returns VBox status code.
* @param pVM The VM to operate on.
*/
{
uint32_t i;
/*
* Get the host CPUIDs.
*/
ASMCpuId(i,
ASMCpuId(0x80000000 + i,
/*
* Only report features we can support.
*/
//| X86_CPUID_FEATURE_EDX_VME - recompiler doesn't do this.
//| X86_CPUID_FEATURE_EDX_PAE - not implemented yet.
//| X86_CPUID_FEATURE_EDX_APIC - set by the APIC device if present.
//| X86_CPUID_FEATURE_EDX_MTRR - no MTRRs.
//| X86_CPUID_FEATURE_EDX_MCA - not virtualized.
//| X86_CPUID_FEATURE_EDX_PAT - not virtualized.
//| X86_CPUID_FEATURE_EDX_PSE36 - not virtualized.
//| X86_CPUID_FEATURE_EDX_PSN - no serial number.
//| X86_CPUID_FEATURE_EDX_CLFSH - no CLFLUSH instruction.
//| X86_CPUID_FEATURE_EDX_DS - no debug store.
//| X86_CPUID_FEATURE_EDX_ACPI - not virtualized yet.
//| X86_CPUID_FEATURE_EDX_SS - no self snoop.
//| X86_CPUID_FEATURE_EDX_HTT - no hyperthreading.
//| X86_CPUID_FEATURE_EDX_TM - no thermal monitor.
//| X86_CPUID_FEATURE_EDX_PBE - no pneding break enabled.
| 0;
pCPUM->aGuestCpuIdStd[1].ecx &= 0//X86_CPUID_FEATURE_ECX_SSE3 - not supported by the recompiler yet.
//| X86_CPUID_FEATURE_ECX_CPLDS - no CPL qualified debug store.
//| X86_CPUID_FEATURE_ECX_VMX - not virtualized.
//| X86_CPUID_FEATURE_ECX_EST - no extended speed step.
//| X86_CPUID_FEATURE_ECX_TM2 - no thermal monitor 2.
//| X86_CPUID_FEATURE_ECX_CNTXID - no L1 context id (MSR++).
| 0;
#if 1 /* we didn't used to do this, but I guess we should */
/* ASSUMES that this is ALLWAYS the AMD define feature set if present. */
//| X86_CPUID_AMD_FEATURE_EDX_VME - recompiler doesn't do this.
| X86_CPUID_AMD_FEATURE_EDX_MSR //?? this means AMD MSRs..
//| X86_CPUID_AMD_FEATURE_EDX_PAE - not implemented yet.
//| X86_CPUID_AMD_FEATURE_EDX_MCE - not virtualized yet.
//| X86_CPUID_AMD_FEATURE_EDX_APIC - set by the APIC device if present.
/** @note we don't report sysenter/sysexit support due to our inability to keep the IOPL part of eflags in sync while in ring 1 (see #1757) */
//| X86_CPUID_AMD_FEATURE_EDX_SEP
//| X86_CPUID_AMD_FEATURE_EDX_MTRR - not virtualized.
//| X86_CPUID_AMD_FEATURE_EDX_MCA - not virtualized.
//| X86_CPUID_AMD_FEATURE_EDX_PSE36 - not virtualized.
//| X86_CPUID_AMD_FEATURE_EDX_NX - not virtualized, requires PAE.
//| X86_CPUID_AMD_FEATURE_EDX_LONG_MODE - definintly not.
| 0;
| 0;
#endif
#if 0 /* this is what we used to do. */
/*
* Set BrandIndex=0, CLFLUSH-line-size=0, Num-Logical-Cpus=0 and APIC-ID=0.
*/
/*
* Set the max standard index to 2.
*/
pCPUM->GuestCpuIdDef = pCPUM->aGuestCpuIdStd[2]; /** @todo this default is *NOT* right for AMD, only Intel CPUs. (see tstInlineAsm) */
#else /* this is what we probably should do */
/*
* Hide HTT, multicode, SMP, whatever.
* (APIC-ID := 0 and #LogCpus := 0)
*/
/*
* Determin the default value and limit it the number of entries.
* Intel returns values of the highest standard function, while AMD returns zeros.
*/
#endif
/*
* Assign defaults to the entries we chopped off.
*/
/*
* Load CPUID overrides from configuration.
*/
for (;;)
{
while (cElements-- < 0)
{
if (pNode)
{
if (VBOX_SUCCESS(rc))
else
if (VBOX_SUCCESS(rc))
else
if (VBOX_SUCCESS(rc))
else
if (VBOX_SUCCESS(rc))
else
}
}
/* next */
if (i & 0x80000000)
break;
i = 0x80000000;
}
/*
* Log the cpuid and we're good.
*/
LogRel(("Logical host processors: %d, processor active mask: %08x\n",
LogRel(("************************* CPUID dump ************************\n"));
LogRel(("\n"));
LogRel(("******************** End of CPUID dump **********************\n"));
return VINF_SUCCESS;
}
/**
* Applies relocations to data and code managed by this
* component. This function will be called at init and
* whenever the VMM need to relocate it self inside the GC.
*
* The CPUM will update the addresses used by the switcher.
*
* @param pVM The VM.
*/
{
LogFlow(("CPUMR3Relocate\n"));
/*
* Switcher pointers.
*/
}
/**
* Queries the pointer to the internal CPUMCTX structure
*
* @returns VBox status code.
* @param pVM Handle to the virtual machine.
* @param ppCtx Receives the CPUMCTX GC pointer when successful.
*/
{
LogFlow(("CPUMR3QueryGuestCtxGCPtr\n"));
/*
* Store the address. (Later we might check how's calling, thus the RC.)
*/
return VINF_SUCCESS;
}
/**
* Terminates the CPUM.
*
* Termination means cleaning up and freeing all resources,
* the VM it self is at this point powered off or suspended.
*
* @returns VBox status code.
* @param pVM The VM to operate on.
*/
{
/** @todo */
return 0;
}
/**
* Resets the CPU.
*
* @returns VINF_SUCCESS.
* @param pVM The VM handle.
*/
{
/*
* Initialize everything to ZERO first.
*/
}
/**
* Execute state save operation.
*
* @returns VBox status code.
* @param pVM VM Handle.
* @param pSSM SSM operation handle.
*/
{
/*
* Save.
*/
/* Add the cpuid for checking that the cpu is unchanged. */
}
/**
* Execute state load operation.
*
* @returns VBox status code.
* @param pVM VM Handle.
* @param pSSM SSM operation handle.
* @param u32Version Data layout version.
*/
{
/*
* Validate version.
*/
if (u32Version != CPUM_SAVED_STATE_VERSION)
{
}
/*
* Restore.
*/
/*
* Check that the basic cpuid id information is unchanged.
*/
if (VBOX_SUCCESS(rc))
{
/* Ignore APIC ID (AMD specs). */
/* Ignore the number of Logical CPUs (AMD specs). */
/* do the compare */
{
Log(("cpumR3Load: CpuId mismatch!\n"
"Saved=%.*Vhxs\n"
"Real =%.*Vhxs\n",
sizeof(au32CpuIdSaved), au32CpuIdSaved,
}
}
return rc;
}
/**
* Formats the EFLAGS value into mnemonics.
*
* @param pszEFlags Where to write the mnemonics. (Assumes sufficient buffer space.)
* @param efl The EFLAGS value.
*/
{
/*
* Format the flags.
*/
static struct
{
} s_aFlags[] =
{
};
{
if (pszAdd)
{
*psz++ = ' ';
}
}
}
/**
* Formats a full register dump.
*
* @param pCtx The context to format.
* @param pCtxCore The context core to format.
* @param pHlp Output functions.
* @param enmType The dump type.
* @param pszPrefix Register name prefix.
*/
static void cpumR3InfoOne(PCPUMCTX pCtx, PCCPUMCTXCORE pCtxCore, PCDBGFINFOHLP pHlp, CPUMDUMPTYPE enmType, const char *pszPrefix)
{
/*
* Format the EFLAGS.
*/
char szEFlags[80];
/*
* Format the registers.
*/
switch (enmType)
{
case CPUMDUMPTYPE_TERSE:
"%seax=%08x %sebx=%08x %secx=%08x %sedx=%08x %sesi=%08x %sedi=%08x\n"
"%seip=%08x %sesp=%08x %sebp=%08x %siopl=%d %*s\n"
"%scs=%04x %sds=%04x %ses=%04x %sfs=%04x %sgs=%04x %seflags=%08x\n",
pszPrefix, pCtxCore->eax, pszPrefix, pCtxCore->ebx, pszPrefix, pCtxCore->ecx, pszPrefix, pCtxCore->edx, pszPrefix, pCtxCore->esi, pszPrefix, pCtxCore->edi,
pszPrefix, pCtxCore->eip, pszPrefix, pCtxCore->esp, pszPrefix, pCtxCore->ebp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
break;
case CPUMDUMPTYPE_DEFAULT:
"%seax=%08x %sebx=%08x %secx=%08x %sedx=%08x %sesi=%08x %sedi=%08x\n"
"%seip=%08x %sesp=%08x %sebp=%08x %siopl=%d %*s\n"
"%scs=%04x %sds=%04x %ses=%04x %sfs=%04x %sgs=%04x %seflags=%08x\n"
"%scr0=%08x %scr2=%08x %scr3=%08x %scr4=%08x %sgdtr=%08x:%04x %sldtr=%04x\n"
,
pszPrefix, pCtxCore->eax, pszPrefix, pCtxCore->ebx, pszPrefix, pCtxCore->ecx, pszPrefix, pCtxCore->edx, pszPrefix, pCtxCore->esi, pszPrefix, pCtxCore->edi,
pszPrefix, pCtxCore->eip, pszPrefix, pCtxCore->esp, pszPrefix, pCtxCore->ebp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
break;
case CPUMDUMPTYPE_VERBOSE:
"%seax=%08x %sebx=%08x %secx=%08x %sedx=%08x %sesi=%08x %sedi=%08x\n"
"%seip=%08x %sesp=%08x %sebp=%08x %siopl=%d %*s\n"
"%scs={%04x base=%08x limit=%08x flags=%08x} %sdr0=%08x %sdr1=%08x\n"
"%sds={%04x base=%08x limit=%08x flags=%08x} %sdr2=%08x %sdr3=%08x\n"
"%ses={%04x base=%08x limit=%08x flags=%08x} %sdr4=%08x %sdr5=%08x\n"
"%sfs={%04x base=%08x limit=%08x flags=%08x} %sdr6=%08x %sdr7=%08x\n"
"%sgs={%04x base=%08x limit=%08x flags=%08x} %scr0=%08x %scr2=%08x\n"
"%sss={%04x base=%08x limit=%08x flags=%08x} %scr3=%08x %scr4=%08x\n"
"%sgdtr=%08x:%04x %sidtr=%08x:%04x %seflags=%08x\n"
"%sldtr={%04x base=%08x limit=%08x flags=%08x}\n"
"%str ={%04x base=%08x limit=%08x flags=%08x}\n"
"%sSysEnter={cs=%04llx eip=%08llx esp=%08llx}\n"
"%sFCW=%04x %sFSW=%04x %sFTW=%04x\n"
,
pszPrefix, pCtxCore->eax, pszPrefix, pCtxCore->ebx, pszPrefix, pCtxCore->ecx, pszPrefix, pCtxCore->edx, pszPrefix, pCtxCore->esi, pszPrefix, pCtxCore->edi,
pszPrefix, pCtxCore->eip, pszPrefix, pCtxCore->esp, pszPrefix, pCtxCore->ebp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
pszPrefix, (RTSEL)pCtxCore->cs, pCtx->csHid.u32Base, pCtx->csHid.u32Limit, pCtx->csHid.Attr.u, pszPrefix, pCtx->dr0, pszPrefix, pCtx->dr1,
pszPrefix, (RTSEL)pCtxCore->ds, pCtx->dsHid.u32Base, pCtx->dsHid.u32Limit, pCtx->dsHid.Attr.u, pszPrefix, pCtx->dr2, pszPrefix, pCtx->dr3,
pszPrefix, (RTSEL)pCtxCore->es, pCtx->esHid.u32Base, pCtx->esHid.u32Limit, pCtx->esHid.Attr.u, pszPrefix, pCtx->dr4, pszPrefix, pCtx->dr5,
pszPrefix, (RTSEL)pCtxCore->fs, pCtx->fsHid.u32Base, pCtx->fsHid.u32Limit, pCtx->fsHid.Attr.u, pszPrefix, pCtx->dr6, pszPrefix, pCtx->dr7,
pszPrefix, (RTSEL)pCtxCore->gs, pCtx->gsHid.u32Base, pCtx->gsHid.u32Limit, pCtx->gsHid.Attr.u, pszPrefix, pCtx->cr0, pszPrefix, pCtx->cr2,
pszPrefix, (RTSEL)pCtxCore->ss, pCtx->ssHid.u32Base, pCtx->ssHid.u32Limit, pCtx->ssHid.Attr.u, pszPrefix, pCtx->cr3, pszPrefix, pCtx->cr4,
pszPrefix, pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pszPrefix, pCtx->idtr.pIdt, pCtx->idtr.cbIdt, pszPrefix, efl,
break;
}
}
/**
* Display all cpu states and any other cpum info.
*
* @param pVM VM Handle.
* @param pHlp The info helper functions.
* @param pszArgs Arguments, ignored.
*/
{
}
/**
* Parses the info argument.
*
* The argument starts with 'verbose', 'terse' or 'default' and then
* continues with the comment string.
*
* @param pszArgs The pointer to the argument string.
* @param penmType Where to store the dump type request.
* @param ppszComment Where to store the pointer to the comment string.
*/
static void cpumR3InfoParseArg(const char *pszArgs, CPUMDUMPTYPE *penmType, const char **ppszComment)
{
if (!pszArgs)
{
*ppszComment = "";
}
else
{
{
pszArgs += 5;
}
{
pszArgs += 5;
}
{
pszArgs += 7;
}
else
}
}
/**
* Display the guest cpu state.
*
* @param pVM VM Handle.
* @param pHlp The info helper functions.
* @param pszArgs Arguments, ignored.
*/
{
const char *pszComment;
}
/**
* Display the hypervisor cpu state.
*
* @param pVM VM Handle.
* @param pHlp The info helper functions.
* @param pszArgs Arguments, ignored.
*/
{
const char *pszComment;
}
/**
* Display the host cpu state.
*
* @param pVM VM Handle.
* @param pHlp The info helper functions.
* @param pszArgs Arguments, ignored.
*/
{
const char *pszComment;
/*
* Format the EFLAGS.
*/
#if HC_ARCH_BITS == 32
#else
#endif
char szEFlags[80];
/*
* Format the registers.
*/
#if HC_ARCH_BITS == 32
"eax=xxxxxxxx ebx=%08x ecx=xxxxxxxx edx=xxxxxxxx esi=%08x edi=%08x\n"
"eip=xxxxxxxx esp=%08x ebp=%08x iopl=%d %31s\n"
"cs=%04x ds=%04x es=%04x fs=%04x gs=%04x eflags=%08x\n"
"cr0=%08x cr2=xxxxxxxx cr3=%08x cr4=%08x gdtr=%08x:%04x ldtr=%04x\n"
"dr0=%08x dr1=%08x dr2=%08x dr3=%08x dr6=%08x dr7=%08x\n"
"SysEnter={cs=%04x eip=%08x esp=%08x}\n"
,
#else /* 64-bit */
"rax=xxxxxxxxxxxxxxxx rbx=%016RX64 rcx=xxxxxxxxxxxxxxxx\n"
"rdx=xxxxxxxxxxxxxxxx rsi=%016RX64 rdi=%016RX64\n"
"rip=xxxxxxxxxxxxxxxx rsp=%016RX64 rbp=%016RX64\n"
" r8=xxxxxxxxxxxxxxxx r9=xxxxxxxxxxxxxxxx r10=%016RX64\n"
"r11=%016RX64 r12=%016RX64 r13=%016RX64\n"
"r14=%016RX64 r15=%016RX64\n"
"iopl=%d %31s\n"
"cs=%04x ds=%04x es=%04x fs=%04x gs=%04x eflags=%08RX64\n"
"cr0=%016RX64 cr2=xxxxxxxxxxxxxxxx cr3=%016RX64\n"
"cr4=%016RX64 cr8=%016RX64 ldtr=%04x tr=%04x\n"
"dr0=%016RX64 dr1=%016RX64 dr2=%016RX64\n"
"dr3=%016RX64 dr6=%016RX64 dr7=%016RX64\n"
"gdtr=%016RX64:%04x idtr=%016RX64:%04x\n"
"SysEnter={cs=%04x eip=%08x esp=%08x}\n"
"FSbase=%016RX64 GSbase=%016RX64 efer=%08RX64\n"
,
*(uint64_t *)&pCtx->gdtr[2], *(uint16_t *)&pCtx->gdtr[0], *(uint64_t *)&pCtx->idtr[2], *(uint16_t *)&pCtx->idtr[0],
#endif
}
/**
* Get L1 cache / TLS associativity.
*/
static const char *getCacheAss(unsigned u, char *pszBuf)
{
if (u == 0)
return "res0 ";
if (u == 1)
return "direct";
if (u >= 256)
return "???";
return pszBuf;
}
/**
* Get L2 cache soociativity.
*/
const char *getL2CacheAss(unsigned u)
{
switch (u)
{
case 0: return "off ";
case 1: return "direct";
case 2: return "2 way ";
case 3: return "res3 ";
case 4: return "4 way ";
case 5: return "res5 ";
case 6: return "8 way ";
case 7: return "res7 ";
case 8: return "16 way";
case 9: return "res9 ";
case 10: return "res10 ";
case 11: return "res11 ";
case 12: return "res12 ";
case 13: return "res13 ";
case 14: return "res14 ";
case 15: return "fully ";
default:
return "????";
}
}
/**
* Display the guest CpuId leafs.
*
* @param pVM VM Handle.
* @param pHlp The info helper functions.
* @param pszArgs "terse", "default" or "verbose".
*/
{
/*
* Parse the argument.
*/
unsigned iVerbosity = 1;
if (pszArgs)
{
iVerbosity--;
iVerbosity++;
}
/*
* Start cracking.
*/
" RAW Standard CPUIDs\n"
" Function eax ebx ecx edx\n");
{
"Gst: %08x %08x %08x %08x %08x%s\n"
"Hst: %08x %08x %08x %08x\n",
}
/*
* If verbose, decode it.
*/
if (iVerbosity)
{
"Name: %.04s%.04s%.04s\n"
"Supports: 0-%x\n",
}
/*
* Get Features.
*/
{
"Family: %d \tExtended: %d \tEffectiv: %d\n"
"Model: %d \tExtended: %d \tEffectiv: %d\n"
"Stepping: %d\n"
"APIC ID: %#04x\n"
"Logical CPUs: %d\n"
"CLFLUSH Size: %d\n"
"Brand ID: %#04x\n",
(uEAX >> 8) & 0xf, (uEAX >> 20) & 0x7f, ((uEAX >> 8) & 0xf) + (((uEAX >> 8) & 0xf) == 0xf ? (uEAX >> 20) & 0x7f : 0),
(uEAX >> 4) & 0xf, (uEAX >> 16) & 0x0f, ((uEAX >> 4) & 0xf) | (((uEAX >> 4) & 0xf) == 0xf ? (uEAX >> 16) & 0x0f : 0),
(uEAX >> 0) & 0xf,
if (iVerbosity == 1)
{
}
else
{
pHlp->pfnPrintf(pHlp, "VME - Virtual 8086 Mode Enhancements = %d (%d)\n", EdxGuest.u1VME, EdxHost.u1VME);
pHlp->pfnPrintf(pHlp, "PAE - Physical Address Extension = %d (%d)\n", EdxGuest.u1PAE, EdxHost.u1PAE);
pHlp->pfnPrintf(pHlp, "MTRR - Memory Type Range Registers = %d (%d)\n", EdxGuest.u1MTRR, EdxHost.u1MTRR);
pHlp->pfnPrintf(pHlp, "MCA - Machine Check Architecture = %d (%d)\n", EdxGuest.u1MCA, EdxHost.u1MCA);
pHlp->pfnPrintf(pHlp, "CMOV - Conditional Move Instructions = %d (%d)\n", EdxGuest.u1CMOV, EdxHost.u1CMOV);
pHlp->pfnPrintf(pHlp, "PSE-36 - 36-bit Page Size Extention = %d (%d)\n", EdxGuest.u1PSE36, EdxHost.u1PSE36);
pHlp->pfnPrintf(pHlp, "CLFSH - CLFLUSH Instruction. = %d (%d)\n", EdxGuest.u1CLFSH, EdxHost.u1CLFSH);
pHlp->pfnPrintf(pHlp, "ACPI - Thermal Mon. & Soft. Clock Ctrl.= %d (%d)\n", EdxGuest.u1ACPI, EdxHost.u1ACPI);
pHlp->pfnPrintf(pHlp, "FXSR - FXSAVE and FXRSTOR Instructions = %d (%d)\n", EdxGuest.u1FXSR, EdxHost.u1FXSR);
pHlp->pfnPrintf(pHlp, "HTT - Hyper-Threading Technolog = %d (%d)\n", EdxGuest.u1HTT, EdxHost.u1HTT);
pHlp->pfnPrintf(pHlp, "CPL-DS - CPL Qualified Debug Store = %d (%d)\n", EcxGuest.u1CPLDS, EcxHost.u1CPLDS);
pHlp->pfnPrintf(pHlp, "VMX - Virtual Machine Technology = %d (%d)\n", EcxGuest.u1VMX, EcxHost.u1VMX);
}
}
{
/** @todo */
}
/*
* Extended.
* Implemented after AMD specs.
*/
"\n"
" RAW Extended CPUIDs\n"
" Function eax ebx ecx edx\n");
{
"Gst: %08x %08x %08x %08x %08x%s\n"
"Hst: %08x %08x %08x %08x\n",
}
/*
* Understandable output
*/
if (iVerbosity && cExtMax >= 0)
{
"Ext Name: %.4s%.4s%.4s\n"
"Ext Supports: 0x80000000-%#010x\n",
}
{
"Family: %d \tExtended: %d \tEffectiv: %d\n"
"Model: %d \tExtended: %d \tEffectiv: %d\n"
"Stepping: %d\n"
"Brand ID: %#05x\n",
(uEAX >> 8) & 0xf, (uEAX >> 20) & 0x7f, ((uEAX >> 8) & 0xf) + (((uEAX >> 8) & 0xf) == 0xf ? (uEAX >> 20) & 0x7f : 0),
(uEAX >> 4) & 0xf, (uEAX >> 16) & 0x0f, ((uEAX >> 4) & 0xf) | (((uEAX >> 4) & 0xf) == 0xf ? (uEAX >> 16) & 0x0f : 0),
(uEAX >> 0) & 0xf,
if (iVerbosity == 1)
{
}
else
{
pHlp->pfnPrintf(pHlp, "FPU - x87 FPU on Chip = %d (%d)\n", !!(uEdxGst & BIT( 0)), !!(uEdxHst & BIT( 0)));
pHlp->pfnPrintf(pHlp, "VME - Virtual 8086 Mode Enhancements = %d (%d)\n", !!(uEdxGst & BIT( 1)), !!(uEdxHst & BIT( 1)));
pHlp->pfnPrintf(pHlp, "DE - Debugging extensions = %d (%d)\n", !!(uEdxGst & BIT( 2)), !!(uEdxHst & BIT( 2)));
pHlp->pfnPrintf(pHlp, "PSE - Page Size Extension = %d (%d)\n", !!(uEdxGst & BIT( 3)), !!(uEdxHst & BIT( 3)));
pHlp->pfnPrintf(pHlp, "TSC - Time Stamp Counter = %d (%d)\n", !!(uEdxGst & BIT( 4)), !!(uEdxHst & BIT( 4)));
pHlp->pfnPrintf(pHlp, "MSR - K86 Model Specific Registers = %d (%d)\n", !!(uEdxGst & BIT( 5)), !!(uEdxHst & BIT( 5)));
pHlp->pfnPrintf(pHlp, "PAE - Physical Address Extension = %d (%d)\n", !!(uEdxGst & BIT( 6)), !!(uEdxHst & BIT( 6)));
pHlp->pfnPrintf(pHlp, "MCE - Machine Check Exception = %d (%d)\n", !!(uEdxGst & BIT( 7)), !!(uEdxHst & BIT( 7)));
pHlp->pfnPrintf(pHlp, "CX8 - CMPXCHG8B instruction = %d (%d)\n", !!(uEdxGst & BIT( 8)), !!(uEdxHst & BIT( 8)));
pHlp->pfnPrintf(pHlp, "APIC - APIC On-Chip = %d (%d)\n", !!(uEdxGst & BIT( 9)), !!(uEdxHst & BIT( 9)));
pHlp->pfnPrintf(pHlp, "SEP - SYSCALL and SYSRET = %d (%d)\n", !!(uEdxGst & BIT(11)), !!(uEdxHst & BIT(11)));
pHlp->pfnPrintf(pHlp, "MTRR - Memory Type Range Registers = %d (%d)\n", !!(uEdxGst & BIT(12)), !!(uEdxHst & BIT(12)));
pHlp->pfnPrintf(pHlp, "PGE - PTE Global Bit = %d (%d)\n", !!(uEdxGst & BIT(13)), !!(uEdxHst & BIT(13)));
pHlp->pfnPrintf(pHlp, "MCA - Machine Check Architecture = %d (%d)\n", !!(uEdxGst & BIT(14)), !!(uEdxHst & BIT(14)));
pHlp->pfnPrintf(pHlp, "CMOV - Conditional Move Instructions = %d (%d)\n", !!(uEdxGst & BIT(15)), !!(uEdxHst & BIT(15)));
pHlp->pfnPrintf(pHlp, "PAT - Page Attribute Table = %d (%d)\n", !!(uEdxGst & BIT(16)), !!(uEdxHst & BIT(16)));
pHlp->pfnPrintf(pHlp, "PSE-36 - 36-bit Page Size Extention = %d (%d)\n", !!(uEdxGst & BIT(17)), !!(uEdxHst & BIT(17)));
pHlp->pfnPrintf(pHlp, "NX - No-Execute Page Protection = %d (%d)\n", !!(uEdxGst & BIT(20)), !!(uEdxHst & BIT(20)));
pHlp->pfnPrintf(pHlp, "DS - Debug Store = %d (%d)\n", !!(uEdxGst & BIT(21)), !!(uEdxHst & BIT(21)));
pHlp->pfnPrintf(pHlp, "AXMMX - AMD Extensions to MMX Instr. = %d (%d)\n", !!(uEdxGst & BIT(22)), !!(uEdxHst & BIT(22)));
pHlp->pfnPrintf(pHlp, "MMX - Intel MMX Technology = %d (%d)\n", !!(uEdxGst & BIT(23)), !!(uEdxHst & BIT(23)));
pHlp->pfnPrintf(pHlp, "FXSR - FXSAVE and FXRSTOR Instructions = %d (%d)\n", !!(uEdxGst & BIT(24)), !!(uEdxHst & BIT(24)));
pHlp->pfnPrintf(pHlp, "?? - AMD fast FXSAVE and FXRSTOR Instr.= %d (%d)\n", !!(uEdxGst & BIT(25)), !!(uEdxHst & BIT(25)));
pHlp->pfnPrintf(pHlp, "?? - AMD Long Mode = %d (%d)\n", !!(uEdxGst & BIT(29)), !!(uEdxHst & BIT(29)));
pHlp->pfnPrintf(pHlp, "?? - AMD Extensions to 3DNow = %d (%d)\n", !!(uEdxGst & BIT(30)), !!(uEdxHst & BIT(30)));
pHlp->pfnPrintf(pHlp, "LahfSahf - LAHF/SAHF in 64-bit mode = %d (%d)\n", !!(uEcxGst & BIT( 0)), !!(uEcxHst & BIT( 0)));
pHlp->pfnPrintf(pHlp, "CmpLegacy - Core MP legacy mode (depr) = %d (%d)\n", !!(uEcxGst & BIT( 1)), !!(uEcxHst & BIT( 1)));
pHlp->pfnPrintf(pHlp, "SVM - AMD VM Extensions = %d (%d)\n", !!(uEcxGst & BIT( 2)), !!(uEcxHst & BIT( 2)));
pHlp->pfnPrintf(pHlp, "AltMovCR8 - LOCK MOV CR0 means MOV CR8 = %d (%d)\n", !!(uEcxGst & BIT( 4)), !!(uEcxHst & BIT( 4)));
}
}
{
if (cExtMax >= 3)
{
}
if (cExtMax >= 4)
{
}
}
{
char sz1[32];
char sz2[32];
"TLB 2/4M Data: %s %3d entries\n",
"TLB 4K Data: %s %3d entries\n",
"L1 Instr Cache Lines Per Tag: %d\n"
"L1 Instr Cache Associativity: %s\n"
"L1 Instr Cache Size: %d KB\n",
(uEDX >> 0) & 0xff,
"L1 Data Cache Line Size: %d bytes\n"
"L1 Data Cache Lines Per Tag: %d\n"
"L1 Data Cache Associativity: %s\n"
"L1 Data Cache Size: %d KB\n",
(uECX >> 0) & 0xff,
}
{
"L2 TLB 2/4M Data: %s %4d entries\n",
"L2 TLB 4K Data: %s %4d entries\n",
"L2 Cache Line Size: %d bytes\n"
"L2 Cache Lines Per Tag: %d\n"
"L2 Cache Associativity: %s\n"
"L2 Cache Size: %d KB\n",
(uEDX >> 0) & 0xff,
}
{
}
{
"Physical Address Width: %d bits\n"
"Virtual Address Width: %d bits\n",
(uEAX >> 0) & 0xff,
"Physical Core Count: %d\n",
(uECX >> 0) & 0xff);
}
}
/**
* Structure used when disassembling and instructions in DBGF.
* This is used so the reader function can get the stuff it needs.
*/
typedef struct CPUMDISASSTATE
{
/** Pointer to the CPU structure. */
/** The VM handle. */
/** Pointer to the first byte in the segemnt. */
/** Pointer to the byte after the end of the segment. (might have wrapped!) */
/** The size of the segment minus 1. */
/** Pointer to the current page - HC Ptr. */
void *pvPageHC;
/** Pointer to the current page - GC Ptr. */
/** The rc of the operation.
*
* @todo r=bird: it's rather annoying that we have to keep track of the status code of the operation.
* When we've got time we should adjust the disassembler to use VBox status codes and not
* boolean returns.
*/
int rc;
/**
* Instruction reader.
*
* @returns VBox status code. (Why this is a int32_t and not just an int is also beyond me.)
* @param PtrSrc Address to read from.
* In our case this is relative to the selector pointed to by the 2nd user argument of uDisCpu.
* @param pu8Dst Where to store the bytes.
* @param cbRead Number of bytes to read.
* @param uDisCpu Pointer to the disassembler cpu state. (Why this is a VBOXHUINTPTR is beyond me...)
* In this context it's always pointer to the Core of a DBGFDISASSTATE.
* @todo r=bird: The status code should be an int. The PtrSrc should *NOT* be a RTHCUINTPTR. The uDisCpu could just as well be
* declared as what it actually is a PDISCPUSTATE.
*/
static DECLCALLBACK(int32_t) cpumR3DisasInstrRead(RTHCUINTPTR PtrSrc, uint8_t *pu8Dst, uint32_t cbRead, RTHCUINTPTR uDisCpu)
{
PCPUMDISASSTATE pState = (PCPUMDISASSTATE)pCpu->dwUserData[0]; /** @todo r=bird: Invalid prefix, dw='double word' which it isn't. Besides it's an array too. And btw. RTHCUINTPTR isn't the right thing either in a 32-bit host 64-bit guest situation */
for (;;)
{
/* Need to update the page translation? */
{
/* translate the address */
{
}
else
{
}
}
/* check the segemnt limit */
/* calc how much we can read */
/* read and advance */
if (!cbRead)
return VINF_SUCCESS;
}
}
/**
* Disassemble an instruction and return the information in the provided structure.
*
* @returns VBox status code.
* @param pVM VM Handle
* @param pCtx CPU context
* @param GCPtrPC Program counter (relative to CS) to disassemble from.
* @param pCpu Disassembly state
* @param pszPrefix String prefix for logging (debug only)
*
*/
CPUMR3DECL(int) CPUMR3DisasmInstrCPU(PVM pVM, PCPUMCTX pCtx, RTGCPTR GCPtrPC, PDISCPUSTATE pCpu, const char *pszPrefix)
{
int rc;
/*
* Get selector information.
*/
{
if (CPUMAreHiddenSelRegsValid(pVM))
{
}
else
{
if (!VBOX_SUCCESS(rc))
{
AssertMsgFailed(("SELMR3GetShadowSelectorInfo failed for %04X:%VGv rc=%d\n", pCtx->cs, GCPtrPC, rc));
return rc;
}
/*
* Validate the selector.
*/
if (!VBOX_SUCCESS(rc))
{
return rc;
}
}
}
else
{
/* V86 mode */
}
/*
* Disassemble the instruction.
*/
#ifdef LOG_ENABLED
{
#else
char szOutput[160];
{
/* log it */
if (pszPrefix)
else
#endif
return VINF_SUCCESS;
}
/* DISInstr failure */
{
Log(("CPUMR3DisasmInstrCPU: DISInstr failed for %04X:%VGv rc=%Vrc\n", pCtx->cs, GCPtrPC, State.rc));
}
return rc;
}
#ifdef DEBUG
/**
* Disassemble an instruction and dump it to the log
*
* @returns VBox status code.
* @param pVM VM Handle
* @param pCtx CPU context
* @param pc GC instruction pointer
* @param prefix String prefix for logging
* @deprecated Use DBGFR3DisasInstrCurrentLog().
*
*/
{
}
/**
* Disassemble an instruction and dump it to the log
*
* @returns VBox status code.
* @param pVM VM Handle
* @param pCtx CPU context
* @param pc GC instruction pointer
* @param prefix String prefix for logging
* @param nrInstructions
*
*/
CPUMR3DECL(void) CPUMR3DisasmBlock(PVM pVM, PCPUMCTX pCtx, RTGCPTR pc, char *prefix, int nrInstructions)
{
for(int i=0;i<nrInstructions;i++)
{
}
}
#endif
#ifdef DEBUG
/**
* Debug helper - Saves guest context on raw mode entry (for fatal dump)
*
* @internal
*/
{
}
#endif