CPUM.cpp revision 1e14a5d8c2801e67e52308f8ccb5639e5ad0e102
8b4a8db7768e94d025f1216ecfcd50d727fa2b7cvboxsync * CPUM - CPU Monitor / Manager.
c7814cf6e1240a519cbec0441e033d0e2470ed00vboxsync * Copyright (C) 2006-2007 Sun Microsystems, Inc.
8b4a8db7768e94d025f1216ecfcd50d727fa2b7cvboxsync * This file is part of VirtualBox Open Source Edition (OSE), as
8b4a8db7768e94d025f1216ecfcd50d727fa2b7cvboxsync * available from http://www.virtualbox.org. This file is free software;
8b4a8db7768e94d025f1216ecfcd50d727fa2b7cvboxsync * you can redistribute it and/or modify it under the terms of the GNU
8b4a8db7768e94d025f1216ecfcd50d727fa2b7cvboxsync * General Public License (GPL) as published by the Free Software
8b4a8db7768e94d025f1216ecfcd50d727fa2b7cvboxsync * Foundation, in version 2 as it comes in the "COPYING" file of the
8b4a8db7768e94d025f1216ecfcd50d727fa2b7cvboxsync * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
8b4a8db7768e94d025f1216ecfcd50d727fa2b7cvboxsync * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
8b4a8db7768e94d025f1216ecfcd50d727fa2b7cvboxsync * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
8b4a8db7768e94d025f1216ecfcd50d727fa2b7cvboxsync * Clara, CA 95054 USA or visit http://www.sun.com if you need
8b4a8db7768e94d025f1216ecfcd50d727fa2b7cvboxsync * additional information or have any questions.
8b4a8db7768e94d025f1216ecfcd50d727fa2b7cvboxsync/** @page pg_cpum
8b4a8db7768e94d025f1216ecfcd50d727fa2b7cvboxsync * The CPU Monitor / Manager keeps track of all the CPU registers. It is
8b4a8db7768e94d025f1216ecfcd50d727fa2b7cvboxsync * also responsible for lazy FPU handling and some of the context loading
8b4a8db7768e94d025f1216ecfcd50d727fa2b7cvboxsync * in raw mode.
aa4bcf0a4b2db3ac352b56a291d49cb8d4b66d32vboxsync * There are three CPU contexts, the most important one is the guest one (GC).
8b4a8db7768e94d025f1216ecfcd50d727fa2b7cvboxsync * When running in raw-mode (RC) there is a special hyper context for the VMM
8b4a8db7768e94d025f1216ecfcd50d727fa2b7cvboxsync * that floats around inside the guest address space. When running in raw-mode
8b4a8db7768e94d025f1216ecfcd50d727fa2b7cvboxsync * or when using 64-bit guests on a 32-bit host, CPUM also maintains a host
daa94352f51be2329ac8660f70396e03a7cb983bvboxsync * context for saving and restoring registers accross world switches. This latter
8b4a8db7768e94d025f1216ecfcd50d727fa2b7cvboxsync * is done in cooperation with the world switcher (@see pg_vmm).
e9525bea57dc13d82fd3392913aebb33d2cb79e3vboxsync/*******************************************************************************
8b4a8db7768e94d025f1216ecfcd50d727fa2b7cvboxsync* Header Files *
172ae196da38208e5f1e3485715a89f2d53c6880vboxsync*******************************************************************************/
172ae196da38208e5f1e3485715a89f2d53c6880vboxsync/*******************************************************************************
172ae196da38208e5f1e3485715a89f2d53c6880vboxsync* Defined Constants And Macros *
172ae196da38208e5f1e3485715a89f2d53c6880vboxsync*******************************************************************************/
172ae196da38208e5f1e3485715a89f2d53c6880vboxsync/** The saved state version. */
172ae196da38208e5f1e3485715a89f2d53c6880vboxsync/*******************************************************************************
1c822ec4298d5d20b0fb1cc20346c5d4e4e596bfvboxsync* Structures and Typedefs *
172ae196da38208e5f1e3485715a89f2d53c6880vboxsync*******************************************************************************/
172ae196da38208e5f1e3485715a89f2d53c6880vboxsync * What kind of cpu info dump to perform.
172ae196da38208e5f1e3485715a89f2d53c6880vboxsync/** Pointer to a cpu info dump type. */
172ae196da38208e5f1e3485715a89f2d53c6880vboxsync/*******************************************************************************
172ae196da38208e5f1e3485715a89f2d53c6880vboxsync* Internal Functions *
172ae196da38208e5f1e3485715a89f2d53c6880vboxsync*******************************************************************************/
172ae196da38208e5f1e3485715a89f2d53c6880vboxsyncstatic DECLCALLBACK(int) cpumR3Save(PVM pVM, PSSMHANDLE pSSM);
172ae196da38208e5f1e3485715a89f2d53c6880vboxsyncstatic DECLCALLBACK(int) cpumR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t u32Version);
172ae196da38208e5f1e3485715a89f2d53c6880vboxsyncstatic DECLCALLBACK(void) cpumR3InfoAll(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
172ae196da38208e5f1e3485715a89f2d53c6880vboxsyncstatic DECLCALLBACK(void) cpumR3InfoGuest(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
172ae196da38208e5f1e3485715a89f2d53c6880vboxsyncstatic DECLCALLBACK(void) cpumR3InfoHyper(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
172ae196da38208e5f1e3485715a89f2d53c6880vboxsyncstatic DECLCALLBACK(void) cpumR3InfoHost(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
172ae196da38208e5f1e3485715a89f2d53c6880vboxsyncstatic DECLCALLBACK(void) cpumR3CpuIdInfo(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
172ae196da38208e5f1e3485715a89f2d53c6880vboxsync * Initializes the CPUM.
172ae196da38208e5f1e3485715a89f2d53c6880vboxsync * @returns VBox status code.
172ae196da38208e5f1e3485715a89f2d53c6880vboxsync * @param pVM The VM to operate on.
172ae196da38208e5f1e3485715a89f2d53c6880vboxsync * Assert alignment and sizes.
172ae196da38208e5f1e3485715a89f2d53c6880vboxsync AssertRelease(sizeof(pVM->cpum.s) <= sizeof(pVM->cpum.padding));
172ae196da38208e5f1e3485715a89f2d53c6880vboxsync * Setup any fixed pointers and offsets.
7af218a7441de38fc9e814919db04bae3e917664vboxsync pVM->cpum.s.pHyperCoreR3 = CPUMCTX2CORE(&pVM->cpum.s.Hyper);
7af218a7441de38fc9e814919db04bae3e917664vboxsync pVM->cpum.s.pHyperCoreR0 = VM_R0_ADDR(pVM, CPUMCTX2CORE(&pVM->cpum.s.Hyper));
172ae196da38208e5f1e3485715a89f2d53c6880vboxsync /* Hidden selector registers are invalid by default. */
7af218a7441de38fc9e814919db04bae3e917664vboxsync * Check that the CPU supports the minimum features we require.
7af218a7441de38fc9e814919db04bae3e917664vboxsync /** @todo check the contract! */
4e47bb772df0d04d1ded3e06354de547d52e2d06vboxsync ASMCpuId_ECX_EDX(1, &pVM->cpum.s.CPUFeatures.ecx, &pVM->cpum.s.CPUFeatures.edx);
7af218a7441de38fc9e814919db04bae3e917664vboxsync /* Setup the CR4 AND and OR masks used in the switcher */
7af218a7441de38fc9e814919db04bae3e917664vboxsync /* Depends on the presence of FXSAVE(SSE) support on the host CPU */
7af218a7441de38fc9e814919db04bae3e917664vboxsync Log(("The CPU doesn't support FXSAVE/FXRSTOR!\n"));
7af218a7441de38fc9e814919db04bae3e917664vboxsync /* No FXSAVE implies no SSE */
7af218a7441de38fc9e814919db04bae3e917664vboxsync pVM->cpum.s.CR4.AndMask = X86_CR4_PVI | X86_CR4_VME;
c58c758d3642ac45d3f12356c406c631fcd8f538vboxsync pVM->cpum.s.CR4.AndMask = X86_CR4_OSXMMEEXCPT | X86_CR4_PVI | X86_CR4_VME;
c58c758d3642ac45d3f12356c406c631fcd8f538vboxsync /* Bogus on AMD? */
72a6fe3989272cb2d409b50caca25e1edbca9398vboxsync Log(("The CPU doesn't support SYSENTER/SYSEXIT!\n"));
72a6fe3989272cb2d409b50caca25e1edbca9398vboxsync * Setup hypervisor startup values.
72a6fe3989272cb2d409b50caca25e1edbca9398vboxsync * Register saved state data item.
72a6fe3989272cb2d409b50caca25e1edbca9398vboxsync int rc = SSMR3RegisterInternal(pVM, "cpum", 1, CPUM_SAVED_STATE_VERSION, sizeof(CPUM),
72a6fe3989272cb2d409b50caca25e1edbca9398vboxsync /* Query the CPU manufacturer. */
7af218a7441de38fc9e814919db04bae3e917664vboxsync else /** @todo Via */
72a6fe3989272cb2d409b50caca25e1edbca9398vboxsync * Register info handlers.
72a6fe3989272cb2d409b50caca25e1edbca9398vboxsync DBGFR3InfoRegisterInternal(pVM, "cpum", "Displays the all the cpu states.", &cpumR3InfoAll);
72a6fe3989272cb2d409b50caca25e1edbca9398vboxsync DBGFR3InfoRegisterInternal(pVM, "cpumguest", "Displays the guest cpu state.", &cpumR3InfoGuest);
72a6fe3989272cb2d409b50caca25e1edbca9398vboxsync DBGFR3InfoRegisterInternal(pVM, "cpumhyper", "Displays the hypervisor cpu state.", &cpumR3InfoHyper);
72a6fe3989272cb2d409b50caca25e1edbca9398vboxsync DBGFR3InfoRegisterInternal(pVM, "cpumhost", "Displays the host cpu state.", &cpumR3InfoHost);
72a6fe3989272cb2d409b50caca25e1edbca9398vboxsync DBGFR3InfoRegisterInternal(pVM, "cpuid", "Displays the guest cpuid leaves.", &cpumR3CpuIdInfo);
72a6fe3989272cb2d409b50caca25e1edbca9398vboxsync * Initialize the Guest CPU state.
c58c758d3642ac45d3f12356c406c631fcd8f538vboxsync * Initializes the emulated CPU's cpuid information.
c58c758d3642ac45d3f12356c406c631fcd8f538vboxsync * @returns VBox status code.
c58c758d3642ac45d3f12356c406c631fcd8f538vboxsync * @param pVM The VM to operate on.
c58c758d3642ac45d3f12356c406c631fcd8f538vboxsync * Get the host CPUIDs.
c58c758d3642ac45d3f12356c406c631fcd8f538vboxsync for (i = 0; i < RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdStd); i++)
c58c758d3642ac45d3f12356c406c631fcd8f538vboxsync &pCPUM->aGuestCpuIdStd[i].eax, &pCPUM->aGuestCpuIdStd[i].ebx,
c58c758d3642ac45d3f12356c406c631fcd8f538vboxsync &pCPUM->aGuestCpuIdStd[i].ecx, &pCPUM->aGuestCpuIdStd[i].edx);
c58c758d3642ac45d3f12356c406c631fcd8f538vboxsync for (i = 0; i < RT_ELEMENTS(pCPUM->aGuestCpuIdExt); i++)
c58c758d3642ac45d3f12356c406c631fcd8f538vboxsync &pCPUM->aGuestCpuIdExt[i].eax, &pCPUM->aGuestCpuIdExt[i].ebx,
c58c758d3642ac45d3f12356c406c631fcd8f538vboxsync &pCPUM->aGuestCpuIdExt[i].ecx, &pCPUM->aGuestCpuIdExt[i].edx);
c58c758d3642ac45d3f12356c406c631fcd8f538vboxsync for (i = 0; i < RT_ELEMENTS(pCPUM->aGuestCpuIdCentaur); i++)
c58c758d3642ac45d3f12356c406c631fcd8f538vboxsync &pCPUM->aGuestCpuIdCentaur[i].eax, &pCPUM->aGuestCpuIdCentaur[i].ebx,
c58c758d3642ac45d3f12356c406c631fcd8f538vboxsync &pCPUM->aGuestCpuIdCentaur[i].ecx, &pCPUM->aGuestCpuIdCentaur[i].edx);
c58c758d3642ac45d3f12356c406c631fcd8f538vboxsync * Only report features we can support.
c58c758d3642ac45d3f12356c406c631fcd8f538vboxsync pCPUM->aGuestCpuIdStd[1].edx &= X86_CPUID_FEATURE_EDX_FPU
c58c758d3642ac45d3f12356c406c631fcd8f538vboxsync //| X86_CPUID_FEATURE_EDX_PAE - not implemented yet.
172ae196da38208e5f1e3485715a89f2d53c6880vboxsync //| X86_CPUID_FEATURE_EDX_APIC - set by the APIC device if present.
172ae196da38208e5f1e3485715a89f2d53c6880vboxsync /** @note we don't report sysenter/sysexit support due to our inability to keep the IOPL part of eflags in sync while in ring 1 (see #1757) */
172ae196da38208e5f1e3485715a89f2d53c6880vboxsync //| X86_CPUID_FEATURE_EDX_SEP
172ae196da38208e5f1e3485715a89f2d53c6880vboxsync //| X86_CPUID_FEATURE_EDX_MTRR - no MTRRs.
a438caaf732f7839dc66b4f8dad672527845a003vboxsync //| X86_CPUID_FEATURE_EDX_MCA - not virtualized.
a438caaf732f7839dc66b4f8dad672527845a003vboxsync //| X86_CPUID_FEATURE_EDX_PAT - not virtualized.
172ae196da38208e5f1e3485715a89f2d53c6880vboxsync //| X86_CPUID_FEATURE_EDX_PSE36 - not virtualized.
a438caaf732f7839dc66b4f8dad672527845a003vboxsync //| X86_CPUID_FEATURE_EDX_PSN - no serial number.
7af218a7441de38fc9e814919db04bae3e917664vboxsync //| X86_CPUID_FEATURE_EDX_DS - no debug store.
7af218a7441de38fc9e814919db04bae3e917664vboxsync //| X86_CPUID_FEATURE_EDX_ACPI - not virtualized yet.
7af218a7441de38fc9e814919db04bae3e917664vboxsync //| X86_CPUID_FEATURE_EDX_SS - no self snoop.
7af218a7441de38fc9e814919db04bae3e917664vboxsync //| X86_CPUID_FEATURE_EDX_HTT - no hyperthreading.
7af218a7441de38fc9e814919db04bae3e917664vboxsync //| X86_CPUID_FEATURE_EDX_TM - no thermal monitor.
7af218a7441de38fc9e814919db04bae3e917664vboxsync //| X86_CPUID_FEATURE_EDX_PBE - no pneding break enabled.
7af218a7441de38fc9e814919db04bae3e917664vboxsync pCPUM->aGuestCpuIdStd[1].ecx &= 0//X86_CPUID_FEATURE_ECX_SSE3 - not supported by the recompiler yet.
c58c758d3642ac45d3f12356c406c631fcd8f538vboxsync //| X86_CPUID_FEATURE_ECX_CPLDS - no CPL qualified debug store.
c58c758d3642ac45d3f12356c406c631fcd8f538vboxsync //| X86_CPUID_FEATURE_ECX_VMX - not virtualized.
e36f03470adaee73199dcdddd8eb9cf39bbdf7advboxsync //| X86_CPUID_FEATURE_ECX_EST - no extended speed step.
e36f03470adaee73199dcdddd8eb9cf39bbdf7advboxsync //| X86_CPUID_FEATURE_ECX_TM2 - no thermal monitor 2.
e36f03470adaee73199dcdddd8eb9cf39bbdf7advboxsync //| X86_CPUID_FEATURE_ECX_CNTXID - no L1 context id (MSR++).
c58c758d3642ac45d3f12356c406c631fcd8f538vboxsync /* ASSUMES that this is ALWAYS the AMD define feature set if present. */
7af218a7441de38fc9e814919db04bae3e917664vboxsync pCPUM->aGuestCpuIdExt[1].edx &= X86_CPUID_AMD_FEATURE_EDX_FPU
7af218a7441de38fc9e814919db04bae3e917664vboxsync | X86_CPUID_AMD_FEATURE_EDX_MSR //?? this means AMD MSRs..
7af218a7441de38fc9e814919db04bae3e917664vboxsync //| X86_CPUID_AMD_FEATURE_EDX_PAE - not implemented yet.
7af218a7441de38fc9e814919db04bae3e917664vboxsync //| X86_CPUID_AMD_FEATURE_EDX_MCE - not virtualized yet.
72a6fe3989272cb2d409b50caca25e1edbca9398vboxsync //| X86_CPUID_AMD_FEATURE_EDX_APIC - set by the APIC device if present.
72a6fe3989272cb2d409b50caca25e1edbca9398vboxsync /** @note we don't report sysenter/sysexit support due to our inability to keep the IOPL part of eflags in sync while in ring 1 (see #1757) */
7af218a7441de38fc9e814919db04bae3e917664vboxsync //| X86_CPUID_AMD_FEATURE_EDX_SEP
72a6fe3989272cb2d409b50caca25e1edbca9398vboxsync //| X86_CPUID_AMD_FEATURE_EDX_MTRR - not virtualized.
72a6fe3989272cb2d409b50caca25e1edbca9398vboxsync //| X86_CPUID_AMD_FEATURE_EDX_MCA - not virtualized.
172ae196da38208e5f1e3485715a89f2d53c6880vboxsync //| X86_CPUID_AMD_FEATURE_EDX_PSE36 - not virtualized.
172ae196da38208e5f1e3485715a89f2d53c6880vboxsync //| X86_CPUID_AMD_FEATURE_EDX_NX - not virtualized, requires PAE.
e9525bea57dc13d82fd3392913aebb33d2cb79e3vboxsync //| X86_CPUID_AMD_FEATURE_EDX_LONG_MODE - not yet.
172ae196da38208e5f1e3485715a89f2d53c6880vboxsync pCPUM->aGuestCpuIdExt[1].ecx &= 0//X86_CPUID_AMD_FEATURE_ECX_SVM - not virtualized.
172ae196da38208e5f1e3485715a89f2d53c6880vboxsync * Hide HTT, multicode, SMP, whatever.
172ae196da38208e5f1e3485715a89f2d53c6880vboxsync * (APIC-ID := 0 and #LogCpus := 0)
172ae196da38208e5f1e3485715a89f2d53c6880vboxsync * Determin the default.
172ae196da38208e5f1e3485715a89f2d53c6880vboxsync * Intel returns values of the highest standard function, while AMD
172ae196da38208e5f1e3485715a89f2d53c6880vboxsync * returns zeros. VIA on the other hand seems to returning nothing or
172ae196da38208e5f1e3485715a89f2d53c6880vboxsync * perhaps some random garbage, we don't try duplicate this behavior.
172ae196da38208e5f1e3485715a89f2d53c6880vboxsync &pCPUM->GuestCpuIdDef.eax, &pCPUM->GuestCpuIdDef.ebx,
172ae196da38208e5f1e3485715a89f2d53c6880vboxsync &pCPUM->GuestCpuIdDef.ecx, &pCPUM->GuestCpuIdDef.edx);
172ae196da38208e5f1e3485715a89f2d53c6880vboxsync * Limit it the number of entries and fill the remaining with the defaults.
172ae196da38208e5f1e3485715a89f2d53c6880vboxsync * The limits are masking off stuff about power saving and similar, this
172ae196da38208e5f1e3485715a89f2d53c6880vboxsync * is perhaps a bit crudely done as there is probably some relatively harmless
172ae196da38208e5f1e3485715a89f2d53c6880vboxsync * info too in these leaves (like words about having a constant TSC).
e9525bea57dc13d82fd3392913aebb33d2cb79e3vboxsync for (i = pCPUM->aGuestCpuIdStd[0].eax + 1; i < RT_ELEMENTS(pCPUM->aGuestCpuIdStd); i++)
172ae196da38208e5f1e3485715a89f2d53c6880vboxsync if (pCPUM->aGuestCpuIdExt[0].eax > UINT32_C(0x80000004))
c0e27f622f9bd6d9e77d2d959aab71d69dabf0d3vboxsync pCPUM->aGuestCpuIdExt[0].eax = UINT32_C(0x80000004);
172ae196da38208e5f1e3485715a89f2d53c6880vboxsync for (i = pCPUM->aGuestCpuIdExt[0].eax >= UINT32_C(0x80000000)
172ae196da38208e5f1e3485715a89f2d53c6880vboxsync ? pCPUM->aGuestCpuIdExt[0].eax - UINT32_C(0x80000000) + 1
172ae196da38208e5f1e3485715a89f2d53c6880vboxsync * Workaround for missing cpuid(0) patches: If we miss to patch a cpuid(0).eax then
172ae196da38208e5f1e3485715a89f2d53c6880vboxsync * Linux tries to determine the number of processors from (cpuid(4).eax >> 26) + 1.
172ae196da38208e5f1e3485715a89f2d53c6880vboxsync * We don't support more than 1 processor.
aa4bcf0a4b2db3ac352b56a291d49cb8d4b66d32vboxsync * Centaur stuff (VIA).
db55f7b1060a6a72704b5369a8e776c59e5e4f64vboxsync * The important part here (we think) is to make sure the 0xc0000000
b7a07b07543924f45c1fffd2f90de582038b8ba6vboxsync * function returns 0xc0000001. As for the features, we don't currently
9939c713bffcfc4305d99d994552aa2ad9bce097vboxsync * let on about any of those... 0xc0000002 seems to be some
c58c758d3642ac45d3f12356c406c631fcd8f538vboxsync * temperature/hz/++ stuff, include it as well (static).
c58c758d3642ac45d3f12356c406c631fcd8f538vboxsync if ( pCPUM->aGuestCpuIdCentaur[0].eax >= UINT32_C(0xc0000000)
c58c758d3642ac45d3f12356c406c631fcd8f538vboxsync && pCPUM->aGuestCpuIdCentaur[0].eax <= UINT32_C(0xc0000004))
c58c758d3642ac45d3f12356c406c631fcd8f538vboxsync pCPUM->aGuestCpuIdCentaur[0].eax = RT_MIN(pCPUM->aGuestCpuIdCentaur[0].eax, UINT32_C(0xc0000002));
c58c758d3642ac45d3f12356c406c631fcd8f538vboxsync pCPUM->aGuestCpuIdCentaur[1].edx = 0; /* all features hidden */
c58c758d3642ac45d3f12356c406c631fcd8f538vboxsync for (i = pCPUM->aGuestCpuIdCentaur[0].eax - UINT32_C(0xc0000000);
c58c758d3642ac45d3f12356c406c631fcd8f538vboxsync pCPUM->aGuestCpuIdCentaur[i] = pCPUM->GuestCpuIdDef;
c58c758d3642ac45d3f12356c406c631fcd8f538vboxsync for (i = 0; i < RT_ELEMENTS(pCPUM->aGuestCpuIdCentaur); i++)
fd66a4782980b7567eb181f809b629e74e4fd697vboxsync pCPUM->aGuestCpuIdCentaur[i] = pCPUM->GuestCpuIdDef;
c58c758d3642ac45d3f12356c406c631fcd8f538vboxsync * Load CPUID overrides from configuration.
c58c758d3642ac45d3f12356c406c631fcd8f538vboxsync uint32_t cElements = ELEMENTS(pCPUM->aGuestCpuIdStd);
c58c758d3642ac45d3f12356c406c631fcd8f538vboxsync for (i=0;; )
c58c758d3642ac45d3f12356c406c631fcd8f538vboxsync while (cElements-- > 0)
c58c758d3642ac45d3f12356c406c631fcd8f538vboxsync PCFGMNODE pNode = CFGMR3GetChildF(CFGMR3GetRoot(pVM), "CPUM/CPUID/%RX32", i);
c58c758d3642ac45d3f12356c406c631fcd8f538vboxsync else if ((i & UINT32_C(0xc0000000)) == UINT32_C(0x80000000))
c58c758d3642ac45d3f12356c406c631fcd8f538vboxsync cElements = RT_ELEMENTS(pCPUM->aGuestCpuIdCentaur);
c58c758d3642ac45d3f12356c406c631fcd8f538vboxsync /* Check if PAE was explicitely enabled by the user. */
c58c758d3642ac45d3f12356c406c631fcd8f538vboxsync bool fEnable = false;
c58c758d3642ac45d3f12356c406c631fcd8f538vboxsync int rc = CFGMR3QueryBool(CFGMR3GetRoot(pVM), "EnablePAE", &fEnable);
c58c758d3642ac45d3f12356c406c631fcd8f538vboxsync CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_PAE);
c58c758d3642ac45d3f12356c406c631fcd8f538vboxsync * Log the cpuid and we're good.
c58c758d3642ac45d3f12356c406c631fcd8f538vboxsync LogRel(("Logical host processors: %d, processor active mask: %08x\n",
c58c758d3642ac45d3f12356c406c631fcd8f538vboxsync RTSystemProcessorGetCount(), RTSystemProcessorGetActiveMask()));
c58c758d3642ac45d3f12356c406c631fcd8f538vboxsync LogRel(("************************* CPUID dump ************************\n"));
c58c758d3642ac45d3f12356c406c631fcd8f538vboxsync DBGFR3Info(pVM, "cpuid", "verbose", DBGFR3InfoLogRelHlp());
c58c758d3642ac45d3f12356c406c631fcd8f538vboxsync DBGFR3InfoLog(pVM, "cpuid", "verbose"); /* macro */
c58c758d3642ac45d3f12356c406c631fcd8f538vboxsync LogRel(("******************** End of CPUID dump **********************\n"));
c58c758d3642ac45d3f12356c406c631fcd8f538vboxsync * Applies relocations to data and code managed by this
c58c758d3642ac45d3f12356c406c631fcd8f538vboxsync * component. This function will be called at init and
c58c758d3642ac45d3f12356c406c631fcd8f538vboxsync * whenever the VMM need to relocate it self inside the GC.
c58c758d3642ac45d3f12356c406c631fcd8f538vboxsync * The CPUM will update the addresses used by the switcher.
c58c758d3642ac45d3f12356c406c631fcd8f538vboxsync * @param pVM The VM.
c58c758d3642ac45d3f12356c406c631fcd8f538vboxsync * Switcher pointers.
c58c758d3642ac45d3f12356c406c631fcd8f538vboxsync pVM->cpum.s.pCPUMGC = VM_GUEST_ADDR(pVM, &pVM->cpum.s);
c58c758d3642ac45d3f12356c406c631fcd8f538vboxsync pVM->cpum.s.pHyperCoreGC = MMHyperCCToGC(pVM, pVM->cpum.s.pHyperCoreR3);
e9525bea57dc13d82fd3392913aebb33d2cb79e3vboxsync * Queries the pointer to the internal CPUMCTX structure
c58c758d3642ac45d3f12356c406c631fcd8f538vboxsync * @returns VBox status code.
daa94352f51be2329ac8660f70396e03a7cb983bvboxsync * @param pVM Handle to the virtual machine.
daa94352f51be2329ac8660f70396e03a7cb983bvboxsync * @param ppCtx Receives the CPUMCTX GC pointer when successful.
c58c758d3642ac45d3f12356c406c631fcd8f538vboxsyncCPUMR3DECL(int) CPUMR3QueryGuestCtxGCPtr(PVM pVM, RCPTRTYPE(PCPUMCTX) *ppCtx)
c58c758d3642ac45d3f12356c406c631fcd8f538vboxsync * Store the address. (Later we might check how's calling, thus the RC.)
b7a07b07543924f45c1fffd2f90de582038b8ba6vboxsync * Terminates the CPUM.
b7a07b07543924f45c1fffd2f90de582038b8ba6vboxsync * Termination means cleaning up and freeing all resources,
8b4a8db7768e94d025f1216ecfcd50d727fa2b7cvboxsync * the VM it self is at this point powered off or suspended.
72a6fe3989272cb2d409b50caca25e1edbca9398vboxsync * @returns VBox status code.
72a6fe3989272cb2d409b50caca25e1edbca9398vboxsync * @param pVM The VM to operate on.
72a6fe3989272cb2d409b50caca25e1edbca9398vboxsync /** @todo ? */
72a6fe3989272cb2d409b50caca25e1edbca9398vboxsync * Resets the CPU.
72a6fe3989272cb2d409b50caca25e1edbca9398vboxsync * @returns VINF_SUCCESS.
fd66a4782980b7567eb181f809b629e74e4fd697vboxsync * @param pVM The VM handle.
72a6fe3989272cb2d409b50caca25e1edbca9398vboxsync * Initialize everything to ZERO first.
72a6fe3989272cb2d409b50caca25e1edbca9398vboxsync uint32_t fUseFlags = pVM->cpum.s.fUseFlags & ~CPUM_USED_FPU_SINCE_REM;
e9525bea57dc13d82fd3392913aebb33d2cb79e3vboxsync pCtx->cr0 = X86_CR0_CD | X86_CR0_NW | X86_CR0_ET; //0x60000010
72a6fe3989272cb2d409b50caca25e1edbca9398vboxsync pCtx->csHid.Attr.n.u1DescType = 1; /* code/data segment */
72a6fe3989272cb2d409b50caca25e1edbca9398vboxsync pCtx->csHid.Attr.n.u4Type = X86_SEL_TYPE_READ | X86_SEL_TYPE_CODE;
72a6fe3989272cb2d409b50caca25e1edbca9398vboxsync pCtx->dsHid.Attr.n.u1DescType = 1; /* code/data segment */
72a6fe3989272cb2d409b50caca25e1edbca9398vboxsync pCtx->esHid.Attr.n.u1DescType = 1; /* code/data segment */
72a6fe3989272cb2d409b50caca25e1edbca9398vboxsync pCtx->fsHid.Attr.n.u1DescType = 1; /* code/data segment */
72a6fe3989272cb2d409b50caca25e1edbca9398vboxsync pCtx->gsHid.Attr.n.u1DescType = 1; /* code/data segment */
72a6fe3989272cb2d409b50caca25e1edbca9398vboxsync pCtx->ssHid.Attr.n.u1DescType = 1; /* code/data segment */
72a6fe3989272cb2d409b50caca25e1edbca9398vboxsync pCtx->ldtrHid.Attr.n.u4Type = X86_SEL_TYPE_SYS_LDT;
72a6fe3989272cb2d409b50caca25e1edbca9398vboxsync pCtx->trHid.Attr.n.u4Type = X86_SEL_TYPE_SYS_286_TSS_BUSY;
daa94352f51be2329ac8660f70396e03a7cb983bvboxsync pCtx->fpu.FTW = 0xff; /* All tags are set, i.e. the regs are empty. */
daa94352f51be2329ac8660f70396e03a7cb983bvboxsync /* Init PAT MSR */
daa94352f51be2329ac8660f70396e03a7cb983bvboxsync pCtx->msrPAT = UINT64_C(0x0007040600070406); /** @todo correct? */
daa94352f51be2329ac8660f70396e03a7cb983bvboxsync * Execute state save operation.
daa94352f51be2329ac8660f70396e03a7cb983bvboxsync * @returns VBox status code.
daa94352f51be2329ac8660f70396e03a7cb983bvboxsync * @param pVM VM Handle.
daa94352f51be2329ac8660f70396e03a7cb983bvboxsync * @param pSSM SSM operation handle.
daa94352f51be2329ac8660f70396e03a7cb983bvboxsyncstatic DECLCALLBACK(int) cpumR3Save(PVM pVM, PSSMHANDLE pSSM)
daa94352f51be2329ac8660f70396e03a7cb983bvboxsync SSMR3PutMem(pSSM, &pVM->cpum.s.Hyper, sizeof(pVM->cpum.s.Hyper));
daa94352f51be2329ac8660f70396e03a7cb983bvboxsync SSMR3PutMem(pSSM, &pVM->cpum.s.Guest, sizeof(pVM->cpum.s.Guest));
daa94352f51be2329ac8660f70396e03a7cb983bvboxsync SSMR3PutU32(pSSM, ELEMENTS(pVM->cpum.s.aGuestCpuIdStd));
daa94352f51be2329ac8660f70396e03a7cb983bvboxsync SSMR3PutMem(pSSM, &pVM->cpum.s.aGuestCpuIdStd[0], sizeof(pVM->cpum.s.aGuestCpuIdStd));
daa94352f51be2329ac8660f70396e03a7cb983bvboxsync SSMR3PutU32(pSSM, ELEMENTS(pVM->cpum.s.aGuestCpuIdExt));
daa94352f51be2329ac8660f70396e03a7cb983bvboxsync SSMR3PutMem(pSSM, &pVM->cpum.s.aGuestCpuIdExt[0], sizeof(pVM->cpum.s.aGuestCpuIdExt));
daa94352f51be2329ac8660f70396e03a7cb983bvboxsync SSMR3PutU32(pSSM, ELEMENTS(pVM->cpum.s.aGuestCpuIdCentaur));
daa94352f51be2329ac8660f70396e03a7cb983bvboxsync SSMR3PutMem(pSSM, &pVM->cpum.s.aGuestCpuIdCentaur[0], sizeof(pVM->cpum.s.aGuestCpuIdCentaur));
daa94352f51be2329ac8660f70396e03a7cb983bvboxsync SSMR3PutMem(pSSM, &pVM->cpum.s.GuestCpuIdDef, sizeof(pVM->cpum.s.GuestCpuIdDef));
daa94352f51be2329ac8660f70396e03a7cb983bvboxsync /* Add the cpuid for checking that the cpu is unchanged. */
daa94352f51be2329ac8660f70396e03a7cb983bvboxsync ASMCpuId(0, &au32CpuId[0], &au32CpuId[1], &au32CpuId[2], &au32CpuId[3]);
daa94352f51be2329ac8660f70396e03a7cb983bvboxsync ASMCpuId(1, &au32CpuId[4], &au32CpuId[5], &au32CpuId[6], &au32CpuId[7]);
daa94352f51be2329ac8660f70396e03a7cb983bvboxsync return SSMR3PutMem(pSSM, &au32CpuId[0], sizeof(au32CpuId));
daa94352f51be2329ac8660f70396e03a7cb983bvboxsync * Execute state load operation.
daa94352f51be2329ac8660f70396e03a7cb983bvboxsync * @returns VBox status code.
daa94352f51be2329ac8660f70396e03a7cb983bvboxsync * @param pVM VM Handle.
daa94352f51be2329ac8660f70396e03a7cb983bvboxsync * @param pSSM SSM operation handle.
daa94352f51be2329ac8660f70396e03a7cb983bvboxsync * @param u32Version Data layout version.
daa94352f51be2329ac8660f70396e03a7cb983bvboxsyncstatic DECLCALLBACK(int) cpumR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t u32Version)
daa94352f51be2329ac8660f70396e03a7cb983bvboxsync * Validate version.
daa94352f51be2329ac8660f70396e03a7cb983bvboxsync Log(("cpuR3Load: Invalid version u32Version=%d!\n", u32Version));
daa94352f51be2329ac8660f70396e03a7cb983bvboxsync uint32_t uESP = pVM->cpum.s.Hyper.esp; /* see VMMR3Relocate(). */
daa94352f51be2329ac8660f70396e03a7cb983bvboxsync SSMR3GetMem(pSSM, &pVM->cpum.s.Hyper, sizeof(pVM->cpum.s.Hyper));
daa94352f51be2329ac8660f70396e03a7cb983bvboxsync SSMR3GetMem(pSSM, &pVM->cpum.s.Guest, sizeof(pVM->cpum.s.Guest));
daa94352f51be2329ac8660f70396e03a7cb983bvboxsync int rc = SSMR3GetU32(pSSM, &cElements); AssertRCReturn(rc, rc);
daa94352f51be2329ac8660f70396e03a7cb983bvboxsync if (cElements != ELEMENTS(pVM->cpum.s.aGuestCpuIdStd))
daa94352f51be2329ac8660f70396e03a7cb983bvboxsync SSMR3GetMem(pSSM, &pVM->cpum.s.aGuestCpuIdStd[0], sizeof(pVM->cpum.s.aGuestCpuIdStd));
daa94352f51be2329ac8660f70396e03a7cb983bvboxsync rc = SSMR3GetU32(pSSM, &cElements); AssertRCReturn(rc, rc);
daa94352f51be2329ac8660f70396e03a7cb983bvboxsync if (cElements != ELEMENTS(pVM->cpum.s.aGuestCpuIdExt))
daa94352f51be2329ac8660f70396e03a7cb983bvboxsync SSMR3GetMem(pSSM, &pVM->cpum.s.aGuestCpuIdExt[0], sizeof(pVM->cpum.s.aGuestCpuIdExt));
daa94352f51be2329ac8660f70396e03a7cb983bvboxsync rc = SSMR3GetU32(pSSM, &cElements); AssertRCReturn(rc, rc);
daa94352f51be2329ac8660f70396e03a7cb983bvboxsync if (cElements != RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdCentaur))
daa94352f51be2329ac8660f70396e03a7cb983bvboxsync SSMR3GetMem(pSSM, &pVM->cpum.s.aGuestCpuIdCentaur[0], sizeof(pVM->cpum.s.aGuestCpuIdCentaur));
daa94352f51be2329ac8660f70396e03a7cb983bvboxsync SSMR3GetMem(pSSM, &pVM->cpum.s.GuestCpuIdDef, sizeof(pVM->cpum.s.GuestCpuIdDef));
daa94352f51be2329ac8660f70396e03a7cb983bvboxsync * Check that the basic cpuid id information is unchanged.
daa94352f51be2329ac8660f70396e03a7cb983bvboxsync ASMCpuId(0, &au32CpuId[0], &au32CpuId[1], &au32CpuId[2], &au32CpuId[3]);
daa94352f51be2329ac8660f70396e03a7cb983bvboxsync ASMCpuId(1, &au32CpuId[4], &au32CpuId[5], &au32CpuId[6], &au32CpuId[7]);
daa94352f51be2329ac8660f70396e03a7cb983bvboxsync rc = SSMR3GetMem(pSSM, &au32CpuIdSaved[0], sizeof(au32CpuIdSaved));
daa94352f51be2329ac8660f70396e03a7cb983bvboxsync /* Ignore APIC ID (AMD specs). */
daa94352f51be2329ac8660f70396e03a7cb983bvboxsync /* Ignore the number of Logical CPUs (AMD specs). */
daa94352f51be2329ac8660f70396e03a7cb983bvboxsync /* do the compare */
daa94352f51be2329ac8660f70396e03a7cb983bvboxsync if (memcmp(au32CpuIdSaved, au32CpuId, sizeof(au32CpuIdSaved)))
e9525bea57dc13d82fd3392913aebb33d2cb79e3vboxsync if (SSMR3HandleGetAfter(pSSM) == SSMAFTER_DEBUG_IT)
e9525bea57dc13d82fd3392913aebb33d2cb79e3vboxsync LogRel(("cpumR3Load: CpuId mismatch! (ignored due to SSMAFTER_DEBUG_IT)\n"
e9525bea57dc13d82fd3392913aebb33d2cb79e3vboxsync "Saved=%.*Vhxs\n"
e9525bea57dc13d82fd3392913aebb33d2cb79e3vboxsync "Real =%.*Vhxs\n",
e9525bea57dc13d82fd3392913aebb33d2cb79e3vboxsync "Saved=%.*Vhxs\n"
e9525bea57dc13d82fd3392913aebb33d2cb79e3vboxsync "Real =%.*Vhxs\n",
e9525bea57dc13d82fd3392913aebb33d2cb79e3vboxsync * Formats the EFLAGS value into mnemonics.
e9525bea57dc13d82fd3392913aebb33d2cb79e3vboxsync * @param pszEFlags Where to write the mnemonics. (Assumes sufficient buffer space.)
e9525bea57dc13d82fd3392913aebb33d2cb79e3vboxsync * @param efl The EFLAGS value.
e9525bea57dc13d82fd3392913aebb33d2cb79e3vboxsyncstatic void cpumR3InfoFormatFlags(char *pszEFlags, uint32_t efl)
e9525bea57dc13d82fd3392913aebb33d2cb79e3vboxsync * Format the flags.
daa94352f51be2329ac8660f70396e03a7cb983bvboxsync static struct
e9525bea57dc13d82fd3392913aebb33d2cb79e3vboxsync const char *pszSet; const char *pszClear; uint32_t fFlag;
daa94352f51be2329ac8660f70396e03a7cb983bvboxsync const char *pszAdd = s_aFlags[i].fFlag & efl ? s_aFlags[i].pszSet : s_aFlags[i].pszClear;
e9525bea57dc13d82fd3392913aebb33d2cb79e3vboxsync * Formats a full register dump.
daa94352f51be2329ac8660f70396e03a7cb983bvboxsync * @param pVM VM Handle.
daa94352f51be2329ac8660f70396e03a7cb983bvboxsync * @param pCtx The context to format.
daa94352f51be2329ac8660f70396e03a7cb983bvboxsync * @param pCtxCore The context core to format.
daa94352f51be2329ac8660f70396e03a7cb983bvboxsync * @param pHlp Output functions.
daa94352f51be2329ac8660f70396e03a7cb983bvboxsync * @param enmType The dump type.
daa94352f51be2329ac8660f70396e03a7cb983bvboxsync * @param pszPrefix Register name prefix.
daa94352f51be2329ac8660f70396e03a7cb983bvboxsyncstatic void cpumR3InfoOne(PVM pVM, PCPUMCTX pCtx, PCCPUMCTXCORE pCtxCore, PCDBGFINFOHLP pHlp, CPUMDUMPTYPE enmType, const char *pszPrefix)
daa94352f51be2329ac8660f70396e03a7cb983bvboxsync * Format the EFLAGS.
daa94352f51be2329ac8660f70396e03a7cb983bvboxsync * Format the registers.
daa94352f51be2329ac8660f70396e03a7cb983bvboxsync "%srax=%016RX64 %srbx=%016RX64 %srcx=%016RX64 %srdx=%016RX64\n"
daa94352f51be2329ac8660f70396e03a7cb983bvboxsync "%srsi=%016RX64 %srdi=%016RX64 %sr8 =%016RX64 %sr9 =%016RX64\n"
daa94352f51be2329ac8660f70396e03a7cb983bvboxsync "%sr10=%016RX64 %sr11=%016RX64 %sr12=%016RX64 %sr13=%016RX64\n"
daa94352f51be2329ac8660f70396e03a7cb983bvboxsync "%sr14=%016RX64 %sr15=%016RX64\n"
daa94352f51be2329ac8660f70396e03a7cb983bvboxsync "%srip=%016RX64 %srsp=%016RX64 %srbp=%016RX64 %siopl=%d %*s\n"
e9525bea57dc13d82fd3392913aebb33d2cb79e3vboxsync "%scs=%04x %sss=%04x %sds=%04x %ses=%04x %sfs=%04x %sgs=%04x %seflags=%08x\n",
e9525bea57dc13d82fd3392913aebb33d2cb79e3vboxsync pszPrefix, pCtxCore->rax, pszPrefix, pCtxCore->rbx, pszPrefix, pCtxCore->rcx, pszPrefix, pCtxCore->rdx, pszPrefix, pCtxCore->rsi, pszPrefix, pCtxCore->rdi,
daa94352f51be2329ac8660f70396e03a7cb983bvboxsync pszPrefix, pCtxCore->r8, pszPrefix, pCtxCore->r9, pszPrefix, pCtxCore->r10, pszPrefix, pCtxCore->r11, pszPrefix, pCtxCore->r12, pszPrefix, pCtxCore->r13,
daa94352f51be2329ac8660f70396e03a7cb983bvboxsync pszPrefix, pCtxCore->r14, pszPrefix, pCtxCore->r15,
daa94352f51be2329ac8660f70396e03a7cb983bvboxsync pszPrefix, pCtxCore->rip, pszPrefix, pCtxCore->rsp, pszPrefix, pCtxCore->rbp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
daa94352f51be2329ac8660f70396e03a7cb983bvboxsync pszPrefix, (RTSEL)pCtxCore->cs, pszPrefix, (RTSEL)pCtxCore->ss, pszPrefix, (RTSEL)pCtxCore->ds, pszPrefix, (RTSEL)pCtxCore->es,
daa94352f51be2329ac8660f70396e03a7cb983bvboxsync pszPrefix, (RTSEL)pCtxCore->fs, pszPrefix, (RTSEL)pCtxCore->gs, pszPrefix, efl);
daa94352f51be2329ac8660f70396e03a7cb983bvboxsync "%seax=%08x %sebx=%08x %secx=%08x %sedx=%08x %sesi=%08x %sedi=%08x\n"
daa94352f51be2329ac8660f70396e03a7cb983bvboxsync "%seip=%08x %sesp=%08x %sebp=%08x %siopl=%d %*s\n"
daa94352f51be2329ac8660f70396e03a7cb983bvboxsync "%scs=%04x %sss=%04x %sds=%04x %ses=%04x %sfs=%04x %sgs=%04x %seflags=%08x\n",
daa94352f51be2329ac8660f70396e03a7cb983bvboxsync pszPrefix, pCtxCore->eax, pszPrefix, pCtxCore->ebx, pszPrefix, pCtxCore->ecx, pszPrefix, pCtxCore->edx, pszPrefix, pCtxCore->esi, pszPrefix, pCtxCore->edi,
daa94352f51be2329ac8660f70396e03a7cb983bvboxsync pszPrefix, pCtxCore->eip, pszPrefix, pCtxCore->esp, pszPrefix, pCtxCore->ebp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
daa94352f51be2329ac8660f70396e03a7cb983bvboxsync pszPrefix, (RTSEL)pCtxCore->cs, pszPrefix, (RTSEL)pCtxCore->ss, pszPrefix, (RTSEL)pCtxCore->ds, pszPrefix, (RTSEL)pCtxCore->es,
daa94352f51be2329ac8660f70396e03a7cb983bvboxsync pszPrefix, (RTSEL)pCtxCore->fs, pszPrefix, (RTSEL)pCtxCore->gs, pszPrefix, efl);
fa6dbd9c9e9645298cca864aa561382469907905vboxsync "%srax=%016RX64 %srbx=%016RX64 %srcx=%016RX64 %srdx=%016RX64\n"
fa6dbd9c9e9645298cca864aa561382469907905vboxsync "%srsi=%016RX64 %srdi=%016RX64 %sr8 =%016RX64 %sr9 =%016RX64\n"
fa6dbd9c9e9645298cca864aa561382469907905vboxsync "%sr10=%016RX64 %sr11=%016RX64 %sr12=%016RX64 %sr13=%016RX64\n"
fa6dbd9c9e9645298cca864aa561382469907905vboxsync "%sr14=%016RX64 %sr15=%016RX64\n"
fa6dbd9c9e9645298cca864aa561382469907905vboxsync "%srip=%016RX64 %srsp=%016RX64 %srbp=%016RX64 %siopl=%d %*s\n"
daa94352f51be2329ac8660f70396e03a7cb983bvboxsync "%scs=%04x %sss=%04x %sds=%04x %ses=%04x %sfs=%04x %sgs=%04x %str=%04x %seflags=%08x\n"
daa94352f51be2329ac8660f70396e03a7cb983bvboxsync "%scr0=%08RX64 %scr2=%08RX64 %scr3=%08RX64 %scr4=%08RX64 %sgdtr=%VGv:%04x %sldtr=%04x\n"
daa94352f51be2329ac8660f70396e03a7cb983bvboxsync pszPrefix, pCtxCore->rax, pszPrefix, pCtxCore->rbx, pszPrefix, pCtxCore->rcx, pszPrefix, pCtxCore->rdx, pszPrefix, pCtxCore->rsi, pszPrefix, pCtxCore->rdi,
daa94352f51be2329ac8660f70396e03a7cb983bvboxsync pszPrefix, pCtxCore->r8, pszPrefix, pCtxCore->r9, pszPrefix, pCtxCore->r10, pszPrefix, pCtxCore->r11, pszPrefix, pCtxCore->r12, pszPrefix, pCtxCore->r13,
daa94352f51be2329ac8660f70396e03a7cb983bvboxsync pszPrefix, pCtxCore->r14, pszPrefix, pCtxCore->r15,
daa94352f51be2329ac8660f70396e03a7cb983bvboxsync pszPrefix, pCtxCore->rip, pszPrefix, pCtxCore->rsp, pszPrefix, pCtxCore->rbp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
daa94352f51be2329ac8660f70396e03a7cb983bvboxsync pszPrefix, (RTSEL)pCtxCore->cs, pszPrefix, (RTSEL)pCtxCore->ss, pszPrefix, (RTSEL)pCtxCore->ds, pszPrefix, (RTSEL)pCtxCore->es,
daa94352f51be2329ac8660f70396e03a7cb983bvboxsync pszPrefix, (RTSEL)pCtxCore->fs, pszPrefix, (RTSEL)pCtxCore->gs, pszPrefix, (RTSEL)pCtx->tr, pszPrefix, efl,
daa94352f51be2329ac8660f70396e03a7cb983bvboxsync pszPrefix, pCtx->cr0, pszPrefix, pCtx->cr2, pszPrefix, pCtx->cr3, pszPrefix, pCtx->cr4,
daa94352f51be2329ac8660f70396e03a7cb983bvboxsync pszPrefix, pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pszPrefix, (RTSEL)pCtx->ldtr);
daa94352f51be2329ac8660f70396e03a7cb983bvboxsync "%seax=%08x %sebx=%08x %secx=%08x %sedx=%08x %sesi=%08x %sedi=%08x\n"
daa94352f51be2329ac8660f70396e03a7cb983bvboxsync "%seip=%08x %sesp=%08x %sebp=%08x %siopl=%d %*s\n"
daa94352f51be2329ac8660f70396e03a7cb983bvboxsync "%scs=%04x %sss=%04x %sds=%04x %ses=%04x %sfs=%04x %sgs=%04x %str=%04x %seflags=%08x\n"
daa94352f51be2329ac8660f70396e03a7cb983bvboxsync "%scr0=%08RX64 %scr2=%08RX64 %scr3=%08RX64 %scr4=%08RX64 %sgdtr=%VGv:%04x %sldtr=%04x\n"
fa6dbd9c9e9645298cca864aa561382469907905vboxsync pszPrefix, pCtxCore->eax, pszPrefix, pCtxCore->ebx, pszPrefix, pCtxCore->ecx, pszPrefix, pCtxCore->edx, pszPrefix, pCtxCore->esi, pszPrefix, pCtxCore->edi,
daa94352f51be2329ac8660f70396e03a7cb983bvboxsync pszPrefix, pCtxCore->eip, pszPrefix, pCtxCore->esp, pszPrefix, pCtxCore->ebp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
daa94352f51be2329ac8660f70396e03a7cb983bvboxsync pszPrefix, (RTSEL)pCtxCore->cs, pszPrefix, (RTSEL)pCtxCore->ss, pszPrefix, (RTSEL)pCtxCore->ds, pszPrefix, (RTSEL)pCtxCore->es,
fa6dbd9c9e9645298cca864aa561382469907905vboxsync pszPrefix, (RTSEL)pCtxCore->fs, pszPrefix, (RTSEL)pCtxCore->gs, pszPrefix, (RTSEL)pCtx->tr, pszPrefix, efl,
daa94352f51be2329ac8660f70396e03a7cb983bvboxsync pszPrefix, pCtx->cr0, pszPrefix, pCtx->cr2, pszPrefix, pCtx->cr3, pszPrefix, pCtx->cr4,
fa6dbd9c9e9645298cca864aa561382469907905vboxsync pszPrefix, pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pszPrefix, (RTSEL)pCtx->ldtr);
fa6dbd9c9e9645298cca864aa561382469907905vboxsync "%srax=%016RX64 %srbx=%016RX64 %srcx=%016RX64 %srdx=%016RX64\n"
fa6dbd9c9e9645298cca864aa561382469907905vboxsync "%srsi=%016RX64 %srdi=%016RX64 %sr8 =%016RX64 %sr9 =%016RX64\n"
daa94352f51be2329ac8660f70396e03a7cb983bvboxsync "%sr10=%016RX64 %sr11=%016RX64 %sr12=%016RX64 %sr13=%016RX64\n"
fa6dbd9c9e9645298cca864aa561382469907905vboxsync "%sr14=%016RX64 %sr15=%016RX64\n"
fa6dbd9c9e9645298cca864aa561382469907905vboxsync "%srip=%016RX64 %srsp=%016RX64 %srbp=%016RX64 %siopl=%d %*s\n"
fa6dbd9c9e9645298cca864aa561382469907905vboxsync "%scs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
fa6dbd9c9e9645298cca864aa561382469907905vboxsync "%sds={%04x base=%016RX64 limit=%08x flags=%08x}\n"
fa6dbd9c9e9645298cca864aa561382469907905vboxsync "%ses={%04x base=%016RX64 limit=%08x flags=%08x}\n"
fa6dbd9c9e9645298cca864aa561382469907905vboxsync "%sfs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
fa6dbd9c9e9645298cca864aa561382469907905vboxsync "%sgs={%04x base=%016RX64 limit=%08x flags=%08x}\n"
fa6dbd9c9e9645298cca864aa561382469907905vboxsync "%sss={%04x base=%016RX64 limit=%08x flags=%08x}\n"
fa6dbd9c9e9645298cca864aa561382469907905vboxsync "%scr0=%016RX64 %scr2=%016RX64 %scr3=%016RX64 %scr4=%016RX64\n"
fa6dbd9c9e9645298cca864aa561382469907905vboxsync "%sdr0=%016RX64 %sdr1=%016RX64 %sdr2=%016RX64 %sdr3=%016RX64\n"
fa6dbd9c9e9645298cca864aa561382469907905vboxsync "%sdr4=%016RX64 %sdr5=%016RX64 %sdr6=%016RX64 %sdr7=%016RX64\n"
fa6dbd9c9e9645298cca864aa561382469907905vboxsync "%sgdtr=%016RX64:%04x %sidtr=%016RX64:%04x %seflags=%08x\n"
fa6dbd9c9e9645298cca864aa561382469907905vboxsync "%sldtr={%04x base=%08RX64 limit=%08x flags=%08x}\n"
fa6dbd9c9e9645298cca864aa561382469907905vboxsync "%str ={%04x base=%08RX64 limit=%08x flags=%08x}\n"
fa6dbd9c9e9645298cca864aa561382469907905vboxsync "%sSysEnter={cs=%04llx eip=%08llx esp=%08llx}\n"
fa6dbd9c9e9645298cca864aa561382469907905vboxsync pszPrefix, pCtxCore->rax, pszPrefix, pCtxCore->rbx, pszPrefix, pCtxCore->rcx, pszPrefix, pCtxCore->rdx, pszPrefix, pCtxCore->rsi, pszPrefix, pCtxCore->rdi,
fa6dbd9c9e9645298cca864aa561382469907905vboxsync pszPrefix, pCtxCore->r8, pszPrefix, pCtxCore->r9, pszPrefix, pCtxCore->r10, pszPrefix, pCtxCore->r11, pszPrefix, pCtxCore->r12, pszPrefix, pCtxCore->r13,
fa6dbd9c9e9645298cca864aa561382469907905vboxsync pszPrefix, pCtxCore->r14, pszPrefix, pCtxCore->r15,
daa94352f51be2329ac8660f70396e03a7cb983bvboxsync pszPrefix, pCtxCore->rip, pszPrefix, pCtxCore->rsp, pszPrefix, pCtxCore->rbp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
fa6dbd9c9e9645298cca864aa561382469907905vboxsync pszPrefix, (RTSEL)pCtxCore->cs, pCtx->csHid.u64Base, pCtx->csHid.u32Limit, pCtx->csHid.Attr.u,
fa6dbd9c9e9645298cca864aa561382469907905vboxsync pszPrefix, (RTSEL)pCtxCore->ds, pCtx->dsHid.u64Base, pCtx->dsHid.u32Limit, pCtx->dsHid.Attr.u,
fa6dbd9c9e9645298cca864aa561382469907905vboxsync pszPrefix, (RTSEL)pCtxCore->es, pCtx->esHid.u64Base, pCtx->esHid.u32Limit, pCtx->esHid.Attr.u,
fa6dbd9c9e9645298cca864aa561382469907905vboxsync pszPrefix, (RTSEL)pCtxCore->fs, pCtx->fsHid.u64Base, pCtx->fsHid.u32Limit, pCtx->fsHid.Attr.u,
fa6dbd9c9e9645298cca864aa561382469907905vboxsync pszPrefix, (RTSEL)pCtxCore->gs, pCtx->gsHid.u64Base, pCtx->gsHid.u32Limit, pCtx->gsHid.Attr.u,
fa6dbd9c9e9645298cca864aa561382469907905vboxsync pszPrefix, (RTSEL)pCtxCore->ss, pCtx->ssHid.u64Base, pCtx->ssHid.u32Limit, pCtx->ssHid.Attr.u,
fa6dbd9c9e9645298cca864aa561382469907905vboxsync pszPrefix, pCtx->cr0, pszPrefix, pCtx->cr2, pszPrefix, pCtx->cr3, pszPrefix, pCtx->cr4,
fa6dbd9c9e9645298cca864aa561382469907905vboxsync pszPrefix, pCtx->dr0, pszPrefix, pCtx->dr1, pszPrefix, pCtx->dr2, pszPrefix, pCtx->dr3,
fa6dbd9c9e9645298cca864aa561382469907905vboxsync pszPrefix, pCtx->dr4, pszPrefix, pCtx->dr5, pszPrefix, pCtx->dr6, pszPrefix, pCtx->dr7,
fa6dbd9c9e9645298cca864aa561382469907905vboxsync pszPrefix, pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pszPrefix, pCtx->idtr.pIdt, pCtx->idtr.cbIdt, pszPrefix, efl,
fa6dbd9c9e9645298cca864aa561382469907905vboxsync pszPrefix, (RTSEL)pCtx->ldtr, pCtx->ldtrHid.u64Base, pCtx->ldtrHid.u32Limit, pCtx->ldtrHid.Attr.u,
fa6dbd9c9e9645298cca864aa561382469907905vboxsync pszPrefix, (RTSEL)pCtx->tr, pCtx->trHid.u64Base, pCtx->trHid.u32Limit, pCtx->trHid.Attr.u,
fa6dbd9c9e9645298cca864aa561382469907905vboxsync pszPrefix, pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp);
fa6dbd9c9e9645298cca864aa561382469907905vboxsync "%seax=%08x %sebx=%08x %secx=%08x %sedx=%08x %sesi=%08x %sedi=%08x\n"
fa6dbd9c9e9645298cca864aa561382469907905vboxsync "%seip=%08x %sesp=%08x %sebp=%08x %siopl=%d %*s\n"
fa6dbd9c9e9645298cca864aa561382469907905vboxsync "%scs={%04x base=%016RX64 limit=%08x flags=%08x} %sdr0=%08RX64 %sdr1=%08RX64\n"
fa6dbd9c9e9645298cca864aa561382469907905vboxsync "%sds={%04x base=%016RX64 limit=%08x flags=%08x} %sdr2=%08RX64 %sdr3=%08RX64\n"
daa94352f51be2329ac8660f70396e03a7cb983bvboxsync "%ses={%04x base=%016RX64 limit=%08x flags=%08x} %sdr4=%08RX64 %sdr5=%08RX64\n"
daa94352f51be2329ac8660f70396e03a7cb983bvboxsync "%sfs={%04x base=%016RX64 limit=%08x flags=%08x} %sdr6=%08RX64 %sdr7=%08RX64\n"
fa6dbd9c9e9645298cca864aa561382469907905vboxsync "%sgs={%04x base=%016RX64 limit=%08x flags=%08x} %scr0=%08RX64 %scr2=%08RX64\n"
daa94352f51be2329ac8660f70396e03a7cb983bvboxsync "%sss={%04x base=%016RX64 limit=%08x flags=%08x} %scr3=%08RX64 %scr4=%08RX64\n"
daa94352f51be2329ac8660f70396e03a7cb983bvboxsync "%sgdtr=%016RX64:%04x %sidtr=%016RX64:%04x %seflags=%08x\n"
fa6dbd9c9e9645298cca864aa561382469907905vboxsync "%sldtr={%04x base=%08RX64 limit=%08x flags=%08x}\n"
fa6dbd9c9e9645298cca864aa561382469907905vboxsync "%str ={%04x base=%08RX64 limit=%08x flags=%08x}\n"
fa6dbd9c9e9645298cca864aa561382469907905vboxsync "%sSysEnter={cs=%04llx eip=%08llx esp=%08llx}\n"
daa94352f51be2329ac8660f70396e03a7cb983bvboxsync pszPrefix, pCtxCore->eax, pszPrefix, pCtxCore->ebx, pszPrefix, pCtxCore->ecx, pszPrefix, pCtxCore->edx, pszPrefix, pCtxCore->esi, pszPrefix, pCtxCore->edi,
daa94352f51be2329ac8660f70396e03a7cb983bvboxsync pszPrefix, pCtxCore->eip, pszPrefix, pCtxCore->esp, pszPrefix, pCtxCore->ebp, pszPrefix, X86_EFL_GET_IOPL(efl), *pszPrefix ? 33 : 31, szEFlags,
daa94352f51be2329ac8660f70396e03a7cb983bvboxsync pszPrefix, (RTSEL)pCtxCore->cs, pCtx->csHid.u64Base, pCtx->csHid.u32Limit, pCtx->csHid.Attr.u, pszPrefix, pCtx->dr0, pszPrefix, pCtx->dr1,
daa94352f51be2329ac8660f70396e03a7cb983bvboxsync pszPrefix, (RTSEL)pCtxCore->ds, pCtx->dsHid.u64Base, pCtx->dsHid.u32Limit, pCtx->dsHid.Attr.u, pszPrefix, pCtx->dr2, pszPrefix, pCtx->dr3,
daa94352f51be2329ac8660f70396e03a7cb983bvboxsync pszPrefix, (RTSEL)pCtxCore->es, pCtx->esHid.u64Base, pCtx->esHid.u32Limit, pCtx->esHid.Attr.u, pszPrefix, pCtx->dr4, pszPrefix, pCtx->dr5,
daa94352f51be2329ac8660f70396e03a7cb983bvboxsync pszPrefix, (RTSEL)pCtxCore->fs, pCtx->fsHid.u64Base, pCtx->fsHid.u32Limit, pCtx->fsHid.Attr.u, pszPrefix, pCtx->dr6, pszPrefix, pCtx->dr7,
daa94352f51be2329ac8660f70396e03a7cb983bvboxsync pszPrefix, (RTSEL)pCtxCore->gs, pCtx->gsHid.u64Base, pCtx->gsHid.u32Limit, pCtx->gsHid.Attr.u, pszPrefix, pCtx->cr0, pszPrefix, pCtx->cr2,
daa94352f51be2329ac8660f70396e03a7cb983bvboxsync pszPrefix, (RTSEL)pCtxCore->ss, pCtx->ssHid.u64Base, pCtx->ssHid.u32Limit, pCtx->ssHid.Attr.u, pszPrefix, pCtx->cr3, pszPrefix, pCtx->cr4,
daa94352f51be2329ac8660f70396e03a7cb983bvboxsync pszPrefix, pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pszPrefix, pCtx->idtr.pIdt, pCtx->idtr.cbIdt, pszPrefix, efl,
830a019ad79a45e6bf7a5419efd5a729a36e599evboxsync pszPrefix, (RTSEL)pCtx->ldtr, pCtx->ldtrHid.u64Base, pCtx->ldtrHid.u32Limit, pCtx->ldtrHid.Attr.u,
daa94352f51be2329ac8660f70396e03a7cb983bvboxsync pszPrefix, (RTSEL)pCtx->tr, pCtx->trHid.u64Base, pCtx->trHid.u32Limit, pCtx->trHid.Attr.u,
daa94352f51be2329ac8660f70396e03a7cb983bvboxsync pszPrefix, pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp);
830a019ad79a45e6bf7a5419efd5a729a36e599evboxsync "%sFCW=%04x %sFSW=%04x %sFTW=%02x\n"
830a019ad79a45e6bf7a5419efd5a729a36e599evboxsync "%sres1=%02x %sFOP=%04x %sFPUIP=%08x %sCS=%04x %sRsvrd1=%04x\n"
830a019ad79a45e6bf7a5419efd5a729a36e599evboxsync "%sFPUDP=%04x %sDS=%04x %sRsvrd2=%04x %sMXCSR=%08x %sMXCSR_MASK=%08x\n"
830a019ad79a45e6bf7a5419efd5a729a36e599evboxsync pszPrefix, pCtx->fpu.FCW, pszPrefix, pCtx->fpu.FSW, pszPrefix, pCtx->fpu.FTW,
830a019ad79a45e6bf7a5419efd5a729a36e599evboxsync pszPrefix, pCtx->fpu.huh1, pszPrefix, pCtx->fpu.FOP, pszPrefix, pCtx->fpu.FPUIP, pszPrefix, pCtx->fpu.CS, pszPrefix, pCtx->fpu.Rsvrd1,
daa94352f51be2329ac8660f70396e03a7cb983bvboxsync pszPrefix, pCtx->fpu.FPUDP, pszPrefix, pCtx->fpu.DS, pszPrefix, pCtx->fpu.Rsrvd2,
daa94352f51be2329ac8660f70396e03a7cb983bvboxsync pszPrefix, pCtx->fpu.MXCSR, pszPrefix, pCtx->fpu.MXCSR_MASK);
daa94352f51be2329ac8660f70396e03a7cb983bvboxsync "%sEFER =%016RX64\n"
daa94352f51be2329ac8660f70396e03a7cb983bvboxsync "%sPAT =%016RX64\n"
daa94352f51be2329ac8660f70396e03a7cb983bvboxsync "%sSTAR =%016RX64\n"
daa94352f51be2329ac8660f70396e03a7cb983bvboxsync "%sCSTAR =%016RX64\n"
daa94352f51be2329ac8660f70396e03a7cb983bvboxsync "%sLSTAR =%016RX64\n"
daa94352f51be2329ac8660f70396e03a7cb983bvboxsync "%sSFMASK =%016RX64\n"
daa94352f51be2329ac8660f70396e03a7cb983bvboxsync "%sFSBASE =%016RX64\n"
daa94352f51be2329ac8660f70396e03a7cb983bvboxsync "%sGSBASE =%016RX64\n"
daa94352f51be2329ac8660f70396e03a7cb983bvboxsync "%sKERNELGSBASE =%016RX64\n",
daa94352f51be2329ac8660f70396e03a7cb983bvboxsync * Display all cpu states and any other cpum info.
daa94352f51be2329ac8660f70396e03a7cb983bvboxsync * @param pVM VM Handle.
daa94352f51be2329ac8660f70396e03a7cb983bvboxsync * @param pHlp The info helper functions.
daa94352f51be2329ac8660f70396e03a7cb983bvboxsync * @param pszArgs Arguments, ignored.
daa94352f51be2329ac8660f70396e03a7cb983bvboxsyncstatic DECLCALLBACK(void) cpumR3InfoAll(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
daa94352f51be2329ac8660f70396e03a7cb983bvboxsync * Parses the info argument.
e9525bea57dc13d82fd3392913aebb33d2cb79e3vboxsync * The argument starts with 'verbose', 'terse' or 'default' and then
e9525bea57dc13d82fd3392913aebb33d2cb79e3vboxsync * continues with the comment string.
830a019ad79a45e6bf7a5419efd5a729a36e599evboxsync * @param pszArgs The pointer to the argument string.
830a019ad79a45e6bf7a5419efd5a729a36e599evboxsync * @param penmType Where to store the dump type request.
daa94352f51be2329ac8660f70396e03a7cb983bvboxsync * @param ppszComment Where to store the pointer to the comment string.
daa94352f51be2329ac8660f70396e03a7cb983bvboxsyncstatic void cpumR3InfoParseArg(const char *pszArgs, CPUMDUMPTYPE *penmType, const char **ppszComment)
830a019ad79a45e6bf7a5419efd5a729a36e599evboxsync if (!strncmp(pszArgs, "verbose", sizeof("verbose") - 1))
830a019ad79a45e6bf7a5419efd5a729a36e599evboxsync else if (!strncmp(pszArgs, "terse", sizeof("terse") - 1))
830a019ad79a45e6bf7a5419efd5a729a36e599evboxsync else if (!strncmp(pszArgs, "default", sizeof("default") - 1))
daa94352f51be2329ac8660f70396e03a7cb983bvboxsync * Display the guest cpu state.
830a019ad79a45e6bf7a5419efd5a729a36e599evboxsync * @param pVM VM Handle.
830a019ad79a45e6bf7a5419efd5a729a36e599evboxsync * @param pHlp The info helper functions.
830a019ad79a45e6bf7a5419efd5a729a36e599evboxsync * @param pszArgs Arguments, ignored.
830a019ad79a45e6bf7a5419efd5a729a36e599evboxsyncstatic DECLCALLBACK(void) cpumR3InfoGuest(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
daa94352f51be2329ac8660f70396e03a7cb983bvboxsync cpumR3InfoParseArg(pszArgs, &enmType, &pszComment);
daa94352f51be2329ac8660f70396e03a7cb983bvboxsync pHlp->pfnPrintf(pHlp, "Guest CPUM state: %s\n", pszComment);
e9525bea57dc13d82fd3392913aebb33d2cb79e3vboxsync cpumR3InfoOne(pVM, &pVM->cpum.s.Guest, CPUMCTX2CORE(&pVM->cpum.s.Guest), pHlp, enmType, "");
daa94352f51be2329ac8660f70396e03a7cb983bvboxsync int rc = DBGFR3DisasInstrCurrent(pVM, szInstruction, sizeof(szInstruction));
daa94352f51be2329ac8660f70396e03a7cb983bvboxsync pHlp->pfnPrintf(pHlp, "\nCPUM: %s\n\n", szInstruction);
daa94352f51be2329ac8660f70396e03a7cb983bvboxsync * Display the hypervisor cpu state.
daa94352f51be2329ac8660f70396e03a7cb983bvboxsync * @param pVM VM Handle.
daa94352f51be2329ac8660f70396e03a7cb983bvboxsync * @param pHlp The info helper functions.
172ae196da38208e5f1e3485715a89f2d53c6880vboxsync * @param pszArgs Arguments, ignored.
172ae196da38208e5f1e3485715a89f2d53c6880vboxsyncstatic DECLCALLBACK(void) cpumR3InfoHyper(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
8b4a8db7768e94d025f1216ecfcd50d727fa2b7cvboxsync cpumR3InfoParseArg(pszArgs, &enmType, &pszComment);
172ae196da38208e5f1e3485715a89f2d53c6880vboxsync pHlp->pfnPrintf(pHlp, "Hypervisor CPUM state: %s\n", pszComment);
172ae196da38208e5f1e3485715a89f2d53c6880vboxsync cpumR3InfoOne(pVM, &pVM->cpum.s.Hyper, pVM->cpum.s.pHyperCoreR3, pHlp, enmType, ".");
172ae196da38208e5f1e3485715a89f2d53c6880vboxsync pHlp->pfnPrintf(pHlp, "CR4OrMask=%#x CR4AndMask=%#x\n", pVM->cpum.s.CR4.OrMask, pVM->cpum.s.CR4.AndMask);
172ae196da38208e5f1e3485715a89f2d53c6880vboxsync * Display the host cpu state.
de6e321f351aa489a6a62bed474390a0056e8093vboxsync * @param pVM VM Handle.
de6e321f351aa489a6a62bed474390a0056e8093vboxsync * @param pHlp The info helper functions.
de6e321f351aa489a6a62bed474390a0056e8093vboxsync * @param pszArgs Arguments, ignored.
de6e321f351aa489a6a62bed474390a0056e8093vboxsyncstatic DECLCALLBACK(void) cpumR3InfoHost(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
de6e321f351aa489a6a62bed474390a0056e8093vboxsync cpumR3InfoParseArg(pszArgs, &enmType, &pszComment);
172ae196da38208e5f1e3485715a89f2d53c6880vboxsync pHlp->pfnPrintf(pHlp, "Host CPUM state: %s\n", pszComment);
172ae196da38208e5f1e3485715a89f2d53c6880vboxsync * Format the EFLAGS.
172ae196da38208e5f1e3485715a89f2d53c6880vboxsync * Format the registers.
172ae196da38208e5f1e3485715a89f2d53c6880vboxsync "eax=xxxxxxxx ebx=%08x ecx=xxxxxxxx edx=xxxxxxxx esi=%08x edi=%08x\n"
172ae196da38208e5f1e3485715a89f2d53c6880vboxsync "eip=xxxxxxxx esp=%08x ebp=%08x iopl=%d %31s\n"
8b4a8db7768e94d025f1216ecfcd50d727fa2b7cvboxsync "cs=%04x ds=%04x es=%04x fs=%04x gs=%04x eflags=%08x\n"
172ae196da38208e5f1e3485715a89f2d53c6880vboxsync "cr0=%08RX64 cr2=xxxxxxxx cr3=%08RX64 cr4=%08RX64 gdtr=%08x:%04x ldtr=%04x\n"
172ae196da38208e5f1e3485715a89f2d53c6880vboxsync "dr0=%08RX64 dr1=%08RX64x dr2=%08RX64 dr3=%08RX64x dr6=%08RX64 dr7=%08RX64\n"
172ae196da38208e5f1e3485715a89f2d53c6880vboxsync "SysEnter={cs=%04x eip=%08x esp=%08x}\n"
172ae196da38208e5f1e3485715a89f2d53c6880vboxsync /*pCtx->eax,*/ pCtx->ebx, /*pCtx->ecx, pCtx->edx,*/ pCtx->esi, pCtx->edi,
172ae196da38208e5f1e3485715a89f2d53c6880vboxsync /*pCtx->eip,*/ pCtx->esp, pCtx->ebp, X86_EFL_GET_IOPL(efl), szEFlags,
172ae196da38208e5f1e3485715a89f2d53c6880vboxsync (RTSEL)pCtx->cs, (RTSEL)pCtx->ds, (RTSEL)pCtx->es, (RTSEL)pCtx->fs, (RTSEL)pCtx->gs, efl,
172ae196da38208e5f1e3485715a89f2d53c6880vboxsync pCtx->dr0, pCtx->dr1, pCtx->dr2, pCtx->dr3, pCtx->dr6, pCtx->dr7,
8b4a8db7768e94d025f1216ecfcd50d727fa2b7cvboxsync (uint32_t)pCtx->gdtr.uAddr, pCtx->gdtr.cb, (RTSEL)pCtx->ldtr,
aa4bcf0a4b2db3ac352b56a291d49cb8d4b66d32vboxsync pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp);
172ae196da38208e5f1e3485715a89f2d53c6880vboxsync#if HC_ARCH_BITS == 64 || defined(VBOX_WITH_HYBIRD_32BIT_KERNEL)
aa4bcf0a4b2db3ac352b56a291d49cb8d4b66d32vboxsync "rax=xxxxxxxxxxxxxxxx rbx=%016RX64 rcx=xxxxxxxxxxxxxxxx\n"
8b4a8db7768e94d025f1216ecfcd50d727fa2b7cvboxsync "rdx=xxxxxxxxxxxxxxxx rsi=%016RX64 rdi=%016RX64\n"
172ae196da38208e5f1e3485715a89f2d53c6880vboxsync "rip=xxxxxxxxxxxxxxxx rsp=%016RX64 rbp=%016RX64\n"
e9525bea57dc13d82fd3392913aebb33d2cb79e3vboxsync " r8=xxxxxxxxxxxxxxxx r9=xxxxxxxxxxxxxxxx r10=%016RX64\n"
e9525bea57dc13d82fd3392913aebb33d2cb79e3vboxsync "r11=%016RX64 r12=%016RX64 r13=%016RX64\n"
e9525bea57dc13d82fd3392913aebb33d2cb79e3vboxsync "r14=%016RX64 r15=%016RX64\n"
e9525bea57dc13d82fd3392913aebb33d2cb79e3vboxsync "iopl=%d %31s\n"
e9525bea57dc13d82fd3392913aebb33d2cb79e3vboxsync "cs=%04x ds=%04x es=%04x fs=%04x gs=%04x eflags=%08RX64\n"
e9525bea57dc13d82fd3392913aebb33d2cb79e3vboxsync "cr0=%016RX64 cr2=xxxxxxxxxxxxxxxx cr3=%016RX64\n"
e9525bea57dc13d82fd3392913aebb33d2cb79e3vboxsync "cr4=%016RX64 cr8=%016RX64 ldtr=%04x tr=%04x\n"
e9525bea57dc13d82fd3392913aebb33d2cb79e3vboxsync "dr0=%016RX64 dr1=%016RX64 dr2=%016RX64\n"
e9525bea57dc13d82fd3392913aebb33d2cb79e3vboxsync "dr3=%016RX64 dr6=%016RX64 dr7=%016RX64\n"
e9525bea57dc13d82fd3392913aebb33d2cb79e3vboxsync "gdtr=%016RX64:%04x idtr=%016RX64:%04x\n"
e9525bea57dc13d82fd3392913aebb33d2cb79e3vboxsync "SysEnter={cs=%04x eip=%08x esp=%08x}\n"
e9525bea57dc13d82fd3392913aebb33d2cb79e3vboxsync "FSbase=%016RX64 GSbase=%016RX64 efer=%08RX64\n"
e9525bea57dc13d82fd3392913aebb33d2cb79e3vboxsync (RTSEL)pCtx->cs, (RTSEL)pCtx->ds, (RTSEL)pCtx->es, (RTSEL)pCtx->fs, (RTSEL)pCtx->gs, efl,
e9525bea57dc13d82fd3392913aebb33d2cb79e3vboxsync pCtx->gdtr.uAddr, pCtx->gdtr.cb, pCtx->idtr.uAddr, pCtx->idtr.cb,
e9525bea57dc13d82fd3392913aebb33d2cb79e3vboxsync pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp,
d90eec53c9dcaa0f3d1054e8734ed46875b9093avboxsync * Get L1 cache / TLS associativity.
d90eec53c9dcaa0f3d1054e8734ed46875b9093avboxsyncstatic const char *getCacheAss(unsigned u, char *pszBuf)
d90eec53c9dcaa0f3d1054e8734ed46875b9093avboxsync if (u == 0)
d90eec53c9dcaa0f3d1054e8734ed46875b9093avboxsync return "res0 ";
d90eec53c9dcaa0f3d1054e8734ed46875b9093avboxsync if (u == 1)
d90eec53c9dcaa0f3d1054e8734ed46875b9093avboxsync return "direct";
d90eec53c9dcaa0f3d1054e8734ed46875b9093avboxsync if (u >= 256)
d90eec53c9dcaa0f3d1054e8734ed46875b9093avboxsync return "???";
c0e27f622f9bd6d9e77d2d959aab71d69dabf0d3vboxsync * Get L2 cache soociativity.
c0e27f622f9bd6d9e77d2d959aab71d69dabf0d3vboxsyncconst char *getL2CacheAss(unsigned u)
8b4a8db7768e94d025f1216ecfcd50d727fa2b7cvboxsync case 0: return "off ";
bbb4c0bfd5ea55e99591d8811771257a437053eevboxsync return "????";
bbb4c0bfd5ea55e99591d8811771257a437053eevboxsync * Display the guest CpuId leaves.
bbb4c0bfd5ea55e99591d8811771257a437053eevboxsync * @param pVM VM Handle.
bbb4c0bfd5ea55e99591d8811771257a437053eevboxsync * @param pHlp The info helper functions.
bbb4c0bfd5ea55e99591d8811771257a437053eevboxsync * @param pszArgs "terse", "default" or "verbose".
bbb4c0bfd5ea55e99591d8811771257a437053eevboxsyncstatic DECLCALLBACK(void) cpumR3CpuIdInfo(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
bbb4c0bfd5ea55e99591d8811771257a437053eevboxsync * Parse the argument.
c0e27f622f9bd6d9e77d2d959aab71d69dabf0d3vboxsync * Start cracking.
72a6fe3989272cb2d409b50caca25e1edbca9398vboxsync unsigned cStdMax = pVM->cpum.s.aGuestCpuIdStd[0].eax;
c0e27f622f9bd6d9e77d2d959aab71d69dabf0d3vboxsync " RAW Standard CPUIDs\n"
c0e27f622f9bd6d9e77d2d959aab71d69dabf0d3vboxsync " Function eax ebx ecx edx\n");
c0e27f622f9bd6d9e77d2d959aab71d69dabf0d3vboxsync for (unsigned i = 0; i < RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdStd); i++)
c0e27f622f9bd6d9e77d2d959aab71d69dabf0d3vboxsync ASMCpuId_Idx_ECX(i, 0, &Host.eax, &Host.ebx, &Host.ecx, &Host.edx);
c0e27f622f9bd6d9e77d2d959aab71d69dabf0d3vboxsync "Gst: %08x %08x %08x %08x %08x%s\n"
c0e27f622f9bd6d9e77d2d959aab71d69dabf0d3vboxsync "Hst: %08x %08x %08x %08x\n",
ca3da10d05961c339b5180fbd40a54587d6bad35vboxsync * If verbose, decode it.
c0e27f622f9bd6d9e77d2d959aab71d69dabf0d3vboxsync "Name: %.04s%.04s%.04s\n"
c0e27f622f9bd6d9e77d2d959aab71d69dabf0d3vboxsync "Supports: 0-%x\n",
c0e27f622f9bd6d9e77d2d959aab71d69dabf0d3vboxsync * Get Features.
c0e27f622f9bd6d9e77d2d959aab71d69dabf0d3vboxsync bool const fIntel = ASMIsIntelCpuEx(pVM->cpum.s.aGuestCpuIdStd[0].ebx,
c0e27f622f9bd6d9e77d2d959aab71d69dabf0d3vboxsync "Family: %d \tExtended: %d \tEffective: %d\n"
c0e27f622f9bd6d9e77d2d959aab71d69dabf0d3vboxsync "Model: %d \tExtended: %d \tEffective: %d\n"
c0e27f622f9bd6d9e77d2d959aab71d69dabf0d3vboxsync "Stepping: %d\n"
72a6fe3989272cb2d409b50caca25e1edbca9398vboxsync "APIC ID: %#04x\n"
c0e27f622f9bd6d9e77d2d959aab71d69dabf0d3vboxsync "Logical CPUs: %d\n"
aa4bcf0a4b2db3ac352b56a291d49cb8d4b66d32vboxsync "CLFLUSH Size: %d\n"
c0e27f622f9bd6d9e77d2d959aab71d69dabf0d3vboxsync "Brand ID: %#04x\n",
c0e27f622f9bd6d9e77d2d959aab71d69dabf0d3vboxsync (uEAX >> 8) & 0xf, (uEAX >> 20) & 0x7f, ASMGetCpuFamily(uEAX),
c0e27f622f9bd6d9e77d2d959aab71d69dabf0d3vboxsync (uEAX >> 4) & 0xf, (uEAX >> 16) & 0x0f, ASMGetCpuModel(uEAX, fIntel),
ca3da10d05961c339b5180fbd40a54587d6bad35vboxsync if (uEDX & RT_BIT(0)) pHlp->pfnPrintf(pHlp, " FPU");
c0e27f622f9bd6d9e77d2d959aab71d69dabf0d3vboxsync if (uEDX & RT_BIT(1)) pHlp->pfnPrintf(pHlp, " VME");
c0e27f622f9bd6d9e77d2d959aab71d69dabf0d3vboxsync if (uEDX & RT_BIT(2)) pHlp->pfnPrintf(pHlp, " DE");
c0e27f622f9bd6d9e77d2d959aab71d69dabf0d3vboxsync if (uEDX & RT_BIT(3)) pHlp->pfnPrintf(pHlp, " PSE");
c0e27f622f9bd6d9e77d2d959aab71d69dabf0d3vboxsync if (uEDX & RT_BIT(4)) pHlp->pfnPrintf(pHlp, " TSC");
c0e27f622f9bd6d9e77d2d959aab71d69dabf0d3vboxsync if (uEDX & RT_BIT(5)) pHlp->pfnPrintf(pHlp, " MSR");
c0e27f622f9bd6d9e77d2d959aab71d69dabf0d3vboxsync if (uEDX & RT_BIT(6)) pHlp->pfnPrintf(pHlp, " PAE");
aa4bcf0a4b2db3ac352b56a291d49cb8d4b66d32vboxsync if (uEDX & RT_BIT(7)) pHlp->pfnPrintf(pHlp, " MCE");
c0e27f622f9bd6d9e77d2d959aab71d69dabf0d3vboxsync if (uEDX & RT_BIT(8)) pHlp->pfnPrintf(pHlp, " CX8");
c0e27f622f9bd6d9e77d2d959aab71d69dabf0d3vboxsync if (uEDX & RT_BIT(9)) pHlp->pfnPrintf(pHlp, " APIC");
a1df400bbe9d64aad400442e56eb637019300a5evboxsync if (uEDX & RT_BIT(10)) pHlp->pfnPrintf(pHlp, " 10");
a1df400bbe9d64aad400442e56eb637019300a5evboxsync if (uEDX & RT_BIT(11)) pHlp->pfnPrintf(pHlp, " SEP");
8b4a8db7768e94d025f1216ecfcd50d727fa2b7cvboxsync if (uEDX & RT_BIT(12)) pHlp->pfnPrintf(pHlp, " MTRR");
ca3da10d05961c339b5180fbd40a54587d6bad35vboxsync if (uEDX & RT_BIT(13)) pHlp->pfnPrintf(pHlp, " PGE");
ca3da10d05961c339b5180fbd40a54587d6bad35vboxsync if (uEDX & RT_BIT(14)) pHlp->pfnPrintf(pHlp, " MCA");
ca3da10d05961c339b5180fbd40a54587d6bad35vboxsync if (uEDX & RT_BIT(15)) pHlp->pfnPrintf(pHlp, " CMOV");
ca3da10d05961c339b5180fbd40a54587d6bad35vboxsync if (uEDX & RT_BIT(16)) pHlp->pfnPrintf(pHlp, " PAT");
ca3da10d05961c339b5180fbd40a54587d6bad35vboxsync if (uEDX & RT_BIT(17)) pHlp->pfnPrintf(pHlp, " PSE36");
ca3da10d05961c339b5180fbd40a54587d6bad35vboxsync if (uEDX & RT_BIT(18)) pHlp->pfnPrintf(pHlp, " PSN");
ca3da10d05961c339b5180fbd40a54587d6bad35vboxsync if (uEDX & RT_BIT(19)) pHlp->pfnPrintf(pHlp, " CLFSH");
ca3da10d05961c339b5180fbd40a54587d6bad35vboxsync if (uEDX & RT_BIT(20)) pHlp->pfnPrintf(pHlp, " 20");
ca3da10d05961c339b5180fbd40a54587d6bad35vboxsync if (uEDX & RT_BIT(21)) pHlp->pfnPrintf(pHlp, " DS");
ca3da10d05961c339b5180fbd40a54587d6bad35vboxsync if (uEDX & RT_BIT(22)) pHlp->pfnPrintf(pHlp, " ACPI");
ca3da10d05961c339b5180fbd40a54587d6bad35vboxsync if (uEDX & RT_BIT(23)) pHlp->pfnPrintf(pHlp, " MMX");
ca3da10d05961c339b5180fbd40a54587d6bad35vboxsync if (uEDX & RT_BIT(24)) pHlp->pfnPrintf(pHlp, " FXSR");
ca3da10d05961c339b5180fbd40a54587d6bad35vboxsync if (uEDX & RT_BIT(25)) pHlp->pfnPrintf(pHlp, " SSE");
ca3da10d05961c339b5180fbd40a54587d6bad35vboxsync if (uEDX & RT_BIT(26)) pHlp->pfnPrintf(pHlp, " SSE2");
a1df400bbe9d64aad400442e56eb637019300a5evboxsync if (uEDX & RT_BIT(27)) pHlp->pfnPrintf(pHlp, " SS");
ca3da10d05961c339b5180fbd40a54587d6bad35vboxsync if (uEDX & RT_BIT(28)) pHlp->pfnPrintf(pHlp, " HTT");
ca3da10d05961c339b5180fbd40a54587d6bad35vboxsync if (uEDX & RT_BIT(29)) pHlp->pfnPrintf(pHlp, " TM");
ca3da10d05961c339b5180fbd40a54587d6bad35vboxsync if (uEDX & RT_BIT(30)) pHlp->pfnPrintf(pHlp, " 30");
ca3da10d05961c339b5180fbd40a54587d6bad35vboxsync if (uEDX & RT_BIT(31)) pHlp->pfnPrintf(pHlp, " PBE");
ca3da10d05961c339b5180fbd40a54587d6bad35vboxsync if (uECX & RT_BIT(0)) pHlp->pfnPrintf(pHlp, " SSE3");
ca3da10d05961c339b5180fbd40a54587d6bad35vboxsync if (uECX & RT_BIT(3)) pHlp->pfnPrintf(pHlp, " MONITOR");
ca3da10d05961c339b5180fbd40a54587d6bad35vboxsync if (uECX & RT_BIT(4)) pHlp->pfnPrintf(pHlp, " DS-CPL");
ca3da10d05961c339b5180fbd40a54587d6bad35vboxsync if (uECX & RT_BIT(5)) pHlp->pfnPrintf(pHlp, " VMX");
ca3da10d05961c339b5180fbd40a54587d6bad35vboxsync if (uECX & RT_BIT(7)) pHlp->pfnPrintf(pHlp, " EST");
ca3da10d05961c339b5180fbd40a54587d6bad35vboxsync if (uECX & RT_BIT(8)) pHlp->pfnPrintf(pHlp, " TM2");
ca3da10d05961c339b5180fbd40a54587d6bad35vboxsync if (uECX & RT_BIT(10)) pHlp->pfnPrintf(pHlp, " CNXT-ID");
ca3da10d05961c339b5180fbd40a54587d6bad35vboxsync if (uECX & RT_BIT(11)) pHlp->pfnPrintf(pHlp, " 11");
044af0d1e6474076366759db86f101778c5f20ccvboxsync if (uECX & RT_BIT(12)) pHlp->pfnPrintf(pHlp, " 12");
ca3da10d05961c339b5180fbd40a54587d6bad35vboxsync if (uECX & RT_BIT(13)) pHlp->pfnPrintf(pHlp, " CX16");
8b4a8db7768e94d025f1216ecfcd50d727fa2b7cvboxsync ASMCpuId(1, &Host.eax, &Host.ebx, &Host.ecx, &Host.edx);
a1df400bbe9d64aad400442e56eb637019300a5evboxsync X86CPUIDFEATEDX EdxHost = *(PX86CPUIDFEATEDX)&Host.edx;
a1df400bbe9d64aad400442e56eb637019300a5evboxsync X86CPUIDFEATECX EcxHost = *(PX86CPUIDFEATECX)&Host.ecx;
a1df400bbe9d64aad400442e56eb637019300a5evboxsync X86CPUIDFEATEDX EdxGuest = *(PX86CPUIDFEATEDX)&Guest.edx;
a1df400bbe9d64aad400442e56eb637019300a5evboxsync X86CPUIDFEATECX EcxGuest = *(PX86CPUIDFEATECX)&Guest.ecx;
a1df400bbe9d64aad400442e56eb637019300a5evboxsync pHlp->pfnPrintf(pHlp, "Mnemonic - Description = guest (host)\n");
a1df400bbe9d64aad400442e56eb637019300a5evboxsync pHlp->pfnPrintf(pHlp, "FPU - x87 FPU on Chip = %d (%d)\n", EdxGuest.u1FPU, EdxHost.u1FPU);
8b4a8db7768e94d025f1216ecfcd50d727fa2b7cvboxsync pHlp->pfnPrintf(pHlp, "VME - Virtual 8086 Mode Enhancements = %d (%d)\n", EdxGuest.u1VME, EdxHost.u1VME);
aa4bcf0a4b2db3ac352b56a291d49cb8d4b66d32vboxsync pHlp->pfnPrintf(pHlp, "DE - Debugging extensions = %d (%d)\n", EdxGuest.u1DE, EdxHost.u1DE);
8b4a8db7768e94d025f1216ecfcd50d727fa2b7cvboxsync pHlp->pfnPrintf(pHlp, "PSE - Page Size Extension = %d (%d)\n", EdxGuest.u1PSE, EdxHost.u1PSE);
a1df400bbe9d64aad400442e56eb637019300a5evboxsync pHlp->pfnPrintf(pHlp, "TSC - Time Stamp Counter = %d (%d)\n", EdxGuest.u1TSC, EdxHost.u1TSC);
a1df400bbe9d64aad400442e56eb637019300a5evboxsync pHlp->pfnPrintf(pHlp, "MSR - Model Specific Registers = %d (%d)\n", EdxGuest.u1MSR, EdxHost.u1MSR);
8b4a8db7768e94d025f1216ecfcd50d727fa2b7cvboxsync pHlp->pfnPrintf(pHlp, "PAE - Physical Address Extension = %d (%d)\n", EdxGuest.u1PAE, EdxHost.u1PAE);
a1df400bbe9d64aad400442e56eb637019300a5evboxsync pHlp->pfnPrintf(pHlp, "MCE - Machine Check Exception = %d (%d)\n", EdxGuest.u1MCE, EdxHost.u1MCE);
a1df400bbe9d64aad400442e56eb637019300a5evboxsync pHlp->pfnPrintf(pHlp, "CX8 - CMPXCHG8B instruction = %d (%d)\n", EdxGuest.u1CX8, EdxHost.u1CX8);
a1df400bbe9d64aad400442e56eb637019300a5evboxsync pHlp->pfnPrintf(pHlp, "APIC - APIC On-Chip = %d (%d)\n", EdxGuest.u1APIC, EdxHost.u1APIC);
a1df400bbe9d64aad400442e56eb637019300a5evboxsync pHlp->pfnPrintf(pHlp, "Reserved = %d (%d)\n", EdxGuest.u1Reserved1, EdxHost.u1Reserved1);
a1df400bbe9d64aad400442e56eb637019300a5evboxsync pHlp->pfnPrintf(pHlp, "SEP - SYSENTER and SYSEXIT = %d (%d)\n", EdxGuest.u1SEP, EdxHost.u1SEP);
a1df400bbe9d64aad400442e56eb637019300a5evboxsync pHlp->pfnPrintf(pHlp, "MTRR - Memory Type Range Registers = %d (%d)\n", EdxGuest.u1MTRR, EdxHost.u1MTRR);
a1df400bbe9d64aad400442e56eb637019300a5evboxsync pHlp->pfnPrintf(pHlp, "PGE - PTE Global Bit = %d (%d)\n", EdxGuest.u1PGE, EdxHost.u1PGE);
a1df400bbe9d64aad400442e56eb637019300a5evboxsync pHlp->pfnPrintf(pHlp, "MCA - Machine Check Architecture = %d (%d)\n", EdxGuest.u1MCA, EdxHost.u1MCA);
8b4a8db7768e94d025f1216ecfcd50d727fa2b7cvboxsync pHlp->pfnPrintf(pHlp, "CMOV - Conditional Move Instructions = %d (%d)\n", EdxGuest.u1CMOV, EdxHost.u1CMOV);
aa4bcf0a4b2db3ac352b56a291d49cb8d4b66d32vboxsync pHlp->pfnPrintf(pHlp, "PAT - Page Attribute Table = %d (%d)\n", EdxGuest.u1PAT, EdxHost.u1PAT);
8b4a8db7768e94d025f1216ecfcd50d727fa2b7cvboxsync pHlp->pfnPrintf(pHlp, "PSE-36 - 36-bit Page Size Extention = %d (%d)\n", EdxGuest.u1PSE36, EdxHost.u1PSE36);
a1df400bbe9d64aad400442e56eb637019300a5evboxsync pHlp->pfnPrintf(pHlp, "PSN - Processor Serial Number = %d (%d)\n", EdxGuest.u1PSN, EdxHost.u1PSN);
a1df400bbe9d64aad400442e56eb637019300a5evboxsync pHlp->pfnPrintf(pHlp, "CLFSH - CLFLUSH Instruction. = %d (%d)\n", EdxGuest.u1CLFSH, EdxHost.u1CLFSH);
8b4a8db7768e94d025f1216ecfcd50d727fa2b7cvboxsync pHlp->pfnPrintf(pHlp, "Reserved = %d (%d)\n", EdxGuest.u1Reserved2, EdxHost.u1Reserved2);
a1df400bbe9d64aad400442e56eb637019300a5evboxsync pHlp->pfnPrintf(pHlp, "DS - Debug Store = %d (%d)\n", EdxGuest.u1DS, EdxHost.u1DS);
a1df400bbe9d64aad400442e56eb637019300a5evboxsync pHlp->pfnPrintf(pHlp, "ACPI - Thermal Mon. & Soft. Clock Ctrl.= %d (%d)\n", EdxGuest.u1ACPI, EdxHost.u1ACPI);
a1df400bbe9d64aad400442e56eb637019300a5evboxsync pHlp->pfnPrintf(pHlp, "MMX - Intel MMX Technology = %d (%d)\n", EdxGuest.u1MMX, EdxHost.u1MMX);
a1df400bbe9d64aad400442e56eb637019300a5evboxsync pHlp->pfnPrintf(pHlp, "FXSR - FXSAVE and FXRSTOR Instructions = %d (%d)\n", EdxGuest.u1FXSR, EdxHost.u1FXSR);
a1df400bbe9d64aad400442e56eb637019300a5evboxsync pHlp->pfnPrintf(pHlp, "SSE - SSE Support = %d (%d)\n", EdxGuest.u1SSE, EdxHost.u1SSE);
a1df400bbe9d64aad400442e56eb637019300a5evboxsync pHlp->pfnPrintf(pHlp, "SSE2 - SSE2 Support = %d (%d)\n", EdxGuest.u1SSE2, EdxHost.u1SSE2);
a1df400bbe9d64aad400442e56eb637019300a5evboxsync pHlp->pfnPrintf(pHlp, "SS - Self Snoop = %d (%d)\n", EdxGuest.u1SS, EdxHost.u1SS);
a1df400bbe9d64aad400442e56eb637019300a5evboxsync pHlp->pfnPrintf(pHlp, "HTT - Hyper-Threading Technolog = %d (%d)\n", EdxGuest.u1HTT, EdxHost.u1HTT);
a1df400bbe9d64aad400442e56eb637019300a5evboxsync pHlp->pfnPrintf(pHlp, "TM - Thermal Monitor = %d (%d)\n", EdxGuest.u1TM, EdxHost.u1TM);
a1df400bbe9d64aad400442e56eb637019300a5evboxsync pHlp->pfnPrintf(pHlp, "30 - Reserved = %d (%d)\n", EdxGuest.u1Reserved3, EdxHost.u1Reserved3);
a1df400bbe9d64aad400442e56eb637019300a5evboxsync pHlp->pfnPrintf(pHlp, "PBE - Pending Break Enable = %d (%d)\n", EdxGuest.u1PBE, EdxHost.u1PBE);
a1df400bbe9d64aad400442e56eb637019300a5evboxsync pHlp->pfnPrintf(pHlp, "Supports SSE3 or not = %d (%d)\n", EcxGuest.u1SSE3, EcxHost.u1SSE3);
a1df400bbe9d64aad400442e56eb637019300a5evboxsync pHlp->pfnPrintf(pHlp, "Reserved = %d (%d)\n", EcxGuest.u2Reserved1, EcxHost.u2Reserved1);
8b4a8db7768e94d025f1216ecfcd50d727fa2b7cvboxsync pHlp->pfnPrintf(pHlp, "Supports MONITOR/MWAIT = %d (%d)\n", EcxGuest.u1Monitor, EcxHost.u1Monitor);
aa4bcf0a4b2db3ac352b56a291d49cb8d4b66d32vboxsync pHlp->pfnPrintf(pHlp, "CPL-DS - CPL Qualified Debug Store = %d (%d)\n", EcxGuest.u1CPLDS, EcxHost.u1CPLDS);
8b4a8db7768e94d025f1216ecfcd50d727fa2b7cvboxsync pHlp->pfnPrintf(pHlp, "VMX - Virtual Machine Technology = %d (%d)\n", EcxGuest.u1VMX, EcxHost.u1VMX);
a1df400bbe9d64aad400442e56eb637019300a5evboxsync pHlp->pfnPrintf(pHlp, "Reserved = %d (%d)\n", EcxGuest.u1Reserved2, EcxHost.u1Reserved2);
2d8870843ff566fee9bd3a6a5942414254106479vboxsync pHlp->pfnPrintf(pHlp, "Enhanced SpeedStep Technology = %d (%d)\n", EcxGuest.u1EST, EcxHost.u1EST);
2d8870843ff566fee9bd3a6a5942414254106479vboxsync pHlp->pfnPrintf(pHlp, "Terminal Monitor 2 = %d (%d)\n", EcxGuest.u1TM2, EcxHost.u1TM2);
8b4a8db7768e94d025f1216ecfcd50d727fa2b7cvboxsync pHlp->pfnPrintf(pHlp, "Supports Supplemental SSE3 or not = %d (%d)\n", EcxGuest.u1SSSE3, EcxHost.u1SSSE3);
a1df400bbe9d64aad400442e56eb637019300a5evboxsync pHlp->pfnPrintf(pHlp, "L1 Context ID = %d (%d)\n", EcxGuest.u1CNTXID, EcxHost.u1CNTXID);
a1df400bbe9d64aad400442e56eb637019300a5evboxsync pHlp->pfnPrintf(pHlp, "Reserved = %#x (%#x)\n",EcxGuest.u2Reserved4, EcxHost.u2Reserved4);
a1df400bbe9d64aad400442e56eb637019300a5evboxsync pHlp->pfnPrintf(pHlp, "CMPXCHG16B = %d (%d)\n", EcxGuest.u1CX16, EcxHost.u1CX16);
a1df400bbe9d64aad400442e56eb637019300a5evboxsync pHlp->pfnPrintf(pHlp, "xTPR Update Control = %d (%d)\n", EcxGuest.u1TPRUpdate, EcxHost.u1TPRUpdate);
df8e6a449f00e1884fbf4a1fc67143614d7d528dvboxsync pHlp->pfnPrintf(pHlp, "Reserved = %#x (%#x)\n",EcxGuest.u17Reserved5, EcxHost.u17Reserved5);
a1df400bbe9d64aad400442e56eb637019300a5evboxsync /** @todo */
a1df400bbe9d64aad400442e56eb637019300a5evboxsync * Extended.
a1df400bbe9d64aad400442e56eb637019300a5evboxsync * Implemented after AMD specs.
a1df400bbe9d64aad400442e56eb637019300a5evboxsync unsigned cExtMax = pVM->cpum.s.aGuestCpuIdExt[0].eax & 0xffff;
a1df400bbe9d64aad400442e56eb637019300a5evboxsync " RAW Extended CPUIDs\n"
a1df400bbe9d64aad400442e56eb637019300a5evboxsync " Function eax ebx ecx edx\n");
a1df400bbe9d64aad400442e56eb637019300a5evboxsync for (unsigned i = 0; i < ELEMENTS(pVM->cpum.s.aGuestCpuIdExt); i++)
a1df400bbe9d64aad400442e56eb637019300a5evboxsync ASMCpuId(0x80000000 | i, &Host.eax, &Host.ebx, &Host.ecx, &Host.edx);
a1df400bbe9d64aad400442e56eb637019300a5evboxsync "Gst: %08x %08x %08x %08x %08x%s\n"
a1df400bbe9d64aad400442e56eb637019300a5evboxsync "Hst: %08x %08x %08x %08x\n",
a1df400bbe9d64aad400442e56eb637019300a5evboxsync 0x80000000 | i, Guest.eax, Guest.ebx, Guest.ecx, Guest.edx,
2d8870843ff566fee9bd3a6a5942414254106479vboxsync * Understandable output
a1df400bbe9d64aad400442e56eb637019300a5evboxsync "Ext Name: %.4s%.4s%.4s\n"
a1df400bbe9d64aad400442e56eb637019300a5evboxsync "Ext Supports: 0x80000000-%#010x\n",
8b4a8db7768e94d025f1216ecfcd50d727fa2b7cvboxsync "Family: %d \tExtended: %d \tEffective: %d\n"
aa4bcf0a4b2db3ac352b56a291d49cb8d4b66d32vboxsync "Model: %d \tExtended: %d \tEffective: %d\n"
8b4a8db7768e94d025f1216ecfcd50d727fa2b7cvboxsync "Stepping: %d\n"
a1df400bbe9d64aad400442e56eb637019300a5evboxsync "Brand ID: %#05x\n",
a1df400bbe9d64aad400442e56eb637019300a5evboxsync (uEAX >> 8) & 0xf, (uEAX >> 20) & 0x7f, ASMGetCpuFamily(uEAX),
8b4a8db7768e94d025f1216ecfcd50d727fa2b7cvboxsync (uEAX >> 4) & 0xf, (uEAX >> 16) & 0x0f, ASMGetCpuModel(uEAX, fIntel),
a1df400bbe9d64aad400442e56eb637019300a5evboxsync if (uEDX & RT_BIT(0)) pHlp->pfnPrintf(pHlp, " FPU");
a1df400bbe9d64aad400442e56eb637019300a5evboxsync if (uEDX & RT_BIT(1)) pHlp->pfnPrintf(pHlp, " VME");
a1df400bbe9d64aad400442e56eb637019300a5evboxsync if (uEDX & RT_BIT(2)) pHlp->pfnPrintf(pHlp, " DE");
a1df400bbe9d64aad400442e56eb637019300a5evboxsync if (uEDX & RT_BIT(3)) pHlp->pfnPrintf(pHlp, " PSE");
a1df400bbe9d64aad400442e56eb637019300a5evboxsync if (uEDX & RT_BIT(4)) pHlp->pfnPrintf(pHlp, " TSC");
a1df400bbe9d64aad400442e56eb637019300a5evboxsync if (uEDX & RT_BIT(5)) pHlp->pfnPrintf(pHlp, " MSR");
a1df400bbe9d64aad400442e56eb637019300a5evboxsync if (uEDX & RT_BIT(6)) pHlp->pfnPrintf(pHlp, " PAE");
a1df400bbe9d64aad400442e56eb637019300a5evboxsync if (uEDX & RT_BIT(7)) pHlp->pfnPrintf(pHlp, " MCE");
a1df400bbe9d64aad400442e56eb637019300a5evboxsync if (uEDX & RT_BIT(8)) pHlp->pfnPrintf(pHlp, " CX8");
a1df400bbe9d64aad400442e56eb637019300a5evboxsync if (uEDX & RT_BIT(9)) pHlp->pfnPrintf(pHlp, " APIC");
a1df400bbe9d64aad400442e56eb637019300a5evboxsync if (uEDX & RT_BIT(10)) pHlp->pfnPrintf(pHlp, " 10");
a1df400bbe9d64aad400442e56eb637019300a5evboxsync if (uEDX & RT_BIT(11)) pHlp->pfnPrintf(pHlp, " SCR");
a1df400bbe9d64aad400442e56eb637019300a5evboxsync if (uEDX & RT_BIT(12)) pHlp->pfnPrintf(pHlp, " MTRR");
aa4bcf0a4b2db3ac352b56a291d49cb8d4b66d32vboxsync if (uEDX & RT_BIT(13)) pHlp->pfnPrintf(pHlp, " PGE");
a1df400bbe9d64aad400442e56eb637019300a5evboxsync if (uEDX & RT_BIT(14)) pHlp->pfnPrintf(pHlp, " MCA");
a1df400bbe9d64aad400442e56eb637019300a5evboxsync if (uEDX & RT_BIT(15)) pHlp->pfnPrintf(pHlp, " CMOV");
a1df400bbe9d64aad400442e56eb637019300a5evboxsync if (uEDX & RT_BIT(16)) pHlp->pfnPrintf(pHlp, " PAT");
a1df400bbe9d64aad400442e56eb637019300a5evboxsync if (uEDX & RT_BIT(17)) pHlp->pfnPrintf(pHlp, " PSE36");
a1df400bbe9d64aad400442e56eb637019300a5evboxsync if (uEDX & RT_BIT(18)) pHlp->pfnPrintf(pHlp, " 18");
a1df400bbe9d64aad400442e56eb637019300a5evboxsync if (uEDX & RT_BIT(19)) pHlp->pfnPrintf(pHlp, " 19");
a1df400bbe9d64aad400442e56eb637019300a5evboxsync if (uEDX & RT_BIT(20)) pHlp->pfnPrintf(pHlp, " NX");
a1df400bbe9d64aad400442e56eb637019300a5evboxsync if (uEDX & RT_BIT(21)) pHlp->pfnPrintf(pHlp, " 21");
a1df400bbe9d64aad400442e56eb637019300a5evboxsync if (uEDX & RT_BIT(22)) pHlp->pfnPrintf(pHlp, " ExtMMX");
a1df400bbe9d64aad400442e56eb637019300a5evboxsync if (uEDX & RT_BIT(23)) pHlp->pfnPrintf(pHlp, " MMX");
a1df400bbe9d64aad400442e56eb637019300a5evboxsync if (uEDX & RT_BIT(24)) pHlp->pfnPrintf(pHlp, " FXSR");
a1df400bbe9d64aad400442e56eb637019300a5evboxsync if (uEDX & RT_BIT(25)) pHlp->pfnPrintf(pHlp, " FastFXSR");
a1df400bbe9d64aad400442e56eb637019300a5evboxsync if (uEDX & RT_BIT(26)) pHlp->pfnPrintf(pHlp, " Page1GB");
a1df400bbe9d64aad400442e56eb637019300a5evboxsync if (uEDX & RT_BIT(27)) pHlp->pfnPrintf(pHlp, " RDTSCP");
a1df400bbe9d64aad400442e56eb637019300a5evboxsync if (uEDX & RT_BIT(28)) pHlp->pfnPrintf(pHlp, " 28");
a1df400bbe9d64aad400442e56eb637019300a5evboxsync if (uEDX & RT_BIT(29)) pHlp->pfnPrintf(pHlp, " LongMode");
a1df400bbe9d64aad400442e56eb637019300a5evboxsync if (uEDX & RT_BIT(30)) pHlp->pfnPrintf(pHlp, " Ext3DNow");
a1df400bbe9d64aad400442e56eb637019300a5evboxsync if (uEDX & RT_BIT(31)) pHlp->pfnPrintf(pHlp, " 3DNow");
df8e6a449f00e1884fbf4a1fc67143614d7d528dvboxsync if (uECX & RT_BIT(0)) pHlp->pfnPrintf(pHlp, " LAHF/SAHF");
df8e6a449f00e1884fbf4a1fc67143614d7d528dvboxsync if (uECX & RT_BIT(1)) pHlp->pfnPrintf(pHlp, " CMPL");
ca3da10d05961c339b5180fbd40a54587d6bad35vboxsync if (uECX & RT_BIT(2)) pHlp->pfnPrintf(pHlp, " SVM");
ca3da10d05961c339b5180fbd40a54587d6bad35vboxsync if (uECX & RT_BIT(3)) pHlp->pfnPrintf(pHlp, " ExtAPIC");
ca3da10d05961c339b5180fbd40a54587d6bad35vboxsync if (uECX & RT_BIT(4)) pHlp->pfnPrintf(pHlp, " CR8L");
ca3da10d05961c339b5180fbd40a54587d6bad35vboxsync if (uECX & RT_BIT(5)) pHlp->pfnPrintf(pHlp, " ABM");
ca3da10d05961c339b5180fbd40a54587d6bad35vboxsync if (uECX & RT_BIT(6)) pHlp->pfnPrintf(pHlp, " SSE4A");
ca3da10d05961c339b5180fbd40a54587d6bad35vboxsync if (uECX & RT_BIT(7)) pHlp->pfnPrintf(pHlp, " MISALNSSE");
ca3da10d05961c339b5180fbd40a54587d6bad35vboxsync if (uECX & RT_BIT(8)) pHlp->pfnPrintf(pHlp, " 3DNOWPRF");
ca3da10d05961c339b5180fbd40a54587d6bad35vboxsync if (uECX & RT_BIT(9)) pHlp->pfnPrintf(pHlp, " OSVW");
ca3da10d05961c339b5180fbd40a54587d6bad35vboxsync if (uECX & RT_BIT(10)) pHlp->pfnPrintf(pHlp, " IBS");
ca3da10d05961c339b5180fbd40a54587d6bad35vboxsync if (uECX & RT_BIT(11)) pHlp->pfnPrintf(pHlp, " SSE5");
ca3da10d05961c339b5180fbd40a54587d6bad35vboxsync if (uECX & RT_BIT(12)) pHlp->pfnPrintf(pHlp, " SKINIT");
ca3da10d05961c339b5180fbd40a54587d6bad35vboxsync if (uECX & RT_BIT(13)) pHlp->pfnPrintf(pHlp, " WDT");
ca3da10d05961c339b5180fbd40a54587d6bad35vboxsync ASMCpuId(0x80000001, &Host.eax, &Host.ebx, &Host.ecx, &Host.edx);
ca3da10d05961c339b5180fbd40a54587d6bad35vboxsync pHlp->pfnPrintf(pHlp, "Mnemonic - Description = guest (host)\n");
ca3da10d05961c339b5180fbd40a54587d6bad35vboxsync pHlp->pfnPrintf(pHlp, "FPU - x87 FPU on Chip = %d (%d)\n", !!(uEdxGst & RT_BIT( 0)), !!(uEdxHst & RT_BIT( 0)));
ca3da10d05961c339b5180fbd40a54587d6bad35vboxsync pHlp->pfnPrintf(pHlp, "VME - Virtual 8086 Mode Enhancements = %d (%d)\n", !!(uEdxGst & RT_BIT( 1)), !!(uEdxHst & RT_BIT( 1)));
ca3da10d05961c339b5180fbd40a54587d6bad35vboxsync pHlp->pfnPrintf(pHlp, "DE - Debugging extensions = %d (%d)\n", !!(uEdxGst & RT_BIT( 2)), !!(uEdxHst & RT_BIT( 2)));
ca3da10d05961c339b5180fbd40a54587d6bad35vboxsync pHlp->pfnPrintf(pHlp, "PSE - Page Size Extension = %d (%d)\n", !!(uEdxGst & RT_BIT( 3)), !!(uEdxHst & RT_BIT( 3)));
ca3da10d05961c339b5180fbd40a54587d6bad35vboxsync pHlp->pfnPrintf(pHlp, "TSC - Time Stamp Counter = %d (%d)\n", !!(uEdxGst & RT_BIT( 4)), !!(uEdxHst & RT_BIT( 4)));
ca3da10d05961c339b5180fbd40a54587d6bad35vboxsync pHlp->pfnPrintf(pHlp, "MSR - K86 Model Specific Registers = %d (%d)\n", !!(uEdxGst & RT_BIT( 5)), !!(uEdxHst & RT_BIT( 5)));
ca3da10d05961c339b5180fbd40a54587d6bad35vboxsync pHlp->pfnPrintf(pHlp, "PAE - Physical Address Extension = %d (%d)\n", !!(uEdxGst & RT_BIT( 6)), !!(uEdxHst & RT_BIT( 6)));
ca3da10d05961c339b5180fbd40a54587d6bad35vboxsync pHlp->pfnPrintf(pHlp, "MCE - Machine Check Exception = %d (%d)\n", !!(uEdxGst & RT_BIT( 7)), !!(uEdxHst & RT_BIT( 7)));
ca3da10d05961c339b5180fbd40a54587d6bad35vboxsync pHlp->pfnPrintf(pHlp, "CX8 - CMPXCHG8B instruction = %d (%d)\n", !!(uEdxGst & RT_BIT( 8)), !!(uEdxHst & RT_BIT( 8)));
ca3da10d05961c339b5180fbd40a54587d6bad35vboxsync pHlp->pfnPrintf(pHlp, "APIC - APIC On-Chip = %d (%d)\n", !!(uEdxGst & RT_BIT( 9)), !!(uEdxHst & RT_BIT( 9)));
044af0d1e6474076366759db86f101778c5f20ccvboxsync pHlp->pfnPrintf(pHlp, "10 - Reserved = %d (%d)\n", !!(uEdxGst & RT_BIT(10)), !!(uEdxHst & RT_BIT(10)));
ca3da10d05961c339b5180fbd40a54587d6bad35vboxsync pHlp->pfnPrintf(pHlp, "SEP - SYSCALL and SYSRET = %d (%d)\n", !!(uEdxGst & RT_BIT(11)), !!(uEdxHst & RT_BIT(11)));
ca3da10d05961c339b5180fbd40a54587d6bad35vboxsync pHlp->pfnPrintf(pHlp, "MTRR - Memory Type Range Registers = %d (%d)\n", !!(uEdxGst & RT_BIT(12)), !!(uEdxHst & RT_BIT(12)));
ca3da10d05961c339b5180fbd40a54587d6bad35vboxsync pHlp->pfnPrintf(pHlp, "PGE - PTE Global Bit = %d (%d)\n", !!(uEdxGst & RT_BIT(13)), !!(uEdxHst & RT_BIT(13)));
ca3da10d05961c339b5180fbd40a54587d6bad35vboxsync pHlp->pfnPrintf(pHlp, "MCA - Machine Check Architecture = %d (%d)\n", !!(uEdxGst & RT_BIT(14)), !!(uEdxHst & RT_BIT(14)));
aa4bcf0a4b2db3ac352b56a291d49cb8d4b66d32vboxsync pHlp->pfnPrintf(pHlp, "CMOV - Conditional Move Instructions = %d (%d)\n", !!(uEdxGst & RT_BIT(15)), !!(uEdxHst & RT_BIT(15)));
ca3da10d05961c339b5180fbd40a54587d6bad35vboxsync pHlp->pfnPrintf(pHlp, "PAT - Page Attribute Table = %d (%d)\n", !!(uEdxGst & RT_BIT(16)), !!(uEdxHst & RT_BIT(16)));
ca3da10d05961c339b5180fbd40a54587d6bad35vboxsync pHlp->pfnPrintf(pHlp, "PSE-36 - 36-bit Page Size Extention = %d (%d)\n", !!(uEdxGst & RT_BIT(17)), !!(uEdxHst & RT_BIT(17)));
df8e6a449f00e1884fbf4a1fc67143614d7d528dvboxsync pHlp->pfnPrintf(pHlp, "18 - Reserved = %d (%d)\n", !!(uEdxGst & RT_BIT(18)), !!(uEdxHst & RT_BIT(18)));
8b4a8db7768e94d025f1216ecfcd50d727fa2b7cvboxsync pHlp->pfnPrintf(pHlp, "19 - Reserved = %d (%d)\n", !!(uEdxGst & RT_BIT(19)), !!(uEdxHst & RT_BIT(19)));
df8e6a449f00e1884fbf4a1fc67143614d7d528dvboxsync pHlp->pfnPrintf(pHlp, "NX - No-Execute Page Protection = %d (%d)\n", !!(uEdxGst & RT_BIT(20)), !!(uEdxHst & RT_BIT(20)));
df8e6a449f00e1884fbf4a1fc67143614d7d528dvboxsync pHlp->pfnPrintf(pHlp, "DS - Debug Store = %d (%d)\n", !!(uEdxGst & RT_BIT(21)), !!(uEdxHst & RT_BIT(21)));
df8e6a449f00e1884fbf4a1fc67143614d7d528dvboxsync pHlp->pfnPrintf(pHlp, "AXMMX - AMD Extensions to MMX Instr. = %d (%d)\n", !!(uEdxGst & RT_BIT(22)), !!(uEdxHst & RT_BIT(22)));
df8e6a449f00e1884fbf4a1fc67143614d7d528dvboxsync pHlp->pfnPrintf(pHlp, "MMX - Intel MMX Technology = %d (%d)\n", !!(uEdxGst & RT_BIT(23)), !!(uEdxHst & RT_BIT(23)));
df8e6a449f00e1884fbf4a1fc67143614d7d528dvboxsync pHlp->pfnPrintf(pHlp, "FXSR - FXSAVE and FXRSTOR Instructions = %d (%d)\n", !!(uEdxGst & RT_BIT(24)), !!(uEdxHst & RT_BIT(24)));
df8e6a449f00e1884fbf4a1fc67143614d7d528dvboxsync pHlp->pfnPrintf(pHlp, "25 - AMD fast FXSAVE and FXRSTOR Instr.= %d (%d)\n", !!(uEdxGst & RT_BIT(25)), !!(uEdxHst & RT_BIT(25)));
df8e6a449f00e1884fbf4a1fc67143614d7d528dvboxsync pHlp->pfnPrintf(pHlp, "26 - 1 GB large page support = %d (%d)\n", !!(uEdxGst & RT_BIT(26)), !!(uEdxHst & RT_BIT(26)));
df8e6a449f00e1884fbf4a1fc67143614d7d528dvboxsync pHlp->pfnPrintf(pHlp, "27 - RDTSCP instruction = %d (%d)\n", !!(uEdxGst & RT_BIT(27)), !!(uEdxHst & RT_BIT(27)));
8b4a8db7768e94d025f1216ecfcd50d727fa2b7cvboxsync pHlp->pfnPrintf(pHlp, "28 - Reserved = %d (%d)\n", !!(uEdxGst & RT_BIT(28)), !!(uEdxHst & RT_BIT(28)));
aa4bcf0a4b2db3ac352b56a291d49cb8d4b66d32vboxsync pHlp->pfnPrintf(pHlp, "29 - AMD Long Mode = %d (%d)\n", !!(uEdxGst & RT_BIT(29)), !!(uEdxHst & RT_BIT(29)));
8b4a8db7768e94d025f1216ecfcd50d727fa2b7cvboxsync pHlp->pfnPrintf(pHlp, "30 - AMD Extensions to 3DNow = %d (%d)\n", !!(uEdxGst & RT_BIT(30)), !!(uEdxHst & RT_BIT(30)));
df8e6a449f00e1884fbf4a1fc67143614d7d528dvboxsync pHlp->pfnPrintf(pHlp, "31 - AMD 3DNow = %d (%d)\n", !!(uEdxGst & RT_BIT(31)), !!(uEdxHst & RT_BIT(31)));
df8e6a449f00e1884fbf4a1fc67143614d7d528dvboxsync pHlp->pfnPrintf(pHlp, "LahfSahf - LAHF/SAHF in 64-bit mode = %d (%d)\n", !!(uEcxGst & RT_BIT( 0)), !!(uEcxHst & RT_BIT( 0)));
df8e6a449f00e1884fbf4a1fc67143614d7d528dvboxsync pHlp->pfnPrintf(pHlp, "CmpLegacy - Core MP legacy mode (depr) = %d (%d)\n", !!(uEcxGst & RT_BIT( 1)), !!(uEcxHst & RT_BIT( 1)));
df8e6a449f00e1884fbf4a1fc67143614d7d528dvboxsync pHlp->pfnPrintf(pHlp, "SVM - AMD VM Extensions = %d (%d)\n", !!(uEcxGst & RT_BIT( 2)), !!(uEcxHst & RT_BIT( 2)));
df8e6a449f00e1884fbf4a1fc67143614d7d528dvboxsync pHlp->pfnPrintf(pHlp, "APIC registers starting at 0x400 = %d (%d)\n", !!(uEcxGst & RT_BIT( 3)), !!(uEcxHst & RT_BIT( 3)));
df8e6a449f00e1884fbf4a1fc67143614d7d528dvboxsync pHlp->pfnPrintf(pHlp, "AltMovCR8 - LOCK MOV CR0 means MOV CR8 = %d (%d)\n", !!(uEcxGst & RT_BIT( 4)), !!(uEcxHst & RT_BIT( 4)));
df8e6a449f00e1884fbf4a1fc67143614d7d528dvboxsync pHlp->pfnPrintf(pHlp, "Advanced bit manipulation = %d (%d)\n", !!(uEcxGst & RT_BIT( 5)), !!(uEcxHst & RT_BIT( 5)));
df8e6a449f00e1884fbf4a1fc67143614d7d528dvboxsync pHlp->pfnPrintf(pHlp, "SSE4A instruction support = %d (%d)\n", !!(uEcxGst & RT_BIT( 6)), !!(uEcxHst & RT_BIT( 6)));
df8e6a449f00e1884fbf4a1fc67143614d7d528dvboxsync pHlp->pfnPrintf(pHlp, "Misaligned SSE mode = %d (%d)\n", !!(uEcxGst & RT_BIT( 7)), !!(uEcxHst & RT_BIT( 7)));
aa4bcf0a4b2db3ac352b56a291d49cb8d4b66d32vboxsync pHlp->pfnPrintf(pHlp, "PREFETCH and PREFETCHW instruction = %d (%d)\n", !!(uEcxGst & RT_BIT( 8)), !!(uEcxHst & RT_BIT( 8)));
df8e6a449f00e1884fbf4a1fc67143614d7d528dvboxsync pHlp->pfnPrintf(pHlp, "OS visible workaround = %d (%d)\n", !!(uEcxGst & RT_BIT( 9)), !!(uEcxHst & RT_BIT( 9)));
df8e6a449f00e1884fbf4a1fc67143614d7d528dvboxsync pHlp->pfnPrintf(pHlp, "Instruction based sampling = %d (%d)\n", !!(uEcxGst & RT_BIT(10)), !!(uEcxHst & RT_BIT(10)));
df8e6a449f00e1884fbf4a1fc67143614d7d528dvboxsync pHlp->pfnPrintf(pHlp, "SSE5 support = %d (%d)\n", !!(uEcxGst & RT_BIT(11)), !!(uEcxHst & RT_BIT(11)));
df8e6a449f00e1884fbf4a1fc67143614d7d528dvboxsync pHlp->pfnPrintf(pHlp, "SKINIT, STGI, and DEV support = %d (%d)\n", !!(uEcxGst & RT_BIT(12)), !!(uEcxHst & RT_BIT(12)));
df8e6a449f00e1884fbf4a1fc67143614d7d528dvboxsync pHlp->pfnPrintf(pHlp, "Watchdog timer support. = %d (%d)\n", !!(uEcxGst & RT_BIT(13)), !!(uEcxHst & RT_BIT(13)));
df8e6a449f00e1884fbf4a1fc67143614d7d528dvboxsync pHlp->pfnPrintf(pHlp, "31:14 - Reserved = %#x (%#x)\n", uEcxGst >> 14, uEcxHst >> 14);
df8e6a449f00e1884fbf4a1fc67143614d7d528dvboxsync pHlp->pfnPrintf(pHlp, "Full Name: %s\n", szString);
df8e6a449f00e1884fbf4a1fc67143614d7d528dvboxsync "TLB 2/4M Instr/Uni: %s %3d entries\n"
df8e6a449f00e1884fbf4a1fc67143614d7d528dvboxsync "TLB 2/4M Data: %s %3d entries\n",
df8e6a449f00e1884fbf4a1fc67143614d7d528dvboxsync getCacheAss((uEAX >> 8) & 0xff, sz1), (uEAX >> 0) & 0xff,
df8e6a449f00e1884fbf4a1fc67143614d7d528dvboxsync getCacheAss((uEAX >> 24) & 0xff, sz2), (uEAX >> 16) & 0xff);
df8e6a449f00e1884fbf4a1fc67143614d7d528dvboxsync "TLB 4K Instr/Uni: %s %3d entries\n"
df8e6a449f00e1884fbf4a1fc67143614d7d528dvboxsync "TLB 4K Data: %s %3d entries\n",
df8e6a449f00e1884fbf4a1fc67143614d7d528dvboxsync getCacheAss((uEBX >> 8) & 0xff, sz1), (uEBX >> 0) & 0xff,
aa4bcf0a4b2db3ac352b56a291d49cb8d4b66d32vboxsync getCacheAss((uEBX >> 24) & 0xff, sz2), (uEBX >> 16) & 0xff);
df8e6a449f00e1884fbf4a1fc67143614d7d528dvboxsync pHlp->pfnPrintf(pHlp, "L1 Instr Cache Line Size: %d bytes\n"
df8e6a449f00e1884fbf4a1fc67143614d7d528dvboxsync "L1 Instr Cache Lines Per Tag: %d\n"
df8e6a449f00e1884fbf4a1fc67143614d7d528dvboxsync "L1 Instr Cache Associativity: %s\n"
df8e6a449f00e1884fbf4a1fc67143614d7d528dvboxsync "L1 Instr Cache Size: %d KB\n",
df8e6a449f00e1884fbf4a1fc67143614d7d528dvboxsync "L1 Data Cache Line Size: %d bytes\n"
df8e6a449f00e1884fbf4a1fc67143614d7d528dvboxsync "L1 Data Cache Lines Per Tag: %d\n"
df8e6a449f00e1884fbf4a1fc67143614d7d528dvboxsync "L1 Data Cache Associativity: %s\n"
df8e6a449f00e1884fbf4a1fc67143614d7d528dvboxsync "L1 Data Cache Size: %d KB\n",
pHlp->pfnPrintf(pHlp, "AIS - Alternate Instruction Set = %d (%d)\n", !!(uEdxGst & RT_BIT( 0)), !!(uEdxHst & RT_BIT( 0)));
pHlp->pfnPrintf(pHlp, "AIS-E - AIS enabled = %d (%d)\n", !!(uEdxGst & RT_BIT( 1)), !!(uEdxHst & RT_BIT( 1)));
pHlp->pfnPrintf(pHlp, "RNG - Random Number Generator = %d (%d)\n", !!(uEdxGst & RT_BIT( 2)), !!(uEdxHst & RT_BIT( 2)));
pHlp->pfnPrintf(pHlp, "RNG-E - RNG enabled = %d (%d)\n", !!(uEdxGst & RT_BIT( 3)), !!(uEdxHst & RT_BIT( 3)));
pHlp->pfnPrintf(pHlp, "LH - LongHaul MSR 0000_110Ah = %d (%d)\n", !!(uEdxGst & RT_BIT( 4)), !!(uEdxHst & RT_BIT( 4)));
pHlp->pfnPrintf(pHlp, "FEMMS - FEMMS = %d (%d)\n", !!(uEdxGst & RT_BIT( 5)), !!(uEdxHst & RT_BIT( 5)));
pHlp->pfnPrintf(pHlp, "ACE - Advanced Cryptography Engine = %d (%d)\n", !!(uEdxGst & RT_BIT( 6)), !!(uEdxHst & RT_BIT( 6)));
pHlp->pfnPrintf(pHlp, "ACE-E - ACE enabled = %d (%d)\n", !!(uEdxGst & RT_BIT( 7)), !!(uEdxHst & RT_BIT( 7)));
pHlp->pfnPrintf(pHlp, "ACE2 - Advanced Cryptography Engine 2 = %d (%d)\n", !!(uEdxGst & RT_BIT( 8)), !!(uEdxHst & RT_BIT( 8)));
pHlp->pfnPrintf(pHlp, "ACE2-E - ACE enabled = %d (%d)\n", !!(uEdxGst & RT_BIT( 9)), !!(uEdxHst & RT_BIT( 9)));
pHlp->pfnPrintf(pHlp, "PHE - Hash Engine = %d (%d)\n", !!(uEdxGst & RT_BIT(10)), !!(uEdxHst & RT_BIT(10)));
pHlp->pfnPrintf(pHlp, "PHE-E - PHE enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(11)), !!(uEdxHst & RT_BIT(11)));
pHlp->pfnPrintf(pHlp, "PMM - Montgomery Multiplier = %d (%d)\n", !!(uEdxGst & RT_BIT(12)), !!(uEdxHst & RT_BIT(12)));
pHlp->pfnPrintf(pHlp, "PMM-E - PMM enabled = %d (%d)\n", !!(uEdxGst & RT_BIT(13)), !!(uEdxHst & RT_BIT(13)));
pHlp->pfnPrintf(pHlp, "Bit %d = %d (%d)\n", !!(uEdxGst & RT_BIT(iBit)), !!(uEdxHst & RT_BIT(iBit)));
typedef struct CPUMDISASSTATE
void const *pvPageHC;
bool fLocked;
bool f64Bits;
static DECLCALLBACK(int) cpumR3DisasInstrRead(RTUINTPTR PtrSrc, uint8_t *pu8Dst, unsigned cbRead, void *uDisCpu)
rc = PGMPhysGCPtr2CCPtrReadOnly(pState->pVM, pState->pvPageGC, &pState->pvPageHC, &pState->PageMapLock);
return rc;
return VERR_OUT_OF_SELECTOR_BOUNDS;
if (!cbRead)
return VINF_SUCCESS;
CPUMR3DECL(int) CPUMR3DisasmInstrCPU(PVM pVM, PCPUMCTX pCtx, RTGCPTR GCPtrPC, PDISCPUSTATE pCpu, const char *pszPrefix)
int rc;
AssertMsgFailed(("SELMR3GetShadowSelectorInfo failed for %04X:%VGv rc=%d\n", pCtx->cs, GCPtrPC, rc));
return rc;
return rc;
#ifndef LOG_ENABLED
if (pszPrefix)
return rc;
#ifdef DEBUG
CPUMR3DECL(void) CPUMR3DisasmBlock(PVM pVM, PCPUMCTX pCtx, RTGCPTR pc, char *prefix, int nrInstructions)
for(int i=0;i<nrInstructions;i++)
#ifdef DEBUG
AssertMsgReturn((fAnd & ~(X86_CR4_TSD)) == ~(X86_CR4_TSD), ("%#x\n", fAnd), VERR_INVALID_PARAMETER);
return VINF_SUCCESS;