tstInlineAsm.cpp revision 3e6c6998d1dfeded8b9a23f5aa94ad63e9a681d9
/* $Id$ */
/** @file
* innotek Portable Runtime Testcase - inline assembly.
*/
/*
* Copyright (C) 2006-2007 innotek GmbH
*
* This file is part of VirtualBox Open Source Edition (OSE), as
* available from http://www.virtualbox.org. This file is free software;
* General Public License as published by the Free Software Foundation,
* in version 2 as it comes in the "COPYING" file of the VirtualBox OSE
* distribution. VirtualBox OSE is distributed in the hope that it will
* be useful, but WITHOUT ANY WARRANTY of any kind.
*/
/*******************************************************************************
* Header Files *
*******************************************************************************/
/*******************************************************************************
* Global Variables *
*******************************************************************************/
/** Global error count. */
static unsigned g_cErrors;
/*******************************************************************************
* Defined Constants And Macros *
*******************************************************************************/
do \
{ \
{ \
g_cErrors++; \
RTPrintf("%s, %d: " #val ": expected " fmt " got " fmt "\n", __FUNCTION__, __LINE__, (expect), (val)); \
} \
} while (0)
do \
{ \
{ \
g_cErrors++; \
RTPrintf("%s, %d: " #op ": expected " fmt " got " fmt "\n", __FUNCTION__, __LINE__, (type)(expect), val); \
} \
} while (0)
#if !defined(PIC) || !defined(RT_ARCH_X86)
const char *getCacheAss(unsigned u)
{
if (u == 0)
return "res0 ";
if (u == 1)
return "direct";
if (u >= 256)
return "???";
char *pszRet;
return pszRet;
}
const char *getL2CacheAss(unsigned u)
{
switch (u)
{
case 0: return "off ";
case 1: return "direct";
case 2: return "2 way ";
case 3: return "res3 ";
case 4: return "4 way ";
case 5: return "res5 ";
case 6: return "8 way ";
case 7: return "res7 ";
case 8: return "16 way";
case 9: return "res9 ";
case 10: return "res10 ";
case 11: return "res11 ";
case 12: return "res12 ";
case 13: return "res13 ";
case 14: return "res14 ";
case 15: return "fully ";
default:
return "????";
}
}
/**
* Test and dump all possible info from the CPUID instruction.
*
* @remark Bits shared with the libc cpuid.c program. This all written by me, so no worries.
* @todo transform the dumping into a generic runtime function. We'll need it for logging!
*/
void tstASMCpuId(void)
{
unsigned iBit;
struct
{
} s;
if (!ASMHasCpuId())
{
RTPrintf("tstInlineAsm: warning! CPU doesn't support CPUID\n");
return;
}
/*
* Try the 0 function and use that for checking the ASMCpuId_* variants.
*/
u32 = ASMCpuId_EDX(0);
/*
* Done testing, dump the information.
*/
RTPrintf("tstInlineAsm: CPUID Dump\n");
/* raw dump */
RTPrintf("\n"
" RAW Standard CPUIDs\n"
"Function eax ebx ecx edx\n");
{
RTPrintf("%08x %08x %08x %08x %08x%s\n",
}
/*
* Understandable output
*/
RTPrintf("Name: %.04s%.04s%.04s\n"
"Support: 0-%u\n",
/*
* Get Features.
*/
if (cFunctions >= 1)
{
RTPrintf("Family: %d \tExtended: %d \tEffectiv: %d\n"
"Model: %d \tExtended: %d \tEffectiv: %d\n"
"Stepping: %d\n"
"APIC ID: %#04x\n"
"Logical CPUs: %d\n"
"CLFLUSH Size: %d\n"
"Brand ID: %#04x\n",
(s.uEAX >> 8) & 0xf, (s.uEAX >> 20) & 0x7f, ((s.uEAX >> 8) & 0xf) + (((s.uEAX >> 8) & 0xf) == 0xf ? (s.uEAX >> 20) & 0x7f : 0),
(s.uEAX >> 4) & 0xf, (s.uEAX >> 16) & 0x0f, ((s.uEAX >> 4) & 0xf) | (((s.uEAX >> 4) & 0xf) == 0xf ? (s.uEAX >> 16) & 0x0f : 0),
(s.uEAX >> 0) & 0xf,
(s.uEBX >> 0) & 0xff);
RTPrintf("Features EDX: ");
RTPrintf("\n");
/** @todo check intel docs. */
RTPrintf("Features ECX: ");
RTPrintf("\n");
}
/*
* Extended.
* Implemented after AMD specs.
*/
/** @todo check out the intel specs. */
{
RTPrintf("No extended CPUID info? Check the manual on how to detect this...\n");
return;
}
/* raw dump */
RTPrintf("\n"
" RAW Extended CPUIDs\n"
"Function eax ebx ecx edx\n");
{
RTPrintf("%08x %08x %08x %08x %08x%s\n",
}
/*
* Understandable output
*/
RTPrintf("Ext Name: %.4s%.4s%.4s\n"
"Ext Supports: 0x80000000-%#010x\n",
if (cExtFunctions >= 0x80000001)
{
RTPrintf("Family: %d \tExtended: %d \tEffectiv: %d\n"
"Model: %d \tExtended: %d \tEffectiv: %d\n"
"Stepping: %d\n"
"Brand ID: %#05x\n",
(s.uEAX >> 8) & 0xf, (s.uEAX >> 20) & 0x7f, ((s.uEAX >> 8) & 0xf) + (((s.uEAX >> 8) & 0xf) == 0xf ? (s.uEAX >> 20) & 0x7f : 0),
(s.uEAX >> 4) & 0xf, (s.uEAX >> 16) & 0x0f, ((s.uEAX >> 4) & 0xf) | (((s.uEAX >> 4) & 0xf) == 0xf ? (s.uEAX >> 16) & 0x0f : 0),
(s.uEAX >> 0) & 0xf,
s.uEBX & 0xfff);
RTPrintf("Features EDX: ");
RTPrintf("\n");
RTPrintf("Features ECX: ");
RTPrintf("\n");
}
if (cExtFunctions >= 0x80000002)
if (cExtFunctions >= 0x80000003)
if (cExtFunctions >= 0x80000004)
if (cExtFunctions >= 0x80000002)
if (cExtFunctions >= 0x80000005)
{
"TLB 2/4M Data: %s %3d entries\n",
"TLB 4K Data: %s %3d entries\n",
RTPrintf("L1 Instr Cache Line Size: %d bytes\n"
"L1 Instr Cache Lines Per Tag: %d\n"
"L1 Instr Cache Associativity: %s\n"
"L1 Instr Cache Size: %d KB\n",
(s.uEDX >> 0) & 0xff,
RTPrintf("L1 Data Cache Line Size: %d bytes\n"
"L1 Data Cache Lines Per Tag: %d\n"
"L1 Data Cache Associativity: %s\n"
"L1 Data Cache Size: %d KB\n",
(s.uECX >> 0) & 0xff,
}
if (cExtFunctions >= 0x80000006)
{
"L2 TLB 2/4M Data: %s %4d entries\n",
"L2 TLB 4K Data: %s %4d entries\n",
RTPrintf("L2 Cache Line Size: %d bytes\n"
"L2 Cache Lines Per Tag: %d\n"
"L2 Cache Associativity: %s\n"
"L2 Cache Size: %d KB\n",
(s.uEDX >> 0) & 0xff,
}
if (cExtFunctions >= 0x80000007)
{
RTPrintf("APM Features: ");
RTPrintf("\n");
}
if (cExtFunctions >= 0x80000008)
{
RTPrintf("Physical Address Width: %d bits\n"
"Virtual Address Width: %d bits\n",
(s.uEAX >> 0) & 0xff,
RTPrintf("Physical Core Count: %d\n",
}
if (cExtFunctions >= 0x8000000a)
{
RTPrintf("SVM Revision: %d (%#x)\n"
"Number of Address Space IDs: %d (%#x)\n",
}
}
#endif /* !PIC || !X86 */
static void tstASMAtomicXchgU8(void)
{
struct
{
} s;
s.u8 = 0;
}
static void tstASMAtomicXchgU16(void)
{
struct
{
} s;
s.u16 = 0;
}
static void tstASMAtomicXchgU32(void)
{
struct
{
} s;
s.u32 = 0;
}
static void tstASMAtomicXchgU64(void)
{
struct
{
} s;
s.u64 = 0;
}
#ifdef RT_ARCH_AMD64
static void tstASMAtomicXchgU128(void)
{
struct
{
} s;
s.u128Dummy1 = s.u128Dummy0;
}
#endif
static void tstASMAtomicXchgPtr(void)
{
}
static void tstASMAtomicCmpXchgU32(void)
{
}
static void tstASMAtomicCmpXchgU64(void)
{
}
static void tstASMAtomicReadU64(void)
{
u64 = 0xfedcba0987654321ULL;
}
static void tstASMAtomicDecIncS32(void)
{
do { \
{ \
g_cErrors++; \
} \
{ \
g_cErrors++; \
} \
} while (0)
}
static void tstASMAtomicAndOrU32(void)
{
ASMAtomicAndU32(&u32, 0);
}
void tstASMMemZeroPage(void)
{
struct
{
{
g_cErrors++;
}
{
RTPrintf("tstInlineAsm: ASMMemZeroPage didn't clear byte at offset %#x!\n", i);
g_cErrors++;
}
{
RTPrintf("tstInlineAsm: ASMMemZeroPage didn't clear byte at offset %#x!\n", i);
g_cErrors++;
}
{
RTPrintf("tstInlineAsm: ASMMemZeroPage didn't clear byte at offset %#x!\n", i);
g_cErrors++;
}
}
void tstASMMath(void)
{
u64 = ASMMultU64ByU32DivByU32(UINT64_C(0x0000000000000001), UINT32_C(0x00000001), UINT32_C(0x00000001));
u64 = ASMMultU64ByU32DivByU32(UINT64_C(0x0000000100000000), UINT32_C(0x80000000), UINT32_C(0x00000002));
u64 = ASMMultU64ByU32DivByU32(UINT64_C(0xfedcba9876543210), UINT32_C(0xffffffff), UINT32_C(0xffffffff));
u64 = ASMMultU64ByU32DivByU32(UINT64_C(0xffffffffffffffff), UINT32_C(0xffffffff), UINT32_C(0xffffffff));
u64 = ASMMultU64ByU32DivByU32(UINT64_C(0xffffffffffffffff), UINT32_C(0xfffffff0), UINT32_C(0xffffffff));
u64 = ASMMultU64ByU32DivByU32(UINT64_C(0x3415934810359583), UINT32_C(0x58734981), UINT32_C(0xf8694045));
u64 = ASMMultU64ByU32DivByU32(UINT64_C(0x3415934810359583), UINT32_C(0xf8694045), UINT32_C(0x58734981));
#if 0 /* bird: question is whether this should trap or not:
*
* frank: Of course it must trap:
*
* 0xfffffff8 * 0x77d7daf8 = 0x77d7daf441412840
*
* During the following division, the quotient must fit into a 32-bit register.
* Therefore the smallest valid divisor is
*
* (0x77d7daf441412840 >> 32) + 1 = 0x77d7daf5
*
* which is definitely greater than 0x3b9aca00.
*
* bird: No, the C version does *not* crash. So, the question is whether there any
* code depending on it not crashing.
*
* Of course the assembly versions of the code crash right now for the reasons you've
* given, but the the 32-bit MSC version does not crash.
*
* frank: The C version does not crash but delivers incorrect results for this case.
* The reason is
*
* u.s.Hi = (unsigned long)(u64Hi / u32C);
*
* Here the division is actually 64-bit by 64-bit but the 64-bit result is truncated
* to 32 bit. If using this (optimized and fast) function we should just be sure that
* the operands are in a valid range.
*/
u64 = ASMMultU64ByU32DivByU32(UINT64_C(0xfffffff8c65d6731), UINT32_C(0x77d7daf8), UINT32_C(0x3b9aca00));
#endif
}
{
RTR3Init();
RTPrintf("tstInlineAsm: TESTING\n");
/*
* Execute the tests.
*/
#if !defined(PIC) || !defined(RT_ARCH_X86)
tstASMCpuId();
#endif
#ifdef RT_ARCH_AMD64
#endif
tstASMMath();
/*
* Show the result.
*/
if (!g_cErrors)
else
return !!g_cErrors;
}