semrw-lockless-generic.cpp revision d0a2a9ce3384a88aeb052555867cb9aea43142b7
/* $Id$ */
/** @file
* IPRT - Read-Write Semaphore, Generic, lockless variant.
*/
/*
* Copyright (C) 2009-2013 Oracle Corporation
*
* This file is part of VirtualBox Open Source Edition (OSE), as
* available from http://www.virtualbox.org. This file is free software;
* General Public License (GPL) as published by the Free Software
* Foundation, in version 2 as it comes in the "COPYING" file of the
* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
*
* The contents of this file may alternatively be used under the terms
* of the Common Development and Distribution License Version 1.0
* (CDDL) only, as it comes in the "COPYING.CDDL" file of the
* VirtualBox OSE distribution, in which case the provisions of the
* CDDL are applicable instead of those of the GPL.
*
* You may elect to license modified versions of this file under the
* terms and conditions of either the GPL or the CDDL or both.
*/
/*******************************************************************************
* Header Files *
*******************************************************************************/
#define RTSEMRW_WITHOUT_REMAPPING
#define RTASSERT_QUIET
#include <iprt/semaphore.h>
#include <iprt/lockvalidator.h>
/*******************************************************************************
* Structures and Typedefs *
*******************************************************************************/
typedef struct RTSEMRWINTERNAL
{
/** Magic value (RTSEMRW_MAGIC). */
/** Indicates whether hEvtRead needs resetting. */
bool volatile fNeedReset;
/** The state variable.
* All accesses are atomic and it bits are defined like this:
* Bits 0..14 - cReads.
* Bit 15 - Unused.
* Bits 16..31 - cWrites. - doesn't make sense here
* Bit 31 - fDirection; 0=Read, 1=Write.
* Bits 32..46 - cWaitingReads
* Bit 47 - Unused.
* Bits 48..62 - cWaitingWrites
* Bit 63 - Unused.
*/
/** The write owner. */
RTNATIVETHREAD volatile hNativeWriter;
/** The number of reads made by the current writer. */
uint32_t volatile cWriterReads;
/** The number of recursions made by the current writer. (The initial grabbing
* of the lock counts as the first one.) */
uint32_t volatile cWriteRecursions;
/** What the writer threads are blocking on. */
/** What the read threads are blocking on when waiting for the writer to
* finish. */
#ifdef RTSEMRW_STRICT
/** The validator record for the writer. */
/** The validator record for the readers. */
#endif
/*******************************************************************************
* Defined Constants And Macros *
*******************************************************************************/
#define RTSEMRW_CNT_BITS 15
#define RTSEMRW_CNT_RD_SHIFT 0
#define RTSEMRW_CNT_WR_SHIFT 16
#define RTSEMRW_DIR_SHIFT 31
#define RTSEMRW_DIR_READ UINT64_C(0)
#define RTSEMRW_WAIT_CNT_RD_SHIFT 32
//#define RTSEMRW_WAIT_CNT_WR_SHIFT 48
//#define RTSEMRW_WAIT_CNT_WR_MASK (RTSEMRW_CNT_MASK << RTSEMRW_WAIT_CNT_WR_SHIFT)
{
return RTSemRWCreateEx(phRWSem, 0 /*fFlags*/, NIL_RTLOCKVALCLASS, RTLOCKVAL_SUB_CLASS_NONE, "RTSemRW");
}
{
if (!pThis)
return VERR_NO_MEMORY;
if (RT_SUCCESS(rc))
{
if (RT_SUCCESS(rc))
{
pThis->u32Padding = 0;
pThis->cWriterReads = 0;
pThis->cWriteRecursions = 0;
pThis->fNeedReset = false;
#ifdef RTSEMRW_STRICT
if (!pszNameFmt)
{
static uint32_t volatile s_iSemRWAnon = 0;
fLVEnabled, "RTSemRW-%u", i);
}
else
{
}
#endif
return VINF_SUCCESS;
}
}
return rc;
}
{
/*
* Validate input.
*/
if (pThis == NIL_RTSEMRW)
return VINF_SUCCESS;
/*
* Invalidate the object and free up the resources.
*/
AssertReturn(ASMAtomicCmpXchgU32(&pThis->u32Magic, ~RTSEMRW_MAGIC, RTSEMRW_MAGIC), VERR_INVALID_HANDLE);
#ifdef RTSEMRW_STRICT
#endif
return VINF_SUCCESS;
}
{
#ifdef RTSEMRW_STRICT
/*
* Validate handle.
*/
#else
return RTLOCKVAL_SUB_CLASS_INVALID;
#endif
}
static int rtSemRWRequestRead(RTSEMRW hRWSem, RTMSINTERVAL cMillies, bool fInterruptible, PCRTLOCKVALSRCPOS pSrcPos)
{
/*
* Validate input.
*/
if (pThis == NIL_RTSEMRW)
return VINF_SUCCESS;
#ifdef RTSEMRW_STRICT
if (cMillies > 0)
{
int rc9;
else
if (RT_FAILURE(rc9))
return rc9;
}
#endif
/*
* Get cracking...
*/
for (;;)
{
{
/* It flows in the right direction, try follow it before it changes. */
c++;
u64State |= c << RTSEMRW_CNT_RD_SHIFT;
{
#ifdef RTSEMRW_STRICT
#endif
break;
}
}
{
/* Wrong direction, but we're alone here and can simply try switch the direction. */
{
#ifdef RTSEMRW_STRICT
#endif
break;
}
}
else
{
/* Is the writer perhaps doing a read recursion? */
if (hNativeSelf == hNativeWriter)
{
#ifdef RTSEMRW_STRICT
int rc9 = RTLockValidatorRecExclRecursionMixed(&pThis->ValidatorWrite, &pThis->ValidatorRead.Core, pSrcPos);
if (RT_FAILURE(rc9))
return rc9;
#endif
return VINF_SUCCESS; /* don't break! */
}
/* If the timeout is 0, return already. */
if (!cMillies)
return VERR_TIMEOUT;
/* Add ourselves to the queue and wait for the direction to change. */
c++;
cWait++;
{
{
int rc;
#ifdef RTSEMRW_STRICT
cMillies, RTTHREADSTATE_RW_READ, false);
if (RT_SUCCESS(rc))
#else
#endif
{
if (fInterruptible)
else
return VERR_SEM_DESTROYED;
}
if (RT_FAILURE(rc))
{
/* Decrement the counts and return the error. */
for (;;)
{
c--;
cWait--;
break;
}
return rc;
}
break;
}
/* Decrement the wait count and maybe reset the semaphore (if we're last). */
for (;;)
{
cWait--;
{
if (cWait == 0)
{
{
}
}
break;
}
}
#ifdef RTSEMRW_STRICT
#endif
break;
}
}
return VERR_SEM_DESTROYED;
ASMNopPause();
}
/* got it! */
Assert((ASMAtomicReadU64(&pThis->u64State) & RTSEMRW_DIR_MASK) == (RTSEMRW_DIR_READ << RTSEMRW_DIR_SHIFT));
return VINF_SUCCESS;
}
{
#ifndef RTSEMRW_STRICT
#else
#endif
}
RTDECL(int) RTSemRWRequestReadDebug(RTSEMRW hRWSem, RTMSINTERVAL cMillies, RTHCUINTPTR uId, RT_SRC_POS_DECL)
{
}
{
#ifndef RTSEMRW_STRICT
#else
#endif
}
RTDECL(int) RTSemRWRequestReadNoResumeDebug(RTSEMRW hRWSem, RTMSINTERVAL cMillies, RTHCUINTPTR uId, RT_SRC_POS_DECL)
{
}
{
/*
* Validate handle.
*/
/*
* Check the direction and take action accordingly.
*/
{
#ifdef RTSEMRW_STRICT
if (RT_FAILURE(rc9))
return rc9;
#endif
for (;;)
{
AssertReturn(c > 0, VERR_NOT_OWNER);
c--;
if ( c > 0
|| (u64State & RTSEMRW_CNT_WD_MASK) == 0)
{
/* Don't change the direction. */
u64State |= c << RTSEMRW_CNT_RD_SHIFT;
break;
}
else
{
/* Reverse the direction and signal the reader threads. */
{
break;
}
}
ASMNopPause();
}
}
else
{
#ifdef RTSEMRW_STRICT
if (RT_FAILURE(rc))
return rc;
#endif
}
return VINF_SUCCESS;
}
DECL_FORCE_INLINE(int) rtSemRWRequestWrite(RTSEMRW hRWSem, RTMSINTERVAL cMillies, bool fInterruptible, PCRTLOCKVALSRCPOS pSrcPos)
{
/*
* Validate input.
*/
if (pThis == NIL_RTSEMRW)
return VINF_SUCCESS;
#ifdef RTSEMRW_STRICT
if (cMillies)
{
if (RT_FAILURE(rc9))
return rc9;
}
#endif
/*
* Check if we're already the owner and just recursing.
*/
if (hNativeSelf == hNativeWriter)
{
Assert((ASMAtomicReadU64(&pThis->u64State) & RTSEMRW_DIR_MASK) == (RTSEMRW_DIR_WRITE << RTSEMRW_DIR_SHIFT));
#ifdef RTSEMRW_STRICT
if (RT_FAILURE(rc9))
return rc9;
#endif
return VINF_SUCCESS;
}
/*
* Get cracking.
*/
for (;;)
{
{
/* It flows in the right direction, try follow it before it changes. */
c++;
u64State |= c << RTSEMRW_CNT_WR_SHIFT;
break;
}
{
/* Wrong direction, but we're alone here and can simply try switch the direction. */
break;
}
else if (!cMillies)
/* Wrong direction and we're not supposed to wait, just return. */
return VERR_TIMEOUT;
else
{
/* Add ourselves to the write count and break out to do the wait. */
c++;
u64State |= c << RTSEMRW_CNT_WR_SHIFT;
break;
}
return VERR_SEM_DESTROYED;
ASMNopPause();
}
/*
* If we're in write mode now try grab the ownership. Play fair if there
* are threads already waiting.
*/
|| cMillies == 0);
if (fDone)
if (!fDone)
{
/*
* Wait for our turn.
*/
{
int rc;
#ifdef RTSEMRW_STRICT
if (cMillies)
{
if (hThreadSelf == NIL_RTTHREAD)
cMillies, RTTHREADSTATE_RW_WRITE, false);
}
else
rc = VINF_SUCCESS;
if (RT_SUCCESS(rc))
#else
#endif
{
if (fInterruptible)
else
return VERR_SEM_DESTROYED;
}
if (RT_FAILURE(rc))
{
/* Decrement the counts and return the error. */
for (;;)
{
c--;
u64State |= c << RTSEMRW_CNT_WR_SHIFT;
break;
}
return rc;
}
{
if (fDone)
break;
}
}
}
/*
* Got it!
*/
Assert((ASMAtomicReadU64(&pThis->u64State) & RTSEMRW_DIR_MASK) == (RTSEMRW_DIR_WRITE << RTSEMRW_DIR_SHIFT));
#ifdef RTSEMRW_STRICT
#endif
return VINF_SUCCESS;
}
{
#ifndef RTSEMRW_STRICT
#else
#endif
}
RTDECL(int) RTSemRWRequestWriteDebug(RTSEMRW hRWSem, RTMSINTERVAL cMillies, RTHCUINTPTR uId, RT_SRC_POS_DECL)
{
}
{
#ifndef RTSEMRW_STRICT
#else
#endif
}
RTDECL(int) RTSemRWRequestWriteNoResumeDebug(RTSEMRW hRWSem, RTMSINTERVAL cMillies, RTHCUINTPTR uId, RT_SRC_POS_DECL)
{
}
{
/*
* Validate handle.
*/
/*
* Unwind a recursion.
*/
{
AssertReturn(pThis->cWriterReads == 0, VERR_WRONG_ORDER); /* (must release all read recursions before the final write.) */
#ifdef RTSEMRW_STRICT
if (RT_FAILURE(rc9))
return rc9;
#endif
/*
* Update the state.
*/
for (;;)
{
Assert(c > 0);
c--;
if ( c > 0
|| (u64State & RTSEMRW_CNT_RD_MASK) == 0)
{
/* Don't change the direction, wait up the next writer if any. */
u64State |= c << RTSEMRW_CNT_WR_SHIFT;
{
if (c > 0)
{
}
break;
}
}
else
{
/* Reverse the direction and signal the reader threads. */
{
break;
}
}
ASMNopPause();
return VERR_SEM_DESTROYED;
}
}
else
{
#ifdef RTSEMRW_STRICT
if (RT_FAILURE(rc9))
return rc9;
#endif
}
return VINF_SUCCESS;
}
{
/*
* Validate handle.
*/
AssertPtrReturn(pThis, false);
/*
* Check ownership.
*/
return hNativeWriter == hNativeSelf;
}
{
/*
* Validate handle.
*/
AssertPtrReturn(pThis, false);
/*
* Inspect the state.
*/
{
/*
* It's in write mode, so we can only be a reader if we're also the
* current writer.
*/
return hWriter == hNativeSelf;
}
/*
* Read mode. If there are no current readers, then we cannot be a reader.
*/
if (!(u64State & RTSEMRW_CNT_RD_MASK))
return false;
#ifdef RTSEMRW_STRICT
/*
* Ask the lock validator.
*/
#else
/*
* Ok, we don't know, just tell the caller what he want to hear.
*/
return fWannaHear;
#endif
}
{
/*
* Validate handle.
*/
AssertPtrReturn(pThis, 0);
/*
* Return the requested data.
*/
return pThis->cWriteRecursions;
}
{
/*
* Validate handle.
*/
AssertPtrReturn(pThis, 0);
/*
* Return the requested data.
*/
return pThis->cWriterReads;
}
{
/*
* Validate input.
*/
AssertPtrReturn(pThis, 0);
0);
/*
* Return the requested data.
*/
return 0;
}