tstGIP-2.cpp revision a9064b2c635be12f06d446ec409725235f55899d
0ba2cbe97e0678a691742f98d2532caed0a2c4aaxc * SUP Testcase - Global Info Page interface (ring 3).
0ba2cbe97e0678a691742f98d2532caed0a2c4aaxc * Copyright (C) 2006-2014 Oracle Corporation
0ba2cbe97e0678a691742f98d2532caed0a2c4aaxc * This file is part of VirtualBox Open Source Edition (OSE), as
0ba2cbe97e0678a691742f98d2532caed0a2c4aaxc * available from http://www.virtualbox.org. This file is free software;
0ba2cbe97e0678a691742f98d2532caed0a2c4aaxc * you can redistribute it and/or modify it under the terms of the GNU
0ba2cbe97e0678a691742f98d2532caed0a2c4aaxc * General Public License (GPL) as published by the Free Software
0ba2cbe97e0678a691742f98d2532caed0a2c4aaxc * Foundation, in version 2 as it comes in the "COPYING" file of the
0ba2cbe97e0678a691742f98d2532caed0a2c4aaxc * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
0ba2cbe97e0678a691742f98d2532caed0a2c4aaxc * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
0ba2cbe97e0678a691742f98d2532caed0a2c4aaxc * The contents of this file may alternatively be used under the terms
0ba2cbe97e0678a691742f98d2532caed0a2c4aaxc * of the Common Development and Distribution License Version 1.0
0ba2cbe97e0678a691742f98d2532caed0a2c4aaxc * (CDDL) only, as it comes in the "COPYING.CDDL" file of the
0ba2cbe97e0678a691742f98d2532caed0a2c4aaxc * VirtualBox OSE distribution, in which case the provisions of the
0ba2cbe97e0678a691742f98d2532caed0a2c4aaxc * CDDL are applicable instead of those of the GPL.
0ba2cbe97e0678a691742f98d2532caed0a2c4aaxc * You may elect to license modified versions of this file under the
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0ba2cbe97e0678a691742f98d2532caed0a2c4aaxc/*******************************************************************************
0ba2cbe97e0678a691742f98d2532caed0a2c4aaxc* Header Files *
0ba2cbe97e0678a691742f98d2532caed0a2c4aaxc*******************************************************************************/
0ba2cbe97e0678a691742f98d2532caed0a2c4aaxc * Checks whether the CPU advertises an invariant TSC or not.
0ba2cbe97e0678a691742f98d2532caed0a2c4aaxc * @returns true if invariant, false otherwise.
bcb5c89da22515e2ccf139578bad3caebcd716adSowmini Varadhan ASMCpuId(0x80000000, &uEax, &uEbx, &uEcx, &uEdx);
bcb5c89da22515e2ccf139578bad3caebcd716adSowmini Varadhan ASMCpuId(0x80000007, &uEax, &uEbx, &uEcx, &uEdx);
bcb5c89da22515e2ccf139578bad3caebcd716adSowmini Varadhan if (uEdx & X86_CPUID_AMD_ADVPOWER_EDX_TSCINVAR)
bcb5c89da22515e2ccf139578bad3caebcd716adSowmini Varadhan return false;
127ac1c2b792d87fda08d45d8b25e5ffe9293b3efei feng - Sun Microsystems - Beijing China { "--iterations", 'i', RTGETOPT_REQ_INT32 },
127ac1c2b792d87fda08d45d8b25e5ffe9293b3efei feng - Sun Microsystems - Beijing China { "--hex", 'h', RTGETOPT_REQ_NOTHING },
bcb5c89da22515e2ccf139578bad3caebcd716adSowmini Varadhan { "--decimal", 'd', RTGETOPT_REQ_NOTHING },
0ba2cbe97e0678a691742f98d2532caed0a2c4aaxc { "--reference", 'r', RTGETOPT_REQ_UINT64 }, /* reference value of CpuHz, display the
0ba2cbe97e0678a691742f98d2532caed0a2c4aaxc * CpuHz deviation in a separate column. */
0ba2cbe97e0678a691742f98d2532caed0a2c4aaxc bool fHex = true;
0ba2cbe97e0678a691742f98d2532caed0a2c4aaxc bool fSpin = false;
0ba2cbe97e0678a691742f98d2532caed0a2c4aaxc RTGetOptInit(&GetState, argc, argv, g_aOptions, RT_ELEMENTS(g_aOptions), 1, RTGETOPTINIT_FLAGS_NO_STD_OPTS);
0ba2cbe97e0678a691742f98d2532caed0a2c4aaxc RTPrintf("tstGIP-2: cCpus=%d u32UpdateHz=%RU32 u32UpdateIntervalNS=%RU32 u64NanoTSLastUpdateHz=%RX64 u64CpuHz=%RU64 uCpuHzRef=%RU64 u32Mode=%d (%s) u32Version=%#x\n",
0ba2cbe97e0678a691742f98d2532caed0a2c4aaxc ? "tstGIP-2: it: u64NanoTS delta u64TSC UpIntTSC H TransId CpuHz %sTSC Interval History...\n"
0ba2cbe97e0678a691742f98d2532caed0a2c4aaxc : "tstGIP-2: it: u64NanoTS delta u64TSC UpIntTSC H TransId CpuHz %sTSC Interval History...\n",
0ba2cbe97e0678a691742f98d2532caed0a2c4aaxc /* copy the data */
0ba2cbe97e0678a691742f98d2532caed0a2c4aaxc memcpy(&s_aaCPUs[i & 1][0], &g_pSUPGlobalInfoPage->aCPUs[0], g_pSUPGlobalInfoPage->cCpus * sizeof(g_pSUPGlobalInfoPage->aCPUs[0]));
0ba2cbe97e0678a691742f98d2532caed0a2c4aaxc /* display it & find something to spin on. */
0ba2cbe97e0678a691742f98d2532caed0a2c4aaxc for (unsigned iCpu = 0; iCpu < g_pSUPGlobalInfoPage->cCpus; iCpu++)
0ba2cbe97e0678a691742f98d2532caed0a2c4aaxc && g_pSUPGlobalInfoPage->aCPUs[iCpu].u64CpuHz != _4G + 1)
0ba2cbe97e0678a691742f98d2532caed0a2c4aaxc RTStrPrintf(szCpuHzDeviation, sizeof(szCpuHzDeviation), "%17s ", "?");
0ba2cbe97e0678a691742f98d2532caed0a2c4aaxc /* Wait until the history validation code takes effect. */
0ba2cbe97e0678a691742f98d2532caed0a2c4aaxc if (RT_ABS(iCpuHzDeviation) > RT_ABS(iCpuHzMaxDeviation))
0ba2cbe97e0678a691742f98d2532caed0a2c4aaxc uint32_t uPct = (uint32_t)(uCpuHzDeviation * 100000 / uCpuHzRef + 5);
bcb5c89da22515e2ccf139578bad3caebcd716adSowmini Varadhan RTStrPrintf(szCpuHzDeviation, sizeof(szCpuHzDeviation), "%10RI64%3d.%02d%% ",
0ba2cbe97e0678a691742f98d2532caed0a2c4aaxc ? "tstGIP-2: %4d/%d: %016llx %09llx %016llx %08x %d %08x %15llu %s%08x %08x %08x %08x %08x %08x %08x %08x (%d)\n"
0ba2cbe97e0678a691742f98d2532caed0a2c4aaxc : "tstGIP-2: %4d/%d: %016llu %09llu %016llu %010u %d %010u %15llu %s%08x %08x %08x %08x %08x %08x %08x %08x (%d)\n",
0ba2cbe97e0678a691742f98d2532caed0a2c4aaxc pu32TransactionId = &g_pSUPGlobalInfoPage->aCPUs[iCpu].u32TransactionId;
0ba2cbe97e0678a691742f98d2532caed0a2c4aaxc /* wait a bit / spin */
0ba2cbe97e0678a691742f98d2532caed0a2c4aaxc * Display TSC deltas.
0ba2cbe97e0678a691742f98d2532caed0a2c4aaxc * First iterative over the APIC ID array to get mostly consistent CPUID to APIC ID mapping.
0ba2cbe97e0678a691742f98d2532caed0a2c4aaxc * Then iterate over the offline CPUs. It is possible that there's a race between the online/offline
0ba2cbe97e0678a691742f98d2532caed0a2c4aaxc * states between the two iterations, but that cannot be helped from ring-3 anyway and not a biggie.
0ba2cbe97e0678a691742f98d2532caed0a2c4aaxc for (unsigned i = 0; i < RT_ELEMENTS(g_pSUPGlobalInfoPage->aiCpuFromApicId); i++)
0ba2cbe97e0678a691742f98d2532caed0a2c4aaxc uint16_t iCpu = g_pSUPGlobalInfoPage->aiCpuFromApicId[i];
0ba2cbe97e0678a691742f98d2532caed0a2c4aaxc RTPrintf("tstGIP-2: %7d: %lld\n", g_pSUPGlobalInfoPage->aCPUs[iCpu].idApic,
0ba2cbe97e0678a691742f98d2532caed0a2c4aaxc for (unsigned iCpu = 0; iCpu < g_pSUPGlobalInfoPage->cCpus; iCpu++)
0ba2cbe97e0678a691742f98d2532caed0a2c4aaxc if (g_pSUPGlobalInfoPage->aCPUs[iCpu].idApic == UINT16_MAX)
0ba2cbe97e0678a691742f98d2532caed0a2c4aaxc RTPrintf("tstGIP-2: offline: %lld\n", g_pSUPGlobalInfoPage->aCPUs[iCpu].i64TSCDelta);
0ba2cbe97e0678a691742f98d2532caed0a2c4aaxc RTPrintf("fTscDeltasRoughlyInSync: %RTbool\n", g_pSUPGlobalInfoPage->fTscDeltasRoughlyInSync);
0ba2cbe97e0678a691742f98d2532caed0a2c4aaxc RTPrintf("CPUID.Invariant-TSC : %RTbool\n", tstIsInvariantTsc());
0ba2cbe97e0678a691742f98d2532caed0a2c4aaxc uint32_t uPct = (uint32_t)(uCpuHzOverallDeviation * 100000 / cCpuHzOverallDevCnt / uCpuHzRef + 5);
0ba2cbe97e0678a691742f98d2532caed0a2c4aaxc uint32_t uMaxPct = (uint32_t)(RT_ABS(iCpuHzMaxDeviation) * 100000 / uCpuHzRef + 5);
0ba2cbe97e0678a691742f98d2532caed0a2c4aaxc RTPrintf("Average CpuHz deviation: %d.%02d%%\n", uPct / 1000, (uPct % 1000) / 10);
0ba2cbe97e0678a691742f98d2532caed0a2c4aaxc RTPrintf("Maximum CpuHz deviation: %d.%02d%% (%RI64 ticks)\n", uMaxPct / 1000, (uMaxPct % 1000) / 10, iCpuHzMaxDeviation);
bcb5c89da22515e2ccf139578bad3caebcd716adSowmini Varadhan RTPrintf("tstGIP-2: SUPR3Init failed: %Rrc\n", rc);
0ba2cbe97e0678a691742f98d2532caed0a2c4aaxc return !!rc;