tstDisasm-2.cpp revision 92473d1de9ab080ff886ad61a4d908f7c3429608
9055f61bb57d2a625c6434d55beac7565c3b3c0dvboxsync * Testcase - Generic Disassembler Tool.
9055f61bb57d2a625c6434d55beac7565c3b3c0dvboxsync * Copyright (C) 2008 Sun Microsystems, Inc.
9055f61bb57d2a625c6434d55beac7565c3b3c0dvboxsync * This file is part of VirtualBox Open Source Edition (OSE), as
9055f61bb57d2a625c6434d55beac7565c3b3c0dvboxsync * available from http://www.virtualbox.org. This file is free software;
9055f61bb57d2a625c6434d55beac7565c3b3c0dvboxsync * you can redistribute it and/or modify it under the terms of the GNU
9055f61bb57d2a625c6434d55beac7565c3b3c0dvboxsync * General Public License (GPL) as published by the Free Software
9055f61bb57d2a625c6434d55beac7565c3b3c0dvboxsync * Foundation, in version 2 as it comes in the "COPYING" file of the
9055f61bb57d2a625c6434d55beac7565c3b3c0dvboxsync * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
9055f61bb57d2a625c6434d55beac7565c3b3c0dvboxsync * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
9055f61bb57d2a625c6434d55beac7565c3b3c0dvboxsync * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
9055f61bb57d2a625c6434d55beac7565c3b3c0dvboxsync * Clara, CA 95054 USA or visit http://www.sun.com if you need
9055f61bb57d2a625c6434d55beac7565c3b3c0dvboxsync * additional information or have any questions.
9055f61bb57d2a625c6434d55beac7565c3b3c0dvboxsync/*******************************************************************************
9055f61bb57d2a625c6434d55beac7565c3b3c0dvboxsync* Header Files *
9055f61bb57d2a625c6434d55beac7565c3b3c0dvboxsync*******************************************************************************/
73ba84f95f918cc170be38908ad240fbb2f8f354vboxsync/*******************************************************************************
73ba84f95f918cc170be38908ad240fbb2f8f354vboxsync* Structures and Typedefs *
384478d3896257fbce9ceb8c01e74040b969e6d7vboxsync*******************************************************************************/
9055f61bb57d2a625c6434d55beac7565c3b3c0dvboxsynctypedef enum { kAsmStyle_Default, kAsmStyle_yasm, kAsmStyle_masm, kAsmStyle_gas, kAsmStyle_invalid } ASMSTYLE;
9055f61bb57d2a625c6434d55beac7565c3b3c0dvboxsynctypedef enum { kUndefOp_Fail, kUndefOp_All, kUndefOp_DefineByte, kUndefOp_End } UNDEFOPHANDLING;
9055f61bb57d2a625c6434d55beac7565c3b3c0dvboxsynctypedef struct MYDISSTATE
9055f61bb57d2a625c6434d55beac7565c3b3c0dvboxsync uint64_t uAddress; /**< The current instruction address. */
9055f61bb57d2a625c6434d55beac7565c3b3c0dvboxsync uint8_t *pbInstr; /**< The current instruction (pointer). */
9055f61bb57d2a625c6434d55beac7565c3b3c0dvboxsync uint32_t cbInstr; /**< The size of the current instruction. */
9055f61bb57d2a625c6434d55beac7565c3b3c0dvboxsync bool fUndefOp; /**< Whether the current instruction is really an undefined opcode.*/
9055f61bb57d2a625c6434d55beac7565c3b3c0dvboxsync UNDEFOPHANDLING enmUndefOp; /**< How to treat undefined opcodes. */
9055f61bb57d2a625c6434d55beac7565c3b3c0dvboxsync size_t cbLeft; /**< The number of bytes left. (read) */
9055f61bb57d2a625c6434d55beac7565c3b3c0dvboxsync uint64_t uNextAddr; /**< The address of the next byte. (read) */
9055f61bb57d2a625c6434d55beac7565c3b3c0dvboxsync char szLine[256]; /**< The disassembler text output. */
4a9af9a8062589b741444d717d2dd1ed22b0f583vboxsync * Default style.
4a9af9a8062589b741444d717d2dd1ed22b0f583vboxsync * @param pState The disassembler state.
4a9af9a8062589b741444d717d2dd1ed22b0f583vboxsyncstatic void MyDisasDefaultFormatter(PMYDISSTATE pState)
4a9af9a8062589b741444d717d2dd1ed22b0f583vboxsync * Yasm style.
4a9af9a8062589b741444d717d2dd1ed22b0f583vboxsync * @param pState The disassembler state.
4a9af9a8062589b741444d717d2dd1ed22b0f583vboxsyncstatic void MyDisasYasmFormatter(PMYDISSTATE pState)
4a9af9a8062589b741444d717d2dd1ed22b0f583vboxsync /* a very quick hack. */
4a9af9a8062589b741444d717d2dd1ed22b0f583vboxsync strcpy(szTmp, RTStrStripL(strchr(pState->szLine, ':') + 1));
4a9af9a8062589b741444d717d2dd1ed22b0f583vboxsync size_t cch = DISFormatYasmEx(&pState->Cpu, szTmp, sizeof(szTmp),
4a9af9a8062589b741444d717d2dd1ed22b0f583vboxsync DIS_FMT_FLAGS_STRICT | DIS_FMT_FLAGS_ADDR_RIGHT | DIS_FMT_FLAGS_ADDR_COMMENT
4a9af9a8062589b741444d717d2dd1ed22b0f583vboxsync | DIS_FMT_FLAGS_BYTES_RIGHT | DIS_FMT_FLAGS_BYTES_COMMENT | DIS_FMT_FLAGS_BYTES_SPACED,
9055f61bb57d2a625c6434d55beac7565c3b3c0dvboxsync RTPrintf(" %s ; %08llu %s", szTmp, pState->uAddress, pState->szLine);
3a343ca21a267ec3c54e2317e2ed18fe99b8ebbbvboxsync * Checks if the encoding of the current instruction is something
9055f61bb57d2a625c6434d55beac7565c3b3c0dvboxsync * we can never get the assembler to produce.
9055f61bb57d2a625c6434d55beac7565c3b3c0dvboxsync * @returns true if it's odd, false if it isn't.
9055f61bb57d2a625c6434d55beac7565c3b3c0dvboxsync * @param pCpu The disassembler output.
9055f61bb57d2a625c6434d55beac7565c3b3c0dvboxsyncstatic bool MyDisasYasmFormatterIsOddEncoding(PMYDISSTATE pState)
9055f61bb57d2a625c6434d55beac7565c3b3c0dvboxsync * Mod rm + SIB: Check for duplicate EBP encodings that yasm won't use for very good reasons.
9055f61bb57d2a625c6434d55beac7565c3b3c0dvboxsync if ( pState->Cpu.addrmode != CPUMODE_16BIT ///@todo correct?
9055f61bb57d2a625c6434d55beac7565c3b3c0dvboxsync /* No scaled index SIB (index=4), except for ESP. */
9055f61bb57d2a625c6434d55beac7565c3b3c0dvboxsync return true;
9055f61bb57d2a625c6434d55beac7565c3b3c0dvboxsync /* EBP + displacement */
9055f61bb57d2a625c6434d55beac7565c3b3c0dvboxsync return true;
9055f61bb57d2a625c6434d55beac7565c3b3c0dvboxsync * Seems to be an instruction alias here, but I cannot find any docs on it... hrmpf!
9055f61bb57d2a625c6434d55beac7565c3b3c0dvboxsync return true;
9055f61bb57d2a625c6434d55beac7565c3b3c0dvboxsync * Check for multiple prefixes of the same kind.
7b4ea63789001468ec3662bdfcd6432bf89095dfvboxsync case 0x40: case 0x41: case 0x42: case 0x43: case 0x44: case 0x45: case 0x46: case 0x47:
7b4ea63789001468ec3662bdfcd6432bf89095dfvboxsync case 0x48: case 0x49: case 0x4a: case 0x4b: case 0x4c: case 0x4d: case 0x4e: case 0x4f:
7b4ea63789001468ec3662bdfcd6432bf89095dfvboxsync f = pState->Cpu.mode == CPUMODE_64BIT ? PREFIX_REX : 0;
9055f61bb57d2a625c6434d55beac7565c3b3c0dvboxsync break; /* done */
9055f61bb57d2a625c6434d55beac7565c3b3c0dvboxsync return true;
73ba84f95f918cc170be38908ad240fbb2f8f354vboxsync /* segment overrides are fun */
9055f61bb57d2a625c6434d55beac7565c3b3c0dvboxsync /* no effective address which it may apply to. */
9055f61bb57d2a625c6434d55beac7565c3b3c0dvboxsync Assert((pState->Cpu.prefix & PREFIX_SEG) || pState->Cpu.mode == CPUMODE_64BIT);
9055f61bb57d2a625c6434d55beac7565c3b3c0dvboxsync if ( !DIS_IS_EFFECTIVE_ADDR(pState->Cpu.param1.flags)
9055f61bb57d2a625c6434d55beac7565c3b3c0dvboxsync && !DIS_IS_EFFECTIVE_ADDR(pState->Cpu.param2.flags)
9055f61bb57d2a625c6434d55beac7565c3b3c0dvboxsync && !DIS_IS_EFFECTIVE_ADDR(pState->Cpu.param3.flags))
9055f61bb57d2a625c6434d55beac7565c3b3c0dvboxsync return true;
9055f61bb57d2a625c6434d55beac7565c3b3c0dvboxsync /* fixed register + addr override doesn't go down all that well. */
9055f61bb57d2a625c6434d55beac7565c3b3c0dvboxsync && ( pState->Cpu.pCurInstr->param1 >= OP_PARM_REG_GEN32_START
9055f61bb57d2a625c6434d55beac7565c3b3c0dvboxsync && pState->Cpu.pCurInstr->param1 <= OP_PARM_REG_GEN32_END))
9055f61bb57d2a625c6434d55beac7565c3b3c0dvboxsync return true;
9055f61bb57d2a625c6434d55beac7565c3b3c0dvboxsync /* Almost all prefixes are bad. */
9055f61bb57d2a625c6434d55beac7565c3b3c0dvboxsync /* nop w/ prefix(es). */
73ba84f95f918cc170be38908ad240fbb2f8f354vboxsync return true;
73ba84f95f918cc170be38908ad240fbb2f8f354vboxsync /* fall thru */
9055f61bb57d2a625c6434d55beac7565c3b3c0dvboxsync /** @todo branch hinting 0x2e/0x3e... */
9055f61bb57d2a625c6434d55beac7565c3b3c0dvboxsync return true;
9055f61bb57d2a625c6434d55beac7565c3b3c0dvboxsync /* All but the segment prefix is bad news. */
9055f61bb57d2a625c6434d55beac7565c3b3c0dvboxsync if ( pState->Cpu.pCurInstr->param1 >= OP_PARM_REG_SEG_START
9055f61bb57d2a625c6434d55beac7565c3b3c0dvboxsync && pState->Cpu.pCurInstr->param1 <= OP_PARM_REG_SEG_END)
9055f61bb57d2a625c6434d55beac7565c3b3c0dvboxsync return true;
9055f61bb57d2a625c6434d55beac7565c3b3c0dvboxsync && pState->Cpu.pCurInstr->param1 >= OP_PARM_REG_GEN32_START
9055f61bb57d2a625c6434d55beac7565c3b3c0dvboxsync && pState->Cpu.pCurInstr->param1 <= OP_PARM_REG_GEN32_END)
73ba84f95f918cc170be38908ad240fbb2f8f354vboxsync return true;
9055f61bb57d2a625c6434d55beac7565c3b3c0dvboxsync return true;
9055f61bb57d2a625c6434d55beac7565c3b3c0dvboxsync /* Implicit 8-bit register instructions doesn't mix with operand size. */
329df9696e709dc71611f504a4774f323545be0avboxsync && ( ( pState->Cpu.pCurInstr->param1 == OP_PARM_Gb /* r8 */
9055f61bb57d2a625c6434d55beac7565c3b3c0dvboxsync && pState->Cpu.pCurInstr->param2 == OP_PARM_Eb /* r8/mem8 */)
329df9696e709dc71611f504a4774f323545be0avboxsync || ( pState->Cpu.pCurInstr->param2 == OP_PARM_Gb /* r8 */
9055f61bb57d2a625c6434d55beac7565c3b3c0dvboxsync && pState->Cpu.pCurInstr->param1 == OP_PARM_Eb /* r8/mem8 */))
4ecd4ad59281328476ad14f2baa51716b6f5f804vboxsync return true;
4ecd4ad59281328476ad14f2baa51716b6f5f804vboxsync * Check for the version of xyz reg,reg instruction that the assembler doesn't use.
4ecd4ad59281328476ad14f2baa51716b6f5f804vboxsync * For example:
4ecd4ad59281328476ad14f2baa51716b6f5f804vboxsync * expected: 1aee sbb ch, dh ; SBB r8, r/m8
4ecd4ad59281328476ad14f2baa51716b6f5f804vboxsync * yasm: 18F5 sbb ch, dh ; SBB r/m8, r8
329df9696e709dc71611f504a4774f323545be0avboxsync if ( ( pState->Cpu.pCurInstr->param1 == OP_PARM_Gb /* r8 */
329df9696e709dc71611f504a4774f323545be0avboxsync && pState->Cpu.pCurInstr->param2 == OP_PARM_Eb /* r8/mem8 */)
329df9696e709dc71611f504a4774f323545be0avboxsync || ( pState->Cpu.pCurInstr->param1 == OP_PARM_Gv /* rX */
329df9696e709dc71611f504a4774f323545be0avboxsync && pState->Cpu.pCurInstr->param2 == OP_PARM_Ev /* rX/memX */))
329df9696e709dc71611f504a4774f323545be0avboxsync return true;
329df9696e709dc71611f504a4774f323545be0avboxsync /* 82 (see table A-6). */
329df9696e709dc71611f504a4774f323545be0avboxsync return true;
4ecd4ad59281328476ad14f2baa51716b6f5f804vboxsync /* ff /0, fe /0, ff /1, fe /0 */
329df9696e709dc71611f504a4774f323545be0avboxsync return true;
09f4b412099acda62997fd82c8608075c453b3ebvboxsync return true;
09f4b412099acda62997fd82c8608075c453b3ebvboxsync /* shl eax,1 will be assembled to the form without the immediate byte. */
73ba84f95f918cc170be38908ad240fbb2f8f354vboxsync return true;
09f4b412099acda62997fd82c8608075c453b3ebvboxsync /* And some more - see table A-6. */
09f4b412099acda62997fd82c8608075c453b3ebvboxsync return true;
09f4b412099acda62997fd82c8608075c453b3ebvboxsync /* check for REX.X = 1 without SIB. */
09f4b412099acda62997fd82c8608075c453b3ebvboxsync /* Yasm encodes setnbe al with /2 instead of /0 like the AMD manual
09f4b412099acda62997fd82c8608075c453b3ebvboxsync says (intel doesn't appear to care). */
09f4b412099acda62997fd82c8608075c453b3ebvboxsync AssertMsg(pState->Cpu.opcode >= 0x90 && pState->Cpu.opcode <= 0x9f, ("%#x\n", pState->Cpu.opcode));
09f4b412099acda62997fd82c8608075c453b3ebvboxsync return true;
09f4b412099acda62997fd82c8608075c453b3ebvboxsync * The MOVZX reg32,mem16 instruction without an operand size prefix
09f4b412099acda62997fd82c8608075c453b3ebvboxsync * doesn't quite make sense...
9055f61bb57d2a625c6434d55beac7565c3b3c0dvboxsync && (pState->Cpu.mode == CPUMODE_16BIT) != !!(fPrefixes & PREFIX_OPSIZE))
9055f61bb57d2a625c6434d55beac7565c3b3c0dvboxsync return true;
4ecd4ad59281328476ad14f2baa51716b6f5f804vboxsync return false;
9055f61bb57d2a625c6434d55beac7565c3b3c0dvboxsync * Masm style.
9055f61bb57d2a625c6434d55beac7565c3b3c0dvboxsync * @param pState The disassembler state.
9055f61bb57d2a625c6434d55beac7565c3b3c0dvboxsyncstatic void MyDisasMasmFormatter(PMYDISSTATE pState)
dc959f60f6d3e0cba86f7da4d39aa475913a7e10vboxsync RTPrintf("masm not implemented: %s", pState->szLine);
9055f61bb57d2a625c6434d55beac7565c3b3c0dvboxsync * This is a temporary workaround for catching a few illegal opcodes
9055f61bb57d2a625c6434d55beac7565c3b3c0dvboxsync * that the disassembler is currently letting thru, just enough to make
9055f61bb57d2a625c6434d55beac7565c3b3c0dvboxsync * the assemblers happy.
9055f61bb57d2a625c6434d55beac7565c3b3c0dvboxsync * We're too close to a release to dare mess with these things now as
9055f61bb57d2a625c6434d55beac7565c3b3c0dvboxsync * they may consequences for performance and let alone introduce bugs.
9055f61bb57d2a625c6434d55beac7565c3b3c0dvboxsync * @returns true if it's valid. false if it isn't.
9055f61bb57d2a625c6434d55beac7565c3b3c0dvboxsync * @param pCpu The disassembler output.
9055f61bb57d2a625c6434d55beac7565c3b3c0dvboxsyncstatic bool MyDisasIsValidInstruction(DISCPUSTATE const *pCpu)
dc959f60f6d3e0cba86f7da4d39aa475913a7e10vboxsync /* These doesn't take memory operands. */
9055f61bb57d2a625c6434d55beac7565c3b3c0dvboxsync return false;
340ee06f35257fee1bd68223ab3504cf2b1d0c3evboxsync /* The 0x8f /0 variant of this instruction doesn't get its /r value verified. */
340ee06f35257fee1bd68223ab3504cf2b1d0c3evboxsync return false;
340ee06f35257fee1bd68223ab3504cf2b1d0c3evboxsync /* The 0xc6 /0 and 0xc7 /0 variants of this instruction don't get their /r values verified. */
340ee06f35257fee1bd68223ab3504cf2b1d0c3evboxsync return false;
340ee06f35257fee1bd68223ab3504cf2b1d0c3evboxsync return true;
340ee06f35257fee1bd68223ab3504cf2b1d0c3evboxsync * Callback for reading bytes.
340ee06f35257fee1bd68223ab3504cf2b1d0c3evboxsync * @todo This should check that the disassembler doesn't do unnecessary reads,
340ee06f35257fee1bd68223ab3504cf2b1d0c3evboxsync * however the current doesn't do this and is just complicated...
340ee06f35257fee1bd68223ab3504cf2b1d0c3evboxsyncstatic DECLCALLBACK(int) MyDisasInstrRead(RTUINTPTR uSrcAddr, uint8_t *pbDst, uint32_t cbRead, void *pvDisCpu)
340ee06f35257fee1bd68223ab3504cf2b1d0c3evboxsync * Straight forward reading.
340ee06f35257fee1bd68223ab3504cf2b1d0c3evboxsync * Jumping up the stream.
340ee06f35257fee1bd68223ab3504cf2b1d0c3evboxsync * This occures when the byte sequence is added to the output string.
07b405d3b41cfce6f5f989a6c95a5819af3841a1vboxsync /* reset the stream. */
340ee06f35257fee1bd68223ab3504cf2b1d0c3evboxsync /* skip ahead. */
340ee06f35257fee1bd68223ab3504cf2b1d0c3evboxsync /* do the reading. */
340ee06f35257fee1bd68223ab3504cf2b1d0c3evboxsync RTStrmPrintf(g_pStdErr, "Reading before current instruction!\n");
1ff34f218a5354068e4df9017f77fc5871e6b7c6vboxsync * Disassembles a block of memory.
1ff34f218a5354068e4df9017f77fc5871e6b7c6vboxsync * @returns VBox status code.
1ff34f218a5354068e4df9017f77fc5871e6b7c6vboxsync * @param argv0 Program name (for errors and warnings).
1ff34f218a5354068e4df9017f77fc5871e6b7c6vboxsync * @param enmCpuMode The cpu mode to disassemble in.
1ff34f218a5354068e4df9017f77fc5871e6b7c6vboxsync * @param uAddress The address we're starting to disassemble at.
1ff34f218a5354068e4df9017f77fc5871e6b7c6vboxsync * @param pbFile Where to start disassemble.
1ff34f218a5354068e4df9017f77fc5871e6b7c6vboxsync * @param cbFile How much to disassemble.
1ff34f218a5354068e4df9017f77fc5871e6b7c6vboxsync * @param enmStyle The assembly output style.
1ff34f218a5354068e4df9017f77fc5871e6b7c6vboxsync * @param fListing Whether to print in a listing like mode.
1ff34f218a5354068e4df9017f77fc5871e6b7c6vboxsync * @param enmUndefOp How to deal with undefined opcodes.
1ff34f218a5354068e4df9017f77fc5871e6b7c6vboxsyncstatic int MyDisasmBlock(const char *argv0, DISCPUMODE enmCpuMode, uint64_t uAddress, uint8_t *pbFile, size_t cbFile,
1ff34f218a5354068e4df9017f77fc5871e6b7c6vboxsync ASMSTYLE enmStyle, bool fListing, UNDEFOPHANDLING enmUndefOp)
340ee06f35257fee1bd68223ab3504cf2b1d0c3evboxsync * Initialize the CPU context.
340ee06f35257fee1bd68223ab3504cf2b1d0c3evboxsync RTPrintf(" BITS %d\n", enmCpuMode == CPUMODE_16BIT ? 16 : enmCpuMode == CPUMODE_32BIT ? 32 : 64);
340ee06f35257fee1bd68223ab3504cf2b1d0c3evboxsync * The loop.
340ee06f35257fee1bd68223ab3504cf2b1d0c3evboxsync * Disassemble it.
340ee06f35257fee1bd68223ab3504cf2b1d0c3evboxsync int rc = DISInstr(&State.Cpu, State.uAddress, 0, &State.cbInstr, State.szLine);
340ee06f35257fee1bd68223ab3504cf2b1d0c3evboxsync if (State.fUndefOp && State.enmUndefOp == kUndefOp_DefineByte)
1ff34f218a5354068e4df9017f77fc5871e6b7c6vboxsync State.Cpu.pfnReadBytes(State.uAddress + off, &b, 1, &State.Cpu);
1ff34f218a5354068e4df9017f77fc5871e6b7c6vboxsync else if (!State.fUndefOp && State.enmUndefOp == kUndefOp_All)
1ff34f218a5354068e4df9017f77fc5871e6b7c6vboxsync RTPrintf("%s: error at %#RX64: unexpected valid instruction (op=%d)\n", argv0, State.uAddress, State.Cpu.pCurInstr->opcode);
1ff34f218a5354068e4df9017f77fc5871e6b7c6vboxsync else if (State.fUndefOp && State.enmUndefOp == kUndefOp_Fail)
340ee06f35257fee1bd68223ab3504cf2b1d0c3evboxsync RTPrintf("%s: error at %#RX64: undefined opcode (op=%d)\n", argv0, State.uAddress, State.Cpu.pCurInstr->opcode);
340ee06f35257fee1bd68223ab3504cf2b1d0c3evboxsync /* Use db for odd encodings that we can't make the assembler use. */
07b405d3b41cfce6f5f989a6c95a5819af3841a1vboxsync State.Cpu.pfnReadBytes(State.uAddress + off, &b, 1, &State.Cpu);
340ee06f35257fee1bd68223ab3504cf2b1d0c3evboxsync RTPrintf("%s: error at %#RX64: read beyond the end (%Rrc)\n", argv0, State.uAddress, rc);
c7d2f5508ab9703a7a6c5cce5c9d4bf335af660avboxsync RTPrintf("%s: error at %#RX64: %Rrc cbInstr=%d\n", argv0, State.uAddress, rc, State.cbInstr);
c7d2f5508ab9703a7a6c5cce5c9d4bf335af660avboxsync RTPrintf("%s: error at %#RX64: %Rrc cbInstr=%d!\n", argv0, State.uAddress, rc, State.cbInstr);
340ee06f35257fee1bd68223ab3504cf2b1d0c3evboxsync * Prints usage info.
340ee06f35257fee1bd68223ab3504cf2b1d0c3evboxsync * @returns 1.
340ee06f35257fee1bd68223ab3504cf2b1d0c3evboxsync * @param argv0 The program name.
340ee06f35257fee1bd68223ab3504cf2b1d0c3evboxsync"usage: %s [options] <file1> [file2..fileN]\n"
340ee06f35257fee1bd68223ab3504cf2b1d0c3evboxsync" or: %s <--help|-h>\n"
340ee06f35257fee1bd68223ab3504cf2b1d0c3evboxsync"Options:\n"
340ee06f35257fee1bd68223ab3504cf2b1d0c3evboxsync" --address|-a <address>\n"
340ee06f35257fee1bd68223ab3504cf2b1d0c3evboxsync" The base address. Default: 0\n"
340ee06f35257fee1bd68223ab3504cf2b1d0c3evboxsync" --max-bytes|-b <bytes>\n"
340ee06f35257fee1bd68223ab3504cf2b1d0c3evboxsync" The maximum number of bytes to disassemble. Default: 1GB\n"
340ee06f35257fee1bd68223ab3504cf2b1d0c3evboxsync" --cpumode|-c <16|32|64>\n"
340ee06f35257fee1bd68223ab3504cf2b1d0c3evboxsync" The cpu mode. Default: 32\n"
340ee06f35257fee1bd68223ab3504cf2b1d0c3evboxsync" --listing|-l, --no-listing|-L\n"
340ee06f35257fee1bd68223ab3504cf2b1d0c3evboxsync" Enables or disables listing mode. Default: --no-listing\n"
340ee06f35257fee1bd68223ab3504cf2b1d0c3evboxsync" --offset|-o <offset>\n"
340ee06f35257fee1bd68223ab3504cf2b1d0c3evboxsync" The file offset at which to start disassembling. Default: 0\n"
340ee06f35257fee1bd68223ab3504cf2b1d0c3evboxsync" --style|-s <default|yasm|masm>\n"
340ee06f35257fee1bd68223ab3504cf2b1d0c3evboxsync" The assembly output style. Default: default\n"
340ee06f35257fee1bd68223ab3504cf2b1d0c3evboxsync" --undef-op|-u <fail|all|db>\n"
340ee06f35257fee1bd68223ab3504cf2b1d0c3evboxsync" How to treat undefined opcodes. Default: fail\n"
340ee06f35257fee1bd68223ab3504cf2b1d0c3evboxsync const char * const argv0 = RTPathFilename(argv[0]);
340ee06f35257fee1bd68223ab3504cf2b1d0c3evboxsync /* options */
340ee06f35257fee1bd68223ab3504cf2b1d0c3evboxsync bool fListing = true;
340ee06f35257fee1bd68223ab3504cf2b1d0c3evboxsync * Parse arguments.
9055f61bb57d2a625c6434d55beac7565c3b3c0dvboxsync while ((ch = RTGetOpt(argc, argv, g_aOptions, RT_ELEMENTS(g_aOptions), &iArg, &ValueUnion)))
4c98b8b05f3783351cf256cc90cd4478fb28b62bvboxsync RTStrmPrintf(g_pStdErr, "%s: Invalid CPU mode value %RU32\n", argv0, ValueUnion.u32);
9055f61bb57d2a625c6434d55beac7565c3b3c0dvboxsync RTStrmPrintf(g_pStdErr, "%s: masm style isn't implemented yet\n", argv0);
9055f61bb57d2a625c6434d55beac7565c3b3c0dvboxsync RTStrmPrintf(g_pStdErr, "%s: unknown assembly style: %s\n", argv0, ValueUnion.psz);
9055f61bb57d2a625c6434d55beac7565c3b3c0dvboxsync RTStrmPrintf(g_pStdErr, "%s: unknown undefined opcode handling method: %s\n", argv0, ValueUnion.psz);
9055f61bb57d2a625c6434d55beac7565c3b3c0dvboxsync RTStrmPrintf(g_pStdErr, "%s: syntax error: %Rrc\n", argv0, ch);
9055f61bb57d2a625c6434d55beac7565c3b3c0dvboxsync * Process the files.
9055f61bb57d2a625c6434d55beac7565c3b3c0dvboxsync * Read the file into memory.
9055f61bb57d2a625c6434d55beac7565c3b3c0dvboxsync rc = RTFileReadAllEx(argv[iArg], off, cbMax, 0, &pvFile, &cbFile);
9055f61bb57d2a625c6434d55beac7565c3b3c0dvboxsync RTStrmPrintf(g_pStdErr, "%s: %s: %Rrc\n", argv0, argv[iArg], rc);
9055f61bb57d2a625c6434d55beac7565c3b3c0dvboxsync * Disassemble it.