tstDisasm-2.cpp revision 87bcc85487fed8c2c8141050ac5ca55640713cd4
7bf0220c3332700233120b513c9b4ba20a0caa9bvboxsync * Testcase - Generic Disassembler Tool.
7bf0220c3332700233120b513c9b4ba20a0caa9bvboxsync * Copyright (C) 2008 Sun Microsystems, Inc.
7bf0220c3332700233120b513c9b4ba20a0caa9bvboxsync * This file is part of VirtualBox Open Source Edition (OSE), as
7bf0220c3332700233120b513c9b4ba20a0caa9bvboxsync * available from http://www.virtualbox.org. This file is free software;
7bf0220c3332700233120b513c9b4ba20a0caa9bvboxsync * you can redistribute it and/or modify it under the terms of the GNU
7bf0220c3332700233120b513c9b4ba20a0caa9bvboxsync * General Public License (GPL) as published by the Free Software
7bf0220c3332700233120b513c9b4ba20a0caa9bvboxsync * Foundation, in version 2 as it comes in the "COPYING" file of the
7bf0220c3332700233120b513c9b4ba20a0caa9bvboxsync * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
7bf0220c3332700233120b513c9b4ba20a0caa9bvboxsync * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
7bf0220c3332700233120b513c9b4ba20a0caa9bvboxsync * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
7bf0220c3332700233120b513c9b4ba20a0caa9bvboxsync * Clara, CA 95054 USA or visit http://www.sun.com if you need
7bf0220c3332700233120b513c9b4ba20a0caa9bvboxsync * additional information or have any questions.
7bf0220c3332700233120b513c9b4ba20a0caa9bvboxsync/*******************************************************************************
7bf0220c3332700233120b513c9b4ba20a0caa9bvboxsync* Header Files *
7bf0220c3332700233120b513c9b4ba20a0caa9bvboxsync*******************************************************************************/
7bf0220c3332700233120b513c9b4ba20a0caa9bvboxsync/*******************************************************************************
7bf0220c3332700233120b513c9b4ba20a0caa9bvboxsync* Structures and Typedefs *
7bf0220c3332700233120b513c9b4ba20a0caa9bvboxsync*******************************************************************************/
8599686860198730ae53d5895386d1b57dbc060evboxsynctypedef enum { kAsmStyle_Default, kAsmStyle_yasm, kAsmStyle_masm, kAsmStyle_gas, kAsmStyle_invalid } ASMSTYLE;
7748b9362d6a39df9045d5d05ccb57871145a649vboxsynctypedef enum { kUndefOp_Fail, kUndefOp_All, kUndefOp_DefineByte, kUndefOp_End } UNDEFOPHANDLING;
7bf0220c3332700233120b513c9b4ba20a0caa9bvboxsynctypedef struct MYDISSTATE
7bf0220c3332700233120b513c9b4ba20a0caa9bvboxsync uint64_t uAddress; /**< The current instruction address. */
7bf0220c3332700233120b513c9b4ba20a0caa9bvboxsync uint8_t *pbInstr; /**< The current instruction (pointer). */
7bf0220c3332700233120b513c9b4ba20a0caa9bvboxsync uint32_t cbInstr; /**< The size of the current instruction. */
7748b9362d6a39df9045d5d05ccb57871145a649vboxsync bool fUndefOp; /**< Whether the current instruction is really an undefined opcode.*/
7748b9362d6a39df9045d5d05ccb57871145a649vboxsync UNDEFOPHANDLING enmUndefOp; /**< How to treat undefined opcodes. */
7bf0220c3332700233120b513c9b4ba20a0caa9bvboxsync size_t cbLeft; /**< The number of bytes left. (read) */
7bf0220c3332700233120b513c9b4ba20a0caa9bvboxsync uint64_t uNextAddr; /**< The address of the next byte. (read) */
7bf0220c3332700233120b513c9b4ba20a0caa9bvboxsync char szLine[256]; /**< The disassembler text output. */
7bf0220c3332700233120b513c9b4ba20a0caa9bvboxsync * Default style.
7bf0220c3332700233120b513c9b4ba20a0caa9bvboxsync * @param pState The disassembler state.
7bf0220c3332700233120b513c9b4ba20a0caa9bvboxsyncstatic void MyDisasDefaultFormatter(PMYDISSTATE pState)
7bf0220c3332700233120b513c9b4ba20a0caa9bvboxsync * Yasm style.
7bf0220c3332700233120b513c9b4ba20a0caa9bvboxsync * @param pState The disassembler state.
7bf0220c3332700233120b513c9b4ba20a0caa9bvboxsyncstatic void MyDisasYasmFormatter(PMYDISSTATE pState)
8599686860198730ae53d5895386d1b57dbc060evboxsync /* a very quick hack. */
8fa1e8a8a8702ee38195fbe7ad5959bf971eb93bvboxsync strcpy(szTmp, RTStrStripL(strchr(pState->szLine, ':') + 1));
de6ba1989c812829372828f1801b232b3e7f09bfvboxsync size_t cch = DISFormatYasmEx(&pState->Cpu, szTmp, sizeof(szTmp),
92473d1de9ab080ff886ad61a4d908f7c3429608vboxsync DIS_FMT_FLAGS_STRICT | DIS_FMT_FLAGS_ADDR_RIGHT | DIS_FMT_FLAGS_ADDR_COMMENT
de6ba1989c812829372828f1801b232b3e7f09bfvboxsync | DIS_FMT_FLAGS_BYTES_RIGHT | DIS_FMT_FLAGS_BYTES_COMMENT | DIS_FMT_FLAGS_BYTES_SPACED,
8599686860198730ae53d5895386d1b57dbc060evboxsync RTPrintf(" %s ; %08llu %s", szTmp, pState->uAddress, pState->szLine);
8599686860198730ae53d5895386d1b57dbc060evboxsync * Checks if the encoding of the current instruction is something
8599686860198730ae53d5895386d1b57dbc060evboxsync * we can never get the assembler to produce.
8599686860198730ae53d5895386d1b57dbc060evboxsync * @returns true if it's odd, false if it isn't.
8599686860198730ae53d5895386d1b57dbc060evboxsync * @param pCpu The disassembler output.
8599686860198730ae53d5895386d1b57dbc060evboxsyncstatic bool MyDisasYasmFormatterIsOddEncoding(PMYDISSTATE pState)
8599686860198730ae53d5895386d1b57dbc060evboxsync * Mod rm + SIB: Check for duplicate EBP encodings that yasm won't use for very good reasons.
8599686860198730ae53d5895386d1b57dbc060evboxsync if ( pState->Cpu.addrmode != CPUMODE_16BIT ///@todo correct?
8599686860198730ae53d5895386d1b57dbc060evboxsync /* No scaled index SIB (index=4), except for ESP. */
8599686860198730ae53d5895386d1b57dbc060evboxsync return true;
8599686860198730ae53d5895386d1b57dbc060evboxsync /* EBP + displacement */
8599686860198730ae53d5895386d1b57dbc060evboxsync return true;
8599686860198730ae53d5895386d1b57dbc060evboxsync * Seems to be an instruction alias here, but I cannot find any docs on it... hrmpf!
8599686860198730ae53d5895386d1b57dbc060evboxsync return true;
8599686860198730ae53d5895386d1b57dbc060evboxsync * Check for multiple prefixes of the same kind.
8599686860198730ae53d5895386d1b57dbc060evboxsync case 0x40: case 0x41: case 0x42: case 0x43: case 0x44: case 0x45: case 0x46: case 0x47:
8599686860198730ae53d5895386d1b57dbc060evboxsync case 0x48: case 0x49: case 0x4a: case 0x4b: case 0x4c: case 0x4d: case 0x4e: case 0x4f:
2cae8ff5782536dc236e1161d351356ba2ac5e0fvboxsync f = pState->Cpu.mode == CPUMODE_64BIT ? PREFIX_REX : 0;
8599686860198730ae53d5895386d1b57dbc060evboxsync break; /* done */
8599686860198730ae53d5895386d1b57dbc060evboxsync return true;
8599686860198730ae53d5895386d1b57dbc060evboxsync /* segment overrides are fun */
43d3ae55ce9429027a4b71e78ba39bf930433bd3vboxsync /* no effective address which it may apply to. */
8599686860198730ae53d5895386d1b57dbc060evboxsync Assert((pState->Cpu.prefix & PREFIX_SEG) || pState->Cpu.mode == CPUMODE_64BIT);
43d3ae55ce9429027a4b71e78ba39bf930433bd3vboxsync if ( !DIS_IS_EFFECTIVE_ADDR(pState->Cpu.param1.flags)
43d3ae55ce9429027a4b71e78ba39bf930433bd3vboxsync && !DIS_IS_EFFECTIVE_ADDR(pState->Cpu.param2.flags)
43d3ae55ce9429027a4b71e78ba39bf930433bd3vboxsync && !DIS_IS_EFFECTIVE_ADDR(pState->Cpu.param3.flags))
8599686860198730ae53d5895386d1b57dbc060evboxsync return true;
8599686860198730ae53d5895386d1b57dbc060evboxsync /* fixed register + addr override doesn't go down all that well. */
8599686860198730ae53d5895386d1b57dbc060evboxsync && ( pState->Cpu.pCurInstr->param1 >= OP_PARM_REG_GEN32_START
8599686860198730ae53d5895386d1b57dbc060evboxsync && pState->Cpu.pCurInstr->param1 <= OP_PARM_REG_GEN32_END))
8599686860198730ae53d5895386d1b57dbc060evboxsync return true;
b9609c7ffe24b4438bca69c315a3d280decd83d1vboxsync /* Almost all prefixes are bad. */
b9609c7ffe24b4438bca69c315a3d280decd83d1vboxsync /* nop w/ prefix(es). */
b9609c7ffe24b4438bca69c315a3d280decd83d1vboxsync return true;
b9609c7ffe24b4438bca69c315a3d280decd83d1vboxsync /* fall thru */
b9609c7ffe24b4438bca69c315a3d280decd83d1vboxsync /** @todo branch hinting 0x2e/0x3e... */
b9609c7ffe24b4438bca69c315a3d280decd83d1vboxsync return true;
b9609c7ffe24b4438bca69c315a3d280decd83d1vboxsync /* All but the segment prefix is bad news. */
2cae8ff5782536dc236e1161d351356ba2ac5e0fvboxsync if ( pState->Cpu.pCurInstr->param1 >= OP_PARM_REG_SEG_START
2cae8ff5782536dc236e1161d351356ba2ac5e0fvboxsync && pState->Cpu.pCurInstr->param1 <= OP_PARM_REG_SEG_END)
2cae8ff5782536dc236e1161d351356ba2ac5e0fvboxsync return true;
2cae8ff5782536dc236e1161d351356ba2ac5e0fvboxsync && pState->Cpu.pCurInstr->param1 >= OP_PARM_REG_GEN32_START
2cae8ff5782536dc236e1161d351356ba2ac5e0fvboxsync && pState->Cpu.pCurInstr->param1 <= OP_PARM_REG_GEN32_END)
2cae8ff5782536dc236e1161d351356ba2ac5e0fvboxsync return true;
2cae8ff5782536dc236e1161d351356ba2ac5e0fvboxsync return true;
b9609c7ffe24b4438bca69c315a3d280decd83d1vboxsync /* Implicit 8-bit register instructions doesn't mix with operand size. */
b9609c7ffe24b4438bca69c315a3d280decd83d1vboxsync && ( ( pState->Cpu.pCurInstr->param1 == OP_PARM_Gb /* r8 */
b9609c7ffe24b4438bca69c315a3d280decd83d1vboxsync && pState->Cpu.pCurInstr->param2 == OP_PARM_Eb /* r8/mem8 */)
b9609c7ffe24b4438bca69c315a3d280decd83d1vboxsync || ( pState->Cpu.pCurInstr->param2 == OP_PARM_Gb /* r8 */
b9609c7ffe24b4438bca69c315a3d280decd83d1vboxsync && pState->Cpu.pCurInstr->param1 == OP_PARM_Eb /* r8/mem8 */))
b9609c7ffe24b4438bca69c315a3d280decd83d1vboxsync return true;
b9609c7ffe24b4438bca69c315a3d280decd83d1vboxsync * Check for the version of xyz reg,reg instruction that the assembler doesn't use.
b9609c7ffe24b4438bca69c315a3d280decd83d1vboxsync * For example:
b9609c7ffe24b4438bca69c315a3d280decd83d1vboxsync * expected: 1aee sbb ch, dh ; SBB r8, r/m8
b9609c7ffe24b4438bca69c315a3d280decd83d1vboxsync * yasm: 18F5 sbb ch, dh ; SBB r/m8, r8
8599686860198730ae53d5895386d1b57dbc060evboxsync if ( ( pState->Cpu.pCurInstr->param1 == OP_PARM_Gb /* r8 */
8599686860198730ae53d5895386d1b57dbc060evboxsync && pState->Cpu.pCurInstr->param2 == OP_PARM_Eb /* r8/mem8 */)
8599686860198730ae53d5895386d1b57dbc060evboxsync || ( pState->Cpu.pCurInstr->param1 == OP_PARM_Gv /* rX */
8599686860198730ae53d5895386d1b57dbc060evboxsync && pState->Cpu.pCurInstr->param2 == OP_PARM_Ev /* rX/memX */))
8599686860198730ae53d5895386d1b57dbc060evboxsync return true;
2cae8ff5782536dc236e1161d351356ba2ac5e0fvboxsync /* 82 (see table A-6). */
2cae8ff5782536dc236e1161d351356ba2ac5e0fvboxsync return true;
8599686860198730ae53d5895386d1b57dbc060evboxsync /* ff /0, fe /0, ff /1, fe /0 */
8599686860198730ae53d5895386d1b57dbc060evboxsync return true;
2cae8ff5782536dc236e1161d351356ba2ac5e0fvboxsync return true;
b9609c7ffe24b4438bca69c315a3d280decd83d1vboxsync /* shl eax,1 will be assembled to the form without the immediate byte. */
b9609c7ffe24b4438bca69c315a3d280decd83d1vboxsync return true;
2cae8ff5782536dc236e1161d351356ba2ac5e0fvboxsync /* And some more - see table A-6. */
2cae8ff5782536dc236e1161d351356ba2ac5e0fvboxsync return true;
8599686860198730ae53d5895386d1b57dbc060evboxsync /* check for REX.X = 1 without SIB. */
8599686860198730ae53d5895386d1b57dbc060evboxsync /* Yasm encodes setnbe al with /2 instead of /0 like the AMD manual
8599686860198730ae53d5895386d1b57dbc060evboxsync says (intel doesn't appear to care). */
8599686860198730ae53d5895386d1b57dbc060evboxsync AssertMsg(pState->Cpu.opcode >= 0x90 && pState->Cpu.opcode <= 0x9f, ("%#x\n", pState->Cpu.opcode));
8599686860198730ae53d5895386d1b57dbc060evboxsync return true;
2cae8ff5782536dc236e1161d351356ba2ac5e0fvboxsync * The MOVZX reg32,mem16 instruction without an operand size prefix
2cae8ff5782536dc236e1161d351356ba2ac5e0fvboxsync * doesn't quite make sense...
2cae8ff5782536dc236e1161d351356ba2ac5e0fvboxsync && (pState->Cpu.mode == CPUMODE_16BIT) != !!(fPrefixes & PREFIX_OPSIZE))
2cae8ff5782536dc236e1161d351356ba2ac5e0fvboxsync return true;
8599686860198730ae53d5895386d1b57dbc060evboxsync return false;
7bf0220c3332700233120b513c9b4ba20a0caa9bvboxsync * Masm style.
7bf0220c3332700233120b513c9b4ba20a0caa9bvboxsync * @param pState The disassembler state.
7bf0220c3332700233120b513c9b4ba20a0caa9bvboxsyncstatic void MyDisasMasmFormatter(PMYDISSTATE pState)
7bf0220c3332700233120b513c9b4ba20a0caa9bvboxsync RTPrintf("masm not implemented: %s", pState->szLine);
8599686860198730ae53d5895386d1b57dbc060evboxsync * This is a temporary workaround for catching a few illegal opcodes
8599686860198730ae53d5895386d1b57dbc060evboxsync * that the disassembler is currently letting thru, just enough to make
8599686860198730ae53d5895386d1b57dbc060evboxsync * the assemblers happy.
8599686860198730ae53d5895386d1b57dbc060evboxsync * We're too close to a release to dare mess with these things now as
8599686860198730ae53d5895386d1b57dbc060evboxsync * they may consequences for performance and let alone introduce bugs.
8599686860198730ae53d5895386d1b57dbc060evboxsync * @returns true if it's valid. false if it isn't.
8599686860198730ae53d5895386d1b57dbc060evboxsync * @param pCpu The disassembler output.
8599686860198730ae53d5895386d1b57dbc060evboxsyncstatic bool MyDisasIsValidInstruction(DISCPUSTATE const *pCpu)
8599686860198730ae53d5895386d1b57dbc060evboxsync /* These doesn't take memory operands. */
8599686860198730ae53d5895386d1b57dbc060evboxsync return false;
8599686860198730ae53d5895386d1b57dbc060evboxsync /* The 0x8f /0 variant of this instruction doesn't get its /r value verified. */
8599686860198730ae53d5895386d1b57dbc060evboxsync return false;
8599686860198730ae53d5895386d1b57dbc060evboxsync /* The 0xc6 /0 and 0xc7 /0 variants of this instruction don't get their /r values verified. */
8599686860198730ae53d5895386d1b57dbc060evboxsync return false;
8599686860198730ae53d5895386d1b57dbc060evboxsync return true;
7bf0220c3332700233120b513c9b4ba20a0caa9bvboxsync * Callback for reading bytes.
8599686860198730ae53d5895386d1b57dbc060evboxsync * @todo This should check that the disassembler doesn't do unnecessary reads,
8599686860198730ae53d5895386d1b57dbc060evboxsync * however the current doesn't do this and is just complicated...
7bf0220c3332700233120b513c9b4ba20a0caa9bvboxsyncstatic DECLCALLBACK(int) MyDisasInstrRead(RTUINTPTR uSrcAddr, uint8_t *pbDst, uint32_t cbRead, void *pvDisCpu)
7bf0220c3332700233120b513c9b4ba20a0caa9bvboxsync * Straight forward reading.
7bf0220c3332700233120b513c9b4ba20a0caa9bvboxsync * Jumping up the stream.
7748b9362d6a39df9045d5d05ccb57871145a649vboxsync * This occures when the byte sequence is added to the output string.
7bf0220c3332700233120b513c9b4ba20a0caa9bvboxsync /* reset the stream. */
7bf0220c3332700233120b513c9b4ba20a0caa9bvboxsync /* skip ahead. */
7bf0220c3332700233120b513c9b4ba20a0caa9bvboxsync /* do the reading. */
7bf0220c3332700233120b513c9b4ba20a0caa9bvboxsync RTStrmPrintf(g_pStdErr, "Reading before current instruction!\n");
7bf0220c3332700233120b513c9b4ba20a0caa9bvboxsync * Disassembles a block of memory.
7bf0220c3332700233120b513c9b4ba20a0caa9bvboxsync * @returns VBox status code.
7bf0220c3332700233120b513c9b4ba20a0caa9bvboxsync * @param argv0 Program name (for errors and warnings).
7bf0220c3332700233120b513c9b4ba20a0caa9bvboxsync * @param enmCpuMode The cpu mode to disassemble in.
7bf0220c3332700233120b513c9b4ba20a0caa9bvboxsync * @param uAddress The address we're starting to disassemble at.
7bf0220c3332700233120b513c9b4ba20a0caa9bvboxsync * @param pbFile Where to start disassemble.
7bf0220c3332700233120b513c9b4ba20a0caa9bvboxsync * @param cbFile How much to disassemble.
7bf0220c3332700233120b513c9b4ba20a0caa9bvboxsync * @param enmStyle The assembly output style.
7bf0220c3332700233120b513c9b4ba20a0caa9bvboxsync * @param fListing Whether to print in a listing like mode.
7748b9362d6a39df9045d5d05ccb57871145a649vboxsync * @param enmUndefOp How to deal with undefined opcodes.
7bf0220c3332700233120b513c9b4ba20a0caa9bvboxsyncstatic int MyDisasmBlock(const char *argv0, DISCPUMODE enmCpuMode, uint64_t uAddress, uint8_t *pbFile, size_t cbFile,
7748b9362d6a39df9045d5d05ccb57871145a649vboxsync ASMSTYLE enmStyle, bool fListing, UNDEFOPHANDLING enmUndefOp)
7bf0220c3332700233120b513c9b4ba20a0caa9bvboxsync * Initialize the CPU context.
8fa1e8a8a8702ee38195fbe7ad5959bf971eb93bvboxsync RTPrintf(" BITS %d\n", enmCpuMode == CPUMODE_16BIT ? 16 : enmCpuMode == CPUMODE_32BIT ? 32 : 64);
7bf0220c3332700233120b513c9b4ba20a0caa9bvboxsync * The loop.
7bf0220c3332700233120b513c9b4ba20a0caa9bvboxsync * Disassemble it.
7bf0220c3332700233120b513c9b4ba20a0caa9bvboxsync int rc = DISInstr(&State.Cpu, State.uAddress, 0, &State.cbInstr, State.szLine);
8599686860198730ae53d5895386d1b57dbc060evboxsync if (State.fUndefOp && State.enmUndefOp == kUndefOp_DefineByte)
8599686860198730ae53d5895386d1b57dbc060evboxsync State.Cpu.pfnReadBytes(State.uAddress + off, &b, 1, &State.Cpu);
8599686860198730ae53d5895386d1b57dbc060evboxsync else if (!State.fUndefOp && State.enmUndefOp == kUndefOp_All)
8fa1e8a8a8702ee38195fbe7ad5959bf971eb93bvboxsync RTPrintf("%s: error at %#RX64: unexpected valid instruction (op=%d)\n", argv0, State.uAddress, State.Cpu.pCurInstr->opcode);
7748b9362d6a39df9045d5d05ccb57871145a649vboxsync else if (State.fUndefOp && State.enmUndefOp == kUndefOp_Fail)
7748b9362d6a39df9045d5d05ccb57871145a649vboxsync RTPrintf("%s: error at %#RX64: undefined opcode (op=%d)\n", argv0, State.uAddress, State.Cpu.pCurInstr->opcode);
8599686860198730ae53d5895386d1b57dbc060evboxsync /* Use db for odd encodings that we can't make the assembler use. */
8599686860198730ae53d5895386d1b57dbc060evboxsync State.Cpu.pfnReadBytes(State.uAddress + off, &b, 1, &State.Cpu);
7bf0220c3332700233120b513c9b4ba20a0caa9bvboxsync RTPrintf("%s: error at %#RX64: read beyond the end (%Rrc)\n", argv0, State.uAddress, rc);
7bf0220c3332700233120b513c9b4ba20a0caa9bvboxsync RTPrintf("%s: error at %#RX64: %Rrc cbInstr=%d\n", argv0, State.uAddress, rc, State.cbInstr);
7bf0220c3332700233120b513c9b4ba20a0caa9bvboxsync RTPrintf("%s: error at %#RX64: %Rrc cbInstr=%d!\n", argv0, State.uAddress, rc, State.cbInstr);
57a94b9fea6a6400f7a80e322e84b5b453c3bff0vboxsync * Converts a hex char to a number.
57a94b9fea6a6400f7a80e322e84b5b453c3bff0vboxsync * @returns 0..15 on success, -1 on failure.
57a94b9fea6a6400f7a80e322e84b5b453c3bff0vboxsync * @param ch The character.
57a94b9fea6a6400f7a80e322e84b5b453c3bff0vboxsync case '0': return 0;
7bf0220c3332700233120b513c9b4ba20a0caa9bvboxsync * Prints usage info.
7bf0220c3332700233120b513c9b4ba20a0caa9bvboxsync * @returns 1.
7bf0220c3332700233120b513c9b4ba20a0caa9bvboxsync * @param argv0 The program name.
7bf0220c3332700233120b513c9b4ba20a0caa9bvboxsync"usage: %s [options] <file1> [file2..fileN]\n"
57a94b9fea6a6400f7a80e322e84b5b453c3bff0vboxsync" or: %s [options] <-x|--hex-bytes> <hex byte> [more hex..]\n"
7bf0220c3332700233120b513c9b4ba20a0caa9bvboxsync" or: %s <--help|-h>\n"
7bf0220c3332700233120b513c9b4ba20a0caa9bvboxsync"Options:\n"
7bf0220c3332700233120b513c9b4ba20a0caa9bvboxsync" --address|-a <address>\n"
7bf0220c3332700233120b513c9b4ba20a0caa9bvboxsync" The base address. Default: 0\n"
7bf0220c3332700233120b513c9b4ba20a0caa9bvboxsync" --max-bytes|-b <bytes>\n"
7bf0220c3332700233120b513c9b4ba20a0caa9bvboxsync" The maximum number of bytes to disassemble. Default: 1GB\n"
7bf0220c3332700233120b513c9b4ba20a0caa9bvboxsync" --cpumode|-c <16|32|64>\n"
7bf0220c3332700233120b513c9b4ba20a0caa9bvboxsync" The cpu mode. Default: 32\n"
7bf0220c3332700233120b513c9b4ba20a0caa9bvboxsync" --listing|-l, --no-listing|-L\n"
7bf0220c3332700233120b513c9b4ba20a0caa9bvboxsync" Enables or disables listing mode. Default: --no-listing\n"
7bf0220c3332700233120b513c9b4ba20a0caa9bvboxsync" --offset|-o <offset>\n"
7bf0220c3332700233120b513c9b4ba20a0caa9bvboxsync" The file offset at which to start disassembling. Default: 0\n"
7bf0220c3332700233120b513c9b4ba20a0caa9bvboxsync" --style|-s <default|yasm|masm>\n"
7bf0220c3332700233120b513c9b4ba20a0caa9bvboxsync" The assembly output style. Default: default\n"
7748b9362d6a39df9045d5d05ccb57871145a649vboxsync" --undef-op|-u <fail|all|db>\n"
7748b9362d6a39df9045d5d05ccb57871145a649vboxsync" How to treat undefined opcodes. Default: fail\n"
8fa1e8a8a8702ee38195fbe7ad5959bf971eb93bvboxsync const char * const argv0 = RTPathFilename(argv[0]);
7bf0220c3332700233120b513c9b4ba20a0caa9bvboxsync /* options */
7bf0220c3332700233120b513c9b4ba20a0caa9bvboxsync bool fListing = true;
57a94b9fea6a6400f7a80e322e84b5b453c3bff0vboxsync bool fHexBytes = false;
7bf0220c3332700233120b513c9b4ba20a0caa9bvboxsync * Parse arguments.
83dc9ca94cd3c31dabc33a35b945de124d43aaeavboxsync RTGetOptInit(&GetState, argc, argv, g_aOptions, RT_ELEMENTS(g_aOptions), 1, 0 /* fFlags */);
8fa1e8a8a8702ee38195fbe7ad5959bf971eb93bvboxsync RTStrmPrintf(g_pStdErr, "%s: Invalid CPU mode value %RU32\n", argv0, ValueUnion.u32);
8fa1e8a8a8702ee38195fbe7ad5959bf971eb93bvboxsync RTStrmPrintf(g_pStdErr, "%s: masm style isn't implemented yet\n", argv0);
8fa1e8a8a8702ee38195fbe7ad5959bf971eb93bvboxsync RTStrmPrintf(g_pStdErr, "%s: unknown assembly style: %s\n", argv0, ValueUnion.psz);
7748b9362d6a39df9045d5d05ccb57871145a649vboxsync RTStrmPrintf(g_pStdErr, "%s: unknown undefined opcode handling method: %s\n", argv0, ValueUnion.psz);
8fa1e8a8a8702ee38195fbe7ad5959bf971eb93bvboxsync RTStrmPrintf(g_pStdErr, "%s: syntax error: %Rrc\n", argv0, ch);
83dc9ca94cd3c31dabc33a35b945de124d43aaeavboxsync int iArg = GetState.iNext - 1; /** @todo Not pretty, add RTGetOptInit flag for this. */
57a94b9fea6a6400f7a80e322e84b5b453c3bff0vboxsync * Convert the remaining arguments from a hex byte string into
57a94b9fea6a6400f7a80e322e84b5b453c3bff0vboxsync * a buffer that we disassemble.
57a94b9fea6a6400f7a80e322e84b5b453c3bff0vboxsync /** @todo this stuff belongs in IPRT, same stuff as mac address reading. Could be reused for IPv6 with a different item size.*/
57a94b9fea6a6400f7a80e322e84b5b453c3bff0vboxsync /* skip white space */
57a94b9fea6a6400f7a80e322e84b5b453c3bff0vboxsync /* one digit followed by a space or EOS, or two digits. */
57a94b9fea6a6400f7a80e322e84b5b453c3bff0vboxsync /* add the byte */
57a94b9fea6a6400f7a80e322e84b5b453c3bff0vboxsync RTPrintf("%s: error: RTMemRealloc failed\n", argv[0]);
7bf0220c3332700233120b513c9b4ba20a0caa9bvboxsync * Disassemble it.
57a94b9fea6a6400f7a80e322e84b5b453c3bff0vboxsync rc = MyDisasmBlock(argv0, enmCpuMode, uAddress, pb, cb, enmStyle, fListing, enmUndefOp);
57a94b9fea6a6400f7a80e322e84b5b453c3bff0vboxsync * Process the files.
57a94b9fea6a6400f7a80e322e84b5b453c3bff0vboxsync * Read the file into memory.
3f53db546002b7bd0fcfdfa6da646d518490888dvboxsync rc = RTFileReadAllEx(argv[iArg], off, cbMax, RTFILE_RDALL_O_DENY_NONE, &pvFile, &cbFile);
57a94b9fea6a6400f7a80e322e84b5b453c3bff0vboxsync RTStrmPrintf(g_pStdErr, "%s: %s: %Rrc\n", argv0, argv[iArg], rc);
57a94b9fea6a6400f7a80e322e84b5b453c3bff0vboxsync * Disassemble it.