DisasmReg.cpp revision e3e7d748172761a1d90c71103a98a9aa7f876420
3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync/** @file
3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync *
3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync * VBox disassembler:
3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync * Core components
3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync */
3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync
3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync/*
3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync * Copyright (C) 2006-2007 Sun Microsystems, Inc.
3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync *
3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync * This file is part of VirtualBox Open Source Edition (OSE), as
3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync * available from http://www.virtualbox.org. This file is free software;
3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync * you can redistribute it and/or modify it under the terms of the GNU
3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync * General Public License (GPL) as published by the Free Software
3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync * Foundation, in version 2 as it comes in the "COPYING" file of the
3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync *
3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync * Clara, CA 95054 USA or visit http://www.sun.com if you need
3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync * additional information or have any questions.
930b5f872e89407f445d4000d4e4aaecaa6a0998vboxsync */
930b5f872e89407f445d4000d4e4aaecaa6a0998vboxsync
930b5f872e89407f445d4000d4e4aaecaa6a0998vboxsync
930b5f872e89407f445d4000d4e4aaecaa6a0998vboxsync/*******************************************************************************
930b5f872e89407f445d4000d4e4aaecaa6a0998vboxsync* Header Files *
930b5f872e89407f445d4000d4e4aaecaa6a0998vboxsync*******************************************************************************/
930b5f872e89407f445d4000d4e4aaecaa6a0998vboxsync#define LOG_GROUP LOG_GROUP_DIS
930b5f872e89407f445d4000d4e4aaecaa6a0998vboxsync#ifdef USING_VISUAL_STUDIO
930b5f872e89407f445d4000d4e4aaecaa6a0998vboxsync# include <stdafx.h>
3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync#endif
3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync
3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync#include <VBox/dis.h>
3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync#include <VBox/disopcode.h>
3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync#include <VBox/cpum.h>
3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync#include <VBox/err.h>
3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync#include <VBox/log.h>
3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync#include <iprt/assert.h>
3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync#include <iprt/string.h>
3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync#include <iprt/stdarg.h>
3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync#include "DisasmInternal.h"
3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync#include "DisasmTables.h"
3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync
3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync#if !defined(DIS_CORE_ONLY) && defined(LOG_ENABLED)
3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync# include <stdlib.h>
3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync# include <stdio.h>
3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync#endif
3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync
3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync
3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync/*******************************************************************************
3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync* Global Variables *
3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync*******************************************************************************/
3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync
3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync/**
3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync * Array for accessing 64-bit general registers in VMMREGFRAME structure
3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync * by register's index from disasm.
3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync */
3194da424708abdd288b28d96892b3a5f3f7df0bvboxsyncstatic const unsigned g_aReg64Index[] =
3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync{
3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync RT_OFFSETOF(CPUMCTXCORE, rax), /* USE_REG_RAX */
3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync RT_OFFSETOF(CPUMCTXCORE, rcx), /* USE_REG_RCX */
3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync RT_OFFSETOF(CPUMCTXCORE, rdx), /* USE_REG_RDX */
3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync RT_OFFSETOF(CPUMCTXCORE, rbx), /* USE_REG_RBX */
3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync RT_OFFSETOF(CPUMCTXCORE, rsp), /* USE_REG_RSP */
3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync RT_OFFSETOF(CPUMCTXCORE, rbp), /* USE_REG_RBP */
3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync RT_OFFSETOF(CPUMCTXCORE, rsi), /* USE_REG_RSI */
3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync RT_OFFSETOF(CPUMCTXCORE, rdi), /* USE_REG_RDI */
3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync RT_OFFSETOF(CPUMCTXCORE, r8), /* USE_REG_R8 */
3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync RT_OFFSETOF(CPUMCTXCORE, r9), /* USE_REG_R9 */
3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync RT_OFFSETOF(CPUMCTXCORE, r10), /* USE_REG_R10 */
3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync RT_OFFSETOF(CPUMCTXCORE, r11), /* USE_REG_R11 */
3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync RT_OFFSETOF(CPUMCTXCORE, r12), /* USE_REG_R12 */
3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync RT_OFFSETOF(CPUMCTXCORE, r13), /* USE_REG_R13 */
3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync RT_OFFSETOF(CPUMCTXCORE, r14), /* USE_REG_R14 */
3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync RT_OFFSETOF(CPUMCTXCORE, r15) /* USE_REG_R15 */
3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync};
3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync
3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync/**
3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync * Macro for accessing 64-bit general purpose registers in CPUMCTXCORE structure.
3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync */
3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync#define DIS_READ_REG64(p, idx) (*(uint64_t *)((char *)(p) + g_aReg64Index[idx]))
3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync#define DIS_WRITE_REG64(p, idx, val) (*(uint64_t *)((char *)(p) + g_aReg64Index[idx]) = val)
3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync#define DIS_PTR_REG64(p, idx) ( (uint64_t *)((char *)(p) + g_aReg64Index[idx]))
3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync
3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync/**
3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync * Array for accessing 32-bit general registers in VMMREGFRAME structure
3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync * by register's index from disasm.
3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync */
3194da424708abdd288b28d96892b3a5f3f7df0bvboxsyncstatic const unsigned g_aReg32Index[] =
3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync{
3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync RT_OFFSETOF(CPUMCTXCORE, eax), /* USE_REG_EAX */
3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync RT_OFFSETOF(CPUMCTXCORE, ecx), /* USE_REG_ECX */
3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync RT_OFFSETOF(CPUMCTXCORE, edx), /* USE_REG_EDX */
3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync RT_OFFSETOF(CPUMCTXCORE, ebx), /* USE_REG_EBX */
3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync RT_OFFSETOF(CPUMCTXCORE, esp), /* USE_REG_ESP */
3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync RT_OFFSETOF(CPUMCTXCORE, ebp), /* USE_REG_EBP */
3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync RT_OFFSETOF(CPUMCTXCORE, esi), /* USE_REG_ESI */
3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync RT_OFFSETOF(CPUMCTXCORE, edi) /* USE_REG_EDI */
3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync};
3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync
3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync/**
3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync * Macro for accessing 32-bit general purpose registers in CPUMCTXCORE structure.
3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync */
3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync#define DIS_READ_REG32(p, idx) (*(uint32_t *)((char *)(p) + g_aReg32Index[idx]))
3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync#define DIS_WRITE_REG32(p, idx, val) (*(uint32_t *)((char *)(p) + g_aReg32Index[idx]) = val)
3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync#define DIS_PTR_REG32(p, idx) ( (uint32_t *)((char *)(p) + g_aReg32Index[idx]))
3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync
3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync/**
3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync * Array for accessing 16-bit general registers in CPUMCTXCORE structure
3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync * by register's index from disasm.
3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync */
3194da424708abdd288b28d96892b3a5f3f7df0bvboxsyncstatic const unsigned g_aReg16Index[] =
3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync{
3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync RT_OFFSETOF(CPUMCTXCORE, eax), /* USE_REG_AX */
3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync RT_OFFSETOF(CPUMCTXCORE, ecx), /* USE_REG_CX */
3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync RT_OFFSETOF(CPUMCTXCORE, edx), /* USE_REG_DX */
3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync RT_OFFSETOF(CPUMCTXCORE, ebx), /* USE_REG_BX */
3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync RT_OFFSETOF(CPUMCTXCORE, esp), /* USE_REG_SP */
3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync RT_OFFSETOF(CPUMCTXCORE, ebp), /* USE_REG_BP */
3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync RT_OFFSETOF(CPUMCTXCORE, esi), /* USE_REG_SI */
3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync RT_OFFSETOF(CPUMCTXCORE, edi) /* USE_REG_DI */
3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync};
3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync
3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync/**
3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync * Macro for accessing 16-bit general purpose registers in CPUMCTXCORE structure.
3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync */
3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync#define DIS_READ_REG16(p, idx) (*(uint16_t *)((char *)(p) + g_aReg16Index[idx]))
3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync#define DIS_WRITE_REG16(p, idx, val) (*(uint16_t *)((char *)(p) + g_aReg16Index[idx]) = val)
3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync#define DIS_PTR_REG16(p, idx) ( (uint16_t *)((char *)(p) + g_aReg16Index[idx]))
3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync
3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync/**
3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync * Array for accessing 8-bit general registers in CPUMCTXCORE structure
3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync * by register's index from disasm.
3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync */
3194da424708abdd288b28d96892b3a5f3f7df0bvboxsyncstatic const unsigned g_aReg8Index[] =
3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync{
3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync RT_OFFSETOF(CPUMCTXCORE, eax), /* USE_REG_AL */
3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync RT_OFFSETOF(CPUMCTXCORE, ecx), /* USE_REG_CL */
3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync RT_OFFSETOF(CPUMCTXCORE, edx), /* USE_REG_DL */
3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync RT_OFFSETOF(CPUMCTXCORE, ebx), /* USE_REG_BL */
3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync RT_OFFSETOF(CPUMCTXCORE, eax) + 1, /* USE_REG_AH */
3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync RT_OFFSETOF(CPUMCTXCORE, ecx) + 1, /* USE_REG_CH */
3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync RT_OFFSETOF(CPUMCTXCORE, edx) + 1, /* USE_REG_DH */
3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync RT_OFFSETOF(CPUMCTXCORE, ebx) + 1 /* USE_REG_BH */
3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync};
3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync
3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync/**
3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync * Macro for accessing 8-bit general purpose registers in CPUMCTXCORE structure.
3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync */
3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync#define DIS_READ_REG8(p, idx) (*(uint8_t *)((char *)(p) + g_aReg8Index[idx]))
3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync#define DIS_WRITE_REG8(p, idx, val) (*(uint8_t *)((char *)(p) + g_aReg8Index[idx]) = val)
3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync#define DIS_PTR_REG8(p, idx) ( (uint8_t *)((char *)(p) + g_aReg8Index[idx]))
3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync
3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync/**
3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync * Array for accessing segment registers in CPUMCTXCORE structure
3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync * by register's index from disasm.
3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync */
3194da424708abdd288b28d96892b3a5f3f7df0bvboxsyncstatic const unsigned g_aRegSegIndex[] =
3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync{
3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync RT_OFFSETOF(CPUMCTXCORE, es), /* USE_REG_ES */
3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync RT_OFFSETOF(CPUMCTXCORE, cs), /* USE_REG_CS */
3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync RT_OFFSETOF(CPUMCTXCORE, ss), /* USE_REG_SS */
3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync RT_OFFSETOF(CPUMCTXCORE, ds), /* USE_REG_DS */
3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync RT_OFFSETOF(CPUMCTXCORE, fs), /* USE_REG_FS */
3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync RT_OFFSETOF(CPUMCTXCORE, gs) /* USE_REG_GS */
3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync};
3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync
3194da424708abdd288b28d96892b3a5f3f7df0bvboxsyncstatic const unsigned g_aRegHidSegIndex[] =
3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync{
3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync RT_OFFSETOF(CPUMCTXCORE, esHid), /* USE_REG_ES */
3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync RT_OFFSETOF(CPUMCTXCORE, csHid), /* USE_REG_CS */
3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync RT_OFFSETOF(CPUMCTXCORE, ssHid), /* USE_REG_SS */
3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync RT_OFFSETOF(CPUMCTXCORE, dsHid), /* USE_REG_DS */
3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync RT_OFFSETOF(CPUMCTXCORE, fsHid), /* USE_REG_FS */
3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync RT_OFFSETOF(CPUMCTXCORE, gsHid) /* USE_REG_GS */
3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync};
3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync
3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync/**
3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync * Macro for accessing segment registers in CPUMCTXCORE structure.
3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync */
3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync#define DIS_READ_REGSEG(p, idx) (*((uint16_t *)((char *)(p) + g_aRegSegIndex[idx])))
3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync#define DIS_WRITE_REGSEG(p, idx, val) (*((uint16_t *)((char *)(p) + g_aRegSegIndex[idx])) = val)
3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync
3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync//*****************************************************************************
3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync//*****************************************************************************
3194da424708abdd288b28d96892b3a5f3f7df0bvboxsyncDISDECL(int) DISGetParamSize(PDISCPUSTATE pCpu, POP_PARAMETER pParam)
3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync{
3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync int subtype = OP_PARM_VSUBTYPE(pParam->param);
3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync
3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync if (subtype == OP_PARM_v)
3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync subtype = (pCpu->opmode == CPUMODE_32BIT) ? OP_PARM_d : OP_PARM_w;
3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync
3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync switch(subtype)
3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync {
3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync case OP_PARM_b:
3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync return 1;
3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync
3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync case OP_PARM_w:
3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync return 2;
3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync
3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync case OP_PARM_d:
3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync return 4;
3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync
3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync case OP_PARM_q:
3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync case OP_PARM_dq:
3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync return 8;
3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync
3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync case OP_PARM_p: /* far pointer */
3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync if (pCpu->addrmode == CPUMODE_32BIT)
3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync return 6; /* 16:32 */
3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync else
3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync if (pCpu->addrmode == CPUMODE_64BIT)
3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync return 12; /* 16:64 */
3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync else
3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync return 4; /* 16:16 */
3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync
3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync default:
3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync if (pParam->size)
3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync return pParam->size;
3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync else //@todo dangerous!!!
3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync return 4;
3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync }
3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync}
3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync//*****************************************************************************
3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync//*****************************************************************************
3194da424708abdd288b28d96892b3a5f3f7df0bvboxsyncDISDECL(int) DISDetectSegReg(PDISCPUSTATE pCpu, POP_PARAMETER pParam)
3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync{
3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync if (pCpu->prefix & PREFIX_SEG)
3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync {
3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync /* Use specified SEG: prefix. */
3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync return pCpu->prefix_seg;
3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync }
3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync else
3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync {
3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync /* Guess segment register by parameter type. */
3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync if (pParam->flags & (USE_REG_GEN32|USE_REG_GEN64|USE_REG_GEN16))
3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync {
3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync AssertCompile(USE_REG_ESP == USE_REG_RSP);
3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync AssertCompile(USE_REG_EBP == USE_REG_RBP);
3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync AssertCompile(USE_REG_ESP == USE_REG_SP);
3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync AssertCompile(USE_REG_EBP == USE_REG_BP);
3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync if (pParam->base.reg_gen == USE_REG_ESP || pParam->base.reg_gen == USE_REG_EBP)
3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync return USE_REG_SS;
3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync }
3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync /* Default is use DS: for data access. */
3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync return USE_REG_DS;
3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync }
3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync}
3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync//*****************************************************************************
3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync//*****************************************************************************
3194da424708abdd288b28d96892b3a5f3f7df0bvboxsyncDISDECL(uint8_t) DISQuerySegPrefixByte(PDISCPUSTATE pCpu)
3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync{
3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync Assert(pCpu->prefix & PREFIX_SEG);
3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync switch(pCpu->prefix_seg)
3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync {
3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync case USE_REG_ES:
3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync return 0x26;
3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync case USE_REG_CS:
3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync return 0x2E;
3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync case USE_REG_SS:
3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync return 0x36;
3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync case USE_REG_DS:
3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync return 0x3E;
3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync case USE_REG_FS:
3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync return 0x64;
3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync case USE_REG_GS:
3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync return 0x65;
3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync default:
3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync AssertFailed();
3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync return 0;
3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync }
3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync}
3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync
3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync
3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync/**
3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync * Returns the value of the specified 8 bits general purpose register
3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync *
3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync */
3194da424708abdd288b28d96892b3a5f3f7df0bvboxsyncDISDECL(int) DISFetchReg8(PCPUMCTXCORE pCtx, unsigned reg8, uint8_t *pVal)
3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync{
3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync AssertReturn(reg8 < ELEMENTS(g_aReg8Index), VERR_INVALID_PARAMETER);
3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync
3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync *pVal = DIS_READ_REG8(pCtx, reg8);
3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync return VINF_SUCCESS;
3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync}
3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync
3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync/**
3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync * Returns the value of the specified 16 bits general purpose register
3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync *
3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync */
3194da424708abdd288b28d96892b3a5f3f7df0bvboxsyncDISDECL(int) DISFetchReg16(PCPUMCTXCORE pCtx, unsigned reg16, uint16_t *pVal)
3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync{
3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync AssertReturn(reg16 < ELEMENTS(g_aReg16Index), VERR_INVALID_PARAMETER);
3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync
3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync *pVal = DIS_READ_REG16(pCtx, reg16);
3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync return VINF_SUCCESS;
3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync}
3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync
3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync/**
3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync * Returns the value of the specified 32 bits general purpose register
3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync *
3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync */
3194da424708abdd288b28d96892b3a5f3f7df0bvboxsyncDISDECL(int) DISFetchReg32(PCPUMCTXCORE pCtx, unsigned reg32, uint32_t *pVal)
3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync{
3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync AssertReturn(reg32 < ELEMENTS(g_aReg32Index), VERR_INVALID_PARAMETER);
3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync
3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync *pVal = DIS_READ_REG32(pCtx, reg32);
3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync return VINF_SUCCESS;
3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync}
/**
* Returns the value of the specified 64 bits general purpose register
*
*/
DISDECL(int) DISFetchReg64(PCPUMCTXCORE pCtx, unsigned reg64, uint64_t *pVal)
{
AssertReturn(reg64 < ELEMENTS(g_aReg64Index), VERR_INVALID_PARAMETER);
*pVal = DIS_READ_REG64(pCtx, reg64);
return VINF_SUCCESS;
}
/**
* Returns the pointer to the specified 8 bits general purpose register
*
*/
DISDECL(int) DISPtrReg8(PCPUMCTXCORE pCtx, unsigned reg8, uint8_t **ppReg)
{
AssertReturn(reg8 < ELEMENTS(g_aReg8Index), VERR_INVALID_PARAMETER);
*ppReg = DIS_PTR_REG8(pCtx, reg8);
return VINF_SUCCESS;
}
/**
* Returns the pointer to the specified 16 bits general purpose register
*
*/
DISDECL(int) DISPtrReg16(PCPUMCTXCORE pCtx, unsigned reg16, uint16_t **ppReg)
{
AssertReturn(reg16 < ELEMENTS(g_aReg16Index), VERR_INVALID_PARAMETER);
*ppReg = DIS_PTR_REG16(pCtx, reg16);
return VINF_SUCCESS;
}
/**
* Returns the pointer to the specified 32 bits general purpose register
*
*/
DISDECL(int) DISPtrReg32(PCPUMCTXCORE pCtx, unsigned reg32, uint32_t **ppReg)
{
AssertReturn(reg32 < ELEMENTS(g_aReg32Index), VERR_INVALID_PARAMETER);
*ppReg = DIS_PTR_REG32(pCtx, reg32);
return VINF_SUCCESS;
}
/**
* Returns the pointer to the specified 64 bits general purpose register
*
*/
DISDECL(int) DISPtrReg64(PCPUMCTXCORE pCtx, unsigned reg64, uint64_t **ppReg)
{
AssertReturn(reg64 < ELEMENTS(g_aReg64Index), VERR_INVALID_PARAMETER);
*ppReg = DIS_PTR_REG64(pCtx, reg64);
return VINF_SUCCESS;
}
/**
* Returns the value of the specified segment register
*
*/
DISDECL(int) DISFetchRegSeg(PCPUMCTXCORE pCtx, unsigned sel, RTSEL *pVal)
{
AssertReturn(sel < ELEMENTS(g_aRegSegIndex), VERR_INVALID_PARAMETER);
AssertCompile(sizeof(uint16_t) == sizeof(RTSEL));
*pVal = DIS_READ_REGSEG(pCtx, sel);
return VINF_SUCCESS;
}
/**
* Returns the value of the specified segment register including a pointer to the hidden register in the supplied cpu context
*
*/
DISDECL(int) DISFetchRegSegEx(PCPUMCTXCORE pCtx, unsigned sel, RTSEL *pVal, CPUMSELREGHID **ppSelHidReg)
{
AssertReturn(sel < ELEMENTS(g_aRegSegIndex), VERR_INVALID_PARAMETER);
AssertCompile(sizeof(uint16_t) == sizeof(RTSEL));
*pVal = DIS_READ_REGSEG(pCtx, sel);
*ppSelHidReg = (CPUMSELREGHID *)((char *)pCtx + g_aRegHidSegIndex[sel]);
return VINF_SUCCESS;
}
/**
* Updates the value of the specified 64 bits general purpose register
*
*/
DISDECL(int) DISWriteReg64(PCPUMCTXCORE pRegFrame, unsigned reg64, uint64_t val64)
{
AssertReturn(reg64 < ELEMENTS(g_aReg64Index), VERR_INVALID_PARAMETER);
DIS_WRITE_REG64(pRegFrame, reg64, val64);
return VINF_SUCCESS;
}
/**
* Updates the value of the specified 32 bits general purpose register
*
*/
DISDECL(int) DISWriteReg32(PCPUMCTXCORE pRegFrame, unsigned reg32, uint32_t val32)
{
AssertReturn(reg32 < ELEMENTS(g_aReg32Index), VERR_INVALID_PARAMETER);
DIS_WRITE_REG32(pRegFrame, reg32, val32);
return VINF_SUCCESS;
}
/**
* Updates the value of the specified 16 bits general purpose register
*
*/
DISDECL(int) DISWriteReg16(PCPUMCTXCORE pRegFrame, unsigned reg16, uint16_t val16)
{
AssertReturn(reg16 < ELEMENTS(g_aReg16Index), VERR_INVALID_PARAMETER);
DIS_WRITE_REG16(pRegFrame, reg16, val16);
return VINF_SUCCESS;
}
/**
* Updates the specified 8 bits general purpose register
*
*/
DISDECL(int) DISWriteReg8(PCPUMCTXCORE pRegFrame, unsigned reg8, uint8_t val8)
{
AssertReturn(reg8 < ELEMENTS(g_aReg8Index), VERR_INVALID_PARAMETER);
DIS_WRITE_REG8(pRegFrame, reg8, val8);
return VINF_SUCCESS;
}
/**
* Updates the specified segment register
*
*/
DISDECL(int) DISWriteRegSeg(PCPUMCTXCORE pCtx, unsigned sel, RTSEL val)
{
AssertReturn(sel < ELEMENTS(g_aRegSegIndex), VERR_INVALID_PARAMETER);
AssertCompile(sizeof(uint16_t) == sizeof(RTSEL));
DIS_WRITE_REGSEG(pCtx, sel, val);
return VINF_SUCCESS;
}
/**
* Returns the value of the parameter in pParam
*
* @returns VBox error code
* @param pCtx CPU context structure pointer
* @param pCpu Pointer to cpu structure which have DISCPUSTATE::mode
* set correctly.
* @param pParam Pointer to the parameter to parse
* @param pParamVal Pointer to parameter value (OUT)
* @param parmtype Parameter type
*
* @note Currently doesn't handle FPU/XMM/MMX/3DNow! parameters correctly!!
*
*/
DISDECL(int) DISQueryParamVal(PCPUMCTXCORE pCtx, PDISCPUSTATE pCpu, POP_PARAMETER pParam, POP_PARAMVAL pParamVal, PARAM_TYPE parmtype)
{
memset(pParamVal, 0, sizeof(*pParamVal));
if (DIS_IS_EFFECTIVE_ADDR(pParam->flags))
{
// Effective address
pParamVal->type = PARMTYPE_ADDRESS;
pParamVal->size = pParam->size;
if (pParam->flags & USE_BASE)
{
if (pParam->flags & USE_REG_GEN8)
{
pParamVal->flags |= PARAM_VAL8;
if (VBOX_FAILURE(DISFetchReg8(pCtx, pParam->base.reg_gen, &pParamVal->val.val8))) return VERR_INVALID_PARAMETER;
}
else
if (pParam->flags & USE_REG_GEN16)
{
pParamVal->flags |= PARAM_VAL16;
if (VBOX_FAILURE(DISFetchReg16(pCtx, pParam->base.reg_gen, &pParamVal->val.val16))) return VERR_INVALID_PARAMETER;
}
else
if (pParam->flags & USE_REG_GEN32)
{
pParamVal->flags |= PARAM_VAL32;
if (VBOX_FAILURE(DISFetchReg32(pCtx, pParam->base.reg_gen, &pParamVal->val.val32))) return VERR_INVALID_PARAMETER;
}
else
if (pParam->flags & USE_REG_GEN64)
{
pParamVal->flags |= PARAM_VAL64;
if (VBOX_FAILURE(DISFetchReg64(pCtx, pParam->base.reg_gen, &pParamVal->val.val64))) return VERR_INVALID_PARAMETER;
}
else {
AssertFailed();
return VERR_INVALID_PARAMETER;
}
}
// Note that scale implies index (SIB byte)
if (pParam->flags & USE_INDEX)
{
uint32_t val32;
pParamVal->flags |= PARAM_VAL32;
if (VBOX_FAILURE(DISFetchReg32(pCtx, pParam->index.reg_gen, &val32))) return VERR_INVALID_PARAMETER;
if (pParam->flags & USE_SCALE)
val32 *= pParam->scale;
pParamVal->val.val32 += val32;
}
if (pParam->flags & USE_DISPLACEMENT8)
{
if (pCpu->mode == CPUMODE_32BIT)
pParamVal->val.val32 += (int32_t)pParam->disp8;
else
pParamVal->val.val16 += (int16_t)pParam->disp8;
}
else
if (pParam->flags & USE_DISPLACEMENT16)
{
if (pCpu->mode == CPUMODE_32BIT)
pParamVal->val.val32 += (int32_t)pParam->disp16;
else
pParamVal->val.val16 += pParam->disp16;
}
else
if (pParam->flags & USE_DISPLACEMENT32)
{
if (pCpu->mode == CPUMODE_32BIT)
pParamVal->val.val32 += pParam->disp32;
else
AssertFailed();
}
else
if (pParam->flags & USE_RIPDISPLACEMENT32)
{
if (pCpu->mode == CPUMODE_64BIT)
pParamVal->val.val64 += pParam->disp32 + pCtx->rip;
else
AssertFailed();
}
return VINF_SUCCESS;
}
if (pParam->flags & (USE_REG_GEN8|USE_REG_GEN16|USE_REG_GEN32|USE_REG_GEN64|USE_REG_FP|USE_REG_MMX|USE_REG_XMM|USE_REG_CR|USE_REG_DBG|USE_REG_SEG|USE_REG_TEST))
{
if (parmtype == PARAM_DEST)
{
// Caller needs to interpret the register according to the instruction (source/target, special value etc)
pParamVal->type = PARMTYPE_REGISTER;
pParamVal->size = pParam->size;
return VINF_SUCCESS;
}
//else PARAM_SOURCE
pParamVal->type = PARMTYPE_IMMEDIATE;
if (pParam->flags & USE_REG_GEN8)
{
pParamVal->flags |= PARAM_VAL8;
pParamVal->size = sizeof(uint8_t);
if (VBOX_FAILURE(DISFetchReg8(pCtx, pParam->base.reg_gen, &pParamVal->val.val8))) return VERR_INVALID_PARAMETER;
}
else
if (pParam->flags & USE_REG_GEN16)
{
pParamVal->flags |= PARAM_VAL16;
pParamVal->size = sizeof(uint16_t);
if (VBOX_FAILURE(DISFetchReg16(pCtx, pParam->base.reg_gen, &pParamVal->val.val16))) return VERR_INVALID_PARAMETER;
}
else
if (pParam->flags & USE_REG_GEN32)
{
pParamVal->flags |= PARAM_VAL32;
pParamVal->size = sizeof(uint32_t);
if (VBOX_FAILURE(DISFetchReg32(pCtx, pParam->base.reg_gen, &pParamVal->val.val32))) return VERR_INVALID_PARAMETER;
}
else
if (pParam->flags & USE_REG_GEN64)
{
pParamVal->flags |= PARAM_VAL64;
pParamVal->size = sizeof(uint64_t);
if (VBOX_FAILURE(DISFetchReg64(pCtx, pParam->base.reg_gen, &pParamVal->val.val64))) return VERR_INVALID_PARAMETER;
}
else
{
// Caller needs to interpret the register according to the instruction (source/target, special value etc)
pParamVal->type = PARMTYPE_REGISTER;
}
Assert(!(pParam->flags & USE_IMMEDIATE));
return VINF_SUCCESS;
}
if (pParam->flags & USE_IMMEDIATE)
{
pParamVal->type = PARMTYPE_IMMEDIATE;
if (pParam->flags & (USE_IMMEDIATE8|USE_IMMEDIATE8_REL))
{
pParamVal->flags |= PARAM_VAL8;
if (pParam->size == 2)
{
pParamVal->size = sizeof(uint16_t);
pParamVal->val.val16 = (uint8_t)pParam->parval;
}
else
{
pParamVal->size = sizeof(uint8_t);
pParamVal->val.val8 = (uint8_t)pParam->parval;
}
}
else
if (pParam->flags & (USE_IMMEDIATE16|USE_IMMEDIATE16_REL|USE_IMMEDIATE_ADDR_0_16|USE_IMMEDIATE16_SX8))
{
pParamVal->flags |= PARAM_VAL16;
pParamVal->size = sizeof(uint16_t);
pParamVal->val.val16 = (uint16_t)pParam->parval;
AssertMsg(pParamVal->size == pParam->size || ((pParam->size == 1) && (pParam->flags & USE_IMMEDIATE16_SX8)), ("pParamVal->size %d vs %d EIP=%VGv\n", pParamVal->size, pParam->size, pCtx->eip) );
}
else
if (pParam->flags & (USE_IMMEDIATE32|USE_IMMEDIATE32_REL|USE_IMMEDIATE_ADDR_0_32|USE_IMMEDIATE32_SX8))
{
pParamVal->flags |= PARAM_VAL32;
pParamVal->size = sizeof(uint32_t);
pParamVal->val.val32 = (uint32_t)pParam->parval;
Assert(pParamVal->size == pParam->size || ((pParam->size == 1) && (pParam->flags & USE_IMMEDIATE32_SX8)) );
}
else
if (pParam->flags & (USE_IMMEDIATE64 | USE_IMMEDIATE64_REL))
{
pParamVal->flags |= PARAM_VAL64;
pParamVal->size = sizeof(uint64_t);
pParamVal->val.val64 = pParam->parval;
Assert(pParamVal->size == pParam->size);
}
else
if (pParam->flags & (USE_IMMEDIATE_ADDR_16_16))
{
pParamVal->flags |= PARAM_VALFARPTR16;
pParamVal->size = sizeof(uint16_t)*2;
pParamVal->val.farptr.sel = (uint16_t)RT_LOWORD(pParam->parval >> 16);
pParamVal->val.farptr.offset = (uint32_t)RT_LOWORD(pParam->parval);
Assert(pParamVal->size == pParam->size);
}
else
if (pParam->flags & (USE_IMMEDIATE_ADDR_16_32))
{
pParamVal->flags |= PARAM_VALFARPTR32;
pParamVal->size = sizeof(uint16_t) + sizeof(uint32_t);
pParamVal->val.farptr.sel = (uint16_t)RT_LOWORD(pParam->parval >> 32);
pParamVal->val.farptr.offset = (uint32_t)(pParam->parval & 0xFFFFFFFF);
Assert(pParam->size == 8);
}
}
return VINF_SUCCESS;
}
/**
* Returns the pointer to a register of the parameter in pParam. We need this
* pointer when an interpreted instruction updates a register as a side effect.
* In CMPXCHG we know that only [r/e]ax is updated, but with XADD this could
* be every register.
*
* @returns VBox error code
* @param pCtx CPU context structure pointer
* @param pCpu Pointer to cpu structure which have DISCPUSTATE::mode
* set correctly.
* @param pParam Pointer to the parameter to parse
* @param pReg Pointer to parameter value (OUT)
* @param cbsize Parameter size (OUT)
*
* @note Currently doesn't handle FPU/XMM/MMX/3DNow! parameters correctly!!
*
*/
DISDECL(int) DISQueryParamRegPtr(PCPUMCTXCORE pCtx, PDISCPUSTATE pCpu, POP_PARAMETER pParam, void **ppReg, size_t *pcbSize)
{
if (pParam->flags & (USE_REG_GEN8|USE_REG_GEN16|USE_REG_GEN32|USE_REG_FP|USE_REG_MMX|USE_REG_XMM|USE_REG_CR|USE_REG_DBG|USE_REG_SEG|USE_REG_TEST))
{
if (pParam->flags & USE_REG_GEN8)
{
uint8_t *pu8Reg;
if (VBOX_SUCCESS(DISPtrReg8(pCtx, pParam->base.reg_gen, &pu8Reg)))
{
*pcbSize = sizeof(uint8_t);
*ppReg = (void *)pu8Reg;
return VINF_SUCCESS;
}
}
else
if (pParam->flags & USE_REG_GEN16)
{
uint16_t *pu16Reg;
if (VBOX_SUCCESS(DISPtrReg16(pCtx, pParam->base.reg_gen, &pu16Reg)))
{
*pcbSize = sizeof(uint16_t);
*ppReg = (void *)pu16Reg;
return VINF_SUCCESS;
}
}
else
if (pParam->flags & USE_REG_GEN32)
{
uint32_t *pu32Reg;
if (VBOX_SUCCESS(DISPtrReg32(pCtx, pParam->base.reg_gen, &pu32Reg)))
{
*pcbSize = sizeof(uint32_t);
*ppReg = (void *)pu32Reg;
return VINF_SUCCESS;
}
}
else
if (pParam->flags & USE_REG_GEN64)
{
uint64_t *pu64Reg;
if (VBOX_SUCCESS(DISPtrReg64(pCtx, pParam->base.reg_gen, &pu64Reg)))
{
*pcbSize = sizeof(uint64_t);
*ppReg = (void *)pu64Reg;
return VINF_SUCCESS;
}
}
}
return VERR_INVALID_PARAMETER;
}
//*****************************************************************************
//*****************************************************************************