DisasmReg.cpp revision d8c7549806316fefc91a86b1ff20a6c313297c62
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync * VBox disassembler:
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync * Core components
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync * Copyright (C) 2006-2007 Sun Microsystems, Inc.
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync * This file is part of VirtualBox Open Source Edition (OSE), as
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync * available from http://www.virtualbox.org. This file is free software;
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync * you can redistribute it and/or modify it under the terms of the GNU
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync * General Public License (GPL) as published by the Free Software
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync * Foundation, in version 2 as it comes in the "COPYING" file of the
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
a3d06a524c4f1cde2f0eada83656543d5a24115dvboxsync * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync * Clara, CA 95054 USA or visit http://www.sun.com if you need
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync * additional information or have any questions.
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync/*******************************************************************************
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync* Header Files *
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync*******************************************************************************/
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync/*******************************************************************************
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync* Global Variables *
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync*******************************************************************************/
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync * Array for accessing 64-bit general registers in VMMREGFRAME structure
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync * by register's index from disasm.
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsyncstatic const unsigned g_aReg64Index[] =
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync * Macro for accessing 64-bit general purpose registers in CPUMCTXCORE structure.
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync#define DIS_READ_REG64(p, idx) (*(uint64_t *)((char *)(p) + g_aReg64Index[idx]))
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync#define DIS_WRITE_REG64(p, idx, val) (*(uint64_t *)((char *)(p) + g_aReg64Index[idx]) = val)
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync#define DIS_PTR_REG64(p, idx) ( (uint64_t *)((char *)(p) + g_aReg64Index[idx]))
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync * Array for accessing 32-bit general registers in VMMREGFRAME structure
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync * by register's index from disasm.
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsyncstatic const unsigned g_aReg32Index[] =
c48c4d769ded37e2496f97dddbbd36dc62f244b1vboxsync * Macro for accessing 32-bit general purpose registers in CPUMCTXCORE structure.
c48c4d769ded37e2496f97dddbbd36dc62f244b1vboxsync#define DIS_READ_REG32(p, idx) (*(uint32_t *)((char *)(p) + g_aReg32Index[idx]))
1d17a5f9688f3622ffe088b664588629b1e95801vboxsync/* From http://www.cs.cmu.edu/~fp/courses/15213-s06/misc/asm64-handout.pdf:
14dcfe007d2a64583946ed5e4cfdb458a7f7f03bvboxsync * ``Perhaps unexpectedly, instructions that move or generate 32-bit register
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync * values also set the upper 32 bits of the register to zero. Consequently
a3d06a524c4f1cde2f0eada83656543d5a24115dvboxsync * there is no need for an instruction movzlq.''
a3d06a524c4f1cde2f0eada83656543d5a24115dvboxsync#define DIS_WRITE_REG32(p, idx, val) (*(uint64_t *)((char *)(p) + g_aReg32Index[idx]) = (uint32_t)val)
a3d06a524c4f1cde2f0eada83656543d5a24115dvboxsync#define DIS_PTR_REG32(p, idx) ( (uint32_t *)((char *)(p) + g_aReg32Index[idx]))
4bc1bbf45f30ff3ca38c2ad006836e490972c7ccvboxsync * Array for accessing 16-bit general registers in CPUMCTXCORE structure
4bc1bbf45f30ff3ca38c2ad006836e490972c7ccvboxsync * by register's index from disasm.
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsyncstatic const unsigned g_aReg16Index[] =
9704f1d0180960069e2c4eb8fe2ddee350910e5dvboxsync * Macro for accessing 16-bit general purpose registers in CPUMCTXCORE structure.
9704f1d0180960069e2c4eb8fe2ddee350910e5dvboxsync#define DIS_READ_REG16(p, idx) (*(uint16_t *)((char *)(p) + g_aReg16Index[idx]))
9704f1d0180960069e2c4eb8fe2ddee350910e5dvboxsync#define DIS_WRITE_REG16(p, idx, val) (*(uint16_t *)((char *)(p) + g_aReg16Index[idx]) = val)
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync#define DIS_PTR_REG16(p, idx) ( (uint16_t *)((char *)(p) + g_aReg16Index[idx]))
a3d06a524c4f1cde2f0eada83656543d5a24115dvboxsync * Array for accessing 8-bit general registers in CPUMCTXCORE structure
a3d06a524c4f1cde2f0eada83656543d5a24115dvboxsync * by register's index from disasm.
a3d06a524c4f1cde2f0eada83656543d5a24115dvboxsyncstatic const unsigned g_aReg8Index[] =
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync RT_OFFSETOF(CPUMCTXCORE, eax) + 1, /* USE_REG_AH */
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync RT_OFFSETOF(CPUMCTXCORE, ecx) + 1, /* USE_REG_CH */
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync RT_OFFSETOF(CPUMCTXCORE, edx) + 1, /* USE_REG_DH */
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync RT_OFFSETOF(CPUMCTXCORE, ebx) + 1, /* USE_REG_BH */
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync RT_OFFSETOF(CPUMCTXCORE, esp), /* USE_REG_SPL; with REX prefix only */
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync RT_OFFSETOF(CPUMCTXCORE, ebp), /* USE_REG_BPL; with REX prefix only */
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync RT_OFFSETOF(CPUMCTXCORE, esi), /* USE_REG_SIL; with REX prefix only */
58b7773f17a933ab8d53f450bed0afcf2f003508vboxsync RT_OFFSETOF(CPUMCTXCORE, edi) /* USE_REG_DIL; with REX prefix only */
58b7773f17a933ab8d53f450bed0afcf2f003508vboxsync * Macro for accessing 8-bit general purpose registers in CPUMCTXCORE structure.
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync#define DIS_READ_REG8(p, idx) (*(uint8_t *)((char *)(p) + g_aReg8Index[idx]))
58b7773f17a933ab8d53f450bed0afcf2f003508vboxsync#define DIS_WRITE_REG8(p, idx, val) (*(uint8_t *)((char *)(p) + g_aReg8Index[idx]) = val)
17d67aeb3722c094c6493a3e9a9d0cdfb9453ecdvboxsync#define DIS_PTR_REG8(p, idx) ( (uint8_t *)((char *)(p) + g_aReg8Index[idx]))
14dcfe007d2a64583946ed5e4cfdb458a7f7f03bvboxsync * Array for accessing segment registers in CPUMCTXCORE structure
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync * by register's index from disasm.
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsyncstatic const unsigned g_aRegSegIndex[] =
cf5af7fccfec4bef83f4ec21662d6a6e6cbe3835vboxsyncstatic const unsigned g_aRegHidSegIndex[] =
17d67aeb3722c094c6493a3e9a9d0cdfb9453ecdvboxsync RT_OFFSETOF(CPUMCTXCORE, esHid), /* DIS_SELREG_ES */
17d67aeb3722c094c6493a3e9a9d0cdfb9453ecdvboxsync RT_OFFSETOF(CPUMCTXCORE, csHid), /* DIS_SELREG_CS */
17d67aeb3722c094c6493a3e9a9d0cdfb9453ecdvboxsync RT_OFFSETOF(CPUMCTXCORE, ssHid), /* DIS_SELREG_SS */
17d67aeb3722c094c6493a3e9a9d0cdfb9453ecdvboxsync RT_OFFSETOF(CPUMCTXCORE, dsHid), /* DIS_SELREG_DS */
87c50c527af59e43745475c4b8ac907c5f9bc204vboxsync RT_OFFSETOF(CPUMCTXCORE, fsHid), /* DIS_SELREG_FS */
87c50c527af59e43745475c4b8ac907c5f9bc204vboxsync RT_OFFSETOF(CPUMCTXCORE, gsHid) /* DIS_SELREG_GS */
0c587d7af645db20acefebcfc15b6f46c440ba4avboxsync * Macro for accessing segment registers in CPUMCTXCORE structure.
0c587d7af645db20acefebcfc15b6f46c440ba4avboxsync#define DIS_READ_REGSEG(p, idx) (*((uint16_t *)((char *)(p) + g_aRegSegIndex[idx])))
17d67aeb3722c094c6493a3e9a9d0cdfb9453ecdvboxsync#define DIS_WRITE_REGSEG(p, idx, val) (*((uint16_t *)((char *)(p) + g_aRegSegIndex[idx])) = val)
cf5af7fccfec4bef83f4ec21662d6a6e6cbe3835vboxsync//*****************************************************************************
cf5af7fccfec4bef83f4ec21662d6a6e6cbe3835vboxsync//*****************************************************************************
0c587d7af645db20acefebcfc15b6f46c440ba4avboxsyncDISDECL(int) DISGetParamSize(PDISCPUSTATE pCpu, POP_PARAMETER pParam)
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync /* make gcc happy */
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync else //@todo dangerous!!!
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync//*****************************************************************************
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync//*****************************************************************************
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsyncDISDECL(DIS_SELREG) DISDetectSegReg(PDISCPUSTATE pCpu, POP_PARAMETER pParam)
d15e1d56958bda40cd12a7c3a71c962b5a710be2vboxsync /* Use specified SEG: prefix. */
17d67aeb3722c094c6493a3e9a9d0cdfb9453ecdvboxsync /* Guess segment register by parameter type. */
87c50c527af59e43745475c4b8ac907c5f9bc204vboxsync if (pParam->flags & (USE_REG_GEN32|USE_REG_GEN64|USE_REG_GEN16))
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync if (pParam->base.reg_gen == USE_REG_ESP || pParam->base.reg_gen == USE_REG_EBP)
17d67aeb3722c094c6493a3e9a9d0cdfb9453ecdvboxsync /* Default is use DS: for data access. */
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync//*****************************************************************************
c48c4d769ded37e2496f97dddbbd36dc62f244b1vboxsync//*****************************************************************************
47eb60db91f50291b3bd9b72b64d36341972a155vboxsyncDISDECL(uint8_t) DISQuerySegPrefixByte(PDISCPUSTATE pCpu)
f5ab5688c35373443d953e2a9fa8a054defdece8vboxsync return 0x26;
f5ab5688c35373443d953e2a9fa8a054defdece8vboxsync return 0x2E;
f5ab5688c35373443d953e2a9fa8a054defdece8vboxsync return 0x36;
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync return 0x3E;
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync return 0x64;
f5ab5688c35373443d953e2a9fa8a054defdece8vboxsync return 0x65;
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync * Returns the value of the specified 8 bits general purpose register
7eaaa8a4480370b82ef3735994f986f338fb4df2vboxsyncDISDECL(int) DISFetchReg8(PCCPUMCTXCORE pCtx, unsigned reg8, uint8_t *pVal)
0c587d7af645db20acefebcfc15b6f46c440ba4avboxsync AssertReturn(reg8 < ELEMENTS(g_aReg8Index), VERR_INVALID_PARAMETER);
f5ab5688c35373443d953e2a9fa8a054defdece8vboxsync * Returns the value of the specified 16 bits general purpose register
17d67aeb3722c094c6493a3e9a9d0cdfb9453ecdvboxsyncDISDECL(int) DISFetchReg16(PCCPUMCTXCORE pCtx, unsigned reg16, uint16_t *pVal)
7eaaa8a4480370b82ef3735994f986f338fb4df2vboxsync AssertReturn(reg16 < ELEMENTS(g_aReg16Index), VERR_INVALID_PARAMETER);
aca7a56d52c58d8b388343450503c22822fd6620vboxsync * Returns the value of the specified 32 bits general purpose register
aca7a56d52c58d8b388343450503c22822fd6620vboxsyncDISDECL(int) DISFetchReg32(PCCPUMCTXCORE pCtx, unsigned reg32, uint32_t *pVal)
aca7a56d52c58d8b388343450503c22822fd6620vboxsync AssertReturn(reg32 < ELEMENTS(g_aReg32Index), VERR_INVALID_PARAMETER);
17d67aeb3722c094c6493a3e9a9d0cdfb9453ecdvboxsync * Returns the value of the specified 64 bits general purpose register
87c50c527af59e43745475c4b8ac907c5f9bc204vboxsyncDISDECL(int) DISFetchReg64(PCCPUMCTXCORE pCtx, unsigned reg64, uint64_t *pVal)
aca7a56d52c58d8b388343450503c22822fd6620vboxsync AssertReturn(reg64 < ELEMENTS(g_aReg64Index), VERR_INVALID_PARAMETER);
0c587d7af645db20acefebcfc15b6f46c440ba4avboxsync * Returns the pointer to the specified 8 bits general purpose register
0c587d7af645db20acefebcfc15b6f46c440ba4avboxsyncDISDECL(int) DISPtrReg8(PCPUMCTXCORE pCtx, unsigned reg8, uint8_t **ppReg)
0c587d7af645db20acefebcfc15b6f46c440ba4avboxsync AssertReturn(reg8 < ELEMENTS(g_aReg8Index), VERR_INVALID_PARAMETER);
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync * Returns the pointer to the specified 16 bits general purpose register
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsyncDISDECL(int) DISPtrReg16(PCPUMCTXCORE pCtx, unsigned reg16, uint16_t **ppReg)
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync AssertReturn(reg16 < ELEMENTS(g_aReg16Index), VERR_INVALID_PARAMETER);
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync * Returns the pointer to the specified 32 bits general purpose register
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsyncDISDECL(int) DISPtrReg32(PCPUMCTXCORE pCtx, unsigned reg32, uint32_t **ppReg)
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync AssertReturn(reg32 < ELEMENTS(g_aReg32Index), VERR_INVALID_PARAMETER);
17d67aeb3722c094c6493a3e9a9d0cdfb9453ecdvboxsync * Returns the pointer to the specified 64 bits general purpose register
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsyncDISDECL(int) DISPtrReg64(PCPUMCTXCORE pCtx, unsigned reg64, uint64_t **ppReg)
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync AssertReturn(reg64 < ELEMENTS(g_aReg64Index), VERR_INVALID_PARAMETER);
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync * Returns the value of the specified segment register
47eb60db91f50291b3bd9b72b64d36341972a155vboxsyncDISDECL(int) DISFetchRegSeg(PCCPUMCTXCORE pCtx, DIS_SELREG sel, RTSEL *pVal)
c48c4d769ded37e2496f97dddbbd36dc62f244b1vboxsync AssertReturn((unsigned)sel < ELEMENTS(g_aRegSegIndex), VERR_INVALID_PARAMETER);
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync * Returns the value of the specified segment register including a pointer to the hidden register in the supplied cpu context
a0fb1a3d470c09467cd37844f38cf7152c9d2f75vboxsyncDISDECL(int) DISFetchRegSegEx(PCCPUMCTXCORE pCtx, DIS_SELREG sel, RTSEL *pVal, CPUMSELREGHID **ppSelHidReg)
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync AssertReturn((unsigned)sel < ELEMENTS(g_aRegSegIndex), VERR_INVALID_PARAMETER);
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync *ppSelHidReg = (CPUMSELREGHID *)((char *)pCtx + g_aRegHidSegIndex[sel]);
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync * Updates the value of the specified 64 bits general purpose register
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsyncDISDECL(int) DISWriteReg64(PCPUMCTXCORE pRegFrame, unsigned reg64, uint64_t val64)
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync AssertReturn(reg64 < ELEMENTS(g_aReg64Index), VERR_INVALID_PARAMETER);
return VINF_SUCCESS;
return VINF_SUCCESS;
return VINF_SUCCESS;
return VINF_SUCCESS;
DISDECL(int) DISQueryParamVal(PCPUMCTXCORE pCtx, PDISCPUSTATE pCpu, POP_PARAMETER pParam, POP_PARAMVAL pParamVal, PARAM_TYPE parmtype)
if (VBOX_FAILURE(DISFetchReg8(pCtx, pParam->base.reg_gen, &pParamVal->val.val8))) return VERR_INVALID_PARAMETER;
if (VBOX_FAILURE(DISFetchReg16(pCtx, pParam->base.reg_gen, &pParamVal->val.val16))) return VERR_INVALID_PARAMETER;
if (VBOX_FAILURE(DISFetchReg32(pCtx, pParam->base.reg_gen, &pParamVal->val.val32))) return VERR_INVALID_PARAMETER;
if (VBOX_FAILURE(DISFetchReg64(pCtx, pParam->base.reg_gen, &pParamVal->val.val64))) return VERR_INVALID_PARAMETER;
AssertFailed();
return VERR_INVALID_PARAMETER;
if (VBOX_FAILURE(DISFetchReg32(pCtx, pParam->index.reg_gen, &val32))) return VERR_INVALID_PARAMETER;
if (VBOX_FAILURE(DISFetchReg64(pCtx, pParam->index.reg_gen, &val64))) return VERR_INVALID_PARAMETER;
return VINF_SUCCESS;
if (pParam->flags & (USE_REG_GEN8|USE_REG_GEN16|USE_REG_GEN32|USE_REG_GEN64|USE_REG_FP|USE_REG_MMX|USE_REG_XMM|USE_REG_CR|USE_REG_DBG|USE_REG_SEG|USE_REG_TEST))
// Caller needs to interpret the register according to the instruction (source/target, special value etc)
return VINF_SUCCESS;
if (VBOX_FAILURE(DISFetchReg8(pCtx, pParam->base.reg_gen, &pParamVal->val.val8))) return VERR_INVALID_PARAMETER;
if (VBOX_FAILURE(DISFetchReg16(pCtx, pParam->base.reg_gen, &pParamVal->val.val16))) return VERR_INVALID_PARAMETER;
if (VBOX_FAILURE(DISFetchReg32(pCtx, pParam->base.reg_gen, &pParamVal->val.val32))) return VERR_INVALID_PARAMETER;
if (VBOX_FAILURE(DISFetchReg64(pCtx, pParam->base.reg_gen, &pParamVal->val.val64))) return VERR_INVALID_PARAMETER;
// Caller needs to interpret the register according to the instruction (source/target, special value etc)
return VINF_SUCCESS;
if (pParam->flags & (USE_IMMEDIATE16|USE_IMMEDIATE16_REL|USE_IMMEDIATE_ADDR_0_16|USE_IMMEDIATE16_SX8))
AssertMsg(pParamVal->size == pParam->size || ((pParam->size == 1) && (pParam->flags & USE_IMMEDIATE16_SX8)), ("pParamVal->size %d vs %d EIP=%VGv\n", pParamVal->size, pParam->size, pCtx->eip) );
if (pParam->flags & (USE_IMMEDIATE32|USE_IMMEDIATE32_REL|USE_IMMEDIATE_ADDR_0_32|USE_IMMEDIATE32_SX8))
Assert(pParamVal->size == pParam->size || ((pParam->size == 1) && (pParam->flags & USE_IMMEDIATE32_SX8)) );
Assert(pParamVal->size == pParam->size || ((pParam->size == 1) && (pParam->flags & USE_IMMEDIATE64_SX8)) );
return VINF_SUCCESS;
DISDECL(int) DISQueryParamRegPtr(PCPUMCTXCORE pCtx, PDISCPUSTATE pCpu, POP_PARAMETER pParam, void **ppReg, size_t *pcbSize)
if (pParam->flags & (USE_REG_GEN8|USE_REG_GEN16|USE_REG_GEN32|USE_REG_FP|USE_REG_MMX|USE_REG_XMM|USE_REG_CR|USE_REG_DBG|USE_REG_SEG|USE_REG_TEST))
return VINF_SUCCESS;
return VINF_SUCCESS;
return VINF_SUCCESS;
return VINF_SUCCESS;
return VERR_INVALID_PARAMETER;