VBox/Disassembler/DisasmReg.cpp

	DisasmReg.cpp revision d8c7549806316fefc91a86b1ff20a6c313297c62
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync/** @file
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync *
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync * VBox disassembler:
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync * Core components
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync */
4bc1bbf45f30ff3ca38c2ad006836e490972c7ccvboxsync
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync/*
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync * Copyright (C) 2006-2007 Sun Microsystems, Inc.
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync *
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync * This file is part of VirtualBox Open Source Edition (OSE), as
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync * available from http://www.virtualbox.org. This file is free software;
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync * you can redistribute it and/or modify it under the terms of the GNU
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync * General Public License (GPL) as published by the Free Software
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync * Foundation, in version 2 as it comes in the "COPYING" file of the
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync *
a3d06a524c4f1cde2f0eada83656543d5a24115dvboxsync * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync * Clara, CA 95054 USA or visit http://www.sun.com if you need
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync * additional information or have any questions.
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync */
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync/*******************************************************************************
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync*   Header Files                                                               *
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync*******************************************************************************/
88350256a6c78b8631aba5aa5ce249d90a8514a2vboxsync#define LOG_GROUP LOG_GROUP_DIS
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync#ifdef USING_VISUAL_STUDIO
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync# include <stdafx.h>
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync#endif
943d182735b76ecae26ea011cb7b87e449aafea8vboxsync
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync#include <VBox/dis.h>
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync#include <VBox/disopcode.h>
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync#include <VBox/cpum.h>
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync#include <VBox/err.h>
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync#include <VBox/log.h>
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync#include <iprt/assert.h>
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync#include <iprt/string.h>
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync#include <iprt/stdarg.h>
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync#include "DisasmInternal.h"
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync#include "DisasmTables.h"
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync#if !defined(DIS_CORE_ONLY) && defined(LOG_ENABLED)
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync# include <stdlib.h>
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync# include <stdio.h>
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync#endif
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync/*******************************************************************************
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync*   Global Variables                                                           *
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync*******************************************************************************/
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync/**
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync * Array for accessing 64-bit general registers in VMMREGFRAME structure
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync * by register's index from disasm.
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync */
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsyncstatic const unsigned g_aReg64Index[] =
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync{
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync    RT_OFFSETOF(CPUMCTXCORE, rax),        /* USE_REG_RAX */
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync    RT_OFFSETOF(CPUMCTXCORE, rcx),        /* USE_REG_RCX */
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync    RT_OFFSETOF(CPUMCTXCORE, rdx),        /* USE_REG_RDX */
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync    RT_OFFSETOF(CPUMCTXCORE, rbx),        /* USE_REG_RBX */
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync    RT_OFFSETOF(CPUMCTXCORE, rsp),        /* USE_REG_RSP */
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync    RT_OFFSETOF(CPUMCTXCORE, rbp),        /* USE_REG_RBP */
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync    RT_OFFSETOF(CPUMCTXCORE, rsi),        /* USE_REG_RSI */
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync    RT_OFFSETOF(CPUMCTXCORE, rdi),        /* USE_REG_RDI */
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync    RT_OFFSETOF(CPUMCTXCORE, r8),         /* USE_REG_R8  */
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync    RT_OFFSETOF(CPUMCTXCORE, r9),         /* USE_REG_R9  */
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync    RT_OFFSETOF(CPUMCTXCORE, r10),        /* USE_REG_R10 */
c6adb272ec43d5eaadb1493cb2bf45f2f8adf588vboxsync    RT_OFFSETOF(CPUMCTXCORE, r11),        /* USE_REG_R11 */
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync    RT_OFFSETOF(CPUMCTXCORE, r12),        /* USE_REG_R12 */
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync    RT_OFFSETOF(CPUMCTXCORE, r13),        /* USE_REG_R13 */
58b7773f17a933ab8d53f450bed0afcf2f003508vboxsync    RT_OFFSETOF(CPUMCTXCORE, r14),        /* USE_REG_R14 */
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync    RT_OFFSETOF(CPUMCTXCORE, r15)         /* USE_REG_R15 */
c48c4d769ded37e2496f97dddbbd36dc62f244b1vboxsync};
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync/**
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync * Macro for accessing 64-bit general purpose registers in CPUMCTXCORE structure.
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync */
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync#define DIS_READ_REG64(p, idx)       (*(uint64_t *)((char *)(p) + g_aReg64Index[idx]))
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync#define DIS_WRITE_REG64(p, idx, val) (*(uint64_t *)((char *)(p) + g_aReg64Index[idx]) = val)
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync#define DIS_PTR_REG64(p, idx)        ( (uint64_t *)((char *)(p) + g_aReg64Index[idx]))
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync/**
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync * Array for accessing 32-bit general registers in VMMREGFRAME structure
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync * by register's index from disasm.
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync */
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsyncstatic const unsigned g_aReg32Index[] =
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync{
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync    RT_OFFSETOF(CPUMCTXCORE, eax),        /* USE_REG_EAX */
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync    RT_OFFSETOF(CPUMCTXCORE, ecx),        /* USE_REG_ECX */
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync    RT_OFFSETOF(CPUMCTXCORE, edx),        /* USE_REG_EDX */
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync    RT_OFFSETOF(CPUMCTXCORE, ebx),        /* USE_REG_EBX */
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync    RT_OFFSETOF(CPUMCTXCORE, esp),        /* USE_REG_ESP */
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync    RT_OFFSETOF(CPUMCTXCORE, ebp),        /* USE_REG_EBP */
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync    RT_OFFSETOF(CPUMCTXCORE, esi),        /* USE_REG_ESI */
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync    RT_OFFSETOF(CPUMCTXCORE, edi),        /* USE_REG_EDI */
c6adb272ec43d5eaadb1493cb2bf45f2f8adf588vboxsync    RT_OFFSETOF(CPUMCTXCORE, r8),         /* USE_REG_R8D */
b28fef07fef379ecc179e0bc0d5d1be753e482b5vboxsync    RT_OFFSETOF(CPUMCTXCORE, r9),         /* USE_REG_R9D */
c48c4d769ded37e2496f97dddbbd36dc62f244b1vboxsync    RT_OFFSETOF(CPUMCTXCORE, r10),        /* USE_REG_R10D */
c48c4d769ded37e2496f97dddbbd36dc62f244b1vboxsync    RT_OFFSETOF(CPUMCTXCORE, r11),        /* USE_REG_R11D */
257927abbaa6d9774427049fcbea552cda362281vboxsync    RT_OFFSETOF(CPUMCTXCORE, r12),        /* USE_REG_R12D */
257927abbaa6d9774427049fcbea552cda362281vboxsync    RT_OFFSETOF(CPUMCTXCORE, r13),        /* USE_REG_R13D */
257927abbaa6d9774427049fcbea552cda362281vboxsync    RT_OFFSETOF(CPUMCTXCORE, r14),        /* USE_REG_R14D */
257927abbaa6d9774427049fcbea552cda362281vboxsync    RT_OFFSETOF(CPUMCTXCORE, r15)         /* USE_REG_R15D */
24a8dd4360c4b4588fd2c340dd7687379a45e02evboxsync};
3c49234930c10a52368b992781dae0306a72b5f5vboxsync
c48c4d769ded37e2496f97dddbbd36dc62f244b1vboxsync/**
c48c4d769ded37e2496f97dddbbd36dc62f244b1vboxsync * Macro for accessing 32-bit general purpose registers in CPUMCTXCORE structure.
c48c4d769ded37e2496f97dddbbd36dc62f244b1vboxsync */
c48c4d769ded37e2496f97dddbbd36dc62f244b1vboxsync#define DIS_READ_REG32(p, idx)       (*(uint32_t *)((char *)(p) + g_aReg32Index[idx]))
1d17a5f9688f3622ffe088b664588629b1e95801vboxsync/* From http://www.cs.cmu.edu/~fp/courses/15213-s06/misc/asm64-handout.pdf:
14dcfe007d2a64583946ed5e4cfdb458a7f7f03bvboxsync * ``Perhaps unexpectedly, instructions that move or generate 32-bit register
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync *   values also set the upper 32 bits of the register to zero. Consequently
a3d06a524c4f1cde2f0eada83656543d5a24115dvboxsync *   there is no need for an instruction movzlq.''
a3d06a524c4f1cde2f0eada83656543d5a24115dvboxsync */
a3d06a524c4f1cde2f0eada83656543d5a24115dvboxsync#define DIS_WRITE_REG32(p, idx, val) (*(uint64_t *)((char *)(p) + g_aReg32Index[idx]) = (uint32_t)val)
a3d06a524c4f1cde2f0eada83656543d5a24115dvboxsync#define DIS_PTR_REG32(p, idx)        ( (uint32_t *)((char *)(p) + g_aReg32Index[idx]))
81d1b221c2dfff6900e970e273dbb4e81ef6b5d9vboxsync
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync/**
4bc1bbf45f30ff3ca38c2ad006836e490972c7ccvboxsync * Array for accessing 16-bit general registers in CPUMCTXCORE structure
4bc1bbf45f30ff3ca38c2ad006836e490972c7ccvboxsync * by register's index from disasm.
4bc1bbf45f30ff3ca38c2ad006836e490972c7ccvboxsync */
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsyncstatic const unsigned g_aReg16Index[] =
3684b2b9eeb77285df2dc641fcf6f70805568be8vboxsync{
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync    RT_OFFSETOF(CPUMCTXCORE, eax),        /* USE_REG_AX */
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync    RT_OFFSETOF(CPUMCTXCORE, ecx),        /* USE_REG_CX */
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync    RT_OFFSETOF(CPUMCTXCORE, edx),        /* USE_REG_DX */
73e8df2e481cb3697372a3cf4acffd068a7f1296vboxsync    RT_OFFSETOF(CPUMCTXCORE, ebx),        /* USE_REG_BX */
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync    RT_OFFSETOF(CPUMCTXCORE, esp),        /* USE_REG_SP */
d293c8e7a1adaf427e7a361add878676749b7da6vboxsync    RT_OFFSETOF(CPUMCTXCORE, ebp),        /* USE_REG_BP */
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync    RT_OFFSETOF(CPUMCTXCORE, esi),        /* USE_REG_SI */
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync    RT_OFFSETOF(CPUMCTXCORE, edi),        /* USE_REG_DI */
73e8df2e481cb3697372a3cf4acffd068a7f1296vboxsync    RT_OFFSETOF(CPUMCTXCORE, r8),         /* USE_REG_R8W */
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync    RT_OFFSETOF(CPUMCTXCORE, r9),         /* USE_REG_R9W */
d293c8e7a1adaf427e7a361add878676749b7da6vboxsync    RT_OFFSETOF(CPUMCTXCORE, r10),        /* USE_REG_R10W */
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync    RT_OFFSETOF(CPUMCTXCORE, r11),        /* USE_REG_R11W */
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync    RT_OFFSETOF(CPUMCTXCORE, r12),        /* USE_REG_R12W */
73e8df2e481cb3697372a3cf4acffd068a7f1296vboxsync    RT_OFFSETOF(CPUMCTXCORE, r13),        /* USE_REG_R13W */
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync    RT_OFFSETOF(CPUMCTXCORE, r14),        /* USE_REG_R14W */
d293c8e7a1adaf427e7a361add878676749b7da6vboxsync    RT_OFFSETOF(CPUMCTXCORE, r15)         /* USE_REG_R15W */
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync};
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync
73e8df2e481cb3697372a3cf4acffd068a7f1296vboxsync/**
9704f1d0180960069e2c4eb8fe2ddee350910e5dvboxsync * Macro for accessing 16-bit general purpose registers in CPUMCTXCORE structure.
d293c8e7a1adaf427e7a361add878676749b7da6vboxsync */
9704f1d0180960069e2c4eb8fe2ddee350910e5dvboxsync#define DIS_READ_REG16(p, idx)          (*(uint16_t *)((char *)(p) + g_aReg16Index[idx]))
9704f1d0180960069e2c4eb8fe2ddee350910e5dvboxsync#define DIS_WRITE_REG16(p, idx, val)    (*(uint16_t *)((char *)(p) + g_aReg16Index[idx]) = val)
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync#define DIS_PTR_REG16(p, idx)           ( (uint16_t *)((char *)(p) + g_aReg16Index[idx]))
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync
3684b2b9eeb77285df2dc641fcf6f70805568be8vboxsync/**
a3d06a524c4f1cde2f0eada83656543d5a24115dvboxsync * Array for accessing 8-bit general registers in CPUMCTXCORE structure
a3d06a524c4f1cde2f0eada83656543d5a24115dvboxsync * by register's index from disasm.
a3d06a524c4f1cde2f0eada83656543d5a24115dvboxsync */
a3d06a524c4f1cde2f0eada83656543d5a24115dvboxsyncstatic const unsigned g_aReg8Index[] =
a3d06a524c4f1cde2f0eada83656543d5a24115dvboxsync{
a3d06a524c4f1cde2f0eada83656543d5a24115dvboxsync    RT_OFFSETOF(CPUMCTXCORE, eax),        /* USE_REG_AL */
a3d06a524c4f1cde2f0eada83656543d5a24115dvboxsync    RT_OFFSETOF(CPUMCTXCORE, ecx),        /* USE_REG_CL */
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync    RT_OFFSETOF(CPUMCTXCORE, edx),        /* USE_REG_DL */
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync    RT_OFFSETOF(CPUMCTXCORE, ebx),        /* USE_REG_BL */
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync    RT_OFFSETOF(CPUMCTXCORE, eax) + 1,    /* USE_REG_AH */
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync    RT_OFFSETOF(CPUMCTXCORE, ecx) + 1,    /* USE_REG_CH */
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync    RT_OFFSETOF(CPUMCTXCORE, edx) + 1,    /* USE_REG_DH */
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync    RT_OFFSETOF(CPUMCTXCORE, ebx) + 1,    /* USE_REG_BH */
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync    RT_OFFSETOF(CPUMCTXCORE, r8),         /* USE_REG_R8B */
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync    RT_OFFSETOF(CPUMCTXCORE, r9),         /* USE_REG_R9B */
17d67aeb3722c094c6493a3e9a9d0cdfb9453ecdvboxsync    RT_OFFSETOF(CPUMCTXCORE, r10),        /* USE_REG_R10B*/
87c50c527af59e43745475c4b8ac907c5f9bc204vboxsync    RT_OFFSETOF(CPUMCTXCORE, r11),        /* USE_REG_R11B */
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync    RT_OFFSETOF(CPUMCTXCORE, r12),        /* USE_REG_R12B */
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync    RT_OFFSETOF(CPUMCTXCORE, r13),        /* USE_REG_R13B */
17d67aeb3722c094c6493a3e9a9d0cdfb9453ecdvboxsync    RT_OFFSETOF(CPUMCTXCORE, r14),        /* USE_REG_R14B */
87c50c527af59e43745475c4b8ac907c5f9bc204vboxsync    RT_OFFSETOF(CPUMCTXCORE, r15),        /* USE_REG_R15B */
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync    RT_OFFSETOF(CPUMCTXCORE, esp),        /* USE_REG_SPL; with REX prefix only */
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync    RT_OFFSETOF(CPUMCTXCORE, ebp),        /* USE_REG_BPL; with REX prefix only */
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync    RT_OFFSETOF(CPUMCTXCORE, esi),        /* USE_REG_SIL; with REX prefix only */
58b7773f17a933ab8d53f450bed0afcf2f003508vboxsync    RT_OFFSETOF(CPUMCTXCORE, edi)         /* USE_REG_DIL; with REX prefix only */
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync};
58b7773f17a933ab8d53f450bed0afcf2f003508vboxsync
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync/**
58b7773f17a933ab8d53f450bed0afcf2f003508vboxsync * Macro for accessing 8-bit general purpose registers in CPUMCTXCORE structure.
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync */
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync#define DIS_READ_REG8(p, idx)           (*(uint8_t *)((char *)(p) + g_aReg8Index[idx]))
58b7773f17a933ab8d53f450bed0afcf2f003508vboxsync#define DIS_WRITE_REG8(p, idx, val)     (*(uint8_t *)((char *)(p) + g_aReg8Index[idx]) = val)
17d67aeb3722c094c6493a3e9a9d0cdfb9453ecdvboxsync#define DIS_PTR_REG8(p, idx)            ( (uint8_t *)((char *)(p) + g_aReg8Index[idx]))
17d67aeb3722c094c6493a3e9a9d0cdfb9453ecdvboxsync
14dcfe007d2a64583946ed5e4cfdb458a7f7f03bvboxsync/**
14dcfe007d2a64583946ed5e4cfdb458a7f7f03bvboxsync * Array for accessing segment registers in CPUMCTXCORE structure
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync * by register's index from disasm.
7eaaa8a4480370b82ef3735994f986f338fb4df2vboxsync */
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsyncstatic const unsigned g_aRegSegIndex[] =
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync{
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync    RT_OFFSETOF(CPUMCTXCORE, es),         /* DIS_SELREG_ES */
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync    RT_OFFSETOF(CPUMCTXCORE, cs),         /* DIS_SELREG_CS */
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync    RT_OFFSETOF(CPUMCTXCORE, ss),         /* DIS_SELREG_SS */
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync    RT_OFFSETOF(CPUMCTXCORE, ds),         /* DIS_SELREG_DS */
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync    RT_OFFSETOF(CPUMCTXCORE, fs),         /* DIS_SELREG_FS */
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync    RT_OFFSETOF(CPUMCTXCORE, gs)          /* DIS_SELREG_GS */
0c587d7af645db20acefebcfc15b6f46c440ba4avboxsync};
cf5af7fccfec4bef83f4ec21662d6a6e6cbe3835vboxsync
cf5af7fccfec4bef83f4ec21662d6a6e6cbe3835vboxsyncstatic const unsigned g_aRegHidSegIndex[] =
0c587d7af645db20acefebcfc15b6f46c440ba4avboxsync{
17d67aeb3722c094c6493a3e9a9d0cdfb9453ecdvboxsync    RT_OFFSETOF(CPUMCTXCORE, esHid),         /* DIS_SELREG_ES */
17d67aeb3722c094c6493a3e9a9d0cdfb9453ecdvboxsync    RT_OFFSETOF(CPUMCTXCORE, csHid),         /* DIS_SELREG_CS */
17d67aeb3722c094c6493a3e9a9d0cdfb9453ecdvboxsync    RT_OFFSETOF(CPUMCTXCORE, ssHid),         /* DIS_SELREG_SS */
17d67aeb3722c094c6493a3e9a9d0cdfb9453ecdvboxsync    RT_OFFSETOF(CPUMCTXCORE, dsHid),         /* DIS_SELREG_DS */
87c50c527af59e43745475c4b8ac907c5f9bc204vboxsync    RT_OFFSETOF(CPUMCTXCORE, fsHid),         /* DIS_SELREG_FS */
87c50c527af59e43745475c4b8ac907c5f9bc204vboxsync    RT_OFFSETOF(CPUMCTXCORE, gsHid)          /* DIS_SELREG_GS */
87c50c527af59e43745475c4b8ac907c5f9bc204vboxsync};
87c50c527af59e43745475c4b8ac907c5f9bc204vboxsync
0c587d7af645db20acefebcfc15b6f46c440ba4avboxsync/**
0c587d7af645db20acefebcfc15b6f46c440ba4avboxsync * Macro for accessing segment registers in CPUMCTXCORE structure.
0c587d7af645db20acefebcfc15b6f46c440ba4avboxsync */
0c587d7af645db20acefebcfc15b6f46c440ba4avboxsync#define DIS_READ_REGSEG(p, idx)         (*((uint16_t *)((char *)(p) + g_aRegSegIndex[idx])))
17d67aeb3722c094c6493a3e9a9d0cdfb9453ecdvboxsync#define DIS_WRITE_REGSEG(p, idx, val)   (*((uint16_t *)((char *)(p) + g_aRegSegIndex[idx])) = val)
17d67aeb3722c094c6493a3e9a9d0cdfb9453ecdvboxsync
cf5af7fccfec4bef83f4ec21662d6a6e6cbe3835vboxsync//*****************************************************************************
cf5af7fccfec4bef83f4ec21662d6a6e6cbe3835vboxsync//*****************************************************************************
0c587d7af645db20acefebcfc15b6f46c440ba4avboxsyncDISDECL(int) DISGetParamSize(PDISCPUSTATE pCpu, POP_PARAMETER pParam)
0c587d7af645db20acefebcfc15b6f46c440ba4avboxsync{
0c587d7af645db20acefebcfc15b6f46c440ba4avboxsync    int subtype = OP_PARM_VSUBTYPE(pParam->param);
cf5af7fccfec4bef83f4ec21662d6a6e6cbe3835vboxsync
cf5af7fccfec4bef83f4ec21662d6a6e6cbe3835vboxsync    if (subtype == OP_PARM_v)
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync    {
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync        switch(pCpu->opmode)
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync        {
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync        case CPUMODE_32BIT:
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync            subtype = OP_PARM_d;
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync            break;
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync        case CPUMODE_64BIT:
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync            subtype = OP_PARM_q;
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync            break;
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync        case CPUMODE_16BIT:
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync            subtype = OP_PARM_w;
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync            break;
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync        default:
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync            /* make gcc happy */
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync            break;
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync        }
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync    }
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync    switch(subtype)
9704f1d0180960069e2c4eb8fe2ddee350910e5dvboxsync    {
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync    case OP_PARM_b:
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync        return 1;
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync    case OP_PARM_w:
f1acc1e99894e016bd1a6ee65c56b3fc064fa4ebvboxsync        return 2;
09ed5ee011f3a6cd9d4742216ad3bb7dbf855641vboxsync
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync    case OP_PARM_d:
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync        return 4;
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync    case OP_PARM_q:
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync    case OP_PARM_dq:
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync        return 8;
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync    case OP_PARM_p: /* far pointer */
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync        if (pCpu->addrmode == CPUMODE_32BIT)
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync            return 6;   /* 16:32 */
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync        else
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync        if (pCpu->addrmode == CPUMODE_64BIT)
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync            return 12;  /* 16:64 */
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync        else
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync            return 4;   /* 16:16 */
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync    default:
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync        if (pParam->size)
45c2de093cddc990b8d1583aa49b9a40de7a3d97vboxsync            return pParam->size;
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync        else //@todo dangerous!!!
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync            return 4;
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync    }
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync}
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync//*****************************************************************************
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync//*****************************************************************************
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsyncDISDECL(DIS_SELREG) DISDetectSegReg(PDISCPUSTATE pCpu, POP_PARAMETER pParam)
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync{
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync    if (pCpu->prefix & PREFIX_SEG)
d15e1d56958bda40cd12a7c3a71c962b5a710be2vboxsync    {
d15e1d56958bda40cd12a7c3a71c962b5a710be2vboxsync        /* Use specified SEG: prefix. */
d15e1d56958bda40cd12a7c3a71c962b5a710be2vboxsync        return pCpu->enmPrefixSeg;
d15e1d56958bda40cd12a7c3a71c962b5a710be2vboxsync    }
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync    else
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync    {
17d67aeb3722c094c6493a3e9a9d0cdfb9453ecdvboxsync        /* Guess segment register by parameter type. */
87c50c527af59e43745475c4b8ac907c5f9bc204vboxsync        if (pParam->flags & (USE_REG_GEN32|USE_REG_GEN64|USE_REG_GEN16))
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync        {
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync            AssertCompile(USE_REG_ESP == USE_REG_RSP);
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync            AssertCompile(USE_REG_EBP == USE_REG_RBP);
87c50c527af59e43745475c4b8ac907c5f9bc204vboxsync            AssertCompile(USE_REG_ESP == USE_REG_SP);
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync            AssertCompile(USE_REG_EBP == USE_REG_BP);
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync            if (pParam->base.reg_gen == USE_REG_ESP || pParam->base.reg_gen == USE_REG_EBP)
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync                return DIS_SELREG_SS;
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync        }
17d67aeb3722c094c6493a3e9a9d0cdfb9453ecdvboxsync        /* Default is use DS: for data access. */
87c50c527af59e43745475c4b8ac907c5f9bc204vboxsync        return DIS_SELREG_DS;
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync    }
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync}
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync//*****************************************************************************
c48c4d769ded37e2496f97dddbbd36dc62f244b1vboxsync//*****************************************************************************
47eb60db91f50291b3bd9b72b64d36341972a155vboxsyncDISDECL(uint8_t) DISQuerySegPrefixByte(PDISCPUSTATE pCpu)
c48c4d769ded37e2496f97dddbbd36dc62f244b1vboxsync{
c48c4d769ded37e2496f97dddbbd36dc62f244b1vboxsync    Assert(pCpu->prefix & PREFIX_SEG);
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync    switch(pCpu->enmPrefixSeg)
7eaaa8a4480370b82ef3735994f986f338fb4df2vboxsync    {
7eaaa8a4480370b82ef3735994f986f338fb4df2vboxsync    case DIS_SELREG_ES:
f5ab5688c35373443d953e2a9fa8a054defdece8vboxsync        return 0x26;
f5ab5688c35373443d953e2a9fa8a054defdece8vboxsync    case DIS_SELREG_CS:
f5ab5688c35373443d953e2a9fa8a054defdece8vboxsync        return 0x2E;
f5ab5688c35373443d953e2a9fa8a054defdece8vboxsync    case DIS_SELREG_SS:
f5ab5688c35373443d953e2a9fa8a054defdece8vboxsync        return 0x36;
f5ab5688c35373443d953e2a9fa8a054defdece8vboxsync    case DIS_SELREG_DS:
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync        return 0x3E;
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync    case DIS_SELREG_FS:
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync        return 0x64;
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync    case DIS_SELREG_GS:
f5ab5688c35373443d953e2a9fa8a054defdece8vboxsync        return 0x65;
f5ab5688c35373443d953e2a9fa8a054defdece8vboxsync    default:
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync        AssertFailed();
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync        return 0;
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync    }
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync}
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync
9704f1d0180960069e2c4eb8fe2ddee350910e5dvboxsync/**
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync * Returns the value of the specified 8 bits general purpose register
7eaaa8a4480370b82ef3735994f986f338fb4df2vboxsync *
7eaaa8a4480370b82ef3735994f986f338fb4df2vboxsync */
7eaaa8a4480370b82ef3735994f986f338fb4df2vboxsyncDISDECL(int) DISFetchReg8(PCCPUMCTXCORE pCtx, unsigned reg8, uint8_t *pVal)
0c587d7af645db20acefebcfc15b6f46c440ba4avboxsync{
0c587d7af645db20acefebcfc15b6f46c440ba4avboxsync    AssertReturn(reg8 < ELEMENTS(g_aReg8Index), VERR_INVALID_PARAMETER);
0c587d7af645db20acefebcfc15b6f46c440ba4avboxsync
f5ab5688c35373443d953e2a9fa8a054defdece8vboxsync    *pVal = DIS_READ_REG8(pCtx, reg8);
f5ab5688c35373443d953e2a9fa8a054defdece8vboxsync    return VINF_SUCCESS;
f5ab5688c35373443d953e2a9fa8a054defdece8vboxsync}
f5ab5688c35373443d953e2a9fa8a054defdece8vboxsync
f5ab5688c35373443d953e2a9fa8a054defdece8vboxsync/**
f5ab5688c35373443d953e2a9fa8a054defdece8vboxsync * Returns the value of the specified 16 bits general purpose register
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync *
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync */
17d67aeb3722c094c6493a3e9a9d0cdfb9453ecdvboxsyncDISDECL(int) DISFetchReg16(PCCPUMCTXCORE pCtx, unsigned reg16, uint16_t *pVal)
87c50c527af59e43745475c4b8ac907c5f9bc204vboxsync{
7eaaa8a4480370b82ef3735994f986f338fb4df2vboxsync    AssertReturn(reg16 < ELEMENTS(g_aReg16Index), VERR_INVALID_PARAMETER);
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync    *pVal = DIS_READ_REG16(pCtx, reg16);
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync    return VINF_SUCCESS;
0c587d7af645db20acefebcfc15b6f46c440ba4avboxsync}
0c587d7af645db20acefebcfc15b6f46c440ba4avboxsync
0c587d7af645db20acefebcfc15b6f46c440ba4avboxsync/**
aca7a56d52c58d8b388343450503c22822fd6620vboxsync * Returns the value of the specified 32 bits general purpose register
17d67aeb3722c094c6493a3e9a9d0cdfb9453ecdvboxsync *
87c50c527af59e43745475c4b8ac907c5f9bc204vboxsync */
aca7a56d52c58d8b388343450503c22822fd6620vboxsyncDISDECL(int) DISFetchReg32(PCCPUMCTXCORE pCtx, unsigned reg32, uint32_t *pVal)
aca7a56d52c58d8b388343450503c22822fd6620vboxsync{
aca7a56d52c58d8b388343450503c22822fd6620vboxsync    AssertReturn(reg32 < ELEMENTS(g_aReg32Index), VERR_INVALID_PARAMETER);
17d67aeb3722c094c6493a3e9a9d0cdfb9453ecdvboxsync
87c50c527af59e43745475c4b8ac907c5f9bc204vboxsync    *pVal = DIS_READ_REG32(pCtx, reg32);
aca7a56d52c58d8b388343450503c22822fd6620vboxsync    return VINF_SUCCESS;
aca7a56d52c58d8b388343450503c22822fd6620vboxsync}
aca7a56d52c58d8b388343450503c22822fd6620vboxsync
aca7a56d52c58d8b388343450503c22822fd6620vboxsync/**
17d67aeb3722c094c6493a3e9a9d0cdfb9453ecdvboxsync * Returns the value of the specified 64 bits general purpose register
17d67aeb3722c094c6493a3e9a9d0cdfb9453ecdvboxsync *
87c50c527af59e43745475c4b8ac907c5f9bc204vboxsync */
87c50c527af59e43745475c4b8ac907c5f9bc204vboxsyncDISDECL(int) DISFetchReg64(PCCPUMCTXCORE pCtx, unsigned reg64, uint64_t *pVal)
aca7a56d52c58d8b388343450503c22822fd6620vboxsync{
aca7a56d52c58d8b388343450503c22822fd6620vboxsync    AssertReturn(reg64 < ELEMENTS(g_aReg64Index), VERR_INVALID_PARAMETER);
aca7a56d52c58d8b388343450503c22822fd6620vboxsync
aca7a56d52c58d8b388343450503c22822fd6620vboxsync    *pVal = DIS_READ_REG64(pCtx, reg64);
0c587d7af645db20acefebcfc15b6f46c440ba4avboxsync    return VINF_SUCCESS;
0c587d7af645db20acefebcfc15b6f46c440ba4avboxsync}
0c587d7af645db20acefebcfc15b6f46c440ba4avboxsync
0c587d7af645db20acefebcfc15b6f46c440ba4avboxsync/**
0c587d7af645db20acefebcfc15b6f46c440ba4avboxsync * Returns the pointer to the specified 8 bits general purpose register
0c587d7af645db20acefebcfc15b6f46c440ba4avboxsync *
0c587d7af645db20acefebcfc15b6f46c440ba4avboxsync */
0c587d7af645db20acefebcfc15b6f46c440ba4avboxsyncDISDECL(int) DISPtrReg8(PCPUMCTXCORE pCtx, unsigned reg8, uint8_t **ppReg)
0c587d7af645db20acefebcfc15b6f46c440ba4avboxsync{
0c587d7af645db20acefebcfc15b6f46c440ba4avboxsync    AssertReturn(reg8 < ELEMENTS(g_aReg8Index), VERR_INVALID_PARAMETER);
0c587d7af645db20acefebcfc15b6f46c440ba4avboxsync
0c587d7af645db20acefebcfc15b6f46c440ba4avboxsync    *ppReg = DIS_PTR_REG8(pCtx, reg8);
0c587d7af645db20acefebcfc15b6f46c440ba4avboxsync    return VINF_SUCCESS;
cf5af7fccfec4bef83f4ec21662d6a6e6cbe3835vboxsync}
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync/**
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync * Returns the pointer to the specified 16 bits general purpose register
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync *
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync */
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsyncDISDECL(int) DISPtrReg16(PCPUMCTXCORE pCtx, unsigned reg16, uint16_t **ppReg)
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync{
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync    AssertReturn(reg16 < ELEMENTS(g_aReg16Index), VERR_INVALID_PARAMETER);
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync    *ppReg = DIS_PTR_REG16(pCtx, reg16);
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync    return VINF_SUCCESS;
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync}
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync/**
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync * Returns the pointer to the specified 32 bits general purpose register
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync *
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync */
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsyncDISDECL(int) DISPtrReg32(PCPUMCTXCORE pCtx, unsigned reg32, uint32_t **ppReg)
7eaaa8a4480370b82ef3735994f986f338fb4df2vboxsync{
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync    AssertReturn(reg32 < ELEMENTS(g_aReg32Index), VERR_INVALID_PARAMETER);
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync    *ppReg = DIS_PTR_REG32(pCtx, reg32);
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync    return VINF_SUCCESS;
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync}
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync/**
17d67aeb3722c094c6493a3e9a9d0cdfb9453ecdvboxsync * Returns the pointer to the specified 64 bits general purpose register
87c50c527af59e43745475c4b8ac907c5f9bc204vboxsync *
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync */
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsyncDISDECL(int) DISPtrReg64(PCPUMCTXCORE pCtx, unsigned reg64, uint64_t **ppReg)
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync{
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync    AssertReturn(reg64 < ELEMENTS(g_aReg64Index), VERR_INVALID_PARAMETER);
87c50c527af59e43745475c4b8ac907c5f9bc204vboxsync
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync    *ppReg = DIS_PTR_REG64(pCtx, reg64);
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync    return VINF_SUCCESS;
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync}
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync/**
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync * Returns the value of the specified segment register
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync *
c48c4d769ded37e2496f97dddbbd36dc62f244b1vboxsync */
47eb60db91f50291b3bd9b72b64d36341972a155vboxsyncDISDECL(int) DISFetchRegSeg(PCCPUMCTXCORE pCtx, DIS_SELREG sel, RTSEL *pVal)
c48c4d769ded37e2496f97dddbbd36dc62f244b1vboxsync{
c48c4d769ded37e2496f97dddbbd36dc62f244b1vboxsync    AssertReturn((unsigned)sel < ELEMENTS(g_aRegSegIndex), VERR_INVALID_PARAMETER);
4d5da2bfd5523ad009912e6e0cfb8bf480160e32vboxsync
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync    AssertCompile(sizeof(uint16_t) == sizeof(RTSEL));
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync    *pVal = DIS_READ_REGSEG(pCtx, sel);
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync    return VINF_SUCCESS;
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync}
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync/**
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync * Returns the value of the specified segment register including a pointer to the hidden register in the supplied cpu context
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync *
a0fb1a3d470c09467cd37844f38cf7152c9d2f75vboxsync */
a0fb1a3d470c09467cd37844f38cf7152c9d2f75vboxsyncDISDECL(int) DISFetchRegSegEx(PCCPUMCTXCORE pCtx, DIS_SELREG sel, RTSEL *pVal, CPUMSELREGHID **ppSelHidReg)
8e5c5c9547558e845335d3077d17422b4ee85b89vboxsync{
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync    AssertReturn((unsigned)sel < ELEMENTS(g_aRegSegIndex), VERR_INVALID_PARAMETER);
17d67aeb3722c094c6493a3e9a9d0cdfb9453ecdvboxsync
87c50c527af59e43745475c4b8ac907c5f9bc204vboxsync    AssertCompile(sizeof(uint16_t) == sizeof(RTSEL));
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync    *pVal = DIS_READ_REGSEG(pCtx, sel);
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync    *ppSelHidReg = (CPUMSELREGHID *)((char *)pCtx + g_aRegHidSegIndex[sel]);
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync    return VINF_SUCCESS;
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync}
ed970880a556512196471e9cdd0d793e68943ec6vboxsync
87c50c527af59e43745475c4b8ac907c5f9bc204vboxsync/**
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync * Updates the value of the specified 64 bits general purpose register
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync *
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync */
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsyncDISDECL(int) DISWriteReg64(PCPUMCTXCORE pRegFrame, unsigned reg64, uint64_t val64)
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync{
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync    AssertReturn(reg64 < ELEMENTS(g_aReg64Index), VERR_INVALID_PARAMETER);
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync
c48c4d769ded37e2496f97dddbbd36dc62f244b1vboxsync    DIS_WRITE_REG64(pRegFrame, reg64, val64);
c48c4d769ded37e2496f97dddbbd36dc62f244b1vboxsync    return VINF_SUCCESS;
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync}
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync
/**
 * Updates the value of the specified 32 bits general purpose register
 *
 */
DISDECL(int) DISWriteReg32(PCPUMCTXCORE pRegFrame, unsigned reg32, uint32_t val32)
{
    AssertReturn(reg32 < ELEMENTS(g_aReg32Index), VERR_INVALID_PARAMETER);

    DIS_WRITE_REG32(pRegFrame, reg32, val32);
    return VINF_SUCCESS;
}

/**
 * Updates the value of the specified 16 bits general purpose register
 *
 */
DISDECL(int) DISWriteReg16(PCPUMCTXCORE pRegFrame, unsigned reg16, uint16_t val16)
{
    AssertReturn(reg16 < ELEMENTS(g_aReg16Index), VERR_INVALID_PARAMETER);

    DIS_WRITE_REG16(pRegFrame, reg16, val16);
    return VINF_SUCCESS;
}

/**
 * Updates the specified 8 bits general purpose register
 *
 */
DISDECL(int) DISWriteReg8(PCPUMCTXCORE pRegFrame, unsigned reg8, uint8_t val8)
{
    AssertReturn(reg8 < ELEMENTS(g_aReg8Index), VERR_INVALID_PARAMETER);

    DIS_WRITE_REG8(pRegFrame, reg8, val8);
    return VINF_SUCCESS;
}

/**
 * Updates the specified segment register
 *
 */
DISDECL(int) DISWriteRegSeg(PCPUMCTXCORE pCtx, DIS_SELREG sel, RTSEL val)
{
    AssertReturn((unsigned)sel < ELEMENTS(g_aRegSegIndex), VERR_INVALID_PARAMETER);

    AssertCompile(sizeof(uint16_t) == sizeof(RTSEL));
    DIS_WRITE_REGSEG(pCtx, sel, val);
    return VINF_SUCCESS;
}

/**
 * Returns the value of the parameter in pParam
 *
 * @returns VBox error code
 * @param   pCtx            CPU context structure pointer
 * @param   pCpu            Pointer to cpu structure which have DISCPUSTATE::mode
 *                          set correctly.
 * @param   pParam          Pointer to the parameter to parse
 * @param   pParamVal       Pointer to parameter value (OUT)
 * @param   parmtype        Parameter type
 *
 * @note    Currently doesn't handle FPU/XMM/MMX/3DNow! parameters correctly!!
 *
 */
DISDECL(int) DISQueryParamVal(PCPUMCTXCORE pCtx, PDISCPUSTATE pCpu, POP_PARAMETER pParam, POP_PARAMVAL pParamVal, PARAM_TYPE parmtype)
{
    memset(pParamVal, 0, sizeof(*pParamVal));

    if (DIS_IS_EFFECTIVE_ADDR(pParam->flags))
    {
        // Effective address
        pParamVal->type = PARMTYPE_ADDRESS;
        pParamVal->size = pParam->size;

        if (pParam->flags & USE_BASE)
        {
            if (pParam->flags & USE_REG_GEN8)
            {
                pParamVal->flags |= PARAM_VAL8;
                if (VBOX_FAILURE(DISFetchReg8(pCtx, pParam->base.reg_gen, &pParamVal->val.val8))) return VERR_INVALID_PARAMETER;
            }
            else
            if (pParam->flags & USE_REG_GEN16)
            {
                pParamVal->flags |= PARAM_VAL16;
                if (VBOX_FAILURE(DISFetchReg16(pCtx, pParam->base.reg_gen, &pParamVal->val.val16))) return VERR_INVALID_PARAMETER;
            }
            else
            if (pParam->flags & USE_REG_GEN32)
            {
                pParamVal->flags |= PARAM_VAL32;
                if (VBOX_FAILURE(DISFetchReg32(pCtx, pParam->base.reg_gen, &pParamVal->val.val32))) return VERR_INVALID_PARAMETER;
            }
            else
            if (pParam->flags & USE_REG_GEN64)
            {
                pParamVal->flags |= PARAM_VAL64;
                if (VBOX_FAILURE(DISFetchReg64(pCtx, pParam->base.reg_gen, &pParamVal->val.val64))) return VERR_INVALID_PARAMETER;
            }
            else {
                AssertFailed();
                return VERR_INVALID_PARAMETER;
            }
        }
        // Note that scale implies index (SIB byte)
        if (pParam->flags & USE_INDEX)
        {
            uint64_t val64;

            if (pParam->flags & USE_REG_GEN32)
            {
                uint32_t val32;

                pParamVal->flags |= PARAM_VAL32;
                if (VBOX_FAILURE(DISFetchReg32(pCtx, pParam->index.reg_gen, &val32))) return VERR_INVALID_PARAMETER;

                val64 = val32;
            }
            else
            if (pParam->flags & USE_REG_GEN64)
            {
                pParamVal->flags |= PARAM_VAL64;
                if (VBOX_FAILURE(DISFetchReg64(pCtx, pParam->index.reg_gen, &val64))) return VERR_INVALID_PARAMETER;
            }

            if (pParam->flags & USE_SCALE)
                val64 *= pParam->scale;

            pParamVal->val.val64 += val64;
        }

        if (pParam->flags & USE_DISPLACEMENT8)
        {
            if (pCpu->mode == CPUMODE_32BIT)
                pParamVal->val.val32 += (int32_t)pParam->disp8;
            else
            if (pCpu->mode == CPUMODE_64BIT)
                pParamVal->val.val64 += (int64_t)pParam->disp8;
            else
                pParamVal->val.val16 += (int16_t)pParam->disp8;
        }
        else
        if (pParam->flags & USE_DISPLACEMENT16)
        {
            if (pCpu->mode == CPUMODE_32BIT)
                pParamVal->val.val32 += (int32_t)pParam->disp16;
            else
            if (pCpu->mode == CPUMODE_64BIT)
                pParamVal->val.val64 += (int64_t)pParam->disp16;
            else
                pParamVal->val.val16 += pParam->disp16;
        }
        else
        if (pParam->flags & USE_DISPLACEMENT32)
        {
            if (pCpu->mode == CPUMODE_32BIT)
                pParamVal->val.val32 += pParam->disp32;
            else
                pParamVal->val.val64 += pParam->disp32;
        }
        else
        if (pParam->flags & USE_DISPLACEMENT64)
        {
            Assert(pCpu->mode == CPUMODE_64BIT);
            pParamVal->val.val64 += (int64_t)pParam->disp64;
        }
        else
        if (pParam->flags & USE_RIPDISPLACEMENT32)
        {
            Assert(pCpu->mode == CPUMODE_64BIT);
            pParamVal->val.val64 += pParam->disp32 + pCtx->rip;
        }
        return VINF_SUCCESS;
    }

    if (pParam->flags & (USE_REG_GEN8|USE_REG_GEN16|USE_REG_GEN32|USE_REG_GEN64|USE_REG_FP|USE_REG_MMX|USE_REG_XMM|USE_REG_CR|USE_REG_DBG|USE_REG_SEG|USE_REG_TEST))
    {
        if (parmtype == PARAM_DEST)
        {
            // Caller needs to interpret the register according to the instruction (source/target, special value etc)
            pParamVal->type = PARMTYPE_REGISTER;
            pParamVal->size = pParam->size;
            return VINF_SUCCESS;
        }
        //else PARAM_SOURCE

        pParamVal->type = PARMTYPE_IMMEDIATE;

        if (pParam->flags & USE_REG_GEN8)
        {
            pParamVal->flags |= PARAM_VAL8;
            pParamVal->size   = sizeof(uint8_t);
            if (VBOX_FAILURE(DISFetchReg8(pCtx, pParam->base.reg_gen, &pParamVal->val.val8))) return VERR_INVALID_PARAMETER;
        }
        else
        if (pParam->flags & USE_REG_GEN16)
        {
            pParamVal->flags |= PARAM_VAL16;
            pParamVal->size   = sizeof(uint16_t);
            if (VBOX_FAILURE(DISFetchReg16(pCtx, pParam->base.reg_gen, &pParamVal->val.val16))) return VERR_INVALID_PARAMETER;
        }
        else
        if (pParam->flags & USE_REG_GEN32)
        {
            pParamVal->flags |= PARAM_VAL32;
            pParamVal->size   = sizeof(uint32_t);
            if (VBOX_FAILURE(DISFetchReg32(pCtx, pParam->base.reg_gen, &pParamVal->val.val32))) return VERR_INVALID_PARAMETER;
        }
        else
        if (pParam->flags & USE_REG_GEN64)
        {
            pParamVal->flags |= PARAM_VAL64;
            pParamVal->size   = sizeof(uint64_t);
            if (VBOX_FAILURE(DISFetchReg64(pCtx, pParam->base.reg_gen, &pParamVal->val.val64))) return VERR_INVALID_PARAMETER;
        }
        else
        {
            // Caller needs to interpret the register according to the instruction (source/target, special value etc)
            pParamVal->type = PARMTYPE_REGISTER;
        }
        Assert(!(pParam->flags & USE_IMMEDIATE));
        return VINF_SUCCESS;
    }

    if (pParam->flags & USE_IMMEDIATE)
    {
        pParamVal->type = PARMTYPE_IMMEDIATE;
        if (pParam->flags & (USE_IMMEDIATE8|USE_IMMEDIATE8_REL))
        {
            pParamVal->flags |= PARAM_VAL8;
            if (pParam->size == 2)
            {
                pParamVal->size   = sizeof(uint16_t);
                pParamVal->val.val16 = (uint8_t)pParam->parval;
            }
            else
            {
                pParamVal->size   = sizeof(uint8_t);
                pParamVal->val.val8 = (uint8_t)pParam->parval;
            }
        }
        else
        if (pParam->flags & (USE_IMMEDIATE16|USE_IMMEDIATE16_REL|USE_IMMEDIATE_ADDR_0_16|USE_IMMEDIATE16_SX8))
        {
            pParamVal->flags |= PARAM_VAL16;
            pParamVal->size   = sizeof(uint16_t);
            pParamVal->val.val16 = (uint16_t)pParam->parval;
            AssertMsg(pParamVal->size == pParam->size || ((pParam->size == 1) && (pParam->flags & USE_IMMEDIATE16_SX8)), ("pParamVal->size %d vs %d EIP=%VGv\n", pParamVal->size, pParam->size, pCtx->eip) );
        }
        else
        if (pParam->flags & (USE_IMMEDIATE32|USE_IMMEDIATE32_REL|USE_IMMEDIATE_ADDR_0_32|USE_IMMEDIATE32_SX8))
        {
            pParamVal->flags |= PARAM_VAL32;
            pParamVal->size   = sizeof(uint32_t);
            pParamVal->val.val32 = (uint32_t)pParam->parval;
            Assert(pParamVal->size == pParam->size || ((pParam->size == 1) && (pParam->flags & USE_IMMEDIATE32_SX8)) );
        }
        else
        if (pParam->flags & (USE_IMMEDIATE64 | USE_IMMEDIATE64_REL | USE_IMMEDIATE64_SX8))
        {
            pParamVal->flags |= PARAM_VAL64;
            pParamVal->size   = sizeof(uint64_t);
            pParamVal->val.val64 = pParam->parval;
            Assert(pParamVal->size == pParam->size || ((pParam->size == 1) && (pParam->flags & USE_IMMEDIATE64_SX8)) );
        }
        else
        if (pParam->flags & (USE_IMMEDIATE_ADDR_16_16))
        {
            pParamVal->flags |= PARAM_VALFARPTR16;
            pParamVal->size   = sizeof(uint16_t)*2;
            pParamVal->val.farptr.sel    = (uint16_t)RT_LOWORD(pParam->parval >> 16);
            pParamVal->val.farptr.offset = (uint32_t)RT_LOWORD(pParam->parval);
            Assert(pParamVal->size == pParam->size);
        }
        else
        if (pParam->flags & (USE_IMMEDIATE_ADDR_16_32))
        {
            pParamVal->flags |= PARAM_VALFARPTR32;
            pParamVal->size   = sizeof(uint16_t) + sizeof(uint32_t);
            pParamVal->val.farptr.sel    = (uint16_t)RT_LOWORD(pParam->parval >> 32);
            pParamVal->val.farptr.offset = (uint32_t)(pParam->parval & 0xFFFFFFFF);
            Assert(pParam->size == 8);
        }
    }
    return VINF_SUCCESS;
}

/**
 * Returns the pointer to a register of the parameter in pParam. We need this
 * pointer when an interpreted instruction updates a register as a side effect.
 * In CMPXCHG we know that only [r/e]ax is updated, but with XADD this could
 * be every register.
 *
 * @returns VBox error code
 * @param   pCtx            CPU context structure pointer
 * @param   pCpu            Pointer to cpu structure which have DISCPUSTATE::mode
 *                          set correctly.
 * @param   pParam          Pointer to the parameter to parse
 * @param   pReg            Pointer to parameter value (OUT)
 * @param   cbsize          Parameter size (OUT)
 *
 * @note    Currently doesn't handle FPU/XMM/MMX/3DNow! parameters correctly!!
 *
 */
DISDECL(int) DISQueryParamRegPtr(PCPUMCTXCORE pCtx, PDISCPUSTATE pCpu, POP_PARAMETER pParam, void **ppReg, size_t *pcbSize)
{
    if (pParam->flags & (USE_REG_GEN8|USE_REG_GEN16|USE_REG_GEN32|USE_REG_FP|USE_REG_MMX|USE_REG_XMM|USE_REG_CR|USE_REG_DBG|USE_REG_SEG|USE_REG_TEST))
    {
        if (pParam->flags & USE_REG_GEN8)
        {
            uint8_t *pu8Reg;
            if (VBOX_SUCCESS(DISPtrReg8(pCtx, pParam->base.reg_gen, &pu8Reg)))
            {
                *pcbSize = sizeof(uint8_t);
                *ppReg = (void *)pu8Reg;
                return VINF_SUCCESS;
            }
        }
        else
        if (pParam->flags & USE_REG_GEN16)
        {
            uint16_t *pu16Reg;
            if (VBOX_SUCCESS(DISPtrReg16(pCtx, pParam->base.reg_gen, &pu16Reg)))
            {
                *pcbSize = sizeof(uint16_t);
                *ppReg = (void *)pu16Reg;
                return VINF_SUCCESS;
            }
        }
        else
        if (pParam->flags & USE_REG_GEN32)
        {
            uint32_t *pu32Reg;
            if (VBOX_SUCCESS(DISPtrReg32(pCtx, pParam->base.reg_gen, &pu32Reg)))
            {
                *pcbSize = sizeof(uint32_t);
                *ppReg = (void *)pu32Reg;
                return VINF_SUCCESS;
            }
        }
        else
        if (pParam->flags & USE_REG_GEN64)
        {
            uint64_t *pu64Reg;
            if (VBOX_SUCCESS(DISPtrReg64(pCtx, pParam->base.reg_gen, &pu64Reg)))
            {
                *pcbSize = sizeof(uint64_t);
                *ppReg = (void *)pu64Reg;
                return VINF_SUCCESS;
            }
        }
    }
    return VERR_INVALID_PARAMETER;
}
//*****************************************************************************
//*****************************************************************************