DisasmReg.cpp revision 8e2451f7a9a8e6e722d2065fe0eeb5df93799c7a
/* $Id$ */
/** @file
* VBox disassembler- Register Info Helpers.
*/
/*
* Copyright (C) 2006-2012 Oracle Corporation
*
* This file is part of VirtualBox Open Source Edition (OSE), as
* available from http://www.virtualbox.org. This file is free software;
* General Public License (GPL) as published by the Free Software
* Foundation, in version 2 as it comes in the "COPYING" file of the
* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
*/
/*******************************************************************************
* Header Files *
*******************************************************************************/
#define LOG_GROUP LOG_GROUP_DIS
#include <VBox/disopcode.h>
#include "DisasmInternal.h"
#include "DisasmTables.h"
/*******************************************************************************
* Global Variables *
*******************************************************************************/
/**
* Array for accessing 64-bit general registers in VMMREGFRAME structure
* by register's index from disasm.
*/
static const unsigned g_aReg64Index[] =
{
};
/**
* Macro for accessing 64-bit general purpose registers in CPUMCTXCORE structure.
*/
/**
* Array for accessing 32-bit general registers in VMMREGFRAME structure
* by register's index from disasm.
*/
static const unsigned g_aReg32Index[] =
{
};
/**
* Macro for accessing 32-bit general purpose registers in CPUMCTXCORE structure.
*/
* ``Perhaps unexpectedly, instructions that move or generate 32-bit register
* values also set the upper 32 bits of the register to zero. Consequently
* there is no need for an instruction movzlq.''
*/
#define DIS_WRITE_REG32(p, idx, val) (*(uint64_t *)((char *)(p) + g_aReg32Index[idx]) = (uint32_t)val)
/**
* Array for accessing 16-bit general registers in CPUMCTXCORE structure
* by register's index from disasm.
*/
static const unsigned g_aReg16Index[] =
{
};
/**
* Macro for accessing 16-bit general purpose registers in CPUMCTXCORE structure.
*/
/**
* Array for accessing 8-bit general registers in CPUMCTXCORE structure
* by register's index from disasm.
*/
static const unsigned g_aReg8Index[] =
{
};
/**
* Macro for accessing 8-bit general purpose registers in CPUMCTXCORE structure.
*/
/**
* Array for accessing segment registers in CPUMCTXCORE structure
* by register's index from disasm.
*/
static const unsigned g_aRegSegIndex[] =
{
};
static const unsigned g_aRegHidSegIndex[] =
{
};
/**
* Macro for accessing segment registers in CPUMCTXCORE structure.
*/
//*****************************************************************************
//*****************************************************************************
{
{
{
case DISCPUMODE_32BIT:
break;
case DISCPUMODE_64BIT:
break;
case DISCPUMODE_16BIT:
break;
default:
/* make gcc happy */
break;
}
}
switch(subtype)
{
case OP_PARM_b:
return 1;
case OP_PARM_w:
return 2;
case OP_PARM_d:
return 4;
case OP_PARM_q:
case OP_PARM_dq:
return 8;
case OP_PARM_p: /* far pointer */
return 6; /* 16:32 */
else
return 12; /* 16:64 */
else
return 4; /* 16:16 */
default:
else //@todo dangerous!!!
return 4;
}
}
//*****************************************************************************
//*****************************************************************************
{
{
/* Use specified SEG: prefix. */
return pCpu->enmPrefixSeg;
}
else
{
/* Guess segment register by parameter type. */
{
return DIS_SELREG_SS;
}
/* Default is use DS: for data access. */
return DIS_SELREG_DS;
}
}
//*****************************************************************************
//*****************************************************************************
{
switch(pCpu->enmPrefixSeg)
{
case DIS_SELREG_ES:
return 0x26;
case DIS_SELREG_CS:
return 0x2E;
case DIS_SELREG_SS:
return 0x36;
case DIS_SELREG_DS:
return 0x3E;
case DIS_SELREG_FS:
return 0x64;
case DIS_SELREG_GS:
return 0x65;
default:
AssertFailed();
return 0;
}
}
/**
* Returns the value of the specified 8 bits general purpose register
*
*/
{
return VINF_SUCCESS;
}
/**
* Returns the value of the specified 16 bits general purpose register
*
*/
{
return VINF_SUCCESS;
}
/**
* Returns the value of the specified 32 bits general purpose register
*
*/
{
return VINF_SUCCESS;
}
/**
* Returns the value of the specified 64 bits general purpose register
*
*/
{
return VINF_SUCCESS;
}
/**
* Returns the pointer to the specified 8 bits general purpose register
*
*/
{
return VINF_SUCCESS;
}
/**
* Returns the pointer to the specified 16 bits general purpose register
*
*/
{
return VINF_SUCCESS;
}
/**
* Returns the pointer to the specified 32 bits general purpose register
*
*/
{
return VINF_SUCCESS;
}
/**
* Returns the pointer to the specified 64 bits general purpose register
*
*/
{
return VINF_SUCCESS;
}
/**
* Returns the value of the specified segment register
*
*/
{
return VINF_SUCCESS;
}
/**
* Returns the value of the specified segment register including a pointer to the hidden register in the supplied cpu context
*
*/
DISDECL(int) DISFetchRegSegEx(PCCPUMCTXCORE pCtx, DIS_SELREG sel, RTSEL *pVal, CPUMSELREGHID **ppSelHidReg)
{
return VINF_SUCCESS;
}
/**
* Updates the value of the specified 64 bits general purpose register
*
*/
{
return VINF_SUCCESS;
}
/**
* Updates the value of the specified 32 bits general purpose register
*
*/
{
return VINF_SUCCESS;
}
/**
* Updates the value of the specified 16 bits general purpose register
*
*/
{
return VINF_SUCCESS;
}
/**
* Updates the specified 8 bits general purpose register
*
*/
{
return VINF_SUCCESS;
}
/**
* Updates the specified segment register
*
*/
{
return VINF_SUCCESS;
}
/**
* Returns the value of the parameter in pParam
*
* @returns VBox error code
* @param pCtx CPU context structure pointer
* @param pCpu Pointer to cpu structure which have DISCPUSTATE::mode
* set correctly.
* @param pParam Pointer to the parameter to parse
* @param pParamVal Pointer to parameter value (OUT)
* @param parmtype Parameter type
*
*
*/
DISDECL(int) DISQueryParamVal(PCPUMCTXCORE pCtx, PDISCPUSTATE pCpu, POP_PARAMETER pParam, POP_PARAMVAL pParamVal, PARAM_TYPE parmtype)
{
{
// Effective address
{
{
if (RT_FAILURE(DISFetchReg8(pCtx, pParam->base.reg_gen, &pParamVal->val.val8))) return VERR_INVALID_PARAMETER;
}
else
{
if (RT_FAILURE(DISFetchReg16(pCtx, pParam->base.reg_gen, &pParamVal->val.val16))) return VERR_INVALID_PARAMETER;
}
else
{
if (RT_FAILURE(DISFetchReg32(pCtx, pParam->base.reg_gen, &pParamVal->val.val32))) return VERR_INVALID_PARAMETER;
}
else
{
if (RT_FAILURE(DISFetchReg64(pCtx, pParam->base.reg_gen, &pParamVal->val.val64))) return VERR_INVALID_PARAMETER;
}
else
{
AssertFailed();
return VERR_INVALID_PARAMETER;
}
}
// Note that scale implies index (SIB byte)
{
{
}
else
{
}
else
{
}
else
AssertFailed();
}
{
else
else
}
else
{
else
else
}
else
{
else
}
else
{
}
else
{
/* Relative to the RIP of the next instruction. */
}
return VINF_SUCCESS;
}
if (pParam->fUse & (DISUSE_REG_GEN8|DISUSE_REG_GEN16|DISUSE_REG_GEN32|DISUSE_REG_GEN64|DISUSE_REG_FP|DISUSE_REG_MMX|DISUSE_REG_XMM|DISUSE_REG_CR|DISUSE_REG_DBG|DISUSE_REG_SEG|DISUSE_REG_TEST))
{
if (parmtype == PARAM_DEST)
{
// Caller needs to interpret the register according to the instruction (source/target, special value etc)
return VINF_SUCCESS;
}
//else PARAM_SOURCE
{
if (RT_FAILURE(DISFetchReg8(pCtx, pParam->base.reg_gen, &pParamVal->val.val8))) return VERR_INVALID_PARAMETER;
}
else
{
if (RT_FAILURE(DISFetchReg16(pCtx, pParam->base.reg_gen, &pParamVal->val.val16))) return VERR_INVALID_PARAMETER;
}
else
{
if (RT_FAILURE(DISFetchReg32(pCtx, pParam->base.reg_gen, &pParamVal->val.val32))) return VERR_INVALID_PARAMETER;
}
else
{
if (RT_FAILURE(DISFetchReg64(pCtx, pParam->base.reg_gen, &pParamVal->val.val64))) return VERR_INVALID_PARAMETER;
}
else
{
// Caller needs to interpret the register according to the instruction (source/target, special value etc)
}
return VINF_SUCCESS;
}
{
{
{
}
else
{
}
}
else
if (pParam->fUse & (DISUSE_IMMEDIATE16|DISUSE_IMMEDIATE16_REL|DISUSE_IMMEDIATE_ADDR_0_16|DISUSE_IMMEDIATE16_SX8))
{
AssertMsg(pParamVal->size == pParam->cb || ((pParam->cb == 1) && (pParam->fUse & DISUSE_IMMEDIATE16_SX8)), ("pParamVal->size %d vs %d EIP=%RX32\n", pParamVal->size, pParam->cb, pCtx->eip) );
}
else
if (pParam->fUse & (DISUSE_IMMEDIATE32|DISUSE_IMMEDIATE32_REL|DISUSE_IMMEDIATE_ADDR_0_32|DISUSE_IMMEDIATE32_SX8))
{
Assert(pParamVal->size == pParam->cb || ((pParam->cb == 1) && (pParam->fUse & DISUSE_IMMEDIATE32_SX8)) );
}
else
{
Assert(pParamVal->size == pParam->cb || ((pParam->cb == 1) && (pParam->fUse & DISUSE_IMMEDIATE64_SX8)) );
}
else
{
}
else
{
}
}
return VINF_SUCCESS;
}
/**
* Returns the pointer to a register of the parameter in pParam. We need this
* pointer when an interpreted instruction updates a register as a side effect.
* In CMPXCHG we know that only [r/e]ax is updated, but with XADD this could
* be every register.
*
* @returns VBox error code
* @param pCtx CPU context structure pointer
* @param pCpu Pointer to cpu structure which have DISCPUSTATE::mode
* set correctly.
* @param pParam Pointer to the parameter to parse
* @param pReg Pointer to parameter value (OUT)
* @param cbsize Parameter size (OUT)
*
*
*/
DISDECL(int) DISQueryParamRegPtr(PCPUMCTXCORE pCtx, PDISCPUSTATE pCpu, POP_PARAMETER pParam, void **ppReg, size_t *pcbSize)
{
if (pParam->fUse & (DISUSE_REG_GEN8|DISUSE_REG_GEN16|DISUSE_REG_GEN32|DISUSE_REG_FP|DISUSE_REG_MMX|DISUSE_REG_XMM|DISUSE_REG_CR|DISUSE_REG_DBG|DISUSE_REG_SEG|DISUSE_REG_TEST))
{
{
{
return VINF_SUCCESS;
}
}
else
{
{
return VINF_SUCCESS;
}
}
else
{
{
return VINF_SUCCESS;
}
}
else
{
{
return VINF_SUCCESS;
}
}
}
return VERR_INVALID_PARAMETER;
}