DisasmReg.cpp revision 14e483cf65160fb363043534151245ae4c215766
/** @file
*
* VBox disassembler:
* Core components
*/
/*
* Copyright (C) 2006-2007 Sun Microsystems, Inc.
*
* This file is part of VirtualBox Open Source Edition (OSE), as
* available from http://www.virtualbox.org. This file is free software;
* General Public License (GPL) as published by the Free Software
* Foundation, in version 2 as it comes in the "COPYING" file of the
* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
*
* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
* Clara, CA 95054 USA or visit http://www.sun.com if you need
* additional information or have any questions.
*/
/*******************************************************************************
* Header Files *
*******************************************************************************/
#define LOG_GROUP LOG_GROUP_DIS
#ifdef USING_VISUAL_STUDIO
# include <stdafx.h>
#endif
#include <VBox/disopcode.h>
#include "DisasmInternal.h"
#include "DisasmTables.h"
#if !defined(DIS_CORE_ONLY) && defined(LOG_ENABLED)
# include <stdlib.h>
# include <stdio.h>
#endif
/*******************************************************************************
* Global Variables *
*******************************************************************************/
/**
* Array for accessing 64-bit general registers in VMMREGFRAME structure
* by register's index from disasm.
*/
static const unsigned g_aReg64Index[] =
{
};
/**
* Macro for accessing 64-bit general purpose registers in CPUMCTXCORE structure.
*/
/**
* Array for accessing 32-bit general registers in VMMREGFRAME structure
* by register's index from disasm.
*/
static const unsigned g_aReg32Index[] =
{
};
/**
* Macro for accessing 32-bit general purpose registers in CPUMCTXCORE structure.
*/
/**
* Array for accessing 16-bit general registers in CPUMCTXCORE structure
* by register's index from disasm.
*/
static const unsigned g_aReg16Index[] =
{
};
/**
* Macro for accessing 16-bit general purpose registers in CPUMCTXCORE structure.
*/
/**
* Array for accessing 8-bit general registers in CPUMCTXCORE structure
* by register's index from disasm.
*/
static const unsigned g_aReg8Index[] =
{
};
/**
* Macro for accessing 8-bit general purpose registers in CPUMCTXCORE structure.
*/
/**
* Array for accessing segment registers in CPUMCTXCORE structure
* by register's index from disasm.
*/
static const unsigned g_aRegSegIndex[] =
{
};
static const unsigned g_aRegHidSegIndex[] =
{
};
/**
* Macro for accessing segment registers in CPUMCTXCORE structure.
*/
//*****************************************************************************
//*****************************************************************************
{
{
}
switch(subtype)
{
case OP_PARM_b:
return 1;
case OP_PARM_w:
return 2;
case OP_PARM_d:
return 4;
case OP_PARM_q:
case OP_PARM_dq:
return 8;
case OP_PARM_p: /* far pointer */
return 6; /* 16:32 */
else
return 12; /* 16:64 */
else
return 4; /* 16:16 */
default:
else //@todo dangerous!!!
return 4;
}
}
//*****************************************************************************
//*****************************************************************************
{
{
/* Use specified SEG: prefix. */
return pCpu->prefix_seg;
}
else
{
/* Guess segment register by parameter type. */
{
return USE_REG_SS;
}
/* Default is use DS: for data access. */
return USE_REG_DS;
}
}
//*****************************************************************************
//*****************************************************************************
{
switch(pCpu->prefix_seg)
{
case USE_REG_ES:
return 0x26;
case USE_REG_CS:
return 0x2E;
case USE_REG_SS:
return 0x36;
case USE_REG_DS:
return 0x3E;
case USE_REG_FS:
return 0x64;
case USE_REG_GS:
return 0x65;
default:
AssertFailed();
return 0;
}
}
/**
* Returns the value of the specified 8 bits general purpose register
*
*/
{
return VINF_SUCCESS;
}
/**
* Returns the value of the specified 16 bits general purpose register
*
*/
{
return VINF_SUCCESS;
}
/**
* Returns the value of the specified 32 bits general purpose register
*
*/
{
return VINF_SUCCESS;
}
/**
* Returns the value of the specified 64 bits general purpose register
*
*/
{
return VINF_SUCCESS;
}
/**
* Returns the pointer to the specified 8 bits general purpose register
*
*/
{
return VINF_SUCCESS;
}
/**
* Returns the pointer to the specified 16 bits general purpose register
*
*/
{
return VINF_SUCCESS;
}
/**
* Returns the pointer to the specified 32 bits general purpose register
*
*/
{
return VINF_SUCCESS;
}
/**
* Returns the pointer to the specified 64 bits general purpose register
*
*/
{
return VINF_SUCCESS;
}
/**
* Returns the value of the specified segment register
*
*/
{
return VINF_SUCCESS;
}
/**
* Returns the value of the specified segment register including a pointer to the hidden register in the supplied cpu context
*
*/
DISDECL(int) DISFetchRegSegEx(PCPUMCTXCORE pCtx, unsigned sel, RTSEL *pVal, CPUMSELREGHID **ppSelHidReg)
{
return VINF_SUCCESS;
}
/**
* Updates the value of the specified 64 bits general purpose register
*
*/
{
return VINF_SUCCESS;
}
/**
* Updates the value of the specified 32 bits general purpose register
*
*/
{
return VINF_SUCCESS;
}
/**
* Updates the value of the specified 16 bits general purpose register
*
*/
{
return VINF_SUCCESS;
}
/**
* Updates the specified 8 bits general purpose register
*
*/
{
return VINF_SUCCESS;
}
/**
* Updates the specified segment register
*
*/
{
return VINF_SUCCESS;
}
/**
* Returns the value of the parameter in pParam
*
* @returns VBox error code
* @param pCtx CPU context structure pointer
* @param pCpu Pointer to cpu structure which have DISCPUSTATE::mode
* set correctly.
* @param pParam Pointer to the parameter to parse
* @param pParamVal Pointer to parameter value (OUT)
* @param parmtype Parameter type
*
*
*/
DISDECL(int) DISQueryParamVal(PCPUMCTXCORE pCtx, PDISCPUSTATE pCpu, POP_PARAMETER pParam, POP_PARAMVAL pParamVal, PARAM_TYPE parmtype)
{
{
// Effective address
{
{
if (VBOX_FAILURE(DISFetchReg8(pCtx, pParam->base.reg_gen, &pParamVal->val.val8))) return VERR_INVALID_PARAMETER;
}
else
{
if (VBOX_FAILURE(DISFetchReg16(pCtx, pParam->base.reg_gen, &pParamVal->val.val16))) return VERR_INVALID_PARAMETER;
}
else
{
if (VBOX_FAILURE(DISFetchReg32(pCtx, pParam->base.reg_gen, &pParamVal->val.val32))) return VERR_INVALID_PARAMETER;
}
else
{
if (VBOX_FAILURE(DISFetchReg64(pCtx, pParam->base.reg_gen, &pParamVal->val.val64))) return VERR_INVALID_PARAMETER;
}
else {
AssertFailed();
return VERR_INVALID_PARAMETER;
}
}
// Note that scale implies index (SIB byte)
{
if (VBOX_FAILURE(DISFetchReg32(pCtx, pParam->index.reg_gen, &val32))) return VERR_INVALID_PARAMETER;
{
}
}
{
{
}
else
{
}
}
else
{
{
}
else
{
}
}
else
{
{
}
else
{
Assert(0);
}
}
return VINF_SUCCESS;
}
if (pParam->flags & (USE_REG_GEN8|USE_REG_GEN16|USE_REG_GEN32|USE_REG_GEN64|USE_REG_FP|USE_REG_MMX|USE_REG_XMM|USE_REG_CR|USE_REG_DBG|USE_REG_SEG|USE_REG_TEST))
{
if (parmtype == PARAM_DEST)
{
// Caller needs to interpret the register according to the instruction (source/target, special value etc)
return VINF_SUCCESS;
}
//else PARAM_SOURCE
{
if (VBOX_FAILURE(DISFetchReg8(pCtx, pParam->base.reg_gen, &pParamVal->val.val8))) return VERR_INVALID_PARAMETER;
}
else
{
if (VBOX_FAILURE(DISFetchReg16(pCtx, pParam->base.reg_gen, &pParamVal->val.val16))) return VERR_INVALID_PARAMETER;
}
else
{
if (VBOX_FAILURE(DISFetchReg32(pCtx, pParam->base.reg_gen, &pParamVal->val.val32))) return VERR_INVALID_PARAMETER;
}
else
{
if (VBOX_FAILURE(DISFetchReg64(pCtx, pParam->base.reg_gen, &pParamVal->val.val64))) return VERR_INVALID_PARAMETER;
}
else
{
// Caller needs to interpret the register according to the instruction (source/target, special value etc)
}
}
{
{
{
}
else
{
}
}
else
if (pParam->flags & (USE_IMMEDIATE16|USE_IMMEDIATE16_REL|USE_IMMEDIATE_ADDR_0_16|USE_IMMEDIATE16_SX8))
{
Assert(pParamVal->size == pParam->size || ((pParam->size == 1) && (pParam->flags & USE_IMMEDIATE16_SX8)) );
}
else
if (pParam->flags & (USE_IMMEDIATE32|USE_IMMEDIATE32_REL|USE_IMMEDIATE_ADDR_0_32|USE_IMMEDIATE32_SX8))
{
Assert(pParamVal->size == pParam->size || ((pParam->size == 1) && (pParam->flags & USE_IMMEDIATE32_SX8)) );
}
else
{
}
else
{
}
else
{
}
}
return VINF_SUCCESS;
}
/**
* Returns the pointer to a register of the parameter in pParam. We need this
* pointer when an interpreted instruction updates a register as a side effect.
* In CMPXCHG we know that only [r/e]ax is updated, but with XADD this could
* be every register.
*
* @returns VBox error code
* @param pCtx CPU context structure pointer
* @param pCpu Pointer to cpu structure which have DISCPUSTATE::mode
* set correctly.
* @param pParam Pointer to the parameter to parse
* @param pReg Pointer to parameter value (OUT)
* @param cbsize Parameter size (OUT)
*
*
*/
DISDECL(int) DISQueryParamRegPtr(PCPUMCTXCORE pCtx, PDISCPUSTATE pCpu, POP_PARAMETER pParam, void **ppReg, size_t *pcbSize)
{
if (pParam->flags & (USE_REG_GEN8|USE_REG_GEN16|USE_REG_GEN32|USE_REG_FP|USE_REG_MMX|USE_REG_XMM|USE_REG_CR|USE_REG_DBG|USE_REG_SEG|USE_REG_TEST))
{
{
{
return VINF_SUCCESS;
}
}
else
{
{
return VINF_SUCCESS;
}
}
else
{
{
return VINF_SUCCESS;
}
}
else
{
{
return VINF_SUCCESS;
}
}
}
return VERR_INVALID_PARAMETER;
}
//*****************************************************************************
//*****************************************************************************