DisasmReg.cpp revision 0aa1ba1d1ea27baa7762e4fe891824df38697189
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync/* $Id$ */
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync/** @file
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync * VBox disassembler- Register Info Helpers.
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync */
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync
4bc1bbf45f30ff3ca38c2ad006836e490972c7ccvboxsync/*
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync * Copyright (C) 2006-2012 Oracle Corporation
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync *
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync * This file is part of VirtualBox Open Source Edition (OSE), as
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync * available from http://www.virtualbox.org. This file is free software;
d63de4508a08b11f57c307a15eda3cd95485bf2cvboxsync * you can redistribute it and/or modify it under the terms of the GNU
d63de4508a08b11f57c307a15eda3cd95485bf2cvboxsync * General Public License (GPL) as published by the Free Software
d63de4508a08b11f57c307a15eda3cd95485bf2cvboxsync * Foundation, in version 2 as it comes in the "COPYING" file of the
d63de4508a08b11f57c307a15eda3cd95485bf2cvboxsync * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync */
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync
a3d06a524c4f1cde2f0eada83656543d5a24115dvboxsync
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync/*******************************************************************************
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync* Header Files *
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync*******************************************************************************/
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync#define LOG_GROUP LOG_GROUP_DIS
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync#include <VBox/dis.h>
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync#include <VBox/disopcode.h>
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync#include <VBox/err.h>
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync#include <VBox/log.h>
88350256a6c78b8631aba5aa5ce249d90a8514a2vboxsync#include <VBox/vmm/cpum.h>
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync#include <iprt/assert.h>
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync#include <iprt/string.h>
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync#include <iprt/stdarg.h>
943d182735b76ecae26ea011cb7b87e449aafea8vboxsync#include "DisasmInternal.h"
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync/*******************************************************************************
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync* Global Variables *
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync*******************************************************************************/
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync/**
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync * Array for accessing 64-bit general registers in VMMREGFRAME structure
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync * by register's index from disasm.
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync */
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsyncstatic const unsigned g_aReg64Index[] =
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync{
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync RT_OFFSETOF(CPUMCTXCORE, rax), /* DISGREG_RAX */
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync RT_OFFSETOF(CPUMCTXCORE, rcx), /* DISGREG_RCX */
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync RT_OFFSETOF(CPUMCTXCORE, rdx), /* DISGREG_RDX */
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync RT_OFFSETOF(CPUMCTXCORE, rbx), /* DISGREG_RBX */
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync RT_OFFSETOF(CPUMCTXCORE, rsp), /* DISGREG_RSP */
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync RT_OFFSETOF(CPUMCTXCORE, rbp), /* DISGREG_RBP */
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync RT_OFFSETOF(CPUMCTXCORE, rsi), /* DISGREG_RSI */
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync RT_OFFSETOF(CPUMCTXCORE, rdi), /* DISGREG_RDI */
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync RT_OFFSETOF(CPUMCTXCORE, r8), /* DISGREG_R8 */
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync RT_OFFSETOF(CPUMCTXCORE, r9), /* DISGREG_R9 */
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync RT_OFFSETOF(CPUMCTXCORE, r10), /* DISGREG_R10 */
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync RT_OFFSETOF(CPUMCTXCORE, r11), /* DISGREG_R11 */
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync RT_OFFSETOF(CPUMCTXCORE, r12), /* DISGREG_R12 */
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync RT_OFFSETOF(CPUMCTXCORE, r13), /* DISGREG_R13 */
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync RT_OFFSETOF(CPUMCTXCORE, r14), /* DISGREG_R14 */
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync RT_OFFSETOF(CPUMCTXCORE, r15) /* DISGREG_R15 */
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync};
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync/**
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync * Macro for accessing 64-bit general purpose registers in CPUMCTXCORE structure.
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync */
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync#define DIS_READ_REG64(p, idx) (*(uint64_t *)((char *)(p) + g_aReg64Index[idx]))
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync#define DIS_WRITE_REG64(p, idx, val) (*(uint64_t *)((char *)(p) + g_aReg64Index[idx]) = val)
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync#define DIS_PTR_REG64(p, idx) ( (uint64_t *)((char *)(p) + g_aReg64Index[idx]))
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync/**
c6adb272ec43d5eaadb1493cb2bf45f2f8adf588vboxsync * Array for accessing 32-bit general registers in VMMREGFRAME structure
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync * by register's index from disasm.
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync */
58b7773f17a933ab8d53f450bed0afcf2f003508vboxsyncstatic const unsigned g_aReg32Index[] =
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync{
c48c4d769ded37e2496f97dddbbd36dc62f244b1vboxsync RT_OFFSETOF(CPUMCTXCORE, eax), /* DISGREG_EAX */
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync RT_OFFSETOF(CPUMCTXCORE, ecx), /* DISGREG_ECX */
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync RT_OFFSETOF(CPUMCTXCORE, edx), /* DISGREG_EDX */
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync RT_OFFSETOF(CPUMCTXCORE, ebx), /* DISGREG_EBX */
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync RT_OFFSETOF(CPUMCTXCORE, esp), /* DISGREG_ESP */
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync RT_OFFSETOF(CPUMCTXCORE, ebp), /* DISGREG_EBP */
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync RT_OFFSETOF(CPUMCTXCORE, esi), /* DISGREG_ESI */
20fc4a350a4a8e56ffaac6cf57dcd677a7ac36c5vboxsync RT_OFFSETOF(CPUMCTXCORE, edi), /* DISGREG_EDI */
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync RT_OFFSETOF(CPUMCTXCORE, r8), /* DISGREG_R8D */
e7159a7ab092aaf8a7423d811c2b7a8286e2669bvboxsync RT_OFFSETOF(CPUMCTXCORE, r9), /* DISGREG_R9D */
e7159a7ab092aaf8a7423d811c2b7a8286e2669bvboxsync RT_OFFSETOF(CPUMCTXCORE, r10), /* DISGREG_R1D */
e7159a7ab092aaf8a7423d811c2b7a8286e2669bvboxsync RT_OFFSETOF(CPUMCTXCORE, r11), /* DISGREG_R11D */
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync RT_OFFSETOF(CPUMCTXCORE, r12), /* DISGREG_R12D */
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync RT_OFFSETOF(CPUMCTXCORE, r13), /* DISGREG_R13D */
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync RT_OFFSETOF(CPUMCTXCORE, r14), /* DISGREG_R14D */
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync RT_OFFSETOF(CPUMCTXCORE, r15) /* DISGREG_R15D */
a48f6e21f8737ef47d30d716171ae2bcb10c3382vboxsync};
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync/**
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync * Macro for accessing 32-bit general purpose registers in CPUMCTXCORE structure.
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync */
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync#define DIS_READ_REG32(p, idx) (*(uint32_t *)((char *)(p) + g_aReg32Index[idx]))
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync/* From http://www.cs.cmu.edu/~fp/courses/15213-s06/misc/asm64-handout.pdf:
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync * ``Perhaps unexpectedly, instructions that move or generate 32-bit register
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync * values also set the upper 32 bits of the register to zero. Consequently
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync * there is no need for an instruction movzlq.''
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync */
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync#define DIS_WRITE_REG32(p, idx, val) (*(uint64_t *)((char *)(p) + g_aReg32Index[idx]) = (uint32_t)val)
c6adb272ec43d5eaadb1493cb2bf45f2f8adf588vboxsync#define DIS_PTR_REG32(p, idx) ( (uint32_t *)((char *)(p) + g_aReg32Index[idx]))
b28fef07fef379ecc179e0bc0d5d1be753e482b5vboxsync
c48c4d769ded37e2496f97dddbbd36dc62f244b1vboxsync/**
c48c4d769ded37e2496f97dddbbd36dc62f244b1vboxsync * Array for accessing 16-bit general registers in CPUMCTXCORE structure
257927abbaa6d9774427049fcbea552cda362281vboxsync * by register's index from disasm.
257927abbaa6d9774427049fcbea552cda362281vboxsync */
257927abbaa6d9774427049fcbea552cda362281vboxsyncstatic const unsigned g_aReg16Index[] =
257927abbaa6d9774427049fcbea552cda362281vboxsync{
24a8dd4360c4b4588fd2c340dd7687379a45e02evboxsync RT_OFFSETOF(CPUMCTXCORE, eax), /* DISGREG_AX */
3c49234930c10a52368b992781dae0306a72b5f5vboxsync RT_OFFSETOF(CPUMCTXCORE, ecx), /* DISGREG_CX */
c48c4d769ded37e2496f97dddbbd36dc62f244b1vboxsync RT_OFFSETOF(CPUMCTXCORE, edx), /* DISGREG_DX */
c48c4d769ded37e2496f97dddbbd36dc62f244b1vboxsync RT_OFFSETOF(CPUMCTXCORE, ebx), /* DISGREG_BX */
c48c4d769ded37e2496f97dddbbd36dc62f244b1vboxsync RT_OFFSETOF(CPUMCTXCORE, esp), /* DISGREG_SP */
c48c4d769ded37e2496f97dddbbd36dc62f244b1vboxsync RT_OFFSETOF(CPUMCTXCORE, ebp), /* DISGREG_BP */
1d17a5f9688f3622ffe088b664588629b1e95801vboxsync RT_OFFSETOF(CPUMCTXCORE, esi), /* DISGREG_SI */
14dcfe007d2a64583946ed5e4cfdb458a7f7f03bvboxsync RT_OFFSETOF(CPUMCTXCORE, edi), /* DISGREG_DI */
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync RT_OFFSETOF(CPUMCTXCORE, r8), /* DISGREG_R8W */
a3d06a524c4f1cde2f0eada83656543d5a24115dvboxsync RT_OFFSETOF(CPUMCTXCORE, r9), /* DISGREG_R9W */
a3d06a524c4f1cde2f0eada83656543d5a24115dvboxsync RT_OFFSETOF(CPUMCTXCORE, r10), /* DISGREG_R10W */
a3d06a524c4f1cde2f0eada83656543d5a24115dvboxsync RT_OFFSETOF(CPUMCTXCORE, r11), /* DISGREG_R11W */
a3d06a524c4f1cde2f0eada83656543d5a24115dvboxsync RT_OFFSETOF(CPUMCTXCORE, r12), /* DISGREG_R12W */
20fc4a350a4a8e56ffaac6cf57dcd677a7ac36c5vboxsync RT_OFFSETOF(CPUMCTXCORE, r13), /* DISGREG_R13W */
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync RT_OFFSETOF(CPUMCTXCORE, r14), /* DISGREG_R14W */
e7159a7ab092aaf8a7423d811c2b7a8286e2669bvboxsync RT_OFFSETOF(CPUMCTXCORE, r15) /* DISGREG_R15W */
e7159a7ab092aaf8a7423d811c2b7a8286e2669bvboxsync};
e7159a7ab092aaf8a7423d811c2b7a8286e2669bvboxsync
4bc1bbf45f30ff3ca38c2ad006836e490972c7ccvboxsync/**
4bc1bbf45f30ff3ca38c2ad006836e490972c7ccvboxsync * Macro for accessing 16-bit general purpose registers in CPUMCTXCORE structure.
4bc1bbf45f30ff3ca38c2ad006836e490972c7ccvboxsync */
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync#define DIS_READ_REG16(p, idx) (*(uint16_t *)((char *)(p) + g_aReg16Index[idx]))
3684b2b9eeb77285df2dc641fcf6f70805568be8vboxsync#define DIS_WRITE_REG16(p, idx, val) (*(uint16_t *)((char *)(p) + g_aReg16Index[idx]) = val)
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync#define DIS_PTR_REG16(p, idx) ( (uint16_t *)((char *)(p) + g_aReg16Index[idx]))
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync/**
73e8df2e481cb3697372a3cf4acffd068a7f1296vboxsync * Array for accessing 8-bit general registers in CPUMCTXCORE structure
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync * by register's index from disasm.
d293c8e7a1adaf427e7a361add878676749b7da6vboxsync */
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsyncstatic const unsigned g_aReg8Index[] =
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync{
73e8df2e481cb3697372a3cf4acffd068a7f1296vboxsync RT_OFFSETOF(CPUMCTXCORE, eax), /* DISGREG_AL */
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync RT_OFFSETOF(CPUMCTXCORE, ecx), /* DISGREG_CL */
d293c8e7a1adaf427e7a361add878676749b7da6vboxsync RT_OFFSETOF(CPUMCTXCORE, edx), /* DISGREG_DL */
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync RT_OFFSETOF(CPUMCTXCORE, ebx), /* DISGREG_BL */
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync RT_OFFSETOF_ADD(CPUMCTXCORE, eax, 1), /* DISGREG_AH */
73e8df2e481cb3697372a3cf4acffd068a7f1296vboxsync RT_OFFSETOF_ADD(CPUMCTXCORE, ecx, 1), /* DISGREG_CH */
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync RT_OFFSETOF_ADD(CPUMCTXCORE, edx, 1), /* DISGREG_DH */
d293c8e7a1adaf427e7a361add878676749b7da6vboxsync RT_OFFSETOF_ADD(CPUMCTXCORE, ebx, 1), /* DISGREG_BH */
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync RT_OFFSETOF(CPUMCTXCORE, r8), /* DISGREG_R8B */
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync RT_OFFSETOF(CPUMCTXCORE, r9), /* DISGREG_R9B */
73e8df2e481cb3697372a3cf4acffd068a7f1296vboxsync RT_OFFSETOF(CPUMCTXCORE, r10), /* DISGREG_R10B*/
9704f1d0180960069e2c4eb8fe2ddee350910e5dvboxsync RT_OFFSETOF(CPUMCTXCORE, r11), /* DISGREG_R11B */
d293c8e7a1adaf427e7a361add878676749b7da6vboxsync RT_OFFSETOF(CPUMCTXCORE, r12), /* DISGREG_R12B */
9704f1d0180960069e2c4eb8fe2ddee350910e5dvboxsync RT_OFFSETOF(CPUMCTXCORE, r13), /* DISGREG_R13B */
9704f1d0180960069e2c4eb8fe2ddee350910e5dvboxsync RT_OFFSETOF(CPUMCTXCORE, r14), /* DISGREG_R14B */
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync RT_OFFSETOF(CPUMCTXCORE, r15), /* DISGREG_R15B */
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync RT_OFFSETOF(CPUMCTXCORE, esp), /* DISGREG_SPL; with REX prefix only */
3684b2b9eeb77285df2dc641fcf6f70805568be8vboxsync RT_OFFSETOF(CPUMCTXCORE, ebp), /* DISGREG_BPL; with REX prefix only */
a3d06a524c4f1cde2f0eada83656543d5a24115dvboxsync RT_OFFSETOF(CPUMCTXCORE, esi), /* DISGREG_SIL; with REX prefix only */
a3d06a524c4f1cde2f0eada83656543d5a24115dvboxsync RT_OFFSETOF(CPUMCTXCORE, edi) /* DISGREG_DIL; with REX prefix only */
a3d06a524c4f1cde2f0eada83656543d5a24115dvboxsync};
a3d06a524c4f1cde2f0eada83656543d5a24115dvboxsync
a3d06a524c4f1cde2f0eada83656543d5a24115dvboxsync/**
a3d06a524c4f1cde2f0eada83656543d5a24115dvboxsync * Macro for accessing 8-bit general purpose registers in CPUMCTXCORE structure.
a3d06a524c4f1cde2f0eada83656543d5a24115dvboxsync */
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync#define DIS_READ_REG8(p, idx) (*(uint8_t *)((char *)(p) + g_aReg8Index[idx]))
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync#define DIS_WRITE_REG8(p, idx, val) (*(uint8_t *)((char *)(p) + g_aReg8Index[idx]) = val)
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync#define DIS_PTR_REG8(p, idx) ( (uint8_t *)((char *)(p) + g_aReg8Index[idx]))
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync/**
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync * Array for accessing segment registers in CPUMCTXCORE structure
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync * by register's index from disasm.
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync */
17d67aeb3722c094c6493a3e9a9d0cdfb9453ecdvboxsyncstatic const unsigned g_aRegSegIndex[] =
87c50c527af59e43745475c4b8ac907c5f9bc204vboxsync{
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync RT_OFFSETOF(CPUMCTXCORE, es), /* DISSELREG_ES */
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync RT_OFFSETOF(CPUMCTXCORE, cs), /* DISSELREG_CS */
17d67aeb3722c094c6493a3e9a9d0cdfb9453ecdvboxsync RT_OFFSETOF(CPUMCTXCORE, ss), /* DISSELREG_SS */
87c50c527af59e43745475c4b8ac907c5f9bc204vboxsync RT_OFFSETOF(CPUMCTXCORE, ds), /* DISSELREG_DS */
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync RT_OFFSETOF(CPUMCTXCORE, fs), /* DISSELREG_FS */
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync RT_OFFSETOF(CPUMCTXCORE, gs) /* DISSELREG_GS */
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync};
58b7773f17a933ab8d53f450bed0afcf2f003508vboxsync
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsyncstatic const unsigned g_aRegHidSegIndex[] =
58b7773f17a933ab8d53f450bed0afcf2f003508vboxsync{
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync RT_OFFSETOF(CPUMCTXCORE, esHid), /* DISSELREG_ES */
58b7773f17a933ab8d53f450bed0afcf2f003508vboxsync RT_OFFSETOF(CPUMCTXCORE, csHid), /* DISSELREG_CS */
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync RT_OFFSETOF(CPUMCTXCORE, ssHid), /* DISSELREG_SS */
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync RT_OFFSETOF(CPUMCTXCORE, dsHid), /* DISSELREG_DS */
58b7773f17a933ab8d53f450bed0afcf2f003508vboxsync RT_OFFSETOF(CPUMCTXCORE, fsHid), /* DISSELREG_FS */
17d67aeb3722c094c6493a3e9a9d0cdfb9453ecdvboxsync RT_OFFSETOF(CPUMCTXCORE, gsHid) /* DISSELREG_GS */
17d67aeb3722c094c6493a3e9a9d0cdfb9453ecdvboxsync};
14dcfe007d2a64583946ed5e4cfdb458a7f7f03bvboxsync
14dcfe007d2a64583946ed5e4cfdb458a7f7f03bvboxsync/**
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync * Macro for accessing segment registers in CPUMCTXCORE structure.
7eaaa8a4480370b82ef3735994f986f338fb4df2vboxsync */
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync#define DIS_READ_REGSEG(p, idx) (*((uint16_t *)((char *)(p) + g_aRegSegIndex[idx])))
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync#define DIS_WRITE_REGSEG(p, idx, val) (*((uint16_t *)((char *)(p) + g_aRegSegIndex[idx])) = val)
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync//*****************************************************************************
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync//*****************************************************************************
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsyncDISDECL(int) DISGetParamSize(PDISCPUSTATE pCpu, PDISOPPARAM pParam)
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync{
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync int subtype = OP_PARM_VSUBTYPE(pParam->param);
0c587d7af645db20acefebcfc15b6f46c440ba4avboxsync
cf5af7fccfec4bef83f4ec21662d6a6e6cbe3835vboxsync if (subtype == OP_PARM_v)
cf5af7fccfec4bef83f4ec21662d6a6e6cbe3835vboxsync {
0c587d7af645db20acefebcfc15b6f46c440ba4avboxsync switch(pCpu->opmode)
17d67aeb3722c094c6493a3e9a9d0cdfb9453ecdvboxsync {
17d67aeb3722c094c6493a3e9a9d0cdfb9453ecdvboxsync case DISCPUMODE_32BIT:
17d67aeb3722c094c6493a3e9a9d0cdfb9453ecdvboxsync subtype = OP_PARM_d;
17d67aeb3722c094c6493a3e9a9d0cdfb9453ecdvboxsync break;
87c50c527af59e43745475c4b8ac907c5f9bc204vboxsync case DISCPUMODE_64BIT:
87c50c527af59e43745475c4b8ac907c5f9bc204vboxsync subtype = OP_PARM_q;
87c50c527af59e43745475c4b8ac907c5f9bc204vboxsync break;
87c50c527af59e43745475c4b8ac907c5f9bc204vboxsync case DISCPUMODE_16BIT:
0c587d7af645db20acefebcfc15b6f46c440ba4avboxsync subtype = OP_PARM_w;
0c587d7af645db20acefebcfc15b6f46c440ba4avboxsync break;
0c587d7af645db20acefebcfc15b6f46c440ba4avboxsync default:
0c587d7af645db20acefebcfc15b6f46c440ba4avboxsync /* make gcc happy */
17d67aeb3722c094c6493a3e9a9d0cdfb9453ecdvboxsync break;
17d67aeb3722c094c6493a3e9a9d0cdfb9453ecdvboxsync }
cf5af7fccfec4bef83f4ec21662d6a6e6cbe3835vboxsync }
cf5af7fccfec4bef83f4ec21662d6a6e6cbe3835vboxsync
0c587d7af645db20acefebcfc15b6f46c440ba4avboxsync switch(subtype)
0c587d7af645db20acefebcfc15b6f46c440ba4avboxsync {
0c587d7af645db20acefebcfc15b6f46c440ba4avboxsync case OP_PARM_b:
cf5af7fccfec4bef83f4ec21662d6a6e6cbe3835vboxsync return 1;
cf5af7fccfec4bef83f4ec21662d6a6e6cbe3835vboxsync
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync case OP_PARM_w:
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync return 2;
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync case OP_PARM_d:
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync return 4;
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync case OP_PARM_q:
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync case OP_PARM_dq:
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync return 8;
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync case OP_PARM_p: /* far pointer */
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync if (pCpu->addrmode == DISCPUMODE_32BIT)
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync return 6; /* 16:32 */
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync else
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync if (pCpu->addrmode == DISCPUMODE_64BIT)
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync return 12; /* 16:64 */
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync else
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync return 4; /* 16:16 */
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync
9704f1d0180960069e2c4eb8fe2ddee350910e5dvboxsync default:
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync if (pParam->cb)
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync return pParam->cb;
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync else //@todo dangerous!!!
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync return 4;
f1acc1e99894e016bd1a6ee65c56b3fc064fa4ebvboxsync }
09ed5ee011f3a6cd9d4742216ad3bb7dbf855641vboxsync}
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync//*****************************************************************************
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync//*****************************************************************************
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsyncDISDECL(DISSELREG) DISDetectSegReg(PDISCPUSTATE pCpu, PDISOPPARAM pParam)
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync{
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync if (pCpu->prefix & DISPREFIX_SEG)
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync /* Use specified SEG: prefix. */
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync return (DISSELREG)pCpu->idxSegPrefix;
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync /* Guess segment register by parameter type. */
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync if (pParam->fUse & (DISUSE_REG_GEN32|DISUSE_REG_GEN64|DISUSE_REG_GEN16))
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync {
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync AssertCompile(DISGREG_ESP == DISGREG_RSP);
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync AssertCompile(DISGREG_EBP == DISGREG_RBP);
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync AssertCompile(DISGREG_ESP == DISGREG_SP);
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync AssertCompile(DISGREG_EBP == DISGREG_BP);
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync if (pParam->base.reg_gen == DISGREG_ESP || pParam->base.reg_gen == DISGREG_EBP)
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync return DISSELREG_SS;
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync }
45c2de093cddc990b8d1583aa49b9a40de7a3d97vboxsync /* Default is use DS: for data access. */
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync return DISSELREG_DS;
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync}
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync//*****************************************************************************
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync//*****************************************************************************
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsyncDISDECL(uint8_t) DISQuerySegPrefixByte(PDISCPUSTATE pCpu)
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync{
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync Assert(pCpu->prefix & DISPREFIX_SEG);
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync switch (pCpu->idxSegPrefix)
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync {
d15e1d56958bda40cd12a7c3a71c962b5a710be2vboxsync case DISSELREG_ES:
d15e1d56958bda40cd12a7c3a71c962b5a710be2vboxsync return 0x26;
d15e1d56958bda40cd12a7c3a71c962b5a710be2vboxsync case DISSELREG_CS:
d15e1d56958bda40cd12a7c3a71c962b5a710be2vboxsync return 0x2E;
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync case DISSELREG_SS:
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync return 0x36;
17d67aeb3722c094c6493a3e9a9d0cdfb9453ecdvboxsync case DISSELREG_DS:
87c50c527af59e43745475c4b8ac907c5f9bc204vboxsync return 0x3E;
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync case DISSELREG_FS:
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync return 0x64;
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync case DISSELREG_GS:
87c50c527af59e43745475c4b8ac907c5f9bc204vboxsync return 0x65;
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync default:
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync AssertFailed();
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync return 0;
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync }
17d67aeb3722c094c6493a3e9a9d0cdfb9453ecdvboxsync}
87c50c527af59e43745475c4b8ac907c5f9bc204vboxsync
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync/**
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync * Returns the value of the specified 8 bits general purpose register
c48c4d769ded37e2496f97dddbbd36dc62f244b1vboxsync *
47eb60db91f50291b3bd9b72b64d36341972a155vboxsync */
c48c4d769ded37e2496f97dddbbd36dc62f244b1vboxsyncDISDECL(int) DISFetchReg8(PCCPUMCTXCORE pCtx, unsigned reg8, uint8_t *pVal)
c48c4d769ded37e2496f97dddbbd36dc62f244b1vboxsync{
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync AssertReturn(reg8 < RT_ELEMENTS(g_aReg8Index), VERR_INVALID_PARAMETER);
7eaaa8a4480370b82ef3735994f986f338fb4df2vboxsync
7eaaa8a4480370b82ef3735994f986f338fb4df2vboxsync *pVal = DIS_READ_REG8(pCtx, reg8);
f5ab5688c35373443d953e2a9fa8a054defdece8vboxsync return VINF_SUCCESS;
f5ab5688c35373443d953e2a9fa8a054defdece8vboxsync}
f5ab5688c35373443d953e2a9fa8a054defdece8vboxsync
f5ab5688c35373443d953e2a9fa8a054defdece8vboxsync/**
f5ab5688c35373443d953e2a9fa8a054defdece8vboxsync * Returns the value of the specified 16 bits general purpose register
f5ab5688c35373443d953e2a9fa8a054defdece8vboxsync *
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync */
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsyncDISDECL(int) DISFetchReg16(PCCPUMCTXCORE pCtx, unsigned reg16, uint16_t *pVal)
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync{
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync AssertReturn(reg16 < RT_ELEMENTS(g_aReg16Index), VERR_INVALID_PARAMETER);
f5ab5688c35373443d953e2a9fa8a054defdece8vboxsync
f5ab5688c35373443d953e2a9fa8a054defdece8vboxsync *pVal = DIS_READ_REG16(pCtx, reg16);
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync return VINF_SUCCESS;
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync}
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync/**
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync * Returns the value of the specified 32 bits general purpose register
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync *
9704f1d0180960069e2c4eb8fe2ddee350910e5dvboxsync */
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsyncDISDECL(int) DISFetchReg32(PCCPUMCTXCORE pCtx, unsigned reg32, uint32_t *pVal)
7eaaa8a4480370b82ef3735994f986f338fb4df2vboxsync{
7eaaa8a4480370b82ef3735994f986f338fb4df2vboxsync AssertReturn(reg32 < RT_ELEMENTS(g_aReg32Index), VERR_INVALID_PARAMETER);
7eaaa8a4480370b82ef3735994f986f338fb4df2vboxsync
0c587d7af645db20acefebcfc15b6f46c440ba4avboxsync *pVal = DIS_READ_REG32(pCtx, reg32);
0c587d7af645db20acefebcfc15b6f46c440ba4avboxsync return VINF_SUCCESS;
0c587d7af645db20acefebcfc15b6f46c440ba4avboxsync}
f5ab5688c35373443d953e2a9fa8a054defdece8vboxsync
f5ab5688c35373443d953e2a9fa8a054defdece8vboxsync/**
f5ab5688c35373443d953e2a9fa8a054defdece8vboxsync * Returns the value of the specified 64 bits general purpose register
f5ab5688c35373443d953e2a9fa8a054defdece8vboxsync *
f5ab5688c35373443d953e2a9fa8a054defdece8vboxsync */
f5ab5688c35373443d953e2a9fa8a054defdece8vboxsyncDISDECL(int) DISFetchReg64(PCCPUMCTXCORE pCtx, unsigned reg64, uint64_t *pVal)
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync{
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync AssertReturn(reg64 < RT_ELEMENTS(g_aReg64Index), VERR_INVALID_PARAMETER);
17d67aeb3722c094c6493a3e9a9d0cdfb9453ecdvboxsync
87c50c527af59e43745475c4b8ac907c5f9bc204vboxsync *pVal = DIS_READ_REG64(pCtx, reg64);
7eaaa8a4480370b82ef3735994f986f338fb4df2vboxsync return VINF_SUCCESS;
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync}
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync/**
0c587d7af645db20acefebcfc15b6f46c440ba4avboxsync * Returns the pointer to the specified 8 bits general purpose register
0c587d7af645db20acefebcfc15b6f46c440ba4avboxsync *
0c587d7af645db20acefebcfc15b6f46c440ba4avboxsync */
aca7a56d52c58d8b388343450503c22822fd6620vboxsyncDISDECL(int) DISPtrReg8(PCPUMCTXCORE pCtx, unsigned reg8, uint8_t **ppReg)
17d67aeb3722c094c6493a3e9a9d0cdfb9453ecdvboxsync{
87c50c527af59e43745475c4b8ac907c5f9bc204vboxsync AssertReturn(reg8 < RT_ELEMENTS(g_aReg8Index), VERR_INVALID_PARAMETER);
aca7a56d52c58d8b388343450503c22822fd6620vboxsync
aca7a56d52c58d8b388343450503c22822fd6620vboxsync *ppReg = DIS_PTR_REG8(pCtx, reg8);
aca7a56d52c58d8b388343450503c22822fd6620vboxsync return VINF_SUCCESS;
17d67aeb3722c094c6493a3e9a9d0cdfb9453ecdvboxsync}
87c50c527af59e43745475c4b8ac907c5f9bc204vboxsync
aca7a56d52c58d8b388343450503c22822fd6620vboxsync/**
aca7a56d52c58d8b388343450503c22822fd6620vboxsync * Returns the pointer to the specified 16 bits general purpose register
aca7a56d52c58d8b388343450503c22822fd6620vboxsync *
aca7a56d52c58d8b388343450503c22822fd6620vboxsync */
17d67aeb3722c094c6493a3e9a9d0cdfb9453ecdvboxsyncDISDECL(int) DISPtrReg16(PCPUMCTXCORE pCtx, unsigned reg16, uint16_t **ppReg)
17d67aeb3722c094c6493a3e9a9d0cdfb9453ecdvboxsync{
87c50c527af59e43745475c4b8ac907c5f9bc204vboxsync AssertReturn(reg16 < RT_ELEMENTS(g_aReg16Index), VERR_INVALID_PARAMETER);
87c50c527af59e43745475c4b8ac907c5f9bc204vboxsync
aca7a56d52c58d8b388343450503c22822fd6620vboxsync *ppReg = DIS_PTR_REG16(pCtx, reg16);
aca7a56d52c58d8b388343450503c22822fd6620vboxsync return VINF_SUCCESS;
aca7a56d52c58d8b388343450503c22822fd6620vboxsync}
aca7a56d52c58d8b388343450503c22822fd6620vboxsync
0c587d7af645db20acefebcfc15b6f46c440ba4avboxsync/**
0c587d7af645db20acefebcfc15b6f46c440ba4avboxsync * Returns the pointer to the specified 32 bits general purpose register
0c587d7af645db20acefebcfc15b6f46c440ba4avboxsync *
0c587d7af645db20acefebcfc15b6f46c440ba4avboxsync */
0c587d7af645db20acefebcfc15b6f46c440ba4avboxsyncDISDECL(int) DISPtrReg32(PCPUMCTXCORE pCtx, unsigned reg32, uint32_t **ppReg)
0c587d7af645db20acefebcfc15b6f46c440ba4avboxsync{
0c587d7af645db20acefebcfc15b6f46c440ba4avboxsync AssertReturn(reg32 < RT_ELEMENTS(g_aReg32Index), VERR_INVALID_PARAMETER);
0c587d7af645db20acefebcfc15b6f46c440ba4avboxsync
0c587d7af645db20acefebcfc15b6f46c440ba4avboxsync *ppReg = DIS_PTR_REG32(pCtx, reg32);
0c587d7af645db20acefebcfc15b6f46c440ba4avboxsync return VINF_SUCCESS;
0c587d7af645db20acefebcfc15b6f46c440ba4avboxsync}
0c587d7af645db20acefebcfc15b6f46c440ba4avboxsync
0c587d7af645db20acefebcfc15b6f46c440ba4avboxsync/**
cf5af7fccfec4bef83f4ec21662d6a6e6cbe3835vboxsync * Returns the pointer to the specified 64 bits general purpose register
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync *
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync */
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsyncDISDECL(int) DISPtrReg64(PCPUMCTXCORE pCtx, unsigned reg64, uint64_t **ppReg)
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync{
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync AssertReturn(reg64 < RT_ELEMENTS(g_aReg64Index), VERR_INVALID_PARAMETER);
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync *ppReg = DIS_PTR_REG64(pCtx, reg64);
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync return VINF_SUCCESS;
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync}
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync/**
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync * Returns the value of the specified segment register
8ae363736c5bbaa490ae89e3a7174f9ad31fe54bvboxsync *
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync */
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsyncDISDECL(int) DISFetchRegSeg(PCCPUMCTXCORE pCtx, DISSELREG sel, RTSEL *pVal)
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync{
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync AssertReturn((unsigned)sel < RT_ELEMENTS(g_aRegSegIndex), VERR_INVALID_PARAMETER);
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync
7eaaa8a4480370b82ef3735994f986f338fb4df2vboxsync AssertCompile(sizeof(uint16_t) == sizeof(RTSEL));
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync *pVal = DIS_READ_REGSEG(pCtx, sel);
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync return VINF_SUCCESS;
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync}
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync/**
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync * Returns the value of the specified segment register including a pointer to the hidden register in the supplied cpu context
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync *
17d67aeb3722c094c6493a3e9a9d0cdfb9453ecdvboxsync */
87c50c527af59e43745475c4b8ac907c5f9bc204vboxsyncDISDECL(int) DISFetchRegSegEx(PCCPUMCTXCORE pCtx, DISSELREG sel, RTSEL *pVal, CPUMSELREGHID **ppSelHidReg)
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync{
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync AssertReturn((unsigned)sel < RT_ELEMENTS(g_aRegSegIndex), VERR_INVALID_PARAMETER);
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync AssertCompile(sizeof(uint16_t) == sizeof(RTSEL));
87c50c527af59e43745475c4b8ac907c5f9bc204vboxsync *pVal = DIS_READ_REGSEG(pCtx, sel);
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync *ppSelHidReg = (CPUMSELREGHID *)((char *)pCtx + g_aRegHidSegIndex[sel]);
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync return VINF_SUCCESS;
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync}
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync/**
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync * Updates the value of the specified 64 bits general purpose register
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync *
c48c4d769ded37e2496f97dddbbd36dc62f244b1vboxsync */
47eb60db91f50291b3bd9b72b64d36341972a155vboxsyncDISDECL(int) DISWriteReg64(PCPUMCTXCORE pRegFrame, unsigned reg64, uint64_t val64)
c48c4d769ded37e2496f97dddbbd36dc62f244b1vboxsync{
c48c4d769ded37e2496f97dddbbd36dc62f244b1vboxsync AssertReturn(reg64 < RT_ELEMENTS(g_aReg64Index), VERR_INVALID_PARAMETER);
4d5da2bfd5523ad009912e6e0cfb8bf480160e32vboxsync
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync DIS_WRITE_REG64(pRegFrame, reg64, val64);
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync return VINF_SUCCESS;
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync}
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync/**
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync * Updates the value of the specified 32 bits general purpose register
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync *
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync */
a0fb1a3d470c09467cd37844f38cf7152c9d2f75vboxsyncDISDECL(int) DISWriteReg32(PCPUMCTXCORE pRegFrame, unsigned reg32, uint32_t val32)
a0fb1a3d470c09467cd37844f38cf7152c9d2f75vboxsync{
8e5c5c9547558e845335d3077d17422b4ee85b89vboxsync AssertReturn(reg32 < RT_ELEMENTS(g_aReg32Index), VERR_INVALID_PARAMETER);
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync
17d67aeb3722c094c6493a3e9a9d0cdfb9453ecdvboxsync DIS_WRITE_REG32(pRegFrame, reg32, val32);
87c50c527af59e43745475c4b8ac907c5f9bc204vboxsync return VINF_SUCCESS;
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync}
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync/**
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync * Updates the value of the specified 16 bits general purpose register
ed970880a556512196471e9cdd0d793e68943ec6vboxsync *
87c50c527af59e43745475c4b8ac907c5f9bc204vboxsync */
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsyncDISDECL(int) DISWriteReg16(PCPUMCTXCORE pRegFrame, unsigned reg16, uint16_t val16)
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync{
dbfaafc0d352df8a264ef8a09cf56ea20c93cb2cvboxsync AssertReturn(reg16 < RT_ELEMENTS(g_aReg16Index), VERR_INVALID_PARAMETER);
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync DIS_WRITE_REG16(pRegFrame, reg16, val16);
dbfaafc0d352df8a264ef8a09cf56ea20c93cb2cvboxsync return VINF_SUCCESS;
dbfaafc0d352df8a264ef8a09cf56ea20c93cb2cvboxsync}
dbfaafc0d352df8a264ef8a09cf56ea20c93cb2cvboxsync
dbfaafc0d352df8a264ef8a09cf56ea20c93cb2cvboxsync/**
dbfaafc0d352df8a264ef8a09cf56ea20c93cb2cvboxsync * Updates the specified 8 bits general purpose register
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync *
*/
DISDECL(int) DISWriteReg8(PCPUMCTXCORE pRegFrame, unsigned reg8, uint8_t val8)
{
AssertReturn(reg8 < RT_ELEMENTS(g_aReg8Index), VERR_INVALID_PARAMETER);
DIS_WRITE_REG8(pRegFrame, reg8, val8);
return VINF_SUCCESS;
}
/**
* Updates the specified segment register
*
*/
DISDECL(int) DISWriteRegSeg(PCPUMCTXCORE pCtx, DISSELREG sel, RTSEL val)
{
AssertReturn((unsigned)sel < RT_ELEMENTS(g_aRegSegIndex), VERR_INVALID_PARAMETER);
AssertCompile(sizeof(uint16_t) == sizeof(RTSEL));
DIS_WRITE_REGSEG(pCtx, sel, val);
return VINF_SUCCESS;
}
/**
* Returns the value of the parameter in pParam
*
* @returns VBox error code
* @param pCtx CPU context structure pointer
* @param pCpu Pointer to cpu structure which have DISCPUSTATE::mode
* set correctly.
* @param pParam Pointer to the parameter to parse
* @param pParamVal Pointer to parameter value (OUT)
* @param parmtype Parameter type
*
* @note Currently doesn't handle FPU/XMM/MMX/3DNow! parameters correctly!!
*
*/
DISDECL(int) DISQueryParamVal(PCPUMCTXCORE pCtx, PDISCPUSTATE pCpu, PDISOPPARAM pParam, PDISQPVPARAMVAL pParamVal, DISQPVWHICH parmtype)
{
memset(pParamVal, 0, sizeof(*pParamVal));
if (DISUSE_IS_EFFECTIVE_ADDR(pParam->fUse))
{
// Effective address
pParamVal->type = DISQPV_TYPE_ADDRESS;
pParamVal->size = pParam->cb;
if (pParam->fUse & DISUSE_BASE)
{
if (pParam->fUse & DISUSE_REG_GEN8)
{
pParamVal->flags |= DISQPV_FLAG_8;
if (RT_FAILURE(DISFetchReg8(pCtx, pParam->base.reg_gen, &pParamVal->val.val8))) return VERR_INVALID_PARAMETER;
}
else
if (pParam->fUse & DISUSE_REG_GEN16)
{
pParamVal->flags |= DISQPV_FLAG_16;
if (RT_FAILURE(DISFetchReg16(pCtx, pParam->base.reg_gen, &pParamVal->val.val16))) return VERR_INVALID_PARAMETER;
}
else
if (pParam->fUse & DISUSE_REG_GEN32)
{
pParamVal->flags |= DISQPV_FLAG_32;
if (RT_FAILURE(DISFetchReg32(pCtx, pParam->base.reg_gen, &pParamVal->val.val32))) return VERR_INVALID_PARAMETER;
}
else
if (pParam->fUse & DISUSE_REG_GEN64)
{
pParamVal->flags |= DISQPV_FLAG_64;
if (RT_FAILURE(DISFetchReg64(pCtx, pParam->base.reg_gen, &pParamVal->val.val64))) return VERR_INVALID_PARAMETER;
}
else
{
AssertFailed();
return VERR_INVALID_PARAMETER;
}
}
// Note that scale implies index (SIB byte)
if (pParam->fUse & DISUSE_INDEX)
{
if (pParam->fUse & DISUSE_REG_GEN16)
{
uint16_t val16;
pParamVal->flags |= DISQPV_FLAG_16;
if (RT_FAILURE(DISFetchReg16(pCtx, pParam->index.reg_gen, &val16))) return VERR_INVALID_PARAMETER;
Assert(!(pParam->fUse & DISUSE_SCALE)); /* shouldn't be possible in 16 bits mode */
pParamVal->val.val16 += val16;
}
else
if (pParam->fUse & DISUSE_REG_GEN32)
{
uint32_t val32;
pParamVal->flags |= DISQPV_FLAG_32;
if (RT_FAILURE(DISFetchReg32(pCtx, pParam->index.reg_gen, &val32))) return VERR_INVALID_PARAMETER;
if (pParam->fUse & DISUSE_SCALE)
val32 *= pParam->scale;
pParamVal->val.val32 += val32;
}
else
if (pParam->fUse & DISUSE_REG_GEN64)
{
uint64_t val64;
pParamVal->flags |= DISQPV_FLAG_64;
if (RT_FAILURE(DISFetchReg64(pCtx, pParam->index.reg_gen, &val64))) return VERR_INVALID_PARAMETER;
if (pParam->fUse & DISUSE_SCALE)
val64 *= pParam->scale;
pParamVal->val.val64 += val64;
}
else
AssertFailed();
}
if (pParam->fUse & DISUSE_DISPLACEMENT8)
{
if (pCpu->mode == DISCPUMODE_32BIT)
pParamVal->val.val32 += (int32_t)pParam->uDisp.i8;
else
if (pCpu->mode == DISCPUMODE_64BIT)
pParamVal->val.val64 += (int64_t)pParam->uDisp.i8;
else
pParamVal->val.val16 += (int16_t)pParam->uDisp.i8;
}
else
if (pParam->fUse & DISUSE_DISPLACEMENT16)
{
if (pCpu->mode == DISCPUMODE_32BIT)
pParamVal->val.val32 += (int32_t)pParam->uDisp.i16;
else
if (pCpu->mode == DISCPUMODE_64BIT)
pParamVal->val.val64 += (int64_t)pParam->uDisp.i16;
else
pParamVal->val.val16 += pParam->uDisp.i16;
}
else
if (pParam->fUse & DISUSE_DISPLACEMENT32)
{
if (pCpu->mode == DISCPUMODE_32BIT)
pParamVal->val.val32 += pParam->uDisp.i32;
else
pParamVal->val.val64 += pParam->uDisp.i32;
}
else
if (pParam->fUse & DISUSE_DISPLACEMENT64)
{
Assert(pCpu->mode == DISCPUMODE_64BIT);
pParamVal->val.val64 += pParam->uDisp.i64;
}
else
if (pParam->fUse & DISUSE_RIPDISPLACEMENT32)
{
Assert(pCpu->mode == DISCPUMODE_64BIT);
/* Relative to the RIP of the next instruction. */
pParamVal->val.val64 += pParam->uDisp.i32 + pCtx->rip + pCpu->opsize;
}
return VINF_SUCCESS;
}
if (pParam->fUse & (DISUSE_REG_GEN8|DISUSE_REG_GEN16|DISUSE_REG_GEN32|DISUSE_REG_GEN64|DISUSE_REG_FP|DISUSE_REG_MMX|DISUSE_REG_XMM|DISUSE_REG_CR|DISUSE_REG_DBG|DISUSE_REG_SEG|DISUSE_REG_TEST))
{
if (parmtype == DISQPVWHICH_DST)
{
// Caller needs to interpret the register according to the instruction (source/target, special value etc)
pParamVal->type = DISQPV_TYPE_REGISTER;
pParamVal->size = pParam->cb;
return VINF_SUCCESS;
}
//else DISQPVWHICH_SRC
pParamVal->type = DISQPV_TYPE_IMMEDIATE;
if (pParam->fUse & DISUSE_REG_GEN8)
{
pParamVal->flags |= DISQPV_FLAG_8;
pParamVal->size = sizeof(uint8_t);
if (RT_FAILURE(DISFetchReg8(pCtx, pParam->base.reg_gen, &pParamVal->val.val8))) return VERR_INVALID_PARAMETER;
}
else
if (pParam->fUse & DISUSE_REG_GEN16)
{
pParamVal->flags |= DISQPV_FLAG_16;
pParamVal->size = sizeof(uint16_t);
if (RT_FAILURE(DISFetchReg16(pCtx, pParam->base.reg_gen, &pParamVal->val.val16))) return VERR_INVALID_PARAMETER;
}
else
if (pParam->fUse & DISUSE_REG_GEN32)
{
pParamVal->flags |= DISQPV_FLAG_32;
pParamVal->size = sizeof(uint32_t);
if (RT_FAILURE(DISFetchReg32(pCtx, pParam->base.reg_gen, &pParamVal->val.val32))) return VERR_INVALID_PARAMETER;
}
else
if (pParam->fUse & DISUSE_REG_GEN64)
{
pParamVal->flags |= DISQPV_FLAG_64;
pParamVal->size = sizeof(uint64_t);
if (RT_FAILURE(DISFetchReg64(pCtx, pParam->base.reg_gen, &pParamVal->val.val64))) return VERR_INVALID_PARAMETER;
}
else
{
// Caller needs to interpret the register according to the instruction (source/target, special value etc)
pParamVal->type = DISQPV_TYPE_REGISTER;
}
Assert(!(pParam->fUse & DISUSE_IMMEDIATE));
return VINF_SUCCESS;
}
if (pParam->fUse & DISUSE_IMMEDIATE)
{
pParamVal->type = DISQPV_TYPE_IMMEDIATE;
if (pParam->fUse & (DISUSE_IMMEDIATE8|DISUSE_IMMEDIATE8_REL))
{
pParamVal->flags |= DISQPV_FLAG_8;
if (pParam->cb == 2)
{
pParamVal->size = sizeof(uint16_t);
pParamVal->val.val16 = (uint8_t)pParam->parval;
}
else
{
pParamVal->size = sizeof(uint8_t);
pParamVal->val.val8 = (uint8_t)pParam->parval;
}
}
else
if (pParam->fUse & (DISUSE_IMMEDIATE16|DISUSE_IMMEDIATE16_REL|DISUSE_IMMEDIATE_ADDR_0_16|DISUSE_IMMEDIATE16_SX8))
{
pParamVal->flags |= DISQPV_FLAG_16;
pParamVal->size = sizeof(uint16_t);
pParamVal->val.val16 = (uint16_t)pParam->parval;
AssertMsg(pParamVal->size == pParam->cb || ((pParam->cb == 1) && (pParam->fUse & DISUSE_IMMEDIATE16_SX8)), ("pParamVal->size %d vs %d EIP=%RX32\n", pParamVal->size, pParam->cb, pCtx->eip) );
}
else
if (pParam->fUse & (DISUSE_IMMEDIATE32|DISUSE_IMMEDIATE32_REL|DISUSE_IMMEDIATE_ADDR_0_32|DISUSE_IMMEDIATE32_SX8))
{
pParamVal->flags |= DISQPV_FLAG_32;
pParamVal->size = sizeof(uint32_t);
pParamVal->val.val32 = (uint32_t)pParam->parval;
Assert(pParamVal->size == pParam->cb || ((pParam->cb == 1) && (pParam->fUse & DISUSE_IMMEDIATE32_SX8)) );
}
else
if (pParam->fUse & (DISUSE_IMMEDIATE64 | DISUSE_IMMEDIATE64_REL | DISUSE_IMMEDIATE64_SX8))
{
pParamVal->flags |= DISQPV_FLAG_64;
pParamVal->size = sizeof(uint64_t);
pParamVal->val.val64 = pParam->parval;
Assert(pParamVal->size == pParam->cb || ((pParam->cb == 1) && (pParam->fUse & DISUSE_IMMEDIATE64_SX8)) );
}
else
if (pParam->fUse & (DISUSE_IMMEDIATE_ADDR_16_16))
{
pParamVal->flags |= DISQPV_FLAG_FARPTR16;
pParamVal->size = sizeof(uint16_t)*2;
pParamVal->val.farptr.sel = (uint16_t)RT_LOWORD(pParam->parval >> 16);
pParamVal->val.farptr.offset = (uint32_t)RT_LOWORD(pParam->parval);
Assert(pParamVal->size == pParam->cb);
}
else
if (pParam->fUse & (DISUSE_IMMEDIATE_ADDR_16_32))
{
pParamVal->flags |= DISQPV_FLAG_FARPTR32;
pParamVal->size = sizeof(uint16_t) + sizeof(uint32_t);
pParamVal->val.farptr.sel = (uint16_t)RT_LOWORD(pParam->parval >> 32);
pParamVal->val.farptr.offset = (uint32_t)(pParam->parval & 0xFFFFFFFF);
Assert(pParam->cb == 8);
}
}
return VINF_SUCCESS;
}
/**
* Returns the pointer to a register of the parameter in pParam. We need this
* pointer when an interpreted instruction updates a register as a side effect.
* In CMPXCHG we know that only [r/e]ax is updated, but with XADD this could
* be every register.
*
* @returns VBox error code
* @param pCtx CPU context structure pointer
* @param pCpu Pointer to cpu structure which have DISCPUSTATE::mode
* set correctly.
* @param pParam Pointer to the parameter to parse
* @param pReg Pointer to parameter value (OUT)
* @param cbsize Parameter size (OUT)
*
* @note Currently doesn't handle FPU/XMM/MMX/3DNow! parameters correctly!!
*
*/
DISDECL(int) DISQueryParamRegPtr(PCPUMCTXCORE pCtx, PDISCPUSTATE pCpu, PDISOPPARAM pParam, void **ppReg, size_t *pcbSize)
{
NOREF(pCpu);
if (pParam->fUse & (DISUSE_REG_GEN8|DISUSE_REG_GEN16|DISUSE_REG_GEN32|DISUSE_REG_FP|DISUSE_REG_MMX|DISUSE_REG_XMM|DISUSE_REG_CR|DISUSE_REG_DBG|DISUSE_REG_SEG|DISUSE_REG_TEST))
{
if (pParam->fUse & DISUSE_REG_GEN8)
{
uint8_t *pu8Reg;
if (RT_SUCCESS(DISPtrReg8(pCtx, pParam->base.reg_gen, &pu8Reg)))
{
*pcbSize = sizeof(uint8_t);
*ppReg = (void *)pu8Reg;
return VINF_SUCCESS;
}
}
else
if (pParam->fUse & DISUSE_REG_GEN16)
{
uint16_t *pu16Reg;
if (RT_SUCCESS(DISPtrReg16(pCtx, pParam->base.reg_gen, &pu16Reg)))
{
*pcbSize = sizeof(uint16_t);
*ppReg = (void *)pu16Reg;
return VINF_SUCCESS;
}
}
else
if (pParam->fUse & DISUSE_REG_GEN32)
{
uint32_t *pu32Reg;
if (RT_SUCCESS(DISPtrReg32(pCtx, pParam->base.reg_gen, &pu32Reg)))
{
*pcbSize = sizeof(uint32_t);
*ppReg = (void *)pu32Reg;
return VINF_SUCCESS;
}
}
else
if (pParam->fUse & DISUSE_REG_GEN64)
{
uint64_t *pu64Reg;
if (RT_SUCCESS(DISPtrReg64(pCtx, pParam->base.reg_gen, &pu64Reg)))
{
*pcbSize = sizeof(uint64_t);
*ppReg = (void *)pu64Reg;
return VINF_SUCCESS;
}
}
}
return VERR_INVALID_PARAMETER;
}