DisasmReg.cpp revision 0aa1ba1d1ea27baa7762e4fe891824df38697189
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync * VBox disassembler- Register Info Helpers.
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync * Copyright (C) 2006-2012 Oracle Corporation
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync * This file is part of VirtualBox Open Source Edition (OSE), as
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync * available from http://www.virtualbox.org. This file is free software;
d63de4508a08b11f57c307a15eda3cd95485bf2cvboxsync * you can redistribute it and/or modify it under the terms of the GNU
d63de4508a08b11f57c307a15eda3cd95485bf2cvboxsync * General Public License (GPL) as published by the Free Software
d63de4508a08b11f57c307a15eda3cd95485bf2cvboxsync * Foundation, in version 2 as it comes in the "COPYING" file of the
d63de4508a08b11f57c307a15eda3cd95485bf2cvboxsync * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync/*******************************************************************************
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync* Header Files *
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync*******************************************************************************/
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync/*******************************************************************************
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync* Global Variables *
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync*******************************************************************************/
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync * Array for accessing 64-bit general registers in VMMREGFRAME structure
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync * by register's index from disasm.
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsyncstatic const unsigned g_aReg64Index[] =
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync * Macro for accessing 64-bit general purpose registers in CPUMCTXCORE structure.
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync#define DIS_READ_REG64(p, idx) (*(uint64_t *)((char *)(p) + g_aReg64Index[idx]))
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync#define DIS_WRITE_REG64(p, idx, val) (*(uint64_t *)((char *)(p) + g_aReg64Index[idx]) = val)
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync#define DIS_PTR_REG64(p, idx) ( (uint64_t *)((char *)(p) + g_aReg64Index[idx]))
c6adb272ec43d5eaadb1493cb2bf45f2f8adf588vboxsync * Array for accessing 32-bit general registers in VMMREGFRAME structure
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync * by register's index from disasm.
58b7773f17a933ab8d53f450bed0afcf2f003508vboxsyncstatic const unsigned g_aReg32Index[] =
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync * Macro for accessing 32-bit general purpose registers in CPUMCTXCORE structure.
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync#define DIS_READ_REG32(p, idx) (*(uint32_t *)((char *)(p) + g_aReg32Index[idx]))
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync/* From http://www.cs.cmu.edu/~fp/courses/15213-s06/misc/asm64-handout.pdf:
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync * ``Perhaps unexpectedly, instructions that move or generate 32-bit register
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync * values also set the upper 32 bits of the register to zero. Consequently
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync * there is no need for an instruction movzlq.''
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync#define DIS_WRITE_REG32(p, idx, val) (*(uint64_t *)((char *)(p) + g_aReg32Index[idx]) = (uint32_t)val)
c6adb272ec43d5eaadb1493cb2bf45f2f8adf588vboxsync#define DIS_PTR_REG32(p, idx) ( (uint32_t *)((char *)(p) + g_aReg32Index[idx]))
c48c4d769ded37e2496f97dddbbd36dc62f244b1vboxsync * Array for accessing 16-bit general registers in CPUMCTXCORE structure
257927abbaa6d9774427049fcbea552cda362281vboxsync * by register's index from disasm.
257927abbaa6d9774427049fcbea552cda362281vboxsyncstatic const unsigned g_aReg16Index[] =
4bc1bbf45f30ff3ca38c2ad006836e490972c7ccvboxsync * Macro for accessing 16-bit general purpose registers in CPUMCTXCORE structure.
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync#define DIS_READ_REG16(p, idx) (*(uint16_t *)((char *)(p) + g_aReg16Index[idx]))
3684b2b9eeb77285df2dc641fcf6f70805568be8vboxsync#define DIS_WRITE_REG16(p, idx, val) (*(uint16_t *)((char *)(p) + g_aReg16Index[idx]) = val)
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync#define DIS_PTR_REG16(p, idx) ( (uint16_t *)((char *)(p) + g_aReg16Index[idx]))
73e8df2e481cb3697372a3cf4acffd068a7f1296vboxsync * Array for accessing 8-bit general registers in CPUMCTXCORE structure
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync * by register's index from disasm.
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsyncstatic const unsigned g_aReg8Index[] =
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync RT_OFFSETOF_ADD(CPUMCTXCORE, eax, 1), /* DISGREG_AH */
73e8df2e481cb3697372a3cf4acffd068a7f1296vboxsync RT_OFFSETOF_ADD(CPUMCTXCORE, ecx, 1), /* DISGREG_CH */
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync RT_OFFSETOF_ADD(CPUMCTXCORE, edx, 1), /* DISGREG_DH */
d293c8e7a1adaf427e7a361add878676749b7da6vboxsync RT_OFFSETOF_ADD(CPUMCTXCORE, ebx, 1), /* DISGREG_BH */
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync RT_OFFSETOF(CPUMCTXCORE, esp), /* DISGREG_SPL; with REX prefix only */
3684b2b9eeb77285df2dc641fcf6f70805568be8vboxsync RT_OFFSETOF(CPUMCTXCORE, ebp), /* DISGREG_BPL; with REX prefix only */
a3d06a524c4f1cde2f0eada83656543d5a24115dvboxsync RT_OFFSETOF(CPUMCTXCORE, esi), /* DISGREG_SIL; with REX prefix only */
a3d06a524c4f1cde2f0eada83656543d5a24115dvboxsync RT_OFFSETOF(CPUMCTXCORE, edi) /* DISGREG_DIL; with REX prefix only */
a3d06a524c4f1cde2f0eada83656543d5a24115dvboxsync * Macro for accessing 8-bit general purpose registers in CPUMCTXCORE structure.
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync#define DIS_READ_REG8(p, idx) (*(uint8_t *)((char *)(p) + g_aReg8Index[idx]))
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync#define DIS_WRITE_REG8(p, idx, val) (*(uint8_t *)((char *)(p) + g_aReg8Index[idx]) = val)
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync#define DIS_PTR_REG8(p, idx) ( (uint8_t *)((char *)(p) + g_aReg8Index[idx]))
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync * Array for accessing segment registers in CPUMCTXCORE structure
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync * by register's index from disasm.
17d67aeb3722c094c6493a3e9a9d0cdfb9453ecdvboxsyncstatic const unsigned g_aRegSegIndex[] =
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsyncstatic const unsigned g_aRegHidSegIndex[] =
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync RT_OFFSETOF(CPUMCTXCORE, esHid), /* DISSELREG_ES */
58b7773f17a933ab8d53f450bed0afcf2f003508vboxsync RT_OFFSETOF(CPUMCTXCORE, csHid), /* DISSELREG_CS */
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync RT_OFFSETOF(CPUMCTXCORE, ssHid), /* DISSELREG_SS */
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync RT_OFFSETOF(CPUMCTXCORE, dsHid), /* DISSELREG_DS */
58b7773f17a933ab8d53f450bed0afcf2f003508vboxsync RT_OFFSETOF(CPUMCTXCORE, fsHid), /* DISSELREG_FS */
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync * Macro for accessing segment registers in CPUMCTXCORE structure.
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync#define DIS_READ_REGSEG(p, idx) (*((uint16_t *)((char *)(p) + g_aRegSegIndex[idx])))
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync#define DIS_WRITE_REGSEG(p, idx, val) (*((uint16_t *)((char *)(p) + g_aRegSegIndex[idx])) = val)
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync//*****************************************************************************
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync//*****************************************************************************
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsyncDISDECL(int) DISGetParamSize(PDISCPUSTATE pCpu, PDISOPPARAM pParam)
0c587d7af645db20acefebcfc15b6f46c440ba4avboxsync /* make gcc happy */
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync else //@todo dangerous!!!
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync//*****************************************************************************
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync//*****************************************************************************
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsyncDISDECL(DISSELREG) DISDetectSegReg(PDISCPUSTATE pCpu, PDISOPPARAM pParam)
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync /* Use specified SEG: prefix. */
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync /* Guess segment register by parameter type. */
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync if (pParam->fUse & (DISUSE_REG_GEN32|DISUSE_REG_GEN64|DISUSE_REG_GEN16))
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync if (pParam->base.reg_gen == DISGREG_ESP || pParam->base.reg_gen == DISGREG_EBP)
45c2de093cddc990b8d1583aa49b9a40de7a3d97vboxsync /* Default is use DS: for data access. */
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync//*****************************************************************************
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync//*****************************************************************************
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsyncDISDECL(uint8_t) DISQuerySegPrefixByte(PDISCPUSTATE pCpu)
d15e1d56958bda40cd12a7c3a71c962b5a710be2vboxsync return 0x26;
d15e1d56958bda40cd12a7c3a71c962b5a710be2vboxsync return 0x2E;
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync return 0x36;
87c50c527af59e43745475c4b8ac907c5f9bc204vboxsync return 0x3E;
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync return 0x64;
87c50c527af59e43745475c4b8ac907c5f9bc204vboxsync return 0x65;
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync * Returns the value of the specified 8 bits general purpose register
c48c4d769ded37e2496f97dddbbd36dc62f244b1vboxsyncDISDECL(int) DISFetchReg8(PCCPUMCTXCORE pCtx, unsigned reg8, uint8_t *pVal)
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync AssertReturn(reg8 < RT_ELEMENTS(g_aReg8Index), VERR_INVALID_PARAMETER);
f5ab5688c35373443d953e2a9fa8a054defdece8vboxsync * Returns the value of the specified 16 bits general purpose register
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsyncDISDECL(int) DISFetchReg16(PCCPUMCTXCORE pCtx, unsigned reg16, uint16_t *pVal)
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync AssertReturn(reg16 < RT_ELEMENTS(g_aReg16Index), VERR_INVALID_PARAMETER);
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync * Returns the value of the specified 32 bits general purpose register
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsyncDISDECL(int) DISFetchReg32(PCCPUMCTXCORE pCtx, unsigned reg32, uint32_t *pVal)
7eaaa8a4480370b82ef3735994f986f338fb4df2vboxsync AssertReturn(reg32 < RT_ELEMENTS(g_aReg32Index), VERR_INVALID_PARAMETER);
f5ab5688c35373443d953e2a9fa8a054defdece8vboxsync * Returns the value of the specified 64 bits general purpose register
f5ab5688c35373443d953e2a9fa8a054defdece8vboxsyncDISDECL(int) DISFetchReg64(PCCPUMCTXCORE pCtx, unsigned reg64, uint64_t *pVal)
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync AssertReturn(reg64 < RT_ELEMENTS(g_aReg64Index), VERR_INVALID_PARAMETER);
0c587d7af645db20acefebcfc15b6f46c440ba4avboxsync * Returns the pointer to the specified 8 bits general purpose register
aca7a56d52c58d8b388343450503c22822fd6620vboxsyncDISDECL(int) DISPtrReg8(PCPUMCTXCORE pCtx, unsigned reg8, uint8_t **ppReg)
87c50c527af59e43745475c4b8ac907c5f9bc204vboxsync AssertReturn(reg8 < RT_ELEMENTS(g_aReg8Index), VERR_INVALID_PARAMETER);
aca7a56d52c58d8b388343450503c22822fd6620vboxsync * Returns the pointer to the specified 16 bits general purpose register
17d67aeb3722c094c6493a3e9a9d0cdfb9453ecdvboxsyncDISDECL(int) DISPtrReg16(PCPUMCTXCORE pCtx, unsigned reg16, uint16_t **ppReg)
87c50c527af59e43745475c4b8ac907c5f9bc204vboxsync AssertReturn(reg16 < RT_ELEMENTS(g_aReg16Index), VERR_INVALID_PARAMETER);
0c587d7af645db20acefebcfc15b6f46c440ba4avboxsync * Returns the pointer to the specified 32 bits general purpose register
0c587d7af645db20acefebcfc15b6f46c440ba4avboxsyncDISDECL(int) DISPtrReg32(PCPUMCTXCORE pCtx, unsigned reg32, uint32_t **ppReg)
0c587d7af645db20acefebcfc15b6f46c440ba4avboxsync AssertReturn(reg32 < RT_ELEMENTS(g_aReg32Index), VERR_INVALID_PARAMETER);
cf5af7fccfec4bef83f4ec21662d6a6e6cbe3835vboxsync * Returns the pointer to the specified 64 bits general purpose register
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsyncDISDECL(int) DISPtrReg64(PCPUMCTXCORE pCtx, unsigned reg64, uint64_t **ppReg)
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync AssertReturn(reg64 < RT_ELEMENTS(g_aReg64Index), VERR_INVALID_PARAMETER);
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync * Returns the value of the specified segment register
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsyncDISDECL(int) DISFetchRegSeg(PCCPUMCTXCORE pCtx, DISSELREG sel, RTSEL *pVal)
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync AssertReturn((unsigned)sel < RT_ELEMENTS(g_aRegSegIndex), VERR_INVALID_PARAMETER);
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync * Returns the value of the specified segment register including a pointer to the hidden register in the supplied cpu context
87c50c527af59e43745475c4b8ac907c5f9bc204vboxsyncDISDECL(int) DISFetchRegSegEx(PCCPUMCTXCORE pCtx, DISSELREG sel, RTSEL *pVal, CPUMSELREGHID **ppSelHidReg)
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync AssertReturn((unsigned)sel < RT_ELEMENTS(g_aRegSegIndex), VERR_INVALID_PARAMETER);
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync *ppSelHidReg = (CPUMSELREGHID *)((char *)pCtx + g_aRegHidSegIndex[sel]);
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync * Updates the value of the specified 64 bits general purpose register
47eb60db91f50291b3bd9b72b64d36341972a155vboxsyncDISDECL(int) DISWriteReg64(PCPUMCTXCORE pRegFrame, unsigned reg64, uint64_t val64)
c48c4d769ded37e2496f97dddbbd36dc62f244b1vboxsync AssertReturn(reg64 < RT_ELEMENTS(g_aReg64Index), VERR_INVALID_PARAMETER);
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync * Updates the value of the specified 32 bits general purpose register
a0fb1a3d470c09467cd37844f38cf7152c9d2f75vboxsyncDISDECL(int) DISWriteReg32(PCPUMCTXCORE pRegFrame, unsigned reg32, uint32_t val32)
8e5c5c9547558e845335d3077d17422b4ee85b89vboxsync AssertReturn(reg32 < RT_ELEMENTS(g_aReg32Index), VERR_INVALID_PARAMETER);
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsync * Updates the value of the specified 16 bits general purpose register
5f9dfb422a6ed57822f9c0cb94fa7df8d24acc9bvboxsyncDISDECL(int) DISWriteReg16(PCPUMCTXCORE pRegFrame, unsigned reg16, uint16_t val16)
dbfaafc0d352df8a264ef8a09cf56ea20c93cb2cvboxsync AssertReturn(reg16 < RT_ELEMENTS(g_aReg16Index), VERR_INVALID_PARAMETER);
dbfaafc0d352df8a264ef8a09cf56ea20c93cb2cvboxsync * Updates the specified 8 bits general purpose register
return VINF_SUCCESS;
return VINF_SUCCESS;
DISDECL(int) DISQueryParamVal(PCPUMCTXCORE pCtx, PDISCPUSTATE pCpu, PDISOPPARAM pParam, PDISQPVPARAMVAL pParamVal, DISQPVWHICH parmtype)
if (RT_FAILURE(DISFetchReg8(pCtx, pParam->base.reg_gen, &pParamVal->val.val8))) return VERR_INVALID_PARAMETER;
if (RT_FAILURE(DISFetchReg16(pCtx, pParam->base.reg_gen, &pParamVal->val.val16))) return VERR_INVALID_PARAMETER;
if (RT_FAILURE(DISFetchReg32(pCtx, pParam->base.reg_gen, &pParamVal->val.val32))) return VERR_INVALID_PARAMETER;
if (RT_FAILURE(DISFetchReg64(pCtx, pParam->base.reg_gen, &pParamVal->val.val64))) return VERR_INVALID_PARAMETER;
AssertFailed();
return VERR_INVALID_PARAMETER;
AssertFailed();
return VINF_SUCCESS;
if (pParam->fUse & (DISUSE_REG_GEN8|DISUSE_REG_GEN16|DISUSE_REG_GEN32|DISUSE_REG_GEN64|DISUSE_REG_FP|DISUSE_REG_MMX|DISUSE_REG_XMM|DISUSE_REG_CR|DISUSE_REG_DBG|DISUSE_REG_SEG|DISUSE_REG_TEST))
// Caller needs to interpret the register according to the instruction (source/target, special value etc)
return VINF_SUCCESS;
if (RT_FAILURE(DISFetchReg8(pCtx, pParam->base.reg_gen, &pParamVal->val.val8))) return VERR_INVALID_PARAMETER;
if (RT_FAILURE(DISFetchReg16(pCtx, pParam->base.reg_gen, &pParamVal->val.val16))) return VERR_INVALID_PARAMETER;
if (RT_FAILURE(DISFetchReg32(pCtx, pParam->base.reg_gen, &pParamVal->val.val32))) return VERR_INVALID_PARAMETER;
if (RT_FAILURE(DISFetchReg64(pCtx, pParam->base.reg_gen, &pParamVal->val.val64))) return VERR_INVALID_PARAMETER;
// Caller needs to interpret the register according to the instruction (source/target, special value etc)
return VINF_SUCCESS;
if (pParam->fUse & (DISUSE_IMMEDIATE16|DISUSE_IMMEDIATE16_REL|DISUSE_IMMEDIATE_ADDR_0_16|DISUSE_IMMEDIATE16_SX8))
AssertMsg(pParamVal->size == pParam->cb || ((pParam->cb == 1) && (pParam->fUse & DISUSE_IMMEDIATE16_SX8)), ("pParamVal->size %d vs %d EIP=%RX32\n", pParamVal->size, pParam->cb, pCtx->eip) );
if (pParam->fUse & (DISUSE_IMMEDIATE32|DISUSE_IMMEDIATE32_REL|DISUSE_IMMEDIATE_ADDR_0_32|DISUSE_IMMEDIATE32_SX8))
Assert(pParamVal->size == pParam->cb || ((pParam->cb == 1) && (pParam->fUse & DISUSE_IMMEDIATE32_SX8)) );
Assert(pParamVal->size == pParam->cb || ((pParam->cb == 1) && (pParam->fUse & DISUSE_IMMEDIATE64_SX8)) );
return VINF_SUCCESS;
DISDECL(int) DISQueryParamRegPtr(PCPUMCTXCORE pCtx, PDISCPUSTATE pCpu, PDISOPPARAM pParam, void **ppReg, size_t *pcbSize)
if (pParam->fUse & (DISUSE_REG_GEN8|DISUSE_REG_GEN16|DISUSE_REG_GEN32|DISUSE_REG_FP|DISUSE_REG_MMX|DISUSE_REG_XMM|DISUSE_REG_CR|DISUSE_REG_DBG|DISUSE_REG_SEG|DISUSE_REG_TEST))
return VINF_SUCCESS;
return VINF_SUCCESS;
return VINF_SUCCESS;
return VINF_SUCCESS;
return VERR_INVALID_PARAMETER;