DisasmReg.cpp revision 70fa291a159216a90eea85d879c46bf4d86ed545
d7097a142464c500766b2cb3d564986e0a072799vboxsync * VBox disassembler- Register Info Helpers.
d7097a142464c500766b2cb3d564986e0a072799vboxsync * Copyright (C) 2006-2012 Oracle Corporation
b4aee06a140a74517eedd6e55625cb88bd7b3d87vboxsync * This file is part of VirtualBox Open Source Edition (OSE), as
b4aee06a140a74517eedd6e55625cb88bd7b3d87vboxsync * available from http://www.virtualbox.org. This file is free software;
b4aee06a140a74517eedd6e55625cb88bd7b3d87vboxsync * you can redistribute it and/or modify it under the terms of the GNU
b4aee06a140a74517eedd6e55625cb88bd7b3d87vboxsync * General Public License (GPL) as published by the Free Software
b4aee06a140a74517eedd6e55625cb88bd7b3d87vboxsync * Foundation, in version 2 as it comes in the "COPYING" file of the
b4aee06a140a74517eedd6e55625cb88bd7b3d87vboxsync * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
b4aee06a140a74517eedd6e55625cb88bd7b3d87vboxsync * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
b4aee06a140a74517eedd6e55625cb88bd7b3d87vboxsync/*******************************************************************************
b4aee06a140a74517eedd6e55625cb88bd7b3d87vboxsync* Header Files *
b4aee06a140a74517eedd6e55625cb88bd7b3d87vboxsync*******************************************************************************/
b4aee06a140a74517eedd6e55625cb88bd7b3d87vboxsync/*******************************************************************************
b4aee06a140a74517eedd6e55625cb88bd7b3d87vboxsync* Global Variables *
b4aee06a140a74517eedd6e55625cb88bd7b3d87vboxsync*******************************************************************************/
b4aee06a140a74517eedd6e55625cb88bd7b3d87vboxsync * Array for accessing 64-bit general registers in VMMREGFRAME structure
b4aee06a140a74517eedd6e55625cb88bd7b3d87vboxsync * by register's index from disasm.
b4aee06a140a74517eedd6e55625cb88bd7b3d87vboxsyncstatic const unsigned g_aReg64Index[] =
b4aee06a140a74517eedd6e55625cb88bd7b3d87vboxsync * Macro for accessing 64-bit general purpose registers in CPUMCTXCORE structure.
b4aee06a140a74517eedd6e55625cb88bd7b3d87vboxsync#define DIS_READ_REG64(p, idx) (*(uint64_t *)((char *)(p) + g_aReg64Index[idx]))
b4aee06a140a74517eedd6e55625cb88bd7b3d87vboxsync#define DIS_WRITE_REG64(p, idx, val) (*(uint64_t *)((char *)(p) + g_aReg64Index[idx]) = val)
b4aee06a140a74517eedd6e55625cb88bd7b3d87vboxsync#define DIS_PTR_REG64(p, idx) ( (uint64_t *)((char *)(p) + g_aReg64Index[idx]))
b4aee06a140a74517eedd6e55625cb88bd7b3d87vboxsync * Array for accessing 32-bit general registers in VMMREGFRAME structure
b4aee06a140a74517eedd6e55625cb88bd7b3d87vboxsync * by register's index from disasm.
b4aee06a140a74517eedd6e55625cb88bd7b3d87vboxsyncstatic const unsigned g_aReg32Index[] =
b4aee06a140a74517eedd6e55625cb88bd7b3d87vboxsync * Macro for accessing 32-bit general purpose registers in CPUMCTXCORE structure.
b4aee06a140a74517eedd6e55625cb88bd7b3d87vboxsync#define DIS_READ_REG32(p, idx) (*(uint32_t *)((char *)(p) + g_aReg32Index[idx]))
b4aee06a140a74517eedd6e55625cb88bd7b3d87vboxsync/* From http://www.cs.cmu.edu/~fp/courses/15213-s06/misc/asm64-handout.pdf:
b4aee06a140a74517eedd6e55625cb88bd7b3d87vboxsync * ``Perhaps unexpectedly, instructions that move or generate 32-bit register
b4aee06a140a74517eedd6e55625cb88bd7b3d87vboxsync * values also set the upper 32 bits of the register to zero. Consequently
b4aee06a140a74517eedd6e55625cb88bd7b3d87vboxsync * there is no need for an instruction movzlq.''
b4aee06a140a74517eedd6e55625cb88bd7b3d87vboxsync#define DIS_WRITE_REG32(p, idx, val) (*(uint64_t *)((char *)(p) + g_aReg32Index[idx]) = (uint32_t)val)
b4aee06a140a74517eedd6e55625cb88bd7b3d87vboxsync#define DIS_PTR_REG32(p, idx) ( (uint32_t *)((char *)(p) + g_aReg32Index[idx]))
b4aee06a140a74517eedd6e55625cb88bd7b3d87vboxsync * Array for accessing 16-bit general registers in CPUMCTXCORE structure
b4aee06a140a74517eedd6e55625cb88bd7b3d87vboxsync * by register's index from disasm.
b4aee06a140a74517eedd6e55625cb88bd7b3d87vboxsyncstatic const unsigned g_aReg16Index[] =
b4aee06a140a74517eedd6e55625cb88bd7b3d87vboxsync * Macro for accessing 16-bit general purpose registers in CPUMCTXCORE structure.
b4aee06a140a74517eedd6e55625cb88bd7b3d87vboxsync#define DIS_READ_REG16(p, idx) (*(uint16_t *)((char *)(p) + g_aReg16Index[idx]))
b4aee06a140a74517eedd6e55625cb88bd7b3d87vboxsync#define DIS_WRITE_REG16(p, idx, val) (*(uint16_t *)((char *)(p) + g_aReg16Index[idx]) = val)
b4aee06a140a74517eedd6e55625cb88bd7b3d87vboxsync#define DIS_PTR_REG16(p, idx) ( (uint16_t *)((char *)(p) + g_aReg16Index[idx]))
b4aee06a140a74517eedd6e55625cb88bd7b3d87vboxsync * Array for accessing 8-bit general registers in CPUMCTXCORE structure
b4aee06a140a74517eedd6e55625cb88bd7b3d87vboxsync * by register's index from disasm.
b4aee06a140a74517eedd6e55625cb88bd7b3d87vboxsyncstatic const unsigned g_aReg8Index[] =
dcc035155cdf232a3d79024f475c2d4448981e85vboxsync RT_OFFSETOF_ADD(CPUMCTXCORE, eax, 1), /* DISGREG_AH */
dcc035155cdf232a3d79024f475c2d4448981e85vboxsync RT_OFFSETOF_ADD(CPUMCTXCORE, ecx, 1), /* DISGREG_CH */
dcc035155cdf232a3d79024f475c2d4448981e85vboxsync RT_OFFSETOF_ADD(CPUMCTXCORE, edx, 1), /* DISGREG_DH */
dcc035155cdf232a3d79024f475c2d4448981e85vboxsync RT_OFFSETOF_ADD(CPUMCTXCORE, ebx, 1), /* DISGREG_BH */
dcc035155cdf232a3d79024f475c2d4448981e85vboxsync RT_OFFSETOF(CPUMCTXCORE, esp), /* DISGREG_SPL; with REX prefix only */
dcc035155cdf232a3d79024f475c2d4448981e85vboxsync RT_OFFSETOF(CPUMCTXCORE, ebp), /* DISGREG_BPL; with REX prefix only */
dcc035155cdf232a3d79024f475c2d4448981e85vboxsync RT_OFFSETOF(CPUMCTXCORE, esi), /* DISGREG_SIL; with REX prefix only */
dcc035155cdf232a3d79024f475c2d4448981e85vboxsync RT_OFFSETOF(CPUMCTXCORE, edi) /* DISGREG_DIL; with REX prefix only */
b4aee06a140a74517eedd6e55625cb88bd7b3d87vboxsync * Macro for accessing 8-bit general purpose registers in CPUMCTXCORE structure.
b4aee06a140a74517eedd6e55625cb88bd7b3d87vboxsync#define DIS_READ_REG8(p, idx) (*(uint8_t *)((char *)(p) + g_aReg8Index[idx]))
b4aee06a140a74517eedd6e55625cb88bd7b3d87vboxsync#define DIS_WRITE_REG8(p, idx, val) (*(uint8_t *)((char *)(p) + g_aReg8Index[idx]) = val)
b4aee06a140a74517eedd6e55625cb88bd7b3d87vboxsync#define DIS_PTR_REG8(p, idx) ( (uint8_t *)((char *)(p) + g_aReg8Index[idx]))
b4aee06a140a74517eedd6e55625cb88bd7b3d87vboxsync * Array for accessing segment registers in CPUMCTXCORE structure
b4aee06a140a74517eedd6e55625cb88bd7b3d87vboxsync * by register's index from disasm.
b4aee06a140a74517eedd6e55625cb88bd7b3d87vboxsyncstatic const unsigned g_aRegSegIndex[] =
b4aee06a140a74517eedd6e55625cb88bd7b3d87vboxsyncstatic const unsigned g_aRegHidSegIndex[] =
dcc035155cdf232a3d79024f475c2d4448981e85vboxsync RT_OFFSETOF(CPUMCTXCORE, esHid), /* DISSELREG_ES */
dcc035155cdf232a3d79024f475c2d4448981e85vboxsync RT_OFFSETOF(CPUMCTXCORE, csHid), /* DISSELREG_CS */
dcc035155cdf232a3d79024f475c2d4448981e85vboxsync RT_OFFSETOF(CPUMCTXCORE, ssHid), /* DISSELREG_SS */
dcc035155cdf232a3d79024f475c2d4448981e85vboxsync RT_OFFSETOF(CPUMCTXCORE, dsHid), /* DISSELREG_DS */
dcc035155cdf232a3d79024f475c2d4448981e85vboxsync RT_OFFSETOF(CPUMCTXCORE, fsHid), /* DISSELREG_FS */
b4aee06a140a74517eedd6e55625cb88bd7b3d87vboxsync * Macro for accessing segment registers in CPUMCTXCORE structure.
b4aee06a140a74517eedd6e55625cb88bd7b3d87vboxsync#define DIS_READ_REGSEG(p, idx) (*((uint16_t *)((char *)(p) + g_aRegSegIndex[idx])))
b4aee06a140a74517eedd6e55625cb88bd7b3d87vboxsync#define DIS_WRITE_REGSEG(p, idx, val) (*((uint16_t *)((char *)(p) + g_aRegSegIndex[idx])) = val)
b4aee06a140a74517eedd6e55625cb88bd7b3d87vboxsync//*****************************************************************************
b4aee06a140a74517eedd6e55625cb88bd7b3d87vboxsync//*****************************************************************************
0dcab00efb68dbd44bd653d4cb18aaaef7448898vboxsyncDISDECL(int) DISGetParamSize(PDISCPUSTATE pCpu, PDISOPPARAM pParam)
70fa291a159216a90eea85d879c46bf4d86ed545vboxsync unsigned subtype = OP_PARM_VSUBTYPE(pParam->fParam);
b4aee06a140a74517eedd6e55625cb88bd7b3d87vboxsync /* make gcc happy */
b4aee06a140a74517eedd6e55625cb88bd7b3d87vboxsync else //@todo dangerous!!!
b4aee06a140a74517eedd6e55625cb88bd7b3d87vboxsync//*****************************************************************************
b4aee06a140a74517eedd6e55625cb88bd7b3d87vboxsync//*****************************************************************************
dcc035155cdf232a3d79024f475c2d4448981e85vboxsyncDISDECL(DISSELREG) DISDetectSegReg(PDISCPUSTATE pCpu, PDISOPPARAM pParam)
b4aee06a140a74517eedd6e55625cb88bd7b3d87vboxsync /* Use specified SEG: prefix. */
0dcab00efb68dbd44bd653d4cb18aaaef7448898vboxsync /* Guess segment register by parameter type. */
0dcab00efb68dbd44bd653d4cb18aaaef7448898vboxsync if (pParam->fUse & (DISUSE_REG_GEN32|DISUSE_REG_GEN64|DISUSE_REG_GEN16))
dcc035155cdf232a3d79024f475c2d4448981e85vboxsync if (pParam->base.reg_gen == DISGREG_ESP || pParam->base.reg_gen == DISGREG_EBP)
0dcab00efb68dbd44bd653d4cb18aaaef7448898vboxsync /* Default is use DS: for data access. */
b4aee06a140a74517eedd6e55625cb88bd7b3d87vboxsync//*****************************************************************************
b4aee06a140a74517eedd6e55625cb88bd7b3d87vboxsync//*****************************************************************************
b4aee06a140a74517eedd6e55625cb88bd7b3d87vboxsyncDISDECL(uint8_t) DISQuerySegPrefixByte(PDISCPUSTATE pCpu)
b4aee06a140a74517eedd6e55625cb88bd7b3d87vboxsync return 0x26;
b4aee06a140a74517eedd6e55625cb88bd7b3d87vboxsync return 0x2E;
b4aee06a140a74517eedd6e55625cb88bd7b3d87vboxsync return 0x36;
b4aee06a140a74517eedd6e55625cb88bd7b3d87vboxsync return 0x3E;
b4aee06a140a74517eedd6e55625cb88bd7b3d87vboxsync return 0x64;
b4aee06a140a74517eedd6e55625cb88bd7b3d87vboxsync return 0x65;
b4aee06a140a74517eedd6e55625cb88bd7b3d87vboxsync * Returns the value of the specified 8 bits general purpose register
b4aee06a140a74517eedd6e55625cb88bd7b3d87vboxsyncDISDECL(int) DISFetchReg8(PCCPUMCTXCORE pCtx, unsigned reg8, uint8_t *pVal)
e9a584ee0777ab2612e206eeec264ccb1a8ce333vboxsync AssertReturn(reg8 < RT_ELEMENTS(g_aReg8Index), VERR_INVALID_PARAMETER);
b4aee06a140a74517eedd6e55625cb88bd7b3d87vboxsync * Returns the value of the specified 16 bits general purpose register
b4aee06a140a74517eedd6e55625cb88bd7b3d87vboxsyncDISDECL(int) DISFetchReg16(PCCPUMCTXCORE pCtx, unsigned reg16, uint16_t *pVal)
e9a584ee0777ab2612e206eeec264ccb1a8ce333vboxsync AssertReturn(reg16 < RT_ELEMENTS(g_aReg16Index), VERR_INVALID_PARAMETER);
b4aee06a140a74517eedd6e55625cb88bd7b3d87vboxsync * Returns the value of the specified 32 bits general purpose register
b4aee06a140a74517eedd6e55625cb88bd7b3d87vboxsyncDISDECL(int) DISFetchReg32(PCCPUMCTXCORE pCtx, unsigned reg32, uint32_t *pVal)
e9a584ee0777ab2612e206eeec264ccb1a8ce333vboxsync AssertReturn(reg32 < RT_ELEMENTS(g_aReg32Index), VERR_INVALID_PARAMETER);
b4aee06a140a74517eedd6e55625cb88bd7b3d87vboxsync * Returns the value of the specified 64 bits general purpose register
b4aee06a140a74517eedd6e55625cb88bd7b3d87vboxsyncDISDECL(int) DISFetchReg64(PCCPUMCTXCORE pCtx, unsigned reg64, uint64_t *pVal)
e9a584ee0777ab2612e206eeec264ccb1a8ce333vboxsync AssertReturn(reg64 < RT_ELEMENTS(g_aReg64Index), VERR_INVALID_PARAMETER);
b4aee06a140a74517eedd6e55625cb88bd7b3d87vboxsync * Returns the pointer to the specified 8 bits general purpose register
b4aee06a140a74517eedd6e55625cb88bd7b3d87vboxsyncDISDECL(int) DISPtrReg8(PCPUMCTXCORE pCtx, unsigned reg8, uint8_t **ppReg)
e9a584ee0777ab2612e206eeec264ccb1a8ce333vboxsync AssertReturn(reg8 < RT_ELEMENTS(g_aReg8Index), VERR_INVALID_PARAMETER);
b4aee06a140a74517eedd6e55625cb88bd7b3d87vboxsync * Returns the pointer to the specified 16 bits general purpose register
b4aee06a140a74517eedd6e55625cb88bd7b3d87vboxsyncDISDECL(int) DISPtrReg16(PCPUMCTXCORE pCtx, unsigned reg16, uint16_t **ppReg)
e9a584ee0777ab2612e206eeec264ccb1a8ce333vboxsync AssertReturn(reg16 < RT_ELEMENTS(g_aReg16Index), VERR_INVALID_PARAMETER);
b4aee06a140a74517eedd6e55625cb88bd7b3d87vboxsync * Returns the pointer to the specified 32 bits general purpose register
b4aee06a140a74517eedd6e55625cb88bd7b3d87vboxsyncDISDECL(int) DISPtrReg32(PCPUMCTXCORE pCtx, unsigned reg32, uint32_t **ppReg)
e9a584ee0777ab2612e206eeec264ccb1a8ce333vboxsync AssertReturn(reg32 < RT_ELEMENTS(g_aReg32Index), VERR_INVALID_PARAMETER);
b4aee06a140a74517eedd6e55625cb88bd7b3d87vboxsync * Returns the pointer to the specified 64 bits general purpose register
b4aee06a140a74517eedd6e55625cb88bd7b3d87vboxsyncDISDECL(int) DISPtrReg64(PCPUMCTXCORE pCtx, unsigned reg64, uint64_t **ppReg)
e9a584ee0777ab2612e206eeec264ccb1a8ce333vboxsync AssertReturn(reg64 < RT_ELEMENTS(g_aReg64Index), VERR_INVALID_PARAMETER);
b4aee06a140a74517eedd6e55625cb88bd7b3d87vboxsync * Returns the value of the specified segment register
dcc035155cdf232a3d79024f475c2d4448981e85vboxsyncDISDECL(int) DISFetchRegSeg(PCCPUMCTXCORE pCtx, DISSELREG sel, RTSEL *pVal)
e9a584ee0777ab2612e206eeec264ccb1a8ce333vboxsync AssertReturn((unsigned)sel < RT_ELEMENTS(g_aRegSegIndex), VERR_INVALID_PARAMETER);
b4aee06a140a74517eedd6e55625cb88bd7b3d87vboxsync * Returns the value of the specified segment register including a pointer to the hidden register in the supplied cpu context
dcc035155cdf232a3d79024f475c2d4448981e85vboxsyncDISDECL(int) DISFetchRegSegEx(PCCPUMCTXCORE pCtx, DISSELREG sel, RTSEL *pVal, CPUMSELREGHID **ppSelHidReg)
e9a584ee0777ab2612e206eeec264ccb1a8ce333vboxsync AssertReturn((unsigned)sel < RT_ELEMENTS(g_aRegSegIndex), VERR_INVALID_PARAMETER);
b4aee06a140a74517eedd6e55625cb88bd7b3d87vboxsync *ppSelHidReg = (CPUMSELREGHID *)((char *)pCtx + g_aRegHidSegIndex[sel]);
b4aee06a140a74517eedd6e55625cb88bd7b3d87vboxsync * Updates the value of the specified 64 bits general purpose register
b4aee06a140a74517eedd6e55625cb88bd7b3d87vboxsyncDISDECL(int) DISWriteReg64(PCPUMCTXCORE pRegFrame, unsigned reg64, uint64_t val64)
e9a584ee0777ab2612e206eeec264ccb1a8ce333vboxsync AssertReturn(reg64 < RT_ELEMENTS(g_aReg64Index), VERR_INVALID_PARAMETER);
b4aee06a140a74517eedd6e55625cb88bd7b3d87vboxsync * Updates the value of the specified 32 bits general purpose register
b4aee06a140a74517eedd6e55625cb88bd7b3d87vboxsyncDISDECL(int) DISWriteReg32(PCPUMCTXCORE pRegFrame, unsigned reg32, uint32_t val32)
e9a584ee0777ab2612e206eeec264ccb1a8ce333vboxsync AssertReturn(reg32 < RT_ELEMENTS(g_aReg32Index), VERR_INVALID_PARAMETER);
b4aee06a140a74517eedd6e55625cb88bd7b3d87vboxsync * Updates the value of the specified 16 bits general purpose register
b4aee06a140a74517eedd6e55625cb88bd7b3d87vboxsyncDISDECL(int) DISWriteReg16(PCPUMCTXCORE pRegFrame, unsigned reg16, uint16_t val16)
e9a584ee0777ab2612e206eeec264ccb1a8ce333vboxsync AssertReturn(reg16 < RT_ELEMENTS(g_aReg16Index), VERR_INVALID_PARAMETER);
b4aee06a140a74517eedd6e55625cb88bd7b3d87vboxsync * Updates the specified 8 bits general purpose register
b4aee06a140a74517eedd6e55625cb88bd7b3d87vboxsyncDISDECL(int) DISWriteReg8(PCPUMCTXCORE pRegFrame, unsigned reg8, uint8_t val8)
e9a584ee0777ab2612e206eeec264ccb1a8ce333vboxsync AssertReturn(reg8 < RT_ELEMENTS(g_aReg8Index), VERR_INVALID_PARAMETER);
b4aee06a140a74517eedd6e55625cb88bd7b3d87vboxsync * Updates the specified segment register
dcc035155cdf232a3d79024f475c2d4448981e85vboxsyncDISDECL(int) DISWriteRegSeg(PCPUMCTXCORE pCtx, DISSELREG sel, RTSEL val)
e9a584ee0777ab2612e206eeec264ccb1a8ce333vboxsync AssertReturn((unsigned)sel < RT_ELEMENTS(g_aRegSegIndex), VERR_INVALID_PARAMETER);
b4aee06a140a74517eedd6e55625cb88bd7b3d87vboxsync * Returns the value of the parameter in pParam
b4aee06a140a74517eedd6e55625cb88bd7b3d87vboxsync * @returns VBox error code
b4aee06a140a74517eedd6e55625cb88bd7b3d87vboxsync * @param pCtx CPU context structure pointer
b4aee06a140a74517eedd6e55625cb88bd7b3d87vboxsync * @param pCpu Pointer to cpu structure which have DISCPUSTATE::mode
b4aee06a140a74517eedd6e55625cb88bd7b3d87vboxsync * set correctly.
b4aee06a140a74517eedd6e55625cb88bd7b3d87vboxsync * @param pParam Pointer to the parameter to parse
b4aee06a140a74517eedd6e55625cb88bd7b3d87vboxsync * @param pParamVal Pointer to parameter value (OUT)
b4aee06a140a74517eedd6e55625cb88bd7b3d87vboxsync * @param parmtype Parameter type
b4aee06a140a74517eedd6e55625cb88bd7b3d87vboxsync * @note Currently doesn't handle FPU/XMM/MMX/3DNow! parameters correctly!!
0aa1ba1d1ea27baa7762e4fe891824df38697189vboxsyncDISDECL(int) DISQueryParamVal(PCPUMCTXCORE pCtx, PDISCPUSTATE pCpu, PDISOPPARAM pParam, PDISQPVPARAMVAL pParamVal, DISQPVWHICH parmtype)
b4aee06a140a74517eedd6e55625cb88bd7b3d87vboxsync // Effective address
240f7d7012a5f64bcde850bcf048531a710d81cfvboxsync if (RT_FAILURE(DISFetchReg8(pCtx, pParam->base.reg_gen, &pParamVal->val.val8))) return VERR_INVALID_PARAMETER;
240f7d7012a5f64bcde850bcf048531a710d81cfvboxsync if (RT_FAILURE(DISFetchReg16(pCtx, pParam->base.reg_gen, &pParamVal->val.val16))) return VERR_INVALID_PARAMETER;
240f7d7012a5f64bcde850bcf048531a710d81cfvboxsync if (RT_FAILURE(DISFetchReg32(pCtx, pParam->base.reg_gen, &pParamVal->val.val32))) return VERR_INVALID_PARAMETER;
240f7d7012a5f64bcde850bcf048531a710d81cfvboxsync if (RT_FAILURE(DISFetchReg64(pCtx, pParam->base.reg_gen, &pParamVal->val.val64))) return VERR_INVALID_PARAMETER;
b4aee06a140a74517eedd6e55625cb88bd7b3d87vboxsync // Note that scale implies index (SIB byte)
240f7d7012a5f64bcde850bcf048531a710d81cfvboxsync if (RT_FAILURE(DISFetchReg16(pCtx, pParam->index.reg_gen, &val16))) return VERR_INVALID_PARAMETER;
8e2451f7a9a8e6e722d2065fe0eeb5df93799c7avboxsync Assert(!(pParam->fUse & DISUSE_SCALE)); /* shouldn't be possible in 16 bits mode */
240f7d7012a5f64bcde850bcf048531a710d81cfvboxsync if (RT_FAILURE(DISFetchReg32(pCtx, pParam->index.reg_gen, &val32))) return VERR_INVALID_PARAMETER;
240f7d7012a5f64bcde850bcf048531a710d81cfvboxsync if (RT_FAILURE(DISFetchReg64(pCtx, pParam->index.reg_gen, &val64))) return VERR_INVALID_PARAMETER;
a0892a0a33b8ffaa8ff2f252411176f63e8d9f18vboxsync pParamVal->val.val32 += (int32_t)pParam->uDisp.i16;
a0892a0a33b8ffaa8ff2f252411176f63e8d9f18vboxsync pParamVal->val.val64 += (int64_t)pParam->uDisp.i16;
7d126da2d4ddf0f075dbdce89c2fb953a464e6bfvboxsync /* Relative to the RIP of the next instruction. */
faa7602db7e32056326da7e169b5f505c607138fvboxsync pParamVal->val.val64 += pParam->uDisp.i32 + pCtx->rip + pCpu->cbInstr;
8e2451f7a9a8e6e722d2065fe0eeb5df93799c7avboxsync if (pParam->fUse & (DISUSE_REG_GEN8|DISUSE_REG_GEN16|DISUSE_REG_GEN32|DISUSE_REG_GEN64|DISUSE_REG_FP|DISUSE_REG_MMX|DISUSE_REG_XMM|DISUSE_REG_CR|DISUSE_REG_DBG|DISUSE_REG_SEG|DISUSE_REG_TEST))
b4aee06a140a74517eedd6e55625cb88bd7b3d87vboxsync // Caller needs to interpret the register according to the instruction (source/target, special value etc)
0aa1ba1d1ea27baa7762e4fe891824df38697189vboxsync //else DISQPVWHICH_SRC
240f7d7012a5f64bcde850bcf048531a710d81cfvboxsync if (RT_FAILURE(DISFetchReg8(pCtx, pParam->base.reg_gen, &pParamVal->val.val8))) return VERR_INVALID_PARAMETER;
240f7d7012a5f64bcde850bcf048531a710d81cfvboxsync if (RT_FAILURE(DISFetchReg16(pCtx, pParam->base.reg_gen, &pParamVal->val.val16))) return VERR_INVALID_PARAMETER;
240f7d7012a5f64bcde850bcf048531a710d81cfvboxsync if (RT_FAILURE(DISFetchReg32(pCtx, pParam->base.reg_gen, &pParamVal->val.val32))) return VERR_INVALID_PARAMETER;
240f7d7012a5f64bcde850bcf048531a710d81cfvboxsync if (RT_FAILURE(DISFetchReg64(pCtx, pParam->base.reg_gen, &pParamVal->val.val64))) return VERR_INVALID_PARAMETER;
b4aee06a140a74517eedd6e55625cb88bd7b3d87vboxsync // Caller needs to interpret the register according to the instruction (source/target, special value etc)
8e2451f7a9a8e6e722d2065fe0eeb5df93799c7avboxsync if (pParam->fUse & (DISUSE_IMMEDIATE8|DISUSE_IMMEDIATE8_REL))
8e2451f7a9a8e6e722d2065fe0eeb5df93799c7avboxsync if (pParam->fUse & (DISUSE_IMMEDIATE16|DISUSE_IMMEDIATE16_REL|DISUSE_IMMEDIATE_ADDR_0_16|DISUSE_IMMEDIATE16_SX8))
8e2451f7a9a8e6e722d2065fe0eeb5df93799c7avboxsync AssertMsg(pParamVal->size == pParam->cb || ((pParam->cb == 1) && (pParam->fUse & DISUSE_IMMEDIATE16_SX8)), ("pParamVal->size %d vs %d EIP=%RX32\n", pParamVal->size, pParam->cb, pCtx->eip) );
8e2451f7a9a8e6e722d2065fe0eeb5df93799c7avboxsync if (pParam->fUse & (DISUSE_IMMEDIATE32|DISUSE_IMMEDIATE32_REL|DISUSE_IMMEDIATE_ADDR_0_32|DISUSE_IMMEDIATE32_SX8))
8e2451f7a9a8e6e722d2065fe0eeb5df93799c7avboxsync Assert(pParamVal->size == pParam->cb || ((pParam->cb == 1) && (pParam->fUse & DISUSE_IMMEDIATE32_SX8)) );
8e2451f7a9a8e6e722d2065fe0eeb5df93799c7avboxsync if (pParam->fUse & (DISUSE_IMMEDIATE64 | DISUSE_IMMEDIATE64_REL | DISUSE_IMMEDIATE64_SX8))
8e2451f7a9a8e6e722d2065fe0eeb5df93799c7avboxsync Assert(pParamVal->size == pParam->cb || ((pParam->cb == 1) && (pParam->fUse & DISUSE_IMMEDIATE64_SX8)) );
b4aee06a140a74517eedd6e55625cb88bd7b3d87vboxsync pParamVal->val.farptr.sel = (uint16_t)RT_LOWORD(pParam->parval >> 16);
b4aee06a140a74517eedd6e55625cb88bd7b3d87vboxsync pParamVal->val.farptr.offset = (uint32_t)RT_LOWORD(pParam->parval);
b4aee06a140a74517eedd6e55625cb88bd7b3d87vboxsync pParamVal->size = sizeof(uint16_t) + sizeof(uint32_t);
b4aee06a140a74517eedd6e55625cb88bd7b3d87vboxsync pParamVal->val.farptr.sel = (uint16_t)RT_LOWORD(pParam->parval >> 32);
b4aee06a140a74517eedd6e55625cb88bd7b3d87vboxsync pParamVal->val.farptr.offset = (uint32_t)(pParam->parval & 0xFFFFFFFF);
b4aee06a140a74517eedd6e55625cb88bd7b3d87vboxsync * Returns the pointer to a register of the parameter in pParam. We need this
b4aee06a140a74517eedd6e55625cb88bd7b3d87vboxsync * pointer when an interpreted instruction updates a register as a side effect.
b4aee06a140a74517eedd6e55625cb88bd7b3d87vboxsync * In CMPXCHG we know that only [r/e]ax is updated, but with XADD this could
b4aee06a140a74517eedd6e55625cb88bd7b3d87vboxsync * be every register.
b4aee06a140a74517eedd6e55625cb88bd7b3d87vboxsync * @returns VBox error code
b4aee06a140a74517eedd6e55625cb88bd7b3d87vboxsync * @param pCtx CPU context structure pointer
b4aee06a140a74517eedd6e55625cb88bd7b3d87vboxsync * @param pCpu Pointer to cpu structure which have DISCPUSTATE::mode
b4aee06a140a74517eedd6e55625cb88bd7b3d87vboxsync * set correctly.
b4aee06a140a74517eedd6e55625cb88bd7b3d87vboxsync * @param pParam Pointer to the parameter to parse
b4aee06a140a74517eedd6e55625cb88bd7b3d87vboxsync * @param pReg Pointer to parameter value (OUT)
b4aee06a140a74517eedd6e55625cb88bd7b3d87vboxsync * @param cbsize Parameter size (OUT)
b4aee06a140a74517eedd6e55625cb88bd7b3d87vboxsync * @note Currently doesn't handle FPU/XMM/MMX/3DNow! parameters correctly!!
0dcab00efb68dbd44bd653d4cb18aaaef7448898vboxsyncDISDECL(int) DISQueryParamRegPtr(PCPUMCTXCORE pCtx, PDISCPUSTATE pCpu, PDISOPPARAM pParam, void **ppReg, size_t *pcbSize)
8e2451f7a9a8e6e722d2065fe0eeb5df93799c7avboxsync if (pParam->fUse & (DISUSE_REG_GEN8|DISUSE_REG_GEN16|DISUSE_REG_GEN32|DISUSE_REG_FP|DISUSE_REG_MMX|DISUSE_REG_XMM|DISUSE_REG_CR|DISUSE_REG_DBG|DISUSE_REG_SEG|DISUSE_REG_TEST))
240f7d7012a5f64bcde850bcf048531a710d81cfvboxsync if (RT_SUCCESS(DISPtrReg8(pCtx, pParam->base.reg_gen, &pu8Reg)))
240f7d7012a5f64bcde850bcf048531a710d81cfvboxsync if (RT_SUCCESS(DISPtrReg16(pCtx, pParam->base.reg_gen, &pu16Reg)))
240f7d7012a5f64bcde850bcf048531a710d81cfvboxsync if (RT_SUCCESS(DISPtrReg32(pCtx, pParam->base.reg_gen, &pu32Reg)))