DisasmFormatYasm.cpp revision 2309a5a68c254f4881841fbf8118e899c32d7385
/* $Id$ */
/** @file
* VBox Disassembler - Yasm(/Nasm) Style Formatter.
*/
/*
* Copyright (C) 2008-2012 Oracle Corporation
*
* This file is part of VirtualBox Open Source Edition (OSE), as
* available from http://www.virtualbox.org. This file is free software;
* General Public License (GPL) as published by the Free Software
* Foundation, in version 2 as it comes in the "COPYING" file of the
* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
*/
/*******************************************************************************
* Header Files *
*******************************************************************************/
#include "DisasmInternal.h"
/*******************************************************************************
* Global Variables *
*******************************************************************************/
static const char g_szSpaces[] =
" ";
{
"al\0\0", "cl\0\0", "dl\0\0", "bl\0\0", "ah\0\0", "ch\0\0", "dh\0\0", "bh\0\0", "r8b\0", "r9b\0", "r10b", "r11b", "r12b", "r13b", "r14b", "r15b", "spl\0", "bpl\0", "sil\0", "dil\0"
};
{
"ax\0\0", "cx\0\0", "dx\0\0", "bx\0\0", "sp\0\0", "bp\0\0", "si\0\0", "di\0\0", "r8w\0", "r9w\0", "r10w", "r11w", "r12w", "r13w", "r14w", "r15w"
};
{
"bx+si", "bx+di", "bp+si", "bp+di", "si\0\0\0", "di\0\0\0", "bp\0\0\0", "bx\0\0\0"
};
{
"eax\0", "ecx\0", "edx\0", "ebx\0", "esp\0", "ebp\0", "esi\0", "edi\0", "r8d\0", "r9d\0", "r10d", "r11d", "r12d", "r13d", "r14d", "r15d"
};
{
"rax", "rcx", "rdx", "rbx", "rsp", "rbp", "rsi", "rdi", "r8\0", "r9\0", "r10", "r11", "r12", "r13", "r14", "r15"
};
{
"es", "cs", "ss", "ds", "fs", "gs"
};
{
"st0", "st1", "st2", "st3", "st4", "st5", "st6", "st7"
};
{
"mm0", "mm1", "mm2", "mm3", "mm4", "mm5", "mm6", "mm7"
};
{
"xmm0\0", "xmm1\0", "xmm2\0", "xmm3\0", "xmm4\0", "xmm5\0", "xmm6\0", "xmm7\0", "xmm8\0", "xmm9\0", "xmm10", "xmm11", "xmm12", "xmm13", "xmm14", "xmm15"
};
{
"cr0\0", "cr1\0", "cr2\0", "cr3\0", "cr4\0", "cr5\0", "cr6\0", "cr7\0", "cr8\0", "cr9\0", "cr10", "cr11", "cr12", "cr13", "cr14", "cr15"
};
{
"dr0\0", "dr1\0", "dr2\0", "dr3\0", "dr4\0", "dr5\0", "dr6\0", "dr7\0", "dr8\0", "dr9\0", "dr10", "dr11", "dr12", "dr13", "dr14", "dr15"
};
{
"tr0\0", "tr1\0", "tr2\0", "tr3\0", "tr4\0", "tr5\0", "tr6\0", "tr7\0", "tr8\0", "tr9\0", "tr10", "tr11", "tr12", "tr13", "tr14", "tr15"
};
/**
* Gets the base register name for the given parameter.
*
* @returns Pointer to the register name.
* @param pCpu The disassembler cpu state.
* @param pParam The parameter.
* @param pcchReg Where to store the length of the name.
*/
static const char *disasmFormatYasmBaseReg(PCDISCPUSTATE pCpu, PCDISOPPARAM pParam, size_t *pcchReg)
{
{
case DISUSE_REG_GEN8:
{
return psz;
}
case DISUSE_REG_GEN16:
{
return psz;
}
case DISUSE_REG_GEN32:
{
return psz;
}
case DISUSE_REG_GEN64:
{
return psz;
}
case DISUSE_REG_FP:
{
*pcchReg = 3;
return psz;
}
case DISUSE_REG_MMX:
{
*pcchReg = 3;
return psz;
}
case DISUSE_REG_XMM:
{
return psz;
}
case DISUSE_REG_CR:
{
*pcchReg = 3;
return psz;
}
case DISUSE_REG_DBG:
{
*pcchReg = 3;
return psz;
}
case DISUSE_REG_SEG:
{
*pcchReg = 2;
return psz;
}
case DISUSE_REG_TEST:
{
*pcchReg = 3;
return psz;
}
default:
*pcchReg = 3;
return "r??";
}
}
/**
* Gets the index register name for the given parameter.
*
* @returns The index register name.
* @param pCpu The disassembler cpu state.
* @param pParam The parameter.
* @param pcchReg Where to store the length of the name.
*/
static const char *disasmFormatYasmIndexReg(PCDISCPUSTATE pCpu, PCDISOPPARAM pParam, size_t *pcchReg)
{
{
case DISCPUMODE_16BIT:
{
return psz;
}
case DISCPUMODE_32BIT:
{
return psz;
}
case DISCPUMODE_64BIT:
{
return psz;
}
default:
*pcchReg = 3;
return "r??";
}
}
/**
* Formats the current instruction in Yasm (/ Nasm) style.
*
*
* @returns The number of output characters. If this is >= cchBuf, then the content
* of pszBuf will be truncated.
* @param pCpu Pointer to the disassembler CPU state.
* @param pszBuf The output buffer.
* @param cchBuf The size of the output buffer.
* @param fFlags Format flags, see DIS_FORMAT_FLAGS_*.
* @param pfnGetSymbol Get symbol name for a jmp or call target address. Optional.
* @param pvUser User argument for pfnGetSymbol.
*/
{
/*
* Input validation and massaging.
*/
if (fFlags & DIS_FMT_FLAGS_ADDR_COMMENT)
/*
* Output macros
*/
do { \
cchOutput++; \
if (cchDst > 1) \
{ \
cchDst--; \
} \
} while (0)
do { \
{ \
} \
else if (cchDst > 1) \
{ \
cchDst = 1; \
} \
} while (0)
do { \
if (cchDst > 1) \
{ \
} \
} while (0)
/** @todo add two flags for choosing between %X / %x and h / 0x. */
do { \
{ \
PUT_C('+'); \
} \
else \
{ \
PUT_C('-'); \
} \
} while (0)
/*
* The address?
*/
if (fFlags & DIS_FMT_FLAGS_ADDR_LEFT)
{
#endif
PUT_C(' ');
}
/*
* The opcode bytes?
*/
if (fFlags & DIS_FMT_FLAGS_BYTES_LEFT)
{
if (cchDst > 1)
{
{
}
else
{
cchDst = 1;
}
}
/* Some padding to align the instruction. */
+ 2;
}
/*
* Filter out invalid opcodes first as they need special
* treatment. UD2 is an exception and should be handled normally.
*/
{
}
else
{
/*
* Prefixes
*/
PUT_SZ("lock ");
PUT_SZ("rep ");
PUT_SZ("repne ");
/*
* Adjust the format string to the correct mnemonic
* or to avoid things the assembler cannot handle correctly.
*/
char szTmpFmt[48];
{
case OP_JECXZ:
pszFmt = pCpu->uOpMode == DISCPUMODE_16BIT ? "jcxz %Jb" : pCpu->uOpMode == DISCPUMODE_32BIT ? "jecxz %Jb" : "jrcxz %Jb";
break;
case OP_PUSHF:
pszFmt = pCpu->uOpMode == DISCPUMODE_16BIT ? "pushfw" : pCpu->uOpMode == DISCPUMODE_32BIT ? "pushfd" : "pushfq";
break;
case OP_POPF:
pszFmt = pCpu->uOpMode == DISCPUMODE_16BIT ? "popfw" : pCpu->uOpMode == DISCPUMODE_32BIT ? "popfd" : "popfq";
break;
case OP_PUSHA:
break;
case OP_POPA:
break;
case OP_INSB:
pszFmt = "insb";
break;
case OP_INSWD:
pszFmt = pCpu->uOpMode == DISCPUMODE_16BIT ? "insw" : pCpu->uOpMode == DISCPUMODE_32BIT ? "insd" : "insq";
break;
case OP_OUTSB:
pszFmt = "outsb";
break;
case OP_OUTSWD:
pszFmt = pCpu->uOpMode == DISCPUMODE_16BIT ? "outsw" : pCpu->uOpMode == DISCPUMODE_32BIT ? "outsd" : "outsq";
break;
case OP_MOVSB:
pszFmt = "movsb";
break;
case OP_MOVSWD:
pszFmt = pCpu->uOpMode == DISCPUMODE_16BIT ? "movsw" : pCpu->uOpMode == DISCPUMODE_32BIT ? "movsd" : "movsq";
break;
case OP_CMPSB:
pszFmt = "cmpsb";
break;
case OP_CMPWD:
pszFmt = pCpu->uOpMode == DISCPUMODE_16BIT ? "cmpsw" : pCpu->uOpMode == DISCPUMODE_32BIT ? "cmpsd" : "cmpsq";
break;
case OP_SCASB:
pszFmt = "scasb";
break;
case OP_SCASWD:
pszFmt = pCpu->uOpMode == DISCPUMODE_16BIT ? "scasw" : pCpu->uOpMode == DISCPUMODE_32BIT ? "scasd" : "scasq";
break;
case OP_LODSB:
pszFmt = "lodsb";
break;
case OP_LODSWD:
pszFmt = pCpu->uOpMode == DISCPUMODE_16BIT ? "lodsw" : pCpu->uOpMode == DISCPUMODE_32BIT ? "lodsd" : "lodsq";
break;
case OP_STOSB:
pszFmt = "stosb";
break;
case OP_STOSWD:
pszFmt = pCpu->uOpMode == DISCPUMODE_16BIT ? "stosw" : pCpu->uOpMode == DISCPUMODE_32BIT ? "stosd" : "stosq";
break;
case OP_CBW:
pszFmt = pCpu->uOpMode == DISCPUMODE_16BIT ? "cbw" : pCpu->uOpMode == DISCPUMODE_32BIT ? "cwde" : "cdqe";
break;
case OP_CWD:
pszFmt = pCpu->uOpMode == DISCPUMODE_16BIT ? "cwd" : pCpu->uOpMode == DISCPUMODE_32BIT ? "cdq" : "cqo";
break;
case OP_SHL:
pszFmt += 4;
break;
case OP_XLAT:
pszFmt = "xlatb";
break;
case OP_INT3:
pszFmt = "int3";
break;
/*
* Don't know how to tell yasm to generate complicated nop stuff, so 'db' it.
*/
case OP_NOP:
/* fine, fine */;
pszFmt = "prefetch %Eb";
{
PUT_SZ("db 00fh, 01fh,");
{
PUT_C(',');
}
pszFmt = "";
}
break;
default:
/* ST(X) -> stX (floating point) */
{
char ch;
do
{
{
*pszFmtDst++ = 's';
*pszFmtDst++ = 't';
pszFmt += 2;
pszFmt += 2;
}
else
} while (ch != '\0');
}
break;
/*
* Horrible hacks.
*/
case OP_FLD:
break;
case OP_LAR: /* hack w -> v, probably not correct. */
break;
}
/*
* Formatting context and associated macros.
*/
int iParam = 1;
#define PUT_FAR() \
do { \
PUT_SZ("far "); \
} while (0)
/** @todo mov ah,ch ends up with a byte 'override'... - check if this wasn't fixed. */
/** @todo drop the work/dword/qword override when the src/dst is a register (except for movsx/movzx). */
#define PUT_SIZE_OVERRIDE() \
do { \
{ \
case OP_PARM_v: \
{ \
default: break; \
} \
break; \
case OP_PARM_dq: \
if (OP_PARM_VTYPE(pParam->param) != OP_PARM_W) /* these are 128 bit, pray they are all unambiguous.. */ \
PUT_SZ("qword "); \
break; \
case OP_PARM_p: break; /* see PUT_FAR */ \
case OP_PARM_z: break; \
case OP_PARM_NONE: \
PUT_SZ("tword "); \
break; \
} \
} while (0)
#define PUT_SEGMENT_OVERRIDE() \
do { \
} while (0)
/*
* Segment prefixing for instructions that doesn't do memory access.
*/
{
PUT_C(' ');
}
/*
* The formatting loop.
*/
char szSymbol[128];
char ch;
{
if (ch == '%')
{
switch (ch)
{
/*
* ModRM - Register only.
*/
case 'C': /* Control register (ParseModRM / UseModRM). */
case 'D': /* Debug register (ParseModRM / UseModRM). */
case 'G': /* ModRM selects general register (ParseModRM / UseModRM). */
case 'S': /* ModRM byte selects a segment register (ParseModRM / UseModRM). */
case 'T': /* ModRM byte selects a test register (ParseModRM / UseModRM). */
case 'P': /* ModRM byte selects MMX register (ParseModRM / UseModRM). */
{
Assert(!(pParam->fUse & (DISUSE_DISPLACEMENT8 | DISUSE_DISPLACEMENT16 | DISUSE_DISPLACEMENT32 | DISUSE_DISPLACEMENT64 | DISUSE_RIPDISPLACEMENT32)));
break;
}
/*
* ModRM - Register or memory.
*/
case 'E': /* ModRM specifies parameter (ParseModRM / UseModRM / UseSIB). */
case 'Q': /* ModRM byte selects MMX register or memory address (ParseModRM / UseModRM). */
case 'R': /* ModRM byte may only refer to a general register (ParseModRM / UseModRM). */
case 'M': /* ModRM may only refer to memory (ParseModRM / UseModRM). */
{
PUT_FAR();
if (DISUSE_IS_EFFECTIVE_ADDR(fUse))
{
/* Work around mov seg,[mem16] and mov [mem16],seg as these always make a 16-bit mem
while the register variants deals with 16, 32 & 64 in the normal fashion. */
PUT_C('[');
}
if ( (fFlags & DIS_FMT_FLAGS_STRICT)
&& (fUse & (DISUSE_DISPLACEMENT8 | DISUSE_DISPLACEMENT16 | DISUSE_DISPLACEMENT32 | DISUSE_DISPLACEMENT64 | DISUSE_RIPDISPLACEMENT32)))
{
if ( (fUse & DISUSE_DISPLACEMENT8)
PUT_SZ("byte ");
else if ( (fUse & DISUSE_DISPLACEMENT16)
PUT_SZ("word ");
else if ( (fUse & DISUSE_DISPLACEMENT32)
PUT_SZ("dword ");
else if ( (fUse & DISUSE_DISPLACEMENT64)
PUT_SZ("qword ");
}
if (DISUSE_IS_EFFECTIVE_ADDR(fUse))
bool fBase = (fUse & DISUSE_BASE) /* When exactly is DISUSE_BASE supposed to be set? disasmModRMReg doesn't set it. */
|| ( (fUse & ( DISUSE_REG_GEN8
| DISUSE_REG_TEST ))
&& !DISUSE_IS_EFFECTIVE_ADDR(fUse));
if (fBase)
{
}
if (fUse & DISUSE_INDEX)
{
if (fBase)
PUT_C('+');
if (fUse & DISUSE_SCALE)
{
PUT_C('*');
}
}
else
if (fUse & (DISUSE_DISPLACEMENT8 | DISUSE_DISPLACEMENT16 | DISUSE_DISPLACEMENT32 | DISUSE_DISPLACEMENT64 | DISUSE_RIPDISPLACEMENT32))
{
if (fUse & DISUSE_DISPLACEMENT8)
else if (fUse & DISUSE_DISPLACEMENT16)
else if (fUse & DISUSE_DISPLACEMENT64)
else
{
AssertFailed();
off2 = 0;
}
{
if (off2 < 0)
}
if (fUse & DISUSE_DISPLACEMENT8)
else if (fUse & DISUSE_DISPLACEMENT16)
else if (fUse & DISUSE_DISPLACEMENT32)
else if (fUse & DISUSE_DISPLACEMENT64)
else
{
}
}
if (DISUSE_IS_EFFECTIVE_ADDR(fUse))
PUT_C(']');
break;
}
AssertFailed();
break;
case 'I': /* Immediate data (ParseImmByte, ParseImmByteSX, ParseImmV, ParseImmUshort, ParseImmZ). */
switch (pParam->fUse & ( DISUSE_IMMEDIATE8 | DISUSE_IMMEDIATE16 | DISUSE_IMMEDIATE32 | DISUSE_IMMEDIATE64
{
case DISUSE_IMMEDIATE8:
if ( (fFlags & DIS_FMT_FLAGS_STRICT)
)
PUT_SZ("strict byte ");
break;
case DISUSE_IMMEDIATE16:
|| ( (fFlags & DIS_FMT_FLAGS_STRICT)
)
)
{
}
break;
case DISUSE_IMMEDIATE16_SX8:
break;
case DISUSE_IMMEDIATE32:
if ( pCpu->uOpMode != (pCpu->uCpuMode == DISCPUMODE_16BIT ? DISCPUMODE_16BIT : DISCPUMODE_32BIT) /* not perfect */
|| ( (fFlags & DIS_FMT_FLAGS_STRICT)
)
)
{
}
break;
case DISUSE_IMMEDIATE32_SX8:
break;
case DISUSE_IMMEDIATE64_SX8:
break;
case DISUSE_IMMEDIATE64:
break;
default:
AssertFailed();
break;
}
break;
case 'J': /* Relative jump offset (ParseImmBRel + ParseImmVRel). */
{
{
if (fPrefix)
PUT_SZ("short ");
}
{
if (fPrefix)
PUT_SZ("near ");
}
else
{
if (fPrefix)
PUT_SZ("near ");
}
PUT_SZ(" (");
else
if (pfnGetSymbol)
{
int rc = pfnGetSymbol(pCpu, DIS_FMT_SEL_FROM_REG(DISSELREG_CS), uTrgAddr, szSymbol, sizeof(szSymbol), &off, pvUser);
if (RT_SUCCESS(rc))
{
PUT_SZ(" [");
if (off != 0)
{
else
}
PUT_C(']');
}
}
PUT_C(')');
break;
}
{
PUT_FAR();
int rc = VERR_SYMBOL_NOT_FOUND;
switch (pParam->fUse & (DISUSE_IMMEDIATE_ADDR_16_16 | DISUSE_IMMEDIATE_ADDR_16_32 | DISUSE_DISPLACEMENT64 | DISUSE_DISPLACEMENT32 | DISUSE_DISPLACEMENT16))
{
PUT_C(':');
if (pfnGetSymbol)
rc = pfnGetSymbol(pCpu, DIS_FMT_SEL_FROM_VALUE(pParam->parval >> 16), (uint16_t)pParam->parval, szSymbol, sizeof(szSymbol), &off, pvUser);
break;
PUT_C(':');
if (pfnGetSymbol)
rc = pfnGetSymbol(pCpu, DIS_FMT_SEL_FROM_VALUE(pParam->parval >> 16), (uint32_t)pParam->parval, szSymbol, sizeof(szSymbol), &off, pvUser);
break;
case DISUSE_DISPLACEMENT16:
if (pfnGetSymbol)
rc = pfnGetSymbol(pCpu, DIS_FMT_SEL_FROM_REG(DISSELREG_CS), (uint16_t)pParam->parval, szSymbol, sizeof(szSymbol), &off, pvUser);
break;
case DISUSE_DISPLACEMENT32:
if (pfnGetSymbol)
rc = pfnGetSymbol(pCpu, DIS_FMT_SEL_FROM_REG(DISSELREG_CS), (uint32_t)pParam->parval, szSymbol, sizeof(szSymbol), &off, pvUser);
break;
case DISUSE_DISPLACEMENT64:
if (pfnGetSymbol)
rc = pfnGetSymbol(pCpu, DIS_FMT_SEL_FROM_REG(DISSELREG_CS), (uint64_t)pParam->parval, szSymbol, sizeof(szSymbol), &off, pvUser);
break;
default:
AssertFailed();
break;
}
if (RT_SUCCESS(rc))
{
PUT_SZ(" [");
if (off != 0)
{
else
}
PUT_C(']');
}
break;
}
case 'O': /* No ModRM byte (ParseImmAddr). */
{
PUT_FAR();
PUT_C('[');
int rc = VERR_SYMBOL_NOT_FOUND;
switch (pParam->fUse & (DISUSE_IMMEDIATE_ADDR_16_16 | DISUSE_IMMEDIATE_ADDR_16_32 | DISUSE_DISPLACEMENT64 | DISUSE_DISPLACEMENT32 | DISUSE_DISPLACEMENT16))
{
PUT_C(':');
if (pfnGetSymbol)
rc = pfnGetSymbol(pCpu, DIS_FMT_SEL_FROM_VALUE(pParam->parval >> 16), (uint16_t)pParam->parval, szSymbol, sizeof(szSymbol), &off, pvUser);
break;
PUT_C(':');
if (pfnGetSymbol)
rc = pfnGetSymbol(pCpu, DIS_FMT_SEL_FROM_VALUE(pParam->parval >> 16), (uint32_t)pParam->parval, szSymbol, sizeof(szSymbol), &off, pvUser);
break;
case DISUSE_DISPLACEMENT16:
if (pfnGetSymbol)
rc = pfnGetSymbol(pCpu, DIS_FMT_SEL_FROM_REG(DISSELREG_CS), pParam->uDisp.u16, szSymbol, sizeof(szSymbol), &off, pvUser);
break;
case DISUSE_DISPLACEMENT32:
if (pfnGetSymbol)
rc = pfnGetSymbol(pCpu, DIS_FMT_SEL_FROM_REG(DISSELREG_CS), pParam->uDisp.u32, szSymbol, sizeof(szSymbol), &off, pvUser);
break;
case DISUSE_DISPLACEMENT64:
if (pfnGetSymbol)
rc = pfnGetSymbol(pCpu, DIS_FMT_SEL_FROM_REG(DISSELREG_CS), pParam->uDisp.u64, szSymbol, sizeof(szSymbol), &off, pvUser);
break;
default:
AssertFailed();
break;
}
PUT_C(']');
if (RT_SUCCESS(rc))
{
PUT_SZ(" (");
if (off != 0)
{
else
}
PUT_C(')');
}
break;
}
case 'X': /* DS:SI (ParseXb, ParseXv). */
case 'Y': /* ES:DI (ParseYb, ParseYv). */
{
PUT_FAR();
PUT_C('[');
PUT_SZ("ds:");
else
PUT_SZ("es:");
PUT_C(']');
break;
}
case 'e': /* Register based on operand size (e.g. %eAX) (ParseFixedReg). */
{
Assert(RT_C_IS_ALPHA(pszFmt[0]) && RT_C_IS_ALPHA(pszFmt[1]) && !RT_C_IS_ALPHA(pszFmt[2])); pszFmt += 2;
break;
}
default:
break;
}
}
else
{
if (ch == ',')
{
PUT_C(' ');
switch (++iParam)
{
}
}
}
} /* while more to format */
}
/*
* Any additional output to the right of the instruction?
*/
{
/* some up front padding. */
/* comment? */
PUT_SZ(";");
/*
* The address?
*/
if (fFlags & DIS_FMT_FLAGS_ADDR_RIGHT)
{
PUT_C(' ');
#endif
}
/*
* Opcode bytes?
*/
if (fFlags & DIS_FMT_FLAGS_BYTES_RIGHT)
{
PUT_C(' ');
}
}
/*
* Terminate it - on overflow we'll have reserved one byte for this.
*/
if (cchDst > 0)
*pszDst = '\0';
else
/* clean up macros */
return cchOutput;
}
/**
* Formats the current instruction in Yasm (/ Nasm) style.
*
* This is a simplified version of DISFormatYasmEx() provided for your convenience.
*
*
* @returns The number of output characters. If this is >= cchBuf, then the content
* of pszBuf will be truncated.
* @param pCpu Pointer to the disassembler CPU state.
* @param pszBuf The output buffer.
* @param cchBuf The size of the output buffer.
*/
{
return DISFormatYasmEx(pCpu, pszBuf, cchBuf, 0 /* fFlags */, NULL /* pfnGetSymbol */, NULL /* pvUser */);
}
/**
* Checks if the encoding of the given disassembled instruction is something we
* can never get YASM to produce.
*
* @returns true if it's odd, false if it isn't.
* @param pCpu The disassembler output. The byte fetcher callback will
* be used if present as we might need to fetch opcode
* bytes.
*/
{
/*
* Mod rm + SIB: Check for duplicate EBP encodings that yasm won't use for very good reasons.
*/
{
/* No scaled index SIB (index=4), except for ESP. */
return true;
/* EBP + displacement */
return true;
}
/*
* Seems to be an instruction alias here, but I cannot find any docs on it... hrmpf!
*/
return true;
/*
* Check for multiple prefixes of the same kind.
*/
{
uint32_t f;
{
case 0xf0:
f = DISPREFIX_LOCK;
break;
case 0xf2:
case 0xf3:
f = DISPREFIX_REP; /* yes, both */
break;
case 0x2e:
case 0x3e:
case 0x26:
case 0x36:
case 0x64:
case 0x65:
f = DISPREFIX_SEG;
break;
case 0x66:
f = DISPREFIX_OPSIZE;
break;
case 0x67:
f = DISPREFIX_ADDRSIZE;
break;
case 0x40: case 0x41: case 0x42: case 0x43: case 0x44: case 0x45: case 0x46: case 0x47:
case 0x48: case 0x49: case 0x4a: case 0x4b: case 0x4c: case 0x4d: case 0x4e: case 0x4f:
break;
default:
f = 0;
break;
}
if (!f)
break; /* done */
if (fPrefixes & f)
return true;
fPrefixes |= f;
}
/* segment overrides are fun */
if (fPrefixes & DISPREFIX_SEG)
{
/* no effective address which it may apply to. */
return true;
}
/* fixed register + addr override doesn't go down all that well. */
if (fPrefixes & DISPREFIX_ADDRSIZE)
{
return true;
}
/* Almost all prefixes are bad. */
if (fPrefixes)
{
{
/* nop w/ prefix(es). */
case OP_NOP:
return true;
case OP_JMP:
break;
/* fall thru */
case OP_JO:
case OP_JNO:
case OP_JC:
case OP_JNC:
case OP_JE:
case OP_JNE:
case OP_JBE:
case OP_JNBE:
case OP_JS:
case OP_JNS:
case OP_JP:
case OP_JNP:
case OP_JL:
case OP_JNL:
case OP_JLE:
case OP_JNLE:
/** @todo branch hinting 0x2e/0x3e... */
return true;
}
}
/* All but the segment prefix is bad news. */
if (fPrefixes & ~DISPREFIX_SEG)
{
{
case OP_POP:
case OP_PUSH:
return true;
if ( (fPrefixes & ~DISPREFIX_OPSIZE)
return true;
break;
case OP_POPA:
case OP_POPF:
case OP_PUSHA:
case OP_PUSHF:
if (fPrefixes & ~DISPREFIX_OPSIZE)
return true;
break;
}
}
/* Implicit 8-bit register instructions doesn't mix with operand size. */
if ( (fPrefixes & DISPREFIX_OPSIZE)
)
{
{
case OP_ADD:
case OP_OR:
case OP_ADC:
case OP_SBB:
case OP_AND:
case OP_SUB:
case OP_XOR:
case OP_CMP:
return true;
default:
break;
}
}
/*
* Check for the version of xyz reg,reg instruction that the assembler doesn't use.
*
* For example:
*/
{
{
case OP_ADD:
case OP_OR:
case OP_ADC:
case OP_SBB:
case OP_AND:
case OP_SUB:
case OP_XOR:
case OP_CMP:
return true;
/* 82 (see table A-6). */
return true;
break;
/* ff /0, fe /0, ff /1, fe /0 */
case OP_DEC:
case OP_INC:
return true;
case OP_POP:
case OP_PUSH:
return true;
case OP_MOV:
return true;
break;
default:
break;
}
}
/* shl eax,1 will be assembled to the form without the immediate byte. */
{
{
case OP_SHL:
case OP_SHR:
case OP_SAR:
case OP_RCL:
case OP_RCR:
case OP_ROL:
case OP_ROR:
return true;
}
}
/* And some more - see table A-6. */
{
{
case OP_ADD:
case OP_OR:
case OP_ADC:
case OP_SBB:
case OP_AND:
case OP_SUB:
case OP_XOR:
case OP_CMP:
return true;
break;
}
}
/* check for REX.X = 1 without SIB. */
/* Yasm encodes setnbe al with /2 instead of /0 like the AMD manual
says (intel doesn't appear to care). */
{
case OP_SETO:
case OP_SETNO:
case OP_SETC:
case OP_SETNC:
case OP_SETE:
case OP_SETNE:
case OP_SETBE:
case OP_SETNBE:
case OP_SETS:
case OP_SETNS:
case OP_SETP:
case OP_SETNP:
case OP_SETL:
case OP_SETNL:
case OP_SETLE:
case OP_SETNLE:
return true;
break;
}
/*
* The MOVZX reg32,mem16 instruction without an operand size prefix
* doesn't quite make sense...
*/
return true;
return false;
}