DisasmFormatYasm.cpp revision f3701698f9d61fed78c320c3b35c64a0c63d6db1
de6ba1989c812829372828f1801b232b3e7f09bfvboxsync * VBox Disassembler - Yasm(/Nasm) Style Formatter.
701efa93fe91e164d983fdc7b780b9f203381d0bvboxsync * Copyright (C) 2008-2012 Oracle Corporation
de6ba1989c812829372828f1801b232b3e7f09bfvboxsync * This file is part of VirtualBox Open Source Edition (OSE), as
de6ba1989c812829372828f1801b232b3e7f09bfvboxsync * available from http://www.virtualbox.org. This file is free software;
de6ba1989c812829372828f1801b232b3e7f09bfvboxsync * you can redistribute it and/or modify it under the terms of the GNU
de6ba1989c812829372828f1801b232b3e7f09bfvboxsync * General Public License (GPL) as published by the Free Software
de6ba1989c812829372828f1801b232b3e7f09bfvboxsync * Foundation, in version 2 as it comes in the "COPYING" file of the
de6ba1989c812829372828f1801b232b3e7f09bfvboxsync * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
de6ba1989c812829372828f1801b232b3e7f09bfvboxsync * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
de6ba1989c812829372828f1801b232b3e7f09bfvboxsync/*******************************************************************************
de6ba1989c812829372828f1801b232b3e7f09bfvboxsync* Header Files *
de6ba1989c812829372828f1801b232b3e7f09bfvboxsync*******************************************************************************/
de6ba1989c812829372828f1801b232b3e7f09bfvboxsync/*******************************************************************************
de6ba1989c812829372828f1801b232b3e7f09bfvboxsync* Global Variables *
de6ba1989c812829372828f1801b232b3e7f09bfvboxsync*******************************************************************************/
de6ba1989c812829372828f1801b232b3e7f09bfvboxsyncstatic const char g_szSpaces[] =
d3cb168f4c128e4477c3f791d983f84075fb2835vboxsync "al\0\0", "cl\0\0", "dl\0\0", "bl\0\0", "ah\0\0", "ch\0\0", "dh\0\0", "bh\0\0", "r8b\0", "r9b\0", "r10b", "r11b", "r12b", "r13b", "r14b", "r15b", "spl\0", "bpl\0", "sil\0", "dil\0"
de6ba1989c812829372828f1801b232b3e7f09bfvboxsync "ax\0\0", "cx\0\0", "dx\0\0", "bx\0\0", "sp\0\0", "bp\0\0", "si\0\0", "di\0\0", "r8w\0", "r9w\0", "r10w", "r11w", "r12w", "r13w", "r14w", "r15w"
de6ba1989c812829372828f1801b232b3e7f09bfvboxsync "bx+si", "bx+di", "bp+si", "bp+di", "si\0\0\0", "di\0\0\0", "bp\0\0\0", "bx\0\0\0"
de6ba1989c812829372828f1801b232b3e7f09bfvboxsync "eax\0", "ecx\0", "edx\0", "ebx\0", "esp\0", "ebp\0", "esi\0", "edi\0", "r8d\0", "r9d\0", "r10d", "r11d", "r12d", "r13d", "r14d", "r15d"
de6ba1989c812829372828f1801b232b3e7f09bfvboxsync "rax", "rcx", "rdx", "rbx", "rsp", "rbp", "rsi", "rdi", "r8\0", "r9\0", "r10", "r11", "r12", "r13", "r14", "r15"
de6ba1989c812829372828f1801b232b3e7f09bfvboxsync "st0", "st1", "st2", "st3", "st4", "st5", "st6", "st7"
de6ba1989c812829372828f1801b232b3e7f09bfvboxsync "mm0", "mm1", "mm2", "mm3", "mm4", "mm5", "mm6", "mm7"
de6ba1989c812829372828f1801b232b3e7f09bfvboxsync "xmm0\0", "xmm1\0", "xmm2\0", "xmm3\0", "xmm4\0", "xmm5\0", "xmm6\0", "xmm7\0", "xmm8\0", "xmm9\0", "xmm10", "xmm11", "xmm12", "xmm13", "xmm14", "xmm15"
de6ba1989c812829372828f1801b232b3e7f09bfvboxsync "cr0\0", "cr1\0", "cr2\0", "cr3\0", "cr4\0", "cr5\0", "cr6\0", "cr7\0", "cr8\0", "cr9\0", "cr10", "cr11", "cr12", "cr13", "cr14", "cr15"
de6ba1989c812829372828f1801b232b3e7f09bfvboxsync "dr0\0", "dr1\0", "dr2\0", "dr3\0", "dr4\0", "dr5\0", "dr6\0", "dr7\0", "dr8\0", "dr9\0", "dr10", "dr11", "dr12", "dr13", "dr14", "dr15"
de6ba1989c812829372828f1801b232b3e7f09bfvboxsync "tr0\0", "tr1\0", "tr2\0", "tr3\0", "tr4\0", "tr5\0", "tr6\0", "tr7\0", "tr8\0", "tr9\0", "tr10", "tr11", "tr12", "tr13", "tr14", "tr15"
de6ba1989c812829372828f1801b232b3e7f09bfvboxsync * Gets the base register name for the given parameter.
de6ba1989c812829372828f1801b232b3e7f09bfvboxsync * @returns Pointer to the register name.
de6ba1989c812829372828f1801b232b3e7f09bfvboxsync * @param pCpu The disassembler cpu state.
de6ba1989c812829372828f1801b232b3e7f09bfvboxsync * @param pParam The parameter.
de6ba1989c812829372828f1801b232b3e7f09bfvboxsync * @param pcchReg Where to store the length of the name.
c4461ed7d98e36db713a44504c83c5de0430d4ebvboxsyncstatic const char *disasmFormatYasmBaseReg(PCDISCPUSTATE pCpu, PCDISOPPARAM pParam, size_t *pcchReg)
8e2451f7a9a8e6e722d2065fe0eeb5df93799c7avboxsync switch (pParam->fUse & ( DISUSE_REG_GEN8 | DISUSE_REG_GEN16 | DISUSE_REG_GEN32 | DISUSE_REG_GEN64
8e2451f7a9a8e6e722d2065fe0eeb5df93799c7avboxsync | DISUSE_REG_FP | DISUSE_REG_MMX | DISUSE_REG_XMM | DISUSE_REG_CR
8e2451f7a9a8e6e722d2065fe0eeb5df93799c7avboxsync | DISUSE_REG_DBG | DISUSE_REG_SEG | DISUSE_REG_TEST))
d3cb168f4c128e4477c3f791d983f84075fb2835vboxsync Assert(pParam->base.reg_gen < RT_ELEMENTS(g_aszYasmRegGen8));
d3cb168f4c128e4477c3f791d983f84075fb2835vboxsync const char *psz = g_aszYasmRegGen8[pParam->base.reg_gen];
de6ba1989c812829372828f1801b232b3e7f09bfvboxsync Assert(pParam->base.reg_gen < RT_ELEMENTS(g_aszYasmRegGen16));
de6ba1989c812829372828f1801b232b3e7f09bfvboxsync const char *psz = g_aszYasmRegGen16[pParam->base.reg_gen];
de6ba1989c812829372828f1801b232b3e7f09bfvboxsync Assert(pParam->base.reg_gen < RT_ELEMENTS(g_aszYasmRegGen32));
de6ba1989c812829372828f1801b232b3e7f09bfvboxsync const char *psz = g_aszYasmRegGen32[pParam->base.reg_gen];
de6ba1989c812829372828f1801b232b3e7f09bfvboxsync Assert(pParam->base.reg_gen < RT_ELEMENTS(g_aszYasmRegGen64));
de6ba1989c812829372828f1801b232b3e7f09bfvboxsync const char *psz = g_aszYasmRegGen64[pParam->base.reg_gen];
de6ba1989c812829372828f1801b232b3e7f09bfvboxsync Assert(pParam->base.reg_fp < RT_ELEMENTS(g_aszYasmRegFP));
de6ba1989c812829372828f1801b232b3e7f09bfvboxsync const char *psz = g_aszYasmRegFP[pParam->base.reg_fp];
de6ba1989c812829372828f1801b232b3e7f09bfvboxsync Assert(pParam->base.reg_mmx < RT_ELEMENTS(g_aszYasmRegMMX));
de6ba1989c812829372828f1801b232b3e7f09bfvboxsync const char *psz = g_aszYasmRegMMX[pParam->base.reg_mmx];
de6ba1989c812829372828f1801b232b3e7f09bfvboxsync Assert(pParam->base.reg_xmm < RT_ELEMENTS(g_aszYasmRegXMM));
de6ba1989c812829372828f1801b232b3e7f09bfvboxsync const char *psz = g_aszYasmRegXMM[pParam->base.reg_mmx];
de6ba1989c812829372828f1801b232b3e7f09bfvboxsync Assert(pParam->base.reg_ctrl < RT_ELEMENTS(g_aszYasmRegCRx));
de6ba1989c812829372828f1801b232b3e7f09bfvboxsync const char *psz = g_aszYasmRegCRx[pParam->base.reg_ctrl];
de6ba1989c812829372828f1801b232b3e7f09bfvboxsync Assert(pParam->base.reg_dbg < RT_ELEMENTS(g_aszYasmRegDRx));
de6ba1989c812829372828f1801b232b3e7f09bfvboxsync const char *psz = g_aszYasmRegDRx[pParam->base.reg_dbg];
0dcab00efb68dbd44bd653d4cb18aaaef7448898vboxsync Assert(pParam->base.reg_seg < RT_ELEMENTS(g_aszYasmRegCRx));
de6ba1989c812829372828f1801b232b3e7f09bfvboxsync const char *psz = g_aszYasmRegSeg[pParam->base.reg_seg];
de6ba1989c812829372828f1801b232b3e7f09bfvboxsync Assert(pParam->base.reg_test < RT_ELEMENTS(g_aszYasmRegTRx));
de6ba1989c812829372828f1801b232b3e7f09bfvboxsync const char *psz = g_aszYasmRegTRx[pParam->base.reg_test];
de6ba1989c812829372828f1801b232b3e7f09bfvboxsync return "r??";
de6ba1989c812829372828f1801b232b3e7f09bfvboxsync * Gets the index register name for the given parameter.
de6ba1989c812829372828f1801b232b3e7f09bfvboxsync * @returns The index register name.
de6ba1989c812829372828f1801b232b3e7f09bfvboxsync * @param pCpu The disassembler cpu state.
de6ba1989c812829372828f1801b232b3e7f09bfvboxsync * @param pParam The parameter.
de6ba1989c812829372828f1801b232b3e7f09bfvboxsync * @param pcchReg Where to store the length of the name.
c4461ed7d98e36db713a44504c83c5de0430d4ebvboxsyncstatic const char *disasmFormatYasmIndexReg(PCDISCPUSTATE pCpu, PCDISOPPARAM pParam, size_t *pcchReg)
de6ba1989c812829372828f1801b232b3e7f09bfvboxsync Assert(pParam->index.reg_gen < RT_ELEMENTS(g_aszYasmRegGen16));
de6ba1989c812829372828f1801b232b3e7f09bfvboxsync const char *psz = g_aszYasmRegGen16[pParam->index.reg_gen];
de6ba1989c812829372828f1801b232b3e7f09bfvboxsync Assert(pParam->index.reg_gen < RT_ELEMENTS(g_aszYasmRegGen32));
de6ba1989c812829372828f1801b232b3e7f09bfvboxsync const char *psz = g_aszYasmRegGen32[pParam->index.reg_gen];
de6ba1989c812829372828f1801b232b3e7f09bfvboxsync Assert(pParam->index.reg_gen < RT_ELEMENTS(g_aszYasmRegGen64));
de6ba1989c812829372828f1801b232b3e7f09bfvboxsync const char *psz = g_aszYasmRegGen64[pParam->index.reg_gen];
8e2451f7a9a8e6e722d2065fe0eeb5df93799c7avboxsync AssertMsgFailed(("%#x %#x\n", pParam->fUse, pCpu->addrmode));
de6ba1989c812829372828f1801b232b3e7f09bfvboxsync return "r??";
de6ba1989c812829372828f1801b232b3e7f09bfvboxsync * Formats the current instruction in Yasm (/ Nasm) style.
de6ba1989c812829372828f1801b232b3e7f09bfvboxsync * @returns The number of output characters. If this is >= cchBuf, then the content
de6ba1989c812829372828f1801b232b3e7f09bfvboxsync * of pszBuf will be truncated.
de6ba1989c812829372828f1801b232b3e7f09bfvboxsync * @param pCpu Pointer to the disassembler CPU state.
de6ba1989c812829372828f1801b232b3e7f09bfvboxsync * @param pszBuf The output buffer.
de6ba1989c812829372828f1801b232b3e7f09bfvboxsync * @param cchBuf The size of the output buffer.
de6ba1989c812829372828f1801b232b3e7f09bfvboxsync * @param fFlags Format flags, see DIS_FORMAT_FLAGS_*.
de6ba1989c812829372828f1801b232b3e7f09bfvboxsync * @param pfnGetSymbol Get symbol name for a jmp or call target address. Optional.
de6ba1989c812829372828f1801b232b3e7f09bfvboxsync * @param pvUser User argument for pfnGetSymbol.
de6ba1989c812829372828f1801b232b3e7f09bfvboxsyncDISDECL(size_t) DISFormatYasmEx(PCDISCPUSTATE pCpu, char *pszBuf, size_t cchBuf, uint32_t fFlags,
de6ba1989c812829372828f1801b232b3e7f09bfvboxsync * Input validation and massaging.
de6ba1989c812829372828f1801b232b3e7f09bfvboxsync AssertMsg(DIS_FMT_FLAGS_IS_VALID(fFlags), ("%#x\n", fFlags));
de6ba1989c812829372828f1801b232b3e7f09bfvboxsync fFlags = (fFlags & ~DIS_FMT_FLAGS_ADDR_LEFT) | DIS_FMT_FLAGS_ADDR_RIGHT;
de6ba1989c812829372828f1801b232b3e7f09bfvboxsync fFlags = (fFlags & ~DIS_FMT_FLAGS_BYTES_LEFT) | DIS_FMT_FLAGS_BYTES_RIGHT;
de6ba1989c812829372828f1801b232b3e7f09bfvboxsync * Output macros
de6ba1989c812829372828f1801b232b3e7f09bfvboxsync } while (0)
de6ba1989c812829372828f1801b232b3e7f09bfvboxsync } while (0)
92473d1de9ab080ff886ad61a4d908f7c3429608vboxsync do { if (fFlags & DIS_FMT_FLAGS_STRICT) PUT_SZ(szStrict); else PUT_SZ(szRelaxed); } while (0)
de6ba1989c812829372828f1801b232b3e7f09bfvboxsync do { const size_t cchTmp = strlen(psz); PUT_STR((psz), cchTmp); } while (0)
de6ba1989c812829372828f1801b232b3e7f09bfvboxsync const size_t cchTmp = RTStrPrintf(pszDst, cchDst, fmt, (num)); \
de6ba1989c812829372828f1801b232b3e7f09bfvboxsync } while (0)
95ed338027d70aabb68eff2437bf0d08ebbdbea4vboxsync/** @todo add two flags for choosing between %X / %x and h / 0x. */
de6ba1989c812829372828f1801b232b3e7f09bfvboxsync#define PUT_NUM_8(num) PUT_NUM(4, "0%02xh", (uint8_t)(num))
de6ba1989c812829372828f1801b232b3e7f09bfvboxsync#define PUT_NUM_16(num) PUT_NUM(6, "0%04xh", (uint16_t)(num))
de6ba1989c812829372828f1801b232b3e7f09bfvboxsync#define PUT_NUM_32(num) PUT_NUM(10, "0%08xh", (uint32_t)(num))
7917e2039cb1b59b67a3a8e26acce7f445860192vboxsync#define PUT_NUM_64(num) PUT_NUM(18, "0%016RX64h", (uint64_t)(num))
92473d1de9ab080ff886ad61a4d908f7c3429608vboxsync } while (0)
92473d1de9ab080ff886ad61a4d908f7c3429608vboxsync#define PUT_NUM_S8(num) PUT_NUM_SIGN(4, "0%02xh", num, int8_t, uint8_t)
92473d1de9ab080ff886ad61a4d908f7c3429608vboxsync#define PUT_NUM_S16(num) PUT_NUM_SIGN(6, "0%04xh", num, int16_t, uint16_t)
92473d1de9ab080ff886ad61a4d908f7c3429608vboxsync#define PUT_NUM_S32(num) PUT_NUM_SIGN(10, "0%08xh", num, int32_t, uint32_t)
7917e2039cb1b59b67a3a8e26acce7f445860192vboxsync#define PUT_NUM_S64(num) PUT_NUM_SIGN(18, "0%016RX64h", num, int64_t, uint64_t)
de6ba1989c812829372828f1801b232b3e7f09bfvboxsync * The address?
d7097a142464c500766b2cb3d564986e0a072799vboxsync PUT_NUM(9, "%08x`", (uint32_t)(pCpu->uInstrAddr >> 32));
de6ba1989c812829372828f1801b232b3e7f09bfvboxsync * The opcode bytes?
de6ba1989c812829372828f1801b232b3e7f09bfvboxsync size_t cchTmp = disFormatBytes(pCpu, pszDst, cchDst, fFlags);
de6ba1989c812829372828f1801b232b3e7f09bfvboxsync /* Some padding to align the instruction. */
de6ba1989c812829372828f1801b232b3e7f09bfvboxsync size_t cchPadding = (7 * (2 + !!(fFlags & DIS_FMT_FLAGS_BYTES_SPACED)))
de6ba1989c812829372828f1801b232b3e7f09bfvboxsync cchPadding = cchTmp + 1 >= cchPadding ? 1 : cchPadding - cchTmp;
de6ba1989c812829372828f1801b232b3e7f09bfvboxsync * Filter out invalid opcodes first as they need special
de6ba1989c812829372828f1801b232b3e7f09bfvboxsync * treatment. UD2 is an exception and should be handled normally.
de6ba1989c812829372828f1801b232b3e7f09bfvboxsync * Adjust the format string to the correct mnemonic
de6ba1989c812829372828f1801b232b3e7f09bfvboxsync * or to avoid things the assembler cannot handle correctly.
98502a585f6eda30527b54f7df18dd3de3d3d7c6vboxsync pszFmt = pCpu->opmode == DISCPUMODE_16BIT ? "jcxz %Jb" : pCpu->opmode == DISCPUMODE_32BIT ? "jecxz %Jb" : "jrcxz %Jb";
98502a585f6eda30527b54f7df18dd3de3d3d7c6vboxsync pszFmt = pCpu->opmode == DISCPUMODE_16BIT ? "pushfw" : pCpu->opmode == DISCPUMODE_32BIT ? "pushfd" : "pushfq";
98502a585f6eda30527b54f7df18dd3de3d3d7c6vboxsync pszFmt = pCpu->opmode == DISCPUMODE_16BIT ? "popfw" : pCpu->opmode == DISCPUMODE_32BIT ? "popfd" : "popfq";
98502a585f6eda30527b54f7df18dd3de3d3d7c6vboxsync pszFmt = pCpu->opmode == DISCPUMODE_16BIT ? "pushaw" : "pushad";
98502a585f6eda30527b54f7df18dd3de3d3d7c6vboxsync pszFmt = pCpu->opmode == DISCPUMODE_16BIT ? "popaw" : "popad";
98502a585f6eda30527b54f7df18dd3de3d3d7c6vboxsync pszFmt = pCpu->opmode == DISCPUMODE_16BIT ? "insw" : pCpu->opmode == DISCPUMODE_32BIT ? "insd" : "insq";
98502a585f6eda30527b54f7df18dd3de3d3d7c6vboxsync pszFmt = pCpu->opmode == DISCPUMODE_16BIT ? "outsw" : pCpu->opmode == DISCPUMODE_32BIT ? "outsd" : "outsq";
98502a585f6eda30527b54f7df18dd3de3d3d7c6vboxsync pszFmt = pCpu->opmode == DISCPUMODE_16BIT ? "movsw" : pCpu->opmode == DISCPUMODE_32BIT ? "movsd" : "movsq";
98502a585f6eda30527b54f7df18dd3de3d3d7c6vboxsync pszFmt = pCpu->opmode == DISCPUMODE_16BIT ? "cmpsw" : pCpu->opmode == DISCPUMODE_32BIT ? "cmpsd" : "cmpsq";
98502a585f6eda30527b54f7df18dd3de3d3d7c6vboxsync pszFmt = pCpu->opmode == DISCPUMODE_16BIT ? "scasw" : pCpu->opmode == DISCPUMODE_32BIT ? "scasd" : "scasq";
98502a585f6eda30527b54f7df18dd3de3d3d7c6vboxsync pszFmt = pCpu->opmode == DISCPUMODE_16BIT ? "lodsw" : pCpu->opmode == DISCPUMODE_32BIT ? "lodsd" : "lodsq";
98502a585f6eda30527b54f7df18dd3de3d3d7c6vboxsync pszFmt = pCpu->opmode == DISCPUMODE_16BIT ? "stosw" : pCpu->opmode == DISCPUMODE_32BIT ? "stosd" : "stosq";
98502a585f6eda30527b54f7df18dd3de3d3d7c6vboxsync pszFmt = pCpu->opmode == DISCPUMODE_16BIT ? "cbw" : pCpu->opmode == DISCPUMODE_32BIT ? "cwde" : "cdqe";
98502a585f6eda30527b54f7df18dd3de3d3d7c6vboxsync pszFmt = pCpu->opmode == DISCPUMODE_16BIT ? "cwd" : pCpu->opmode == DISCPUMODE_32BIT ? "cdq" : "cqo";
de6ba1989c812829372828f1801b232b3e7f09bfvboxsync * Don't know how to tell yasm to generate complicated nop stuff, so 'db' it.
de6ba1989c812829372828f1801b232b3e7f09bfvboxsync /* fine, fine */;
a1952aa85294c02b76ede695d74f0d3a805d6490vboxsync else if (pszFmt[sizeof("nop %Ev") - 1] == '/' && pszFmt[sizeof("nop %Ev")] == 'p')
de6ba1989c812829372828f1801b232b3e7f09bfvboxsync /* ST(X) -> stX (floating point) */
de6ba1989c812829372828f1801b232b3e7f09bfvboxsync if (ch == 'S' && pszFmt[0] == 'T' && pszFmt[1] == '(')
de6ba1989c812829372828f1801b232b3e7f09bfvboxsync * Horrible hacks.
de6ba1989c812829372828f1801b232b3e7f09bfvboxsync *(int *)&pCpu->param1.param &= ~0x1f; /* make it pure OP_PARM_M */
de6ba1989c812829372828f1801b232b3e7f09bfvboxsync case OP_LAR: /* hack w -> v, probably not correct. */
de6ba1989c812829372828f1801b232b3e7f09bfvboxsync * Formatting context and associated macros.
de6ba1989c812829372828f1801b232b3e7f09bfvboxsync if ( OP_PARM_VSUBTYPE(pParam->param) == OP_PARM_p \
de6ba1989c812829372828f1801b232b3e7f09bfvboxsync } while (0)
95ed338027d70aabb68eff2437bf0d08ebbdbea4vboxsync /** @todo mov ah,ch ends up with a byte 'override'... - check if this wasn't fixed. */
95ed338027d70aabb68eff2437bf0d08ebbdbea4vboxsync /** @todo drop the work/dword/qword override when the src/dst is a register (except for movsx/movzx). */
de6ba1989c812829372828f1801b232b3e7f09bfvboxsync default: break; \
de6ba1989c812829372828f1801b232b3e7f09bfvboxsync if (OP_PARM_VTYPE(pParam->param) != OP_PARM_W) /* these are 128 bit, pray they are all unambiguous.. */ \
8e2451f7a9a8e6e722d2065fe0eeb5df93799c7avboxsync case OP_PARM_s: if (pParam->fUse & DISUSE_REG_FP) PUT_SZ("tword "); break; /* ?? */ \
de6ba1989c812829372828f1801b232b3e7f09bfvboxsync case OP_PARM_z: break; \
8e2451f7a9a8e6e722d2065fe0eeb5df93799c7avboxsync && ((pParam->fUse & DISUSE_REG_FP) || pOp->opcode == OP_FLD)) \
de6ba1989c812829372828f1801b232b3e7f09bfvboxsync default: break; /*no pointer type specified/necessary*/ \
de6ba1989c812829372828f1801b232b3e7f09bfvboxsync } while (0)
de6ba1989c812829372828f1801b232b3e7f09bfvboxsync static const char s_szSegPrefix[6][4] = { "es:", "cs:", "ss:", "ds:", "fs:", "gs:" };
de6ba1989c812829372828f1801b232b3e7f09bfvboxsync } while (0)
de6ba1989c812829372828f1801b232b3e7f09bfvboxsync * Segment prefixing for instructions that doesn't do memory access.
de6ba1989c812829372828f1801b232b3e7f09bfvboxsync * The formatting loop.
de6ba1989c812829372828f1801b232b3e7f09bfvboxsync * ModRM - Register only.
de6ba1989c812829372828f1801b232b3e7f09bfvboxsync case 'C': /* Control register (ParseModRM / UseModRM). */
de6ba1989c812829372828f1801b232b3e7f09bfvboxsync case 'D': /* Debug register (ParseModRM / UseModRM). */
de6ba1989c812829372828f1801b232b3e7f09bfvboxsync case 'G': /* ModRM selects general register (ParseModRM / UseModRM). */
de6ba1989c812829372828f1801b232b3e7f09bfvboxsync case 'S': /* ModRM byte selects a segment register (ParseModRM / UseModRM). */
de6ba1989c812829372828f1801b232b3e7f09bfvboxsync case 'T': /* ModRM byte selects a test register (ParseModRM / UseModRM). */
de6ba1989c812829372828f1801b232b3e7f09bfvboxsync case 'V': /* ModRM byte selects an XMM/SSE register (ParseModRM / UseModRM). */
de6ba1989c812829372828f1801b232b3e7f09bfvboxsync case 'P': /* ModRM byte selects MMX register (ParseModRM / UseModRM). */
de6ba1989c812829372828f1801b232b3e7f09bfvboxsync pszFmt += RT_C_IS_ALPHA(pszFmt[0]) ? RT_C_IS_ALPHA(pszFmt[1]) ? 2 : 1 : 0;
8e2451f7a9a8e6e722d2065fe0eeb5df93799c7avboxsync Assert(!(pParam->fUse & (DISUSE_INDEX | DISUSE_SCALE) /* No SIB here... */));
8e2451f7a9a8e6e722d2065fe0eeb5df93799c7avboxsync Assert(!(pParam->fUse & (DISUSE_DISPLACEMENT8 | DISUSE_DISPLACEMENT16 | DISUSE_DISPLACEMENT32 | DISUSE_DISPLACEMENT64 | DISUSE_RIPDISPLACEMENT32)));
de6ba1989c812829372828f1801b232b3e7f09bfvboxsync const char *pszReg = disasmFormatYasmBaseReg(pCpu, pParam, &cchReg);
de6ba1989c812829372828f1801b232b3e7f09bfvboxsync * ModRM - Register or memory.
de6ba1989c812829372828f1801b232b3e7f09bfvboxsync case 'E': /* ModRM specifies parameter (ParseModRM / UseModRM / UseSIB). */
de6ba1989c812829372828f1801b232b3e7f09bfvboxsync case 'Q': /* ModRM byte selects MMX register or memory address (ParseModRM / UseModRM). */
de6ba1989c812829372828f1801b232b3e7f09bfvboxsync case 'R': /* ModRM byte may only refer to a general register (ParseModRM / UseModRM). */
de6ba1989c812829372828f1801b232b3e7f09bfvboxsync case 'W': /* ModRM byte selects an XMM/SSE register or a memory address (ParseModRM / UseModRM). */
de6ba1989c812829372828f1801b232b3e7f09bfvboxsync case 'M': /* ModRM may only refer to memory (ParseModRM / UseModRM). */
de6ba1989c812829372828f1801b232b3e7f09bfvboxsync pszFmt += RT_C_IS_ALPHA(pszFmt[0]) ? RT_C_IS_ALPHA(pszFmt[1]) ? 2 : 1 : 0;
de6ba1989c812829372828f1801b232b3e7f09bfvboxsync /* Work around mov seg,[mem16] and mov [mem16],seg as these always make a 16-bit mem
de6ba1989c812829372828f1801b232b3e7f09bfvboxsync while the register variants deals with 16, 32 & 64 in the normal fashion. */
3814edbc6a665ea4f1c3dc0c7dc9cb9dd83735b0vboxsync && (fUse & (DISUSE_DISPLACEMENT8 | DISUSE_DISPLACEMENT16 | DISUSE_DISPLACEMENT32 | DISUSE_DISPLACEMENT64 | DISUSE_RIPDISPLACEMENT32)))
a0892a0a33b8ffaa8ff2f252411176f63e8d9f18vboxsync && (int8_t)pParam->uDisp.i16 == (int16_t)pParam->uDisp.i16)
a0892a0a33b8ffaa8ff2f252411176f63e8d9f18vboxsync && (int16_t)pParam->uDisp.i32 == (int32_t)pParam->uDisp.i32) //??
99cd1ce586a12bf6b8c6084cbcdebe8fe3553cc2vboxsync && (pCpu->SIB.Bits.Base != 5 || pCpu->ModRM.Bits.Mod != 0)
a0892a0a33b8ffaa8ff2f252411176f63e8d9f18vboxsync && (int32_t)pParam->uDisp.i64 == (int64_t)pParam->uDisp.i64) //??
3814edbc6a665ea4f1c3dc0c7dc9cb9dd83735b0vboxsync bool fBase = (fUse & DISUSE_BASE) /* When exactly is DISUSE_BASE supposed to be set? disasmModRMReg doesn't set it. */
de6ba1989c812829372828f1801b232b3e7f09bfvboxsync const char *pszReg = disasmFormatYasmBaseReg(pCpu, pParam, &cchReg);
de6ba1989c812829372828f1801b232b3e7f09bfvboxsync const char *pszReg = disasmFormatYasmIndexReg(pCpu, pParam, &cchReg);
3814edbc6a665ea4f1c3dc0c7dc9cb9dd83735b0vboxsync if (fUse & (DISUSE_DISPLACEMENT8 | DISUSE_DISPLACEMENT16 | DISUSE_DISPLACEMENT32 | DISUSE_DISPLACEMENT64 | DISUSE_RIPDISPLACEMENT32))
3814edbc6a665ea4f1c3dc0c7dc9cb9dd83735b0vboxsync else if (fUse & (DISUSE_DISPLACEMENT32 | DISUSE_RIPDISPLACEMENT32))
de6ba1989c812829372828f1801b232b3e7f09bfvboxsync case 'F': /* Eflags register (0 - popf/pushf only, avoided in adjustments above). */
de6ba1989c812829372828f1801b232b3e7f09bfvboxsync case 'I': /* Immediate data (ParseImmByte, ParseImmByteSX, ParseImmV, ParseImmUshort, ParseImmZ). */
de6ba1989c812829372828f1801b232b3e7f09bfvboxsync Assert(*pszFmt == 'b' || *pszFmt == 'v' || *pszFmt == 'w' || *pszFmt == 'z'); pszFmt++;
8e2451f7a9a8e6e722d2065fe0eeb5df93799c7avboxsync switch (pParam->fUse & ( DISUSE_IMMEDIATE8 | DISUSE_IMMEDIATE16 | DISUSE_IMMEDIATE32 | DISUSE_IMMEDIATE64
8e2451f7a9a8e6e722d2065fe0eeb5df93799c7avboxsync | DISUSE_IMMEDIATE16_SX8 | DISUSE_IMMEDIATE32_SX8 | DISUSE_IMMEDIATE64_SX8))
92473d1de9ab080ff886ad61a4d908f7c3429608vboxsync && ( (pOp->param1 >= OP_PARM_REG_GEN8_START && pOp->param1 <= OP_PARM_REG_GEN8_END)
92473d1de9ab080ff886ad61a4d908f7c3429608vboxsync || (pOp->param2 >= OP_PARM_REG_GEN8_START && pOp->param2 <= OP_PARM_REG_GEN8_END))
92473d1de9ab080ff886ad61a4d908f7c3429608vboxsync && ( (int8_t)pParam->parval == (int16_t)pParam->parval
92473d1de9ab080ff886ad61a4d908f7c3429608vboxsync || (pOp->param1 >= OP_PARM_REG_GEN16_START && pOp->param1 <= OP_PARM_REG_GEN16_END)
92473d1de9ab080ff886ad61a4d908f7c3429608vboxsync || (pOp->param2 >= OP_PARM_REG_GEN16_START && pOp->param2 <= OP_PARM_REG_GEN16_END))
d57a37bcf6ddf491c2b649ff9488798e854969a9vboxsync else if ( OP_PARM_VSUBTYPE(pParam->param) == OP_PARM_v
98502a585f6eda30527b54f7df18dd3de3d3d7c6vboxsync if ( pCpu->opmode != (pCpu->mode == DISCPUMODE_16BIT ? DISCPUMODE_16BIT : DISCPUMODE_32BIT) /* not perfect */
92473d1de9ab080ff886ad61a4d908f7c3429608vboxsync && ( (int8_t)pParam->parval == (int32_t)pParam->parval
92473d1de9ab080ff886ad61a4d908f7c3429608vboxsync || (pOp->param1 >= OP_PARM_REG_GEN32_START && pOp->param1 <= OP_PARM_REG_GEN32_END)
92473d1de9ab080ff886ad61a4d908f7c3429608vboxsync || (pOp->param2 >= OP_PARM_REG_GEN32_START && pOp->param2 <= OP_PARM_REG_GEN32_END))
d57a37bcf6ddf491c2b649ff9488798e854969a9vboxsync else if ( OP_PARM_VSUBTYPE(pParam->param) == OP_PARM_v
de6ba1989c812829372828f1801b232b3e7f09bfvboxsync case 'J': /* Relative jump offset (ParseImmBRel + ParseImmVRel). */
8e2451f7a9a8e6e722d2065fe0eeb5df93799c7avboxsync Assert(pParam->fUse & (DISUSE_IMMEDIATE32_REL|DISUSE_IMMEDIATE64_REL));
faa7602db7e32056326da7e169b5f505c607138fvboxsync RTUINTPTR uTrgAddr = pCpu->uInstrAddr + pCpu->cbInstr + offDisplacement;
dcc035155cdf232a3d79024f475c2d4448981e85vboxsync int rc = pfnGetSymbol(pCpu, DIS_FMT_SEL_FROM_REG(DISSELREG_CS), uTrgAddr, szSymbol, sizeof(szSymbol), &off, pvUser);
de6ba1989c812829372828f1801b232b3e7f09bfvboxsync case 'A': /* Direct (jump/call) address (ParseImmAddr). */
8e2451f7a9a8e6e722d2065fe0eeb5df93799c7avboxsync switch (pParam->fUse & (DISUSE_IMMEDIATE_ADDR_16_16 | DISUSE_IMMEDIATE_ADDR_16_32 | DISUSE_DISPLACEMENT64 | DISUSE_DISPLACEMENT32 | DISUSE_DISPLACEMENT16))
1ec912d58b09f1e2eda06b788299d6157cd826b1vboxsync rc = pfnGetSymbol(pCpu, DIS_FMT_SEL_FROM_VALUE(pParam->parval >> 16), (uint16_t)pParam->parval, szSymbol, sizeof(szSymbol), &off, pvUser);
1ec912d58b09f1e2eda06b788299d6157cd826b1vboxsync rc = pfnGetSymbol(pCpu, DIS_FMT_SEL_FROM_VALUE(pParam->parval >> 16), (uint32_t)pParam->parval, szSymbol, sizeof(szSymbol), &off, pvUser);
dcc035155cdf232a3d79024f475c2d4448981e85vboxsync rc = pfnGetSymbol(pCpu, DIS_FMT_SEL_FROM_REG(DISSELREG_CS), (uint16_t)pParam->parval, szSymbol, sizeof(szSymbol), &off, pvUser);
dcc035155cdf232a3d79024f475c2d4448981e85vboxsync rc = pfnGetSymbol(pCpu, DIS_FMT_SEL_FROM_REG(DISSELREG_CS), (uint32_t)pParam->parval, szSymbol, sizeof(szSymbol), &off, pvUser);
dcc035155cdf232a3d79024f475c2d4448981e85vboxsync rc = pfnGetSymbol(pCpu, DIS_FMT_SEL_FROM_REG(DISSELREG_CS), (uint64_t)pParam->parval, szSymbol, sizeof(szSymbol), &off, pvUser);
de6ba1989c812829372828f1801b232b3e7f09bfvboxsync Assert(*pszFmt == 'b' || *pszFmt == 'v'); pszFmt++;
8e2451f7a9a8e6e722d2065fe0eeb5df93799c7avboxsync switch (pParam->fUse & (DISUSE_IMMEDIATE_ADDR_16_16 | DISUSE_IMMEDIATE_ADDR_16_32 | DISUSE_DISPLACEMENT64 | DISUSE_DISPLACEMENT32 | DISUSE_DISPLACEMENT16))
1ec912d58b09f1e2eda06b788299d6157cd826b1vboxsync rc = pfnGetSymbol(pCpu, DIS_FMT_SEL_FROM_VALUE(pParam->parval >> 16), (uint16_t)pParam->parval, szSymbol, sizeof(szSymbol), &off, pvUser);
1ec912d58b09f1e2eda06b788299d6157cd826b1vboxsync rc = pfnGetSymbol(pCpu, DIS_FMT_SEL_FROM_VALUE(pParam->parval >> 16), (uint32_t)pParam->parval, szSymbol, sizeof(szSymbol), &off, pvUser);
dcc035155cdf232a3d79024f475c2d4448981e85vboxsync rc = pfnGetSymbol(pCpu, DIS_FMT_SEL_FROM_REG(DISSELREG_CS), pParam->uDisp.u16, szSymbol, sizeof(szSymbol), &off, pvUser);
dcc035155cdf232a3d79024f475c2d4448981e85vboxsync rc = pfnGetSymbol(pCpu, DIS_FMT_SEL_FROM_REG(DISSELREG_CS), pParam->uDisp.u32, szSymbol, sizeof(szSymbol), &off, pvUser);
dcc035155cdf232a3d79024f475c2d4448981e85vboxsync rc = pfnGetSymbol(pCpu, DIS_FMT_SEL_FROM_REG(DISSELREG_CS), pParam->uDisp.u64, szSymbol, sizeof(szSymbol), &off, pvUser);
de6ba1989c812829372828f1801b232b3e7f09bfvboxsync Assert(*pszFmt == 'b' || *pszFmt == 'v'); pszFmt++;
de6ba1989c812829372828f1801b232b3e7f09bfvboxsync const char *pszReg = disasmFormatYasmBaseReg(pCpu, pParam, &cchReg);
de6ba1989c812829372828f1801b232b3e7f09bfvboxsync case 'e': /* Register based on operand size (e.g. %eAX) (ParseFixedReg). */
de6ba1989c812829372828f1801b232b3e7f09bfvboxsync Assert(RT_C_IS_ALPHA(pszFmt[0]) && RT_C_IS_ALPHA(pszFmt[1]) && !RT_C_IS_ALPHA(pszFmt[2])); pszFmt += 2;
de6ba1989c812829372828f1801b232b3e7f09bfvboxsync const char *pszReg = disasmFormatYasmBaseReg(pCpu, pParam, &cchReg);
de6ba1989c812829372828f1801b232b3e7f09bfvboxsync AssertMsg(*pszFmt == ',' || *pszFmt == '\0', ("%c%s\n", ch, pszFmt));
de6ba1989c812829372828f1801b232b3e7f09bfvboxsync } /* while more to format */
de6ba1989c812829372828f1801b232b3e7f09bfvboxsync * Any additional output to the right of the instruction?
de6ba1989c812829372828f1801b232b3e7f09bfvboxsync if (fFlags & (DIS_FMT_FLAGS_BYTES_RIGHT | DIS_FMT_FLAGS_ADDR_RIGHT))
de6ba1989c812829372828f1801b232b3e7f09bfvboxsync /* some up front padding. */
de6ba1989c812829372828f1801b232b3e7f09bfvboxsync cchPadding = cchPadding + 1 >= 42 ? 1 : 42 - cchPadding;
de6ba1989c812829372828f1801b232b3e7f09bfvboxsync /* comment? */
de6ba1989c812829372828f1801b232b3e7f09bfvboxsync if (fFlags & (DIS_FMT_FLAGS_BYTES_RIGHT | DIS_FMT_FLAGS_ADDR_RIGHT))
de6ba1989c812829372828f1801b232b3e7f09bfvboxsync * The address?
d7097a142464c500766b2cb3d564986e0a072799vboxsync PUT_NUM(9, "%08x`", (uint32_t)(pCpu->uInstrAddr >> 32));
de6ba1989c812829372828f1801b232b3e7f09bfvboxsync * Opcode bytes?
de6ba1989c812829372828f1801b232b3e7f09bfvboxsync size_t cchTmp = disFormatBytes(pCpu, pszDst, cchDst, fFlags);
de6ba1989c812829372828f1801b232b3e7f09bfvboxsync * Terminate it - on overflow we'll have reserved one byte for this.
de6ba1989c812829372828f1801b232b3e7f09bfvboxsync /* clean up macros */
de6ba1989c812829372828f1801b232b3e7f09bfvboxsync * Formats the current instruction in Yasm (/ Nasm) style.
de6ba1989c812829372828f1801b232b3e7f09bfvboxsync * This is a simplified version of DISFormatYasmEx() provided for your convenience.
de6ba1989c812829372828f1801b232b3e7f09bfvboxsync * @returns The number of output characters. If this is >= cchBuf, then the content
de6ba1989c812829372828f1801b232b3e7f09bfvboxsync * of pszBuf will be truncated.
de6ba1989c812829372828f1801b232b3e7f09bfvboxsync * @param pCpu Pointer to the disassembler CPU state.
de6ba1989c812829372828f1801b232b3e7f09bfvboxsync * @param pszBuf The output buffer.
de6ba1989c812829372828f1801b232b3e7f09bfvboxsync * @param cchBuf The size of the output buffer.
de6ba1989c812829372828f1801b232b3e7f09bfvboxsyncDISDECL(size_t) DISFormatYasm(PCDISCPUSTATE pCpu, char *pszBuf, size_t cchBuf)
de6ba1989c812829372828f1801b232b3e7f09bfvboxsync return DISFormatYasmEx(pCpu, pszBuf, cchBuf, 0 /* fFlags */, NULL /* pfnGetSymbol */, NULL /* pvUser */);
b82fef5dcbe08cae8ce37a09825adc4c6b0bf762vboxsync * Checks if the encoding of the given disassembled instruction is something we
b82fef5dcbe08cae8ce37a09825adc4c6b0bf762vboxsync * can never get YASM to produce.
b82fef5dcbe08cae8ce37a09825adc4c6b0bf762vboxsync * @returns true if it's odd, false if it isn't.
b82fef5dcbe08cae8ce37a09825adc4c6b0bf762vboxsync * @param pCpu The disassembler output. The byte fetcher callback will
b82fef5dcbe08cae8ce37a09825adc4c6b0bf762vboxsync * be used if present as we might need to fetch opcode
b82fef5dcbe08cae8ce37a09825adc4c6b0bf762vboxsyncDISDECL(bool) DISFormatYasmIsOddEncoding(PDISCPUSTATE pCpu)
b82fef5dcbe08cae8ce37a09825adc4c6b0bf762vboxsync * Mod rm + SIB: Check for duplicate EBP encodings that yasm won't use for very good reasons.
98502a585f6eda30527b54f7df18dd3de3d3d7c6vboxsync if ( pCpu->addrmode != DISCPUMODE_16BIT ///@todo correct?
b82fef5dcbe08cae8ce37a09825adc4c6b0bf762vboxsync /* No scaled index SIB (index=4), except for ESP. */
b82fef5dcbe08cae8ce37a09825adc4c6b0bf762vboxsync return true;
b82fef5dcbe08cae8ce37a09825adc4c6b0bf762vboxsync /* EBP + displacement */
b82fef5dcbe08cae8ce37a09825adc4c6b0bf762vboxsync return true;
b82fef5dcbe08cae8ce37a09825adc4c6b0bf762vboxsync * Seems to be an instruction alias here, but I cannot find any docs on it... hrmpf!
b82fef5dcbe08cae8ce37a09825adc4c6b0bf762vboxsync return true;
b82fef5dcbe08cae8ce37a09825adc4c6b0bf762vboxsync * Check for multiple prefixes of the same kind.
701efa93fe91e164d983fdc7b780b9f203381d0bvboxsync for (uint32_t offOpcode = 0; offOpcode < RT_ELEMENTS(pCpu->abInstr); offOpcode++)
b82fef5dcbe08cae8ce37a09825adc4c6b0bf762vboxsync case 0x40: case 0x41: case 0x42: case 0x43: case 0x44: case 0x45: case 0x46: case 0x47:
b82fef5dcbe08cae8ce37a09825adc4c6b0bf762vboxsync case 0x48: case 0x49: case 0x4a: case 0x4b: case 0x4c: case 0x4d: case 0x4e: case 0x4f:
98502a585f6eda30527b54f7df18dd3de3d3d7c6vboxsync f = pCpu->mode == DISCPUMODE_64BIT ? DISPREFIX_REX : 0;
b82fef5dcbe08cae8ce37a09825adc4c6b0bf762vboxsync break; /* done */
b82fef5dcbe08cae8ce37a09825adc4c6b0bf762vboxsync return true;
b82fef5dcbe08cae8ce37a09825adc4c6b0bf762vboxsync /* segment overrides are fun */
b82fef5dcbe08cae8ce37a09825adc4c6b0bf762vboxsync /* no effective address which it may apply to. */
f3701698f9d61fed78c320c3b35c64a0c63d6db1vboxsync Assert((pCpu->fPrefix & DISPREFIX_SEG) || pCpu->mode == DISCPUMODE_64BIT);
b82fef5dcbe08cae8ce37a09825adc4c6b0bf762vboxsync return true;
b82fef5dcbe08cae8ce37a09825adc4c6b0bf762vboxsync /* fixed register + addr override doesn't go down all that well. */
b82fef5dcbe08cae8ce37a09825adc4c6b0bf762vboxsync && ( pCpu->pCurInstr->param1 >= OP_PARM_REG_GEN32_START
b82fef5dcbe08cae8ce37a09825adc4c6b0bf762vboxsync && pCpu->pCurInstr->param1 <= OP_PARM_REG_GEN32_END))
b82fef5dcbe08cae8ce37a09825adc4c6b0bf762vboxsync return true;
b82fef5dcbe08cae8ce37a09825adc4c6b0bf762vboxsync /* Almost all prefixes are bad. */
b82fef5dcbe08cae8ce37a09825adc4c6b0bf762vboxsync /* nop w/ prefix(es). */
b82fef5dcbe08cae8ce37a09825adc4c6b0bf762vboxsync return true;
b82fef5dcbe08cae8ce37a09825adc4c6b0bf762vboxsync /* fall thru */
b82fef5dcbe08cae8ce37a09825adc4c6b0bf762vboxsync /** @todo branch hinting 0x2e/0x3e... */
b82fef5dcbe08cae8ce37a09825adc4c6b0bf762vboxsync return true;
b82fef5dcbe08cae8ce37a09825adc4c6b0bf762vboxsync /* All but the segment prefix is bad news. */
b82fef5dcbe08cae8ce37a09825adc4c6b0bf762vboxsync if ( pCpu->pCurInstr->param1 >= OP_PARM_REG_SEG_START
b82fef5dcbe08cae8ce37a09825adc4c6b0bf762vboxsync return true;
b82fef5dcbe08cae8ce37a09825adc4c6b0bf762vboxsync && pCpu->pCurInstr->param1 >= OP_PARM_REG_GEN32_START
b82fef5dcbe08cae8ce37a09825adc4c6b0bf762vboxsync && pCpu->pCurInstr->param1 <= OP_PARM_REG_GEN32_END)
b82fef5dcbe08cae8ce37a09825adc4c6b0bf762vboxsync return true;
b82fef5dcbe08cae8ce37a09825adc4c6b0bf762vboxsync return true;
b82fef5dcbe08cae8ce37a09825adc4c6b0bf762vboxsync /* Implicit 8-bit register instructions doesn't mix with operand size. */
b82fef5dcbe08cae8ce37a09825adc4c6b0bf762vboxsync && ( ( pCpu->pCurInstr->param1 == OP_PARM_Gb /* r8 */
b82fef5dcbe08cae8ce37a09825adc4c6b0bf762vboxsync && pCpu->pCurInstr->param2 == OP_PARM_Eb /* r8/mem8 */)
b82fef5dcbe08cae8ce37a09825adc4c6b0bf762vboxsync || ( pCpu->pCurInstr->param2 == OP_PARM_Gb /* r8 */
b82fef5dcbe08cae8ce37a09825adc4c6b0bf762vboxsync && pCpu->pCurInstr->param1 == OP_PARM_Eb /* r8/mem8 */))
b82fef5dcbe08cae8ce37a09825adc4c6b0bf762vboxsync return true;
b82fef5dcbe08cae8ce37a09825adc4c6b0bf762vboxsync * Check for the version of xyz reg,reg instruction that the assembler doesn't use.
b82fef5dcbe08cae8ce37a09825adc4c6b0bf762vboxsync * For example:
b82fef5dcbe08cae8ce37a09825adc4c6b0bf762vboxsync * expected: 1aee sbb ch, dh ; SBB r8, r/m8
b82fef5dcbe08cae8ce37a09825adc4c6b0bf762vboxsync * yasm: 18F5 sbb ch, dh ; SBB r/m8, r8
b82fef5dcbe08cae8ce37a09825adc4c6b0bf762vboxsync if ( ( pCpu->pCurInstr->param1 == OP_PARM_Gb /* r8 */
b82fef5dcbe08cae8ce37a09825adc4c6b0bf762vboxsync && pCpu->pCurInstr->param2 == OP_PARM_Eb /* r8/mem8 */)
b82fef5dcbe08cae8ce37a09825adc4c6b0bf762vboxsync || ( pCpu->pCurInstr->param1 == OP_PARM_Gv /* rX */
b82fef5dcbe08cae8ce37a09825adc4c6b0bf762vboxsync && pCpu->pCurInstr->param2 == OP_PARM_Ev /* rX/memX */))
b82fef5dcbe08cae8ce37a09825adc4c6b0bf762vboxsync return true;
b82fef5dcbe08cae8ce37a09825adc4c6b0bf762vboxsync /* 82 (see table A-6). */
b82fef5dcbe08cae8ce37a09825adc4c6b0bf762vboxsync return true;
b82fef5dcbe08cae8ce37a09825adc4c6b0bf762vboxsync /* ff /0, fe /0, ff /1, fe /0 */
b82fef5dcbe08cae8ce37a09825adc4c6b0bf762vboxsync return true;
b82fef5dcbe08cae8ce37a09825adc4c6b0bf762vboxsync return true;
76cd534a81a3b479e8a30f0f8182f5fe9c00c3aavboxsync return true;
b82fef5dcbe08cae8ce37a09825adc4c6b0bf762vboxsync /* shl eax,1 will be assembled to the form without the immediate byte. */
b82fef5dcbe08cae8ce37a09825adc4c6b0bf762vboxsync return true;
b82fef5dcbe08cae8ce37a09825adc4c6b0bf762vboxsync /* And some more - see table A-6. */
b82fef5dcbe08cae8ce37a09825adc4c6b0bf762vboxsync return true;
b82fef5dcbe08cae8ce37a09825adc4c6b0bf762vboxsync /* check for REX.X = 1 without SIB. */
b82fef5dcbe08cae8ce37a09825adc4c6b0bf762vboxsync /* Yasm encodes setnbe al with /2 instead of /0 like the AMD manual
b82fef5dcbe08cae8ce37a09825adc4c6b0bf762vboxsync says (intel doesn't appear to care). */
bfcfd0575ea3b853e34e5058debd5ad24693d607vboxsync AssertMsg(pCpu->bOpCode >= 0x90 && pCpu->bOpCode <= 0x9f, ("%#x\n", pCpu->bOpCode));
b82fef5dcbe08cae8ce37a09825adc4c6b0bf762vboxsync return true;
b82fef5dcbe08cae8ce37a09825adc4c6b0bf762vboxsync * The MOVZX reg32,mem16 instruction without an operand size prefix
b82fef5dcbe08cae8ce37a09825adc4c6b0bf762vboxsync * doesn't quite make sense...
98502a585f6eda30527b54f7df18dd3de3d3d7c6vboxsync && (pCpu->mode == DISCPUMODE_16BIT) != !!(fPrefixes & DISPREFIX_OPSIZE))
b82fef5dcbe08cae8ce37a09825adc4c6b0bf762vboxsync return true;
b82fef5dcbe08cae8ce37a09825adc4c6b0bf762vboxsync return false;