DisasmCore.cpp revision bbff18da39d20c00784b2d8d847cbfdfbf6ab7f3
/** @file
*
* VBox disassembler:
* Core components
*/
/*
* Copyright (C) 2006-2007 Sun Microsystems, Inc.
*
* This file is part of VirtualBox Open Source Edition (OSE), as
* available from http://www.virtualbox.org. This file is free software;
* General Public License (GPL) as published by the Free Software
* Foundation, in version 2 as it comes in the "COPYING" file of the
* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
*
* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
* Clara, CA 95054 USA or visit http://www.sun.com if you need
* additional information or have any questions.
*/
/*******************************************************************************
* Header Files *
*******************************************************************************/
#define LOG_GROUP LOG_GROUP_DIS
#ifdef USING_VISUAL_STUDIO
# include <stdafx.h>
#endif
#include <VBox/disopcode.h>
#include "DisasmInternal.h"
#include "DisasmTables.h"
#if !defined(DIS_CORE_ONLY) && defined(LOG_ENABLED)
# include <stdlib.h>
# include <stdio.h>
#endif
/*******************************************************************************
* Internal Functions *
*******************************************************************************/
#if !defined(DIS_CORE_ONLY) && defined(LOG_ENABLED)
#else
# ifdef _MSC_VER
# define disasmAddStringF __noop
# else
# define disasmAddStringF(psz, cbString, pszFormat...) do {} while (0) /* Arg wanna get rid of that warning */
# endif
#endif
static unsigned QueryModRM(RTUINTPTR pu8CodeBlock, PCOPCODE pOp, POP_PARAMETER pParam, PDISCPUSTATE pCpu, unsigned *pSibInc = NULL);
static unsigned QueryModRM_SizeOnly(RTUINTPTR pu8CodeBlock, PCOPCODE pOp, POP_PARAMETER pParam, PDISCPUSTATE pCpu, unsigned *pSibInc = NULL);
static unsigned ParseSIB_SizeOnly(RTUINTPTR lpszCodeBlock, PCOPCODE pOp, POP_PARAMETER pParam, PDISCPUSTATE pCpu);
/*******************************************************************************
* Global Variables *
*******************************************************************************/
{
};
{
};
/**
* Parses one instruction.
* The result is found in pCpu.
*
* @returns Success indicator.
* @param pCpu Pointer to cpu structure which has DISCPUSTATE::mode set correctly.
* @param InstructionAddr Pointer to the instruction to parse.
* @param pcbInstruction Where to store the size of the instruction.
* NULL is allowed.
*/
{
/*
* Reset instruction settings
*/
pCpu->lastprefix = 0;
pCpu->pfnReadBytes = 0;
}
/**
* Parses one guest instruction.
* The result is found in pCpu and pcbInstruction.
*
* @returns VBox status code.
* @param InstructionAddr Address of the instruction to decode. What this means
* is left to the pfnReadBytes function.
* @param enmCpuMode The CPU mode. CPUMODE_32BIT, CPUMODE_16BIT, or CPUMODE_64BIT.
* @param pfnReadBytes Callback for reading instruction bytes.
* @param pvUser User argument for the instruction reader. (Ends up in apvUserData[0].)
* @param pCpu Pointer to cpu structure. Will be initialized.
* @param pcbInstruction Where to store the size of the instruction.
* NULL is allowed.
*/
DISDECL(int) DISCoreOneEx(RTUINTPTR InstructionAddr, DISCPUMODE enmCpuMode, PFN_DIS_READBYTES pfnReadBytes, void *pvUser,
{
/*
* Reset instruction settings
*/
pCpu->lastprefix = 0;
}
/**
* Internal worker for DISCoreOne and DISCoreOneEx.
*
* @returns VBox status code.
* @param pCpu Initialized cpu state.
* @param InstructionAddr Instruction address.
* @param pcbInstruction Where to store the instruction size. Can be NULL.
*/
{
const OPCODE *paOneByteMap;
/*
* Parse byte by byte.
*/
unsigned iByte = 0;
unsigned cbInc;
{
}
else
{
}
#ifdef IN_RING3
# ifndef __L4ENV__ /* Unfortunately, we have no exception handling in l4env */
try
# else
if (setjmp(jumpbuffer) == 0)
# endif
#endif
{
while(1)
{
/* Hardcoded assumption about OP_* values!! */
if (opcode <= OP_LAST_PREFIX)
{
/* The REX prefix must precede the opcode byte(s). Any other placement is ignored. */
{
/** Last prefix byte (for SSE2 extension tables); don't include the REX prefix */
}
switch (opcode)
{
case OP_INVALID:
AssertMsgFailed(("Invalid opcode!!\n"));
return VERR_GENERAL_FAILURE; /** @todo better error code. */
// segment override prefix byte
case OP_SEG:
/* Segment prefixes for CS, DS, ES and SS are ignored in long mode. */
{
}
continue; //fetch the next byte
// lock prefix byte
case OP_LOCK:
continue; //fetch the next byte
// address size override prefix byte
case OP_ADDRSIZE:
else
else
continue; //fetch the next byte
// operand size override prefix byte
case OP_OPSIZE:
else
pCpu->opmode = CPUMODE_16BIT; /* for 32 and 64 bits mode (there is no 32 bits operand size override prefix) */
continue; //fetch the next byte
// rep and repne are not really prefixes, but we'll treat them as such
case OP_REPE:
continue; //fetch the next byte
case OP_REPNE:
continue; //fetch the next byte
case OP_REX:
/* REX prefix byte */
continue; //fetch the next byte
}
}
break;
}
}
#ifdef IN_RING3
# ifndef __L4ENV__
catch(...)
# else
else /* setjmp has returned a non-zero value: an exception occured */
# endif
{
return VERR_DIS_GEN_FAILURE;
}
#endif
if (pcbInstruction)
*pcbInstruction = iByte;
return VINF_SUCCESS;
}
//*****************************************************************************
//*****************************************************************************
{
int size = 0;
bool fFiltered = false;
// Store the opcode format string for disasmPrintf
#ifndef DIS_CORE_ONLY
#endif
/*
* Apply filter to instruction type to determine if a full disassembly is required.
* @note Multibyte opcodes are always marked harmless until the final byte.
*/
{
fFiltered = true;
}
else
{
/* Not filtered out -> full disassembly */
}
// Should contain the parameter type on input
/* Correct the operand size if the instruction is marked as forced or default 64 bits */
{
else
}
{
}
{
}
{
}
// else simple one byte instruction
return size;
}
//*****************************************************************************
/* Floating point opcode parsing */
//*****************************************************************************
{
int index;
if (ModRM <= 0xBF)
{
// Should contain the parameter type on input
}
else
{
}
/*
* Apply filter to instruction type to determine if a full disassembly is required.
* @note Multibyte opcodes are always marked harmless until the final byte.
*/
{
}
else
{
/* Not filtered out -> full disassembly */
}
/* Correct the operand size if the instruction is marked as forced or default 64 bits */
{
/* Note: redundant, but just in case this ever changes */
else
}
// Little hack to make sure the ModRM byte is included in the returned size
// Store the opcode format string for disasmPrintf
#ifndef DIS_CORE_ONLY
#endif
return size;
}
//*****************************************************************************
// SIB byte: (32 bits mode only)
// 7 - 6 5 - 3 2-0
// Scale Index Base
//*****************************************************************************
static const char *szSIBBaseReg64[16] = {"RAX", "RCX", "RDX", "RBX", "RSP", "RBP", "RSI", "RDI", "R8", "R9", "R10", "R11", "R12", "R13", "R14", "R15"};
static const char *szSIBIndexReg64[16]= {"RAX", "RCX", "RDX", "RBX", NULL, "RBP", "RSI", "RDI", "R8", "R9", "R10", "R11", "R12", "R13", "R14", "R15"};
//*****************************************************************************
{
const char **ppszSIBIndexReg;
const char **ppszSIBBaseReg;
char szTemp[32];
szTemp[0] = '\0';
{
}
else
{
}
if (ppszSIBIndexReg[index])
{
if (scale != 0)
{
}
else
disasmAddStringF(szTemp, sizeof(szTemp), "%s+%s%s", ppszSIBBaseReg[base], ppszSIBIndexReg[index], szSIBScale[scale]);
}
else
{
}
{
// [scaled index] + disp32
{
}
else
{ /* sign-extend to 64 bits */
}
}
else
{
}
return; /* Already fetched everything in ParseSIB; no size returned */
}
//*****************************************************************************
//*****************************************************************************
{
unsigned SIB;
lpszCodeBlock += size;
{
/* REX.B extends the Base field if not scaled index + disp32 */
}
{
/* Additional 32 bits displacement. No change in long mode. */
}
return size;
}
//*****************************************************************************
//*****************************************************************************
unsigned ParseSIB_SizeOnly(RTUINTPTR lpszCodeBlock, PCOPCODE pOp, POP_PARAMETER pParam, PDISCPUSTATE pCpu)
{
unsigned SIB;
lpszCodeBlock += size;
{
/* REX.B extends the Base field. */
/* REX.X extends the Index field. */
}
{
/* Additional 32 bits displacement. No change in long mode. */
}
return size;
}
//*****************************************************************************
// ModR/M byte:
// 7 - 6 5 - 3 2-0
//*****************************************************************************
{
switch (vtype)
{
case OP_PARM_G: //general purpose register
return 0;
default:
if (IS_OP_PARM_RARE(vtype))
{
switch (vtype)
{
case OP_PARM_C: //control register
return 0;
case OP_PARM_D: //debug register
return 0;
case OP_PARM_P: //MMX register
return 0;
case OP_PARM_S: //segment register
return 0;
case OP_PARM_T: //test register
return 0;
case OP_PARM_W: //XMM register or memory operand
if (mod != 3)
break; /* memory operand */
/* else no break */
case OP_PARM_V: //XMM register
return 0;
}
}
}
/* @todo bound */
{
/*
* Note: displacements in long mode are 8 or 32 bits and sign-extended to 64 bits
*/
switch (mod)
{
case 0: //effective address
if (rm == 4)
{ /* SIB byte follows ModRM */
}
else
if (rm == 5)
{
/* 32 bits displacement */
{
}
else
{
}
}
else {//register address
}
break;
case 1: //effective address + 8 bits displacement
}
else
{
}
{
}
break;
case 2: //effective address + 32 bits displacement
}
else
{
}
{
}
break;
case 3: //registers
break;
}
}
else
{//16 bits addressing mode
switch (mod)
{
case 0: //effective address
if (rm == 6)
{//16 bits displacement
}
else
{
}
break;
case 1: //effective address + 8 bits displacement
{
}
break;
case 2: //effective address + 16 bits displacement
{
}
break;
case 3: //registers
break;
}
}
return 0; //everything was already fetched in ParseModRM
}
//*****************************************************************************
// Query the size of the ModRM parameters and fetch the immediate data (if any)
//*****************************************************************************
unsigned QueryModRM(RTUINTPTR lpszCodeBlock, PCOPCODE pOp, POP_PARAMETER pParam, PDISCPUSTATE pCpu, unsigned *pSibInc)
{
unsigned sibinc;
unsigned size = 0;
// unsigned reg = pCpu->ModRM.Bits.Reg;
if (!pSibInc)
*pSibInc = 0;
{
/*
* Note: displacements in long mode are 8 or 32 bits and sign-extended to 64 bits
*/
{ /* SIB byte follows ModRM */
lpszCodeBlock += *pSibInc;
}
switch (mod)
{
case 0: /* Effective address */
}
/* else register address */
break;
case 1: /* Effective address + 8 bits displacement */
size += sizeof(char);
break;
case 2: /* Effective address + 32 bits displacement */
break;
case 3: /* registers */
break;
}
}
else
{
/* 16 bits mode */
switch (mod)
{
case 0: /* Effective address */
if (rm == 6) {
}
/* else register address */
break;
case 1: /* Effective address + 8 bits displacement */
size += sizeof(char);
break;
case 2: /* Effective address + 32 bits displacement */
break;
case 3: /* registers */
break;
}
}
return size;
}
//*****************************************************************************
// Query the size of the ModRM parameters and fetch the immediate data (if any)
//*****************************************************************************
unsigned QueryModRM_SizeOnly(RTUINTPTR lpszCodeBlock, PCOPCODE pOp, POP_PARAMETER pParam, PDISCPUSTATE pCpu, unsigned *pSibInc)
{
unsigned sibinc;
unsigned size = 0;
// unsigned reg = pCpu->ModRM.Bits.Reg;
if (!pSibInc)
*pSibInc = 0;
{
/*
* Note: displacements in long mode are 8 or 32 bits and sign-extended to 64 bits
*/
{ /* SIB byte follows ModRM */
lpszCodeBlock += *pSibInc;
}
switch (mod)
{
case 0: //effective address
}
/* else register address */
break;
case 1: /* Effective address + 8 bits displacement */
size += sizeof(char);
break;
case 2: /* Effective address + 32 bits displacement */
break;
case 3: /* registers */
break;
}
}
else
{
/* 16 bits mode */
switch (mod)
{
case 0: //effective address
if (rm == 6) {
}
/* else register address */
break;
case 1: /* Effective address + 8 bits displacement */
size += sizeof(char);
break;
case 2: /* Effective address + 32 bits displacement */
break;
case 3: /* registers */
break;
}
}
return size;
}
//*****************************************************************************
//*****************************************************************************
unsigned ParseIllegal(RTUINTPTR lpszCodeBlock, PCOPCODE pOp, POP_PARAMETER pParam, PDISCPUSTATE pCpu)
{
AssertFailed();
return 0;
}
//*****************************************************************************
//*****************************************************************************
{
lpszCodeBlock += sizeof(uint8_t);
{
/* REX.R extends the Reg field. */
/* REX.B extends the Rm field if there is no SIB byte nor a 32 bits displacement */
&&
{
}
}
lpszCodeBlock += sibinc;
return size;
}
//*****************************************************************************
//*****************************************************************************
unsigned ParseModRM_SizeOnly(RTUINTPTR lpszCodeBlock, PCOPCODE pOp, POP_PARAMETER pParam, PDISCPUSTATE pCpu)
{
lpszCodeBlock += sizeof(uint8_t);
{
/* REX.R extends the Reg field. */
/* REX.B extends the Rm field if there is no SIB byte nor a 32 bits displacement */
&&
{
}
}
lpszCodeBlock += sibinc;
/* UseModRM is not necessary here; we're only interested in the opcode size */
return size;
}
//*****************************************************************************
//*****************************************************************************
unsigned ParseModFence(RTUINTPTR lpszCodeBlock, PCOPCODE pOp, POP_PARAMETER pParam, PDISCPUSTATE pCpu)
{
////AssertMsgFailed(("??\n"));
//nothing to do apparently
return 0;
}
//*****************************************************************************
//*****************************************************************************
unsigned ParseImmByte(RTUINTPTR lpszCodeBlock, PCOPCODE pOp, POP_PARAMETER pParam, PDISCPUSTATE pCpu)
{
return sizeof(uint8_t);
}
//*****************************************************************************
//*****************************************************************************
unsigned ParseImmByte_SizeOnly(RTUINTPTR lpszCodeBlock, PCOPCODE pOp, POP_PARAMETER pParam, PDISCPUSTATE pCpu)
{
return sizeof(uint8_t);
}
//*****************************************************************************
//*****************************************************************************
unsigned ParseImmByteSX(RTUINTPTR lpszCodeBlock, PCOPCODE pOp, POP_PARAMETER pParam, PDISCPUSTATE pCpu)
{
if (pCpu->opmode == CPUMODE_32BIT) /** @todo In AMD64 mode we're ending up with 16-bit parvals now, see the disassembler _output_ for tstAsmSignExtend-1.asm. */
{
}
else
{
}
return sizeof(uint8_t);
}
//*****************************************************************************
//*****************************************************************************
unsigned ParseImmByteSX_SizeOnly(RTUINTPTR lpszCodeBlock, PCOPCODE pOp, POP_PARAMETER pParam, PDISCPUSTATE pCpu)
{
return sizeof(uint8_t);
}
//*****************************************************************************
//*****************************************************************************
unsigned ParseImmUshort(RTUINTPTR lpszCodeBlock, PCOPCODE pOp, POP_PARAMETER pParam, PDISCPUSTATE pCpu)
{
return sizeof(uint16_t);
}
//*****************************************************************************
//*****************************************************************************
unsigned ParseImmUshort_SizeOnly(RTUINTPTR lpszCodeBlock, PCOPCODE pOp, POP_PARAMETER pParam, PDISCPUSTATE pCpu)
{
return sizeof(uint16_t);
}
//*****************************************************************************
//*****************************************************************************
unsigned ParseImmUlong(RTUINTPTR lpszCodeBlock, PCOPCODE pOp, POP_PARAMETER pParam, PDISCPUSTATE pCpu)
{
return sizeof(uint32_t);
}
//*****************************************************************************
//*****************************************************************************
unsigned ParseImmUlong_SizeOnly(RTUINTPTR lpszCodeBlock, PCOPCODE pOp, POP_PARAMETER pParam, PDISCPUSTATE pCpu)
{
return sizeof(uint32_t);
}
//*****************************************************************************
//*****************************************************************************
unsigned ParseImmQword(RTUINTPTR lpszCodeBlock, PCOPCODE pOp, POP_PARAMETER pParam, PDISCPUSTATE pCpu)
{
disasmAddStringF(&pParam->szParam[9], sizeof(pParam->szParam)-9, "%08Xh", (uint32_t)(pParam->parval >> 32));
return sizeof(uint64_t);
}
//*****************************************************************************
//*****************************************************************************
unsigned ParseImmQword_SizeOnly(RTUINTPTR lpszCodeBlock, PCOPCODE pOp, POP_PARAMETER pParam, PDISCPUSTATE pCpu)
{
return sizeof(uint64_t);
}
//*****************************************************************************
//*****************************************************************************
{
{
return sizeof(uint32_t);
}
else
{
return sizeof(uint64_t);
}
else
{
return sizeof(uint16_t);
}
}
//*****************************************************************************
//*****************************************************************************
unsigned ParseImmV_SizeOnly(RTUINTPTR lpszCodeBlock, PCOPCODE pOp, POP_PARAMETER pParam, PDISCPUSTATE pCpu)
{
return sizeof(uint32_t);
else
return sizeof(uint64_t);
return sizeof(uint16_t);
}
//*****************************************************************************
//*****************************************************************************
{
/* Word for 16-bit operand-size or doubleword for 32 or 64-bit operand-size. */
{
return sizeof(uint16_t);
}
else
{
return sizeof(uint32_t);
}
}
//*****************************************************************************
//*****************************************************************************
unsigned ParseImmZ_SizeOnly(RTUINTPTR lpszCodeBlock, PCOPCODE pOp, POP_PARAMETER pParam, PDISCPUSTATE pCpu)
{
/* Word for 16-bit operand-size or doubleword for 32 or 64-bit operand-size. */
return sizeof(uint16_t);
return sizeof(uint32_t);
}
//*****************************************************************************
// Relative displacement for branches (rel. to next instruction)
//*****************************************************************************
unsigned ParseImmBRel(RTUINTPTR lpszCodeBlock, PCOPCODE pOp, POP_PARAMETER pParam, PDISCPUSTATE pCpu)
{
return sizeof(char);
}
//*****************************************************************************
// Relative displacement for branches (rel. to next instruction)
//*****************************************************************************
unsigned ParseImmBRel_SizeOnly(RTUINTPTR lpszCodeBlock, PCOPCODE pOp, POP_PARAMETER pParam, PDISCPUSTATE pCpu)
{
return sizeof(char);
}
//*****************************************************************************
// Relative displacement for branches (rel. to next instruction)
//*****************************************************************************
unsigned ParseImmVRel(RTUINTPTR lpszCodeBlock, PCOPCODE pOp, POP_PARAMETER pParam, PDISCPUSTATE pCpu)
{
{
return sizeof(int32_t);
}
else
{
return sizeof(int64_t);
}
else
{
return sizeof(uint16_t);
}
}
//*****************************************************************************
// Relative displacement for branches (rel. to next instruction)
//*****************************************************************************
unsigned ParseImmVRel_SizeOnly(RTUINTPTR lpszCodeBlock, PCOPCODE pOp, POP_PARAMETER pParam, PDISCPUSTATE pCpu)
{
return sizeof(int32_t);
else
return sizeof(int64_t);
return sizeof(uint16_t);
}
//*****************************************************************************
//*****************************************************************************
unsigned ParseImmAddr(RTUINTPTR lpszCodeBlock, PCOPCODE pOp, POP_PARAMETER pParam, PDISCPUSTATE pCpu)
{
{
{// far 16:32 pointer
disasmAddStringF(pParam->szParam, sizeof(pParam->szParam), "0%04X:0%08Xh", (uint32_t)(pParam->parval>>32), (uint32_t)pParam->parval);
}
else
{// near 32 bits pointer
/*
* Note: used only in "mov al|ax|eax, [Addr]" and "mov [Addr], al|ax|eax"
* so we treat it like displacement.
*/
return sizeof(uint32_t);
}
}
else
{
/* near 64 bits pointer */
/*
* Note: used only in "mov al|ax|eax, [Addr]" and "mov [Addr], al|ax|eax"
* so we treat it like displacement.
*/
disasmAddStringF(pParam->szParam, sizeof(pParam->szParam), "[0%08X%08Xh]", (uint32_t)(pParam->disp64 >> 32), (uint32_t)pParam->disp64);
return sizeof(uint64_t);
}
else
{
{// far 16:16 pointer
disasmAddStringF(pParam->szParam, sizeof(pParam->szParam), "0%04X:0%04Xh", (uint32_t)(pParam->parval>>16), (uint16_t)pParam->parval );
return sizeof(uint32_t);
}
else
{// near 16 bits pointer
/*
* Note: used only in "mov al|ax|eax, [Addr]" and "mov [Addr], al|ax|eax"
* so we treat it like displacement.
*/
return sizeof(uint16_t);
}
}
}
//*****************************************************************************
//*****************************************************************************
unsigned ParseImmAddr_SizeOnly(RTUINTPTR lpszCodeBlock, PCOPCODE pOp, POP_PARAMETER pParam, PDISCPUSTATE pCpu)
{
{
{// far 16:32 pointer
}
else
{// near 32 bits pointer
return sizeof(uint32_t);
}
}
{
return sizeof(uint64_t);
}
else
{
{// far 16:16 pointer
return sizeof(uint32_t);
}
else
{// near 16 bits pointer
return sizeof(uint16_t);
}
}
}
//*****************************************************************************
//*****************************************************************************
unsigned ParseFixedReg(RTUINTPTR lpszCodeBlock, PCOPCODE pOp, POP_PARAMETER pParam, PDISCPUSTATE pCpu)
{
/*
* Sets up flags for stored in OPC fixed registers.
*/
{
/* No parameter at all. */
return 0;
}
{
/* 32-bit EAX..EDI registers. */
{
/* Use 32-bit registers. */
}
else
{
/* Use 64-bit registers. */
}
else
{
/* Use 16-bit registers. */
}
}
else
{
/* Segment ES..GS registers. */
}
else
{
/* 16-bit AX..DI registers. */
}
else
{
/* 8-bit AL..DL, AH..DH registers. */
{
}
}
else
{
/* FPU registers. */
}
/* else - not supported for now registers. */
return 0;
}
//*****************************************************************************
//*****************************************************************************
{
disasmAddStringF(pParam->szParam, sizeof(pParam->szParam), (pCpu->addrmode == CPUMODE_32BIT) ? "DS:ESI" : "DS:SI");
{
}
else
{
}
else
{
}
return 0; //no additional opcode bytes
}
//*****************************************************************************
//*****************************************************************************
{
disasmAddStringF(pParam->szParam, sizeof(pParam->szParam), (pCpu->addrmode == CPUMODE_32BIT) ? "DS:ESI" : "DS:SI");
{
}
else
{
}
else
{
}
return 0; //no additional opcode bytes
}
//*****************************************************************************
//*****************************************************************************
{
disasmAddStringF(pParam->szParam, sizeof(pParam->szParam), (pCpu->addrmode == CPUMODE_32BIT) ? "ES:EDI" : "ES:DI");
{
}
else
{
}
else
{
}
return 0; //no additional opcode bytes
}
//*****************************************************************************
//*****************************************************************************
{
disasmAddStringF(pParam->szParam, sizeof(pParam->szParam), (pCpu->addrmode == CPUMODE_32BIT) ? "ES:EDI" : "ES:DI");
{
}
else
{
}
else
{
}
return 0; //no additional opcode bytes
}
//*****************************************************************************
//*****************************************************************************
unsigned ParseTwoByteEsc(RTUINTPTR lpszCodeBlock, PCOPCODE pOp, POP_PARAMETER pParam, PDISCPUSTATE pCpu)
{
//2nd byte
/* Handle opcode table extensions that rely on the address, repe or repne prefix byte. */
/** @todo Should we take the first or last prefix byte in case of multiple prefix bytes??? */
if (pCpu->lastprefix)
{
switch (pCpu->lastprefix)
{
case OP_OPSIZE: /* 0x66 */
{
/* Table entry is valid, so use the extension table. */
/* Cancel prefix changes. */
}
break;
case OP_REPNE: /* 0xF2 */
{
/* Table entry is valid, so use the extension table. */
/* Cancel prefix changes. */
}
break;
case OP_REPE: /* 0xF3 */
{
/* Table entry is valid, so use the extension table. */
/* Cancel prefix changes. */
}
break;
}
}
return size;
}
//*****************************************************************************
//*****************************************************************************
unsigned ParseNopPause(RTUINTPTR pu8CodeBlock, PCOPCODE pOp, POP_PARAMETER pParam, PDISCPUSTATE pCpu)
{
unsigned size = 0;
{
}
else
return size;
}
//*****************************************************************************
//*****************************************************************************
unsigned ParseImmGrpl(RTUINTPTR lpszCodeBlock, PCOPCODE pOp, POP_PARAMETER pParam, PDISCPUSTATE pCpu)
{
//little hack to make sure the ModRM byte is included in the returned size
return size;
}
//*****************************************************************************
//*****************************************************************************
unsigned ParseShiftGrp2(RTUINTPTR lpszCodeBlock, PCOPCODE pOp, POP_PARAMETER pParam, PDISCPUSTATE pCpu)
{
int idx;
{
case 0xC0:
case 0xC1:
break;
case 0xD0:
case 0xD1:
case 0xD2:
case 0xD3:
break;
default:
AssertMsgFailed(("Oops\n"));
return sizeof(uint8_t);
}
//little hack to make sure the ModRM byte is included in the returned size
return size;
}
//*****************************************************************************
//*****************************************************************************
{
//little hack to make sure the ModRM byte is included in the returned size
return size;
}
//*****************************************************************************
//*****************************************************************************
{
//little hack to make sure the ModRM byte is included in the returned size
return size;
}
//*****************************************************************************
//*****************************************************************************
{
//little hack to make sure the ModRM byte is included in the returned size
return size;
}
//*****************************************************************************
// 0xF 0xF [ModRM] [SIB] [displacement] imm8_opcode
// It would appear the ModRM byte must always be present. How else can you
// determine the offset of the imm8_opcode byte otherwise?
//
//*****************************************************************************
{
#ifdef DEBUG_Sander
//needs testing
AssertMsgFailed(("Test me\n"));
#endif
//little hack to make sure the ModRM byte is included in the returned size
{
#ifdef DEBUG_Sander /* bird, 2005-06-28: Alex is getting this during full installation of win2ksp4. */
#endif
}
return size;
}
//*****************************************************************************
//*****************************************************************************
{
//little hack to make sure the ModRM byte is included in the returned size
return size;
}
//*****************************************************************************
//*****************************************************************************
{
else
else
//little hack to make sure the ModRM byte is included in the returned size
return size;
}
//*****************************************************************************
//*****************************************************************************
{
//little hack to make sure the ModRM byte is included in the returned size
return size;
}
//*****************************************************************************
//*****************************************************************************
{
//little hack to make sure the ModRM byte is included in the returned size
return size;
}
//*****************************************************************************
//*****************************************************************************
{
//little hack to make sure the ModRM byte is included in the returned size
return size;
}
//*****************************************************************************
//*****************************************************************************
{
//little hack to make sure the ModRM byte is included in the returned size
return size;
}
//*****************************************************************************
//*****************************************************************************
{
//little hack to make sure the ModRM byte is included in the returned size
return size;
}
//*****************************************************************************
//*****************************************************************************
{
//little hack to make sure the ModRM byte is included in the returned size
return size;
}
//*****************************************************************************
//*****************************************************************************
{
else
//little hack to make sure the ModRM byte is included in the returned size
return size;
}
//*****************************************************************************
//*****************************************************************************
{
//little hack to make sure the ModRM byte is included in the returned size
return size;
}
//*****************************************************************************
#if !defined(DIS_CORE_ONLY) && defined(LOG_ENABLED)
static const char *szModRMReg8_64[] = {"AL", "CL", "DL", "BL", "AH", "CH", "DH", "BH", "R8L", "R9L", "R10L", "R11L", "R12L", "R13L", "R14L", "R15L"};
static const char *szModRMReg64[] = {"RAX", "RCX", "RDX", "RBX", "RSP", "RBP", "RSI", "RDI", "R8", "R9", "R10", "R11", "R12", "R13", "R14", "R15"};
static const char *szModRMReg1616[8] = {"BX+SI", "BX+DI", "BP+SI", "BP+DI", "SI", "DI", "BP", "BX"};
#endif
static const int BaseModRMReg16[8] = { USE_REG_BX, USE_REG_BX, USE_REG_BP, USE_REG_BP, USE_REG_SI, USE_REG_DI, USE_REG_BP, USE_REG_BX};
//*****************************************************************************
void disasmModRMReg(PDISCPUSTATE pCpu, PCOPCODE pOp, unsigned idx, POP_PARAMETER pParam, int fRegAddr)
{
if (fRegAddr)
else
{
{
case CPUMODE_32BIT:
break;
case CPUMODE_64BIT:
break;
case CPUMODE_16BIT:
break;
default:
/* make gcc happy */
break;
}
}
switch (subtype)
{
case OP_PARM_b:
#if !defined(DIS_CORE_ONLY) && defined(LOG_ENABLED)
else
#endif
break;
case OP_PARM_w:
break;
case OP_PARM_d:
break;
case OP_PARM_q:
break;
default:
#ifdef IN_RING3
#else
AssertMsgFailed(("Oops!\n"));
#endif
break;
}
}
//*****************************************************************************
//*****************************************************************************
{
if (idx < 4)
{
}
}
//*****************************************************************************
//*****************************************************************************
{
#if 0 //def DEBUG_Sander
#endif
#ifdef IN_RING3
{
}
#endif
}
//*****************************************************************************
//*****************************************************************************
{
}
//*****************************************************************************
//*****************************************************************************
{
}
//*****************************************************************************
//*****************************************************************************
{
}
//*****************************************************************************
//*****************************************************************************
{
}
//*****************************************************************************
//*****************************************************************************
{
}
//*****************************************************************************
//*****************************************************************************
{
{
{
case CPUMODE_32BIT:
break;
case CPUMODE_64BIT:
break;
case CPUMODE_16BIT:
break;
default:
/* make gcc happy */
break;
}
}
switch (subtype)
{
case OP_PARM_a: //two words or dwords depending on operand size (bound only)
break;
case OP_PARM_b:
break;
case OP_PARM_w:
break;
case OP_PARM_d:
break;
case OP_PARM_q:
case OP_PARM_dq:
break;
case OP_PARM_p:
break;
case OP_PARM_s:
break; //??
case OP_PARM_z:
break;
default:
}
disasmAddStringF(pParam->szParam, sizeof(pParam->szParam), "%s:", szModRMSegReg[pCpu->enmPrefixSeg]);
}
#ifndef IN_GC
//*****************************************************************************
/* Read functions for getting the opcode bytes */
//*****************************************************************************
{
if (pCpu->pfnReadBytes)
{
int rc;
if (VBOX_FAILURE(rc))
{
Log(("DISReadByte failed!!\n"));
}
return temp;
}
#ifdef IN_RING0
AssertMsgFailed(("DISReadByte with no read callback in ring 0!!\n"));
return 0;
#else
#endif
}
//*****************************************************************************
//*****************************************************************************
{
if (pCpu->pfnReadBytes)
{
int rc;
if (VBOX_FAILURE(rc))
{
Log(("DISReadWord failed!!\n"));
}
return temp;
}
#ifdef IN_RING0
AssertMsgFailed(("DISReadWord with no read callback in ring 0!!\n"));
return 0;
#else
#endif
}
//*****************************************************************************
//*****************************************************************************
{
if (pCpu->pfnReadBytes)
{
int rc;
if (VBOX_FAILURE(rc))
{
Log(("DISReadDWord failed!!\n"));
}
return temp;
}
#ifdef IN_RING0
AssertMsgFailed(("DISReadDWord with no read callback in ring 0!!\n"));
return 0;
#else
#endif
}
//*****************************************************************************
//*****************************************************************************
{
if (pCpu->pfnReadBytes)
{
int rc;
if (VBOX_FAILURE(rc))
{
}
return temp;
}
#ifdef IN_RING0
AssertMsgFailed(("DISReadQWord with no read callback in ring 0!!\n"));
return 0;
#else
#endif
}
#endif /* IN_GC */
#if !defined(DIS_CORE_ONLY) && defined(LOG_ENABLED)
//*****************************************************************************
//*****************************************************************************
{
}
//*****************************************************************************
//*****************************************************************************
{
}
//*****************************************************************************
//*****************************************************************************
{
char sz[2];
}
#endif /* !DIS_CORE_ONLY */
/**
* Validates the lock sequence.
*
* The AMD manual lists the following instructions:
* ADC
* ADD
* AND
* BTC
* BTR
* BTS
* CMPXCHG
* CMPXCHG8B
* CMPXCHG16B
* DEC
* INC
* NEG
* NOT
* OR
* SBB
* SUB
* XADD
* XCHG
* XOR
*
* @param pCpu Fully dissassembled instruction.
*/
{
/*
* Filter out the valid lock sequences.
*/
{
/* simple: no variations */
case OP_CMPXCHG8B: /* == OP_CMPXCHG16B? */
return;
/* simple: /r - reject register destination. */
case OP_BTC:
case OP_BTR:
case OP_BTS:
case OP_CMPXCHG:
case OP_XADD:
break;
return;
/*
* Lots of variants but its sufficient to check that param 1
* is a memory operand.
*/
case OP_ADC:
case OP_ADD:
case OP_AND:
case OP_DEC:
case OP_INC:
case OP_NEG:
case OP_NOT:
case OP_OR:
case OP_SBB:
case OP_SUB:
case OP_XCHG:
case OP_XOR:
if (pCpu->param1.flags & (USE_BASE | USE_INDEX | USE_DISPLACEMENT32 | USE_DISPLACEMENT16 | USE_DISPLACEMENT8 | USE_RIPDISPLACEMENT32))
return;
break;
default:
break;
}
/*
* Invalid lock sequence, make it a OP_ILLUD2.
*/
}