tstOhciRegisterAccess.cpp revision c7a877c301dd99550c6d2e59bd4483c02bb08959
/* $Id$ */
/** @file
* tstOhciRegisterAccess - OHCI Register Access Tests / Experiments.
*/
/*
* Copyright (C) 2011 Oracle Corporation
*
* This file is part of VirtualBox Open Source Edition (OSE), as
* available from http://www.virtualbox.org. This file is free software;
* General Public License (GPL) as published by the Free Software
* Foundation, in version 2 as it comes in the "COPYING" file of the
* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
*/
/*******************************************************************************
* Header Files *
*******************************************************************************/
#include <iprt/asm-amd64-x86.h>
#define LogRel(a) SUPR0Printf a
/*******************************************************************************
* Global Variables *
*******************************************************************************/
/** Register names. */
static const char * const g_apszRegNms[] =
{
"HcRevision",
"HcControl",
"HcCommandStatus",
"HcInterruptStatus",
"HcInterruptEnable",
"HcInterruptDisable",
"HcHCCA",
"HcPeriodCurrentED",
"HcControlHeadED",
"HcControlCurrentED",
"HcBulkHeadED",
"HcBulkCurrentED",
"HcDoneHead",
"HcFmInterval",
"HcFmRemaining",
"HcFmNumber",
"HcPeriodicStart",
"HcLSThreshold",
"HcRhDescriptorA",
"HcRhDescriptorB",
"HcRhStatus",
/* Variable number of root hub ports: */
"HcRhPortStatus[0]",
"HcRhPortStatus[1]",
"HcRhPortStatus[2]",
"HcRhPortStatus[3]",
"HcRhPortStatus[4]",
"HcRhPortStatus[5]",
"HcRhPortStatus[6]",
"HcRhPortStatus[7]"
};
{
static struct
{
unsigned iReg;
} const s_aRegs[] =
{
{ 13 /* HcFmInterval */, 0x58871120, 0 }
};
bool fSuccess = true;
for (unsigned i = 0; i < RT_ELEMENTS(s_aRegs); i++)
{
LogRel(("TestOhciWrites: %p iReg=%2d %20s = %08RX32\n", uPtrReg.pv, iReg, g_apszRegNms[iReg], uInitialValue));
bool fDone = true;
/*
* DWORD writes.
*/
uint32_t const uChangedValue = s_aRegs[i].uVal1 != uInitialValue ? s_aRegs[i].uVal1 : s_aRegs[i].uVal2;
if (u32A == uInitialValue)
{
/* Change the value. */
if (u32A != uChangedValue)
pszError = "Writing changed value failed";
else
{
if (u32A != uInitialValue)
pszError = "Restore error 1";
}
}
else
pszError = "Writing back initial value failed";
/*
* Write byte changes.
*/
{
/* Change the value. */
{
}
else
{
if (u32A != uInitialValue)
pszError = "Restore error 2";
}
}
ASMNopPause();
/*
* Complain on failure.
*/
if (!fDone)
LogRel(("TestOhciWrites: Warning! Register %s was never stable enough for testing! %08RX32 %08RX32 %08RX32\n",
else if (pszError)
{
LogRel(("TestOhciWrites: Error! Register %s failed: %s; uInitialValue=%08RX32 uChangedValue=%08RX32 u32A=%08RX32\n",
fSuccess = false;
}
}
return fSuccess;
}
{
/*
* We can read just about any register we like since read shouldn't have
* any side effects. However, some registers are volatile and makes for
* difficult targets, thus the ugly code.
*/
bool fSuccess = true;
{
bool fDone = false;
LogRel(("TestOhciReads: %p iReg=%2d %20s = %08RX32\n", uPtr.pv, iReg, g_apszRegNms[iReg], uInitialValue));
{
fDone = true;
/* Test byte access. */
{
{
fDone = false;
break;
}
static uint32_t const a_au32Masks[] =
{
};
if (u32B != uInitialValue)
{
break;
}
}
/* Test aligned word access. */
if (fDone)
{
{
{
fDone = false;
break;
}
if (u32B != uInitialValue)
{
break;
}
}
}
/* Test unaligned word access. */
if (fDone)
{
{
{
fDone = false;
break;
}
switch (iWord)
{
}
{
static const char * const s_apsz[] = { "unaligned word 0", "unaligned word 1", "unaligned word 2" };
break;
}
}
}
/* Test unaligned dword access. */
if (fDone)
{
{
{
fDone = false;
break;
}
switch (iByte)
{
case 0: break;
}
{
static const char * const s_apsz[] =
{
"unaligned dword -3", "unaligned dword -2", "unaligned dword -1",
"unaligned dword 0", "unaligned dword 1", "unaligned dword 2", "unaligned dword 3"
};
break;
}
}
}
ASMNopPause();
} /* try loop */
/*
* Complain on failure.
*/
if (!fDone)
LogRel(("TestOhciReads: Warning! Register %s was never stable enough for testing! %08RX32 %08RX32 %08RX32\n",
else if (pszError)
{
LogRel(("TestOhciReads: Error! Register %s failed: %s; uInitialValue=%08RX32 u32B=%08RX32\n",
fSuccess = false;
}
}
return fSuccess;
}
{
/*
* Map the OHCI registers so we can access them.
*/
if (RT_FAILURE(rc))
{
return rc;
}
rc = RTR0MemObjMapKernel(&hMapObj, hMemObj, (void *)-1, 0 /*uAlignment*/, RTMEM_PROT_READ | RTMEM_PROT_WRITE);
if (RT_SUCCESS(rc))
{
{
/*
* Do the access tests.
*/
if (fSuccess)
if (fSuccess)
LogRel(("tstOhciRegisterAccess: Success!\n"));
else
LogRel(("tstOhciRegisterAccess: Failed!\n"));
}
else
/*
* Clean up.
*/
RTR0MemObjFree(hMapObj, false);
}
else
RTR0MemObjFree(hMemObj, false);
return rc;
}