tstOhciRegisterAccess.cpp revision 9fe2ed45aab3bcb2867113b7c9fb60ca7e99ac0b
cde46304e0c614aad7fd63abacb0180e4e83f24cvboxsync * tstOhciRegisterAccess - OHCI Register Access Tests / Experiments.
cde46304e0c614aad7fd63abacb0180e4e83f24cvboxsync * Copyright (C) 2011 Oracle Corporation
cde46304e0c614aad7fd63abacb0180e4e83f24cvboxsync * This file is part of VirtualBox Open Source Edition (OSE), as
cde46304e0c614aad7fd63abacb0180e4e83f24cvboxsync * available from http://www.virtualbox.org. This file is free software;
cde46304e0c614aad7fd63abacb0180e4e83f24cvboxsync * you can redistribute it and/or modify it under the terms of the GNU
cde46304e0c614aad7fd63abacb0180e4e83f24cvboxsync * General Public License (GPL) as published by the Free Software
cde46304e0c614aad7fd63abacb0180e4e83f24cvboxsync * Foundation, in version 2 as it comes in the "COPYING" file of the
cde46304e0c614aad7fd63abacb0180e4e83f24cvboxsync * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
cde46304e0c614aad7fd63abacb0180e4e83f24cvboxsync * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
cde46304e0c614aad7fd63abacb0180e4e83f24cvboxsync/*******************************************************************************
cde46304e0c614aad7fd63abacb0180e4e83f24cvboxsync* Header Files *
cde46304e0c614aad7fd63abacb0180e4e83f24cvboxsync*******************************************************************************/
cde46304e0c614aad7fd63abacb0180e4e83f24cvboxsync/*******************************************************************************
cde46304e0c614aad7fd63abacb0180e4e83f24cvboxsync* Global Variables *
cde46304e0c614aad7fd63abacb0180e4e83f24cvboxsync*******************************************************************************/
cde46304e0c614aad7fd63abacb0180e4e83f24cvboxsync/** Register names. */
cde46304e0c614aad7fd63abacb0180e4e83f24cvboxsyncstatic const char * const g_apszRegNms[] =
cde46304e0c614aad7fd63abacb0180e4e83f24cvboxsync /* Variable number of root hub ports: */
f94dcbf4d4de095572e91b9475d65a68c18ab92avboxsync static struct
22b865436ba33d477830d608663dbe9c57107a72vboxsync#if 0 /* deadly when missing bytes are taken as zero. */
9fe2ed45aab3bcb2867113b7c9fb60ca7e99ac0bvboxsync { 13 /* HcFmInterval */, 0xffffffff, 0x58871120, 0x01010101 },
9fe2ed45aab3bcb2867113b7c9fb60ca7e99ac0bvboxsync { 16 /* HcPeriodicStart */, 0x00003fff, 0x01020304, 0x02010403 },
9fe2ed45aab3bcb2867113b7c9fb60ca7e99ac0bvboxsync { 17 /* HcLSThreshold */, 0x00000fff, 0xffffffff, 0x66666666 },
9fe2ed45aab3bcb2867113b7c9fb60ca7e99ac0bvboxsync { 10 /* HcBulkHeadED */, 0xfffffff0, 0xffffffff, 0xfefefef8 }, /* a bit risky... */
9fe2ed45aab3bcb2867113b7c9fb60ca7e99ac0bvboxsync { 11 /* HcBulkCurrentED */, 0xfffffff0, 0xffffffff, 0xfefefef8 }, /* a bit risky... */
f94dcbf4d4de095572e91b9475d65a68c18ab92avboxsync bool fSuccess = true;
f94dcbf4d4de095572e91b9475d65a68c18ab92avboxsync for (unsigned i = 0; i < RT_ELEMENTS(s_aRegs); i++)
f94dcbf4d4de095572e91b9475d65a68c18ab92avboxsync LogRel(("TestOhciWrites: %p iReg=%2d %20s = %08RX32\n", uPtrReg.pv, iReg, g_apszRegNms[iReg], uInitialValue));
9fe2ed45aab3bcb2867113b7c9fb60ca7e99ac0bvboxsync for (uint32_t iTry = 0; fTryAgain && iTry < 1024; iTry++)
9fe2ed45aab3bcb2867113b7c9fb60ca7e99ac0bvboxsync * DWORD writes.
9fe2ed45aab3bcb2867113b7c9fb60ca7e99ac0bvboxsync if ((fTryAgain = (*uPtrReg.pu32 != uInitialValue)))
9fe2ed45aab3bcb2867113b7c9fb60ca7e99ac0bvboxsync uChangedValue = s_aRegs[i].uVal1 != uInitialValue ? s_aRegs[i].uVal1 : s_aRegs[i].uVal2;
9fe2ed45aab3bcb2867113b7c9fb60ca7e99ac0bvboxsync /* Change the value. */
9fe2ed45aab3bcb2867113b7c9fb60ca7e99ac0bvboxsync * Write aligned word changes.
9fe2ed45aab3bcb2867113b7c9fb60ca7e99ac0bvboxsync for (unsigned iWord = 0; iWord < 2 && !pszError && !fTryAgain; iWord++)
9fe2ed45aab3bcb2867113b7c9fb60ca7e99ac0bvboxsync if ((fTryAgain = (*uPtrReg.pu32 != uInitialValue)))
9fe2ed45aab3bcb2867113b7c9fb60ca7e99ac0bvboxsync /* Change the value. */
9fe2ed45aab3bcb2867113b7c9fb60ca7e99ac0bvboxsync uPtrReg.pu16[iWord] = (uint16_t)(uChangedValue >> iWord * 16);
9fe2ed45aab3bcb2867113b7c9fb60ca7e99ac0bvboxsync uExpectedValue = (uChangedValue & UINT32_C(0xffff) << iWord * 16) & s_aRegs[i].fMask;
9fe2ed45aab3bcb2867113b7c9fb60ca7e99ac0bvboxsync static const char * const s_apsz[] = { "word 0", "word 1" };
9fe2ed45aab3bcb2867113b7c9fb60ca7e99ac0bvboxsync * Write aligned word change. We have to keep within the register,
9fe2ed45aab3bcb2867113b7c9fb60ca7e99ac0bvboxsync * unfortunately.
9fe2ed45aab3bcb2867113b7c9fb60ca7e99ac0bvboxsync /* Change the value. */
9fe2ed45aab3bcb2867113b7c9fb60ca7e99ac0bvboxsync *(uint16_t volatile *)&uPtrReg.pu8[1] = (uint16_t)(uChangedValue >> 8);
9fe2ed45aab3bcb2867113b7c9fb60ca7e99ac0bvboxsync uExpectedValue = (uChangedValue & UINT32_C(0x00ffff00)) & s_aRegs[i].fMask;
9fe2ed45aab3bcb2867113b7c9fb60ca7e99ac0bvboxsync * Write byte changes.
9fe2ed45aab3bcb2867113b7c9fb60ca7e99ac0bvboxsync for (unsigned iByte = 0; iByte < 4 && !pszError && !fTryAgain; iByte++)
9fe2ed45aab3bcb2867113b7c9fb60ca7e99ac0bvboxsync if ((fTryAgain = (*uPtrReg.pu32 != uInitialValue)))
9fe2ed45aab3bcb2867113b7c9fb60ca7e99ac0bvboxsync /* Change the value. */
9fe2ed45aab3bcb2867113b7c9fb60ca7e99ac0bvboxsync uPtrReg.pu8[iByte] = (uint8_t)(uChangedValue >> iByte * 8);
9fe2ed45aab3bcb2867113b7c9fb60ca7e99ac0bvboxsync uExpectedValue = (uChangedValue & UINT32_C(0xff) << iByte * 8) & s_aRegs[i].fMask;
9fe2ed45aab3bcb2867113b7c9fb60ca7e99ac0bvboxsync static const char * const s_apsz[] = { "byte 0", "byte 1", "byte 2", "byte 3" };
f94dcbf4d4de095572e91b9475d65a68c18ab92avboxsync * Complain on failure.
f94dcbf4d4de095572e91b9475d65a68c18ab92avboxsync LogRel(("TestOhciWrites: Warning! Register %s was never stable enough for testing! %08RX32 %08RX32 %08RX32\n",
f94dcbf4d4de095572e91b9475d65a68c18ab92avboxsync g_apszRegNms[iReg], uInitialValue, u32A, uChangedValue, uInitialValue));
9fe2ed45aab3bcb2867113b7c9fb60ca7e99ac0bvboxsync LogRel(("TestOhciWrites: Error! Register %s failed: %s; Initial=%08RX32 Changed=%08RX32 Expected=%08RX32 u32A=%08RX32\n",
9fe2ed45aab3bcb2867113b7c9fb60ca7e99ac0bvboxsync g_apszRegNms[iReg], pszError, uInitialValue, uChangedValue, uExpectedValue, u32A));
22b865436ba33d477830d608663dbe9c57107a72vboxsync static struct
22b865436ba33d477830d608663dbe9c57107a72vboxsync { 0 /* HcRevision */, 8, { 0, UINT32_MAX, 0x10100110, 0x200, 0x111, 0x11f, 0xf110, 0x0f10 } },
22b865436ba33d477830d608663dbe9c57107a72vboxsync { 12 /* HcDoneHead */, 3, { 0, UINT32_MAX, 0x55555555, 0, 0, 0, 0, 0 } },
22b865436ba33d477830d608663dbe9c57107a72vboxsync { 14 /* HcFmRemaining */, 3, { 0, UINT32_MAX, 0x55555555, 0, 0, 0, 0, 0 } },
22b865436ba33d477830d608663dbe9c57107a72vboxsync { 15 /* HcFmNumber */, 5, { 0, UINT32_MAX, 0x55555555, 0x7899, 0x00012222, 0, 0, 0 } },
22b865436ba33d477830d608663dbe9c57107a72vboxsync#if 0 /* HCD can write this */
22b865436ba33d477830d608663dbe9c57107a72vboxsync { 17 /* HcLSThreshold */, 5, { 0x627, 0x628, 0x629, 0x666, 0x599, 0, 0, 0 } } /* ??? */
22b865436ba33d477830d608663dbe9c57107a72vboxsync bool fSuccess = true;
22b865436ba33d477830d608663dbe9c57107a72vboxsync for (unsigned i = 0; i < RT_ELEMENTS(s_aRegs); i++)
22b865436ba33d477830d608663dbe9c57107a72vboxsync LogRel(("TestOhciReadOnly: %p iReg=%2d %20s = %08RX32\n", uPtrReg.pv, iReg, g_apszRegNms[iReg], uInitialValue));
22b865436ba33d477830d608663dbe9c57107a72vboxsync for (uint32_t iTry = 0; fTryAgain && iTry < 1024; iTry++)
22b865436ba33d477830d608663dbe9c57107a72vboxsync * Try aligned dword, word and byte writes for now.
22b865436ba33d477830d608663dbe9c57107a72vboxsync for (unsigned iValue = 0; iValue < s_aRegs[i].cValues && !pszError && !fTryAgain; iValue++)
22b865436ba33d477830d608663dbe9c57107a72vboxsync /* dword */
22b865436ba33d477830d608663dbe9c57107a72vboxsync if ((fTryAgain = (*uPtrReg.pu32 != uInitialValue)))
22b865436ba33d477830d608663dbe9c57107a72vboxsync for (unsigned iWord = 0; iWord < 2 && !pszError && !fTryAgain; iWord++)
22b865436ba33d477830d608663dbe9c57107a72vboxsync if ((fTryAgain = (*uPtrReg.pu32 != uInitialValue)))
22b865436ba33d477830d608663dbe9c57107a72vboxsync uPtrReg.pu16[iWord] = (uint16_t)(uChangedValue >> iWord * 16);
22b865436ba33d477830d608663dbe9c57107a72vboxsync pszError = iWord == 0 ? "aligned word 0 access" : "aligned word 1 access";
22b865436ba33d477830d608663dbe9c57107a72vboxsync for (unsigned iByte = 0; iByte < 4 && !pszError && !fTryAgain; iByte++)
22b865436ba33d477830d608663dbe9c57107a72vboxsync if ((fTryAgain = (*uPtrReg.pu32 != uInitialValue)))
22b865436ba33d477830d608663dbe9c57107a72vboxsync uPtrReg.pu8[iByte] = (uint8_t)(uChangedValue >> iByte * 8);
22b865436ba33d477830d608663dbe9c57107a72vboxsync static const char * const s_apsz[] = { "byte 0", "byte 1", "byte 2", "byte 3" };
22b865436ba33d477830d608663dbe9c57107a72vboxsync * Complain on failure.
22b865436ba33d477830d608663dbe9c57107a72vboxsync LogRel(("TestOhciReadOnly: Warning! Register %s was never stable enough for testing! %08RX32 %08RX32 %08RX32\n",
22b865436ba33d477830d608663dbe9c57107a72vboxsync g_apszRegNms[iReg], uInitialValue, u32A, uChangedValue, uInitialValue));
22b865436ba33d477830d608663dbe9c57107a72vboxsync LogRel(("TestOhciReadOnly: Error! Register %s failed: %s; uInitialValue=%08RX32 uChangedValue=%08RX32 u32A=%08RX32\n",
22b865436ba33d477830d608663dbe9c57107a72vboxsync g_apszRegNms[iReg], pszError, uInitialValue, uChangedValue, u32A));
cde46304e0c614aad7fd63abacb0180e4e83f24cvboxsync * We can read just about any register we like since read shouldn't have
cde46304e0c614aad7fd63abacb0180e4e83f24cvboxsync * any side effects. However, some registers are volatile and makes for
cde46304e0c614aad7fd63abacb0180e4e83f24cvboxsync * difficult targets, thus the ugly code.
cde46304e0c614aad7fd63abacb0180e4e83f24cvboxsync bool fSuccess = true;
cde46304e0c614aad7fd63abacb0180e4e83f24cvboxsync for (uint32_t iReg = 0; iReg < cMaxReg; iReg++, uPtr.pu32++)
cde46304e0c614aad7fd63abacb0180e4e83f24cvboxsync bool fDone = false;
cde46304e0c614aad7fd63abacb0180e4e83f24cvboxsync LogRel(("TestOhciReads: %p iReg=%2d %20s = %08RX32\n", uPtr.pv, iReg, g_apszRegNms[iReg], uInitialValue));
cde46304e0c614aad7fd63abacb0180e4e83f24cvboxsync for (uint32_t iTry = 0; !fDone && iTry < 1024; iTry++)
cde46304e0c614aad7fd63abacb0180e4e83f24cvboxsync /* Test byte access. */
cde46304e0c614aad7fd63abacb0180e4e83f24cvboxsync if (u32A != uInitialValue || u32C != uInitialValue)
cde46304e0c614aad7fd63abacb0180e4e83f24cvboxsync UINT32_C(0xffffff00), UINT32_C(0xffff00ff), UINT32_C(0xff00ffff), UINT32_C(0x00ffffff)
cde46304e0c614aad7fd63abacb0180e4e83f24cvboxsync static const char * const s_apsz[] = { "byte 0", "byte 1", "byte 2", "byte 3" };
cde46304e0c614aad7fd63abacb0180e4e83f24cvboxsync /* Test aligned word access. */
cde46304e0c614aad7fd63abacb0180e4e83f24cvboxsync if (u32A != uInitialValue || u32C != uInitialValue)
cde46304e0c614aad7fd63abacb0180e4e83f24cvboxsync u32B |= uInitialValue & (iWord == 0 ? UINT32_C(0xffff0000) : UINT32_C(0x0000ffff));
cde46304e0c614aad7fd63abacb0180e4e83f24cvboxsync pszError = iWord == 0 ? "aligned word 0 access" : "aligned word 1 access";
cde46304e0c614aad7fd63abacb0180e4e83f24cvboxsync /* Test unaligned word access. */
cde46304e0c614aad7fd63abacb0180e4e83f24cvboxsync for (int iWord = ((uintptr_t)uPtr.pv & PAGE_OFFSET_MASK) == 0; iWord < 3; iWord++)
cde46304e0c614aad7fd63abacb0180e4e83f24cvboxsync u32B = *(volatile uint16_t *)&uPtr.pu8[iWord * 2 - 1];
cde46304e0c614aad7fd63abacb0180e4e83f24cvboxsync if (u32A != uInitialValue || u32C != uInitialValue)
cde46304e0c614aad7fd63abacb0180e4e83f24cvboxsync case 0: u32B = (u32B >> 8) | (u32A & UINT32_C(0xffffff00)); break;
cde46304e0c614aad7fd63abacb0180e4e83f24cvboxsync case 1: u32B = (u32B << 8) | (u32A & UINT32_C(0xff0000ff)); break;
cde46304e0c614aad7fd63abacb0180e4e83f24cvboxsync case 2: u32B = (u32B << 24) | (u32A & UINT32_C(0x00ffffff)); break;
cde46304e0c614aad7fd63abacb0180e4e83f24cvboxsync static const char * const s_apsz[] = { "unaligned word 0", "unaligned word 1", "unaligned word 2" };
cde46304e0c614aad7fd63abacb0180e4e83f24cvboxsync /* Test unaligned dword access. */
cde46304e0c614aad7fd63abacb0180e4e83f24cvboxsync for (int iByte = ((uintptr_t)uPtr.pv & PAGE_OFFSET_MASK) == 0 ? 0 : -3; iByte < 4; iByte++)
cde46304e0c614aad7fd63abacb0180e4e83f24cvboxsync if (u32A != uInitialValue || u32C != uInitialValue)
cde46304e0c614aad7fd63abacb0180e4e83f24cvboxsync case -3: u32B = (u32B >> 24) | (uInitialValue & UINT32_C(0xffffff00)); break;
cde46304e0c614aad7fd63abacb0180e4e83f24cvboxsync case -2: u32B = (u32B >> 16) | (uInitialValue & UINT32_C(0xffff0000)); break;
cde46304e0c614aad7fd63abacb0180e4e83f24cvboxsync case -1: u32B = (u32B >> 8) | (uInitialValue & UINT32_C(0xff000000)); break;
cde46304e0c614aad7fd63abacb0180e4e83f24cvboxsync case 0: break;
cde46304e0c614aad7fd63abacb0180e4e83f24cvboxsync case 1: u32B = (u32B << 8) | (uInitialValue & UINT32_C(0x000000ff)); break;
cde46304e0c614aad7fd63abacb0180e4e83f24cvboxsync case 2: u32B = (u32B << 16) | (uInitialValue & UINT32_C(0x0000ffff)); break;
cde46304e0c614aad7fd63abacb0180e4e83f24cvboxsync case 3: u32B = (u32B << 24) | (uInitialValue & UINT32_C(0x00ffffff)); break;
cde46304e0c614aad7fd63abacb0180e4e83f24cvboxsync static const char * const s_apsz[] =
cde46304e0c614aad7fd63abacb0180e4e83f24cvboxsync "unaligned dword -3", "unaligned dword -2", "unaligned dword -1",
cde46304e0c614aad7fd63abacb0180e4e83f24cvboxsync "unaligned dword 0", "unaligned dword 1", "unaligned dword 2", "unaligned dword 3"
cde46304e0c614aad7fd63abacb0180e4e83f24cvboxsync } /* try loop */
cde46304e0c614aad7fd63abacb0180e4e83f24cvboxsync * Complain on failure.
cde46304e0c614aad7fd63abacb0180e4e83f24cvboxsync LogRel(("TestOhciReads: Warning! Register %s was never stable enough for testing! %08RX32 %08RX32 %08RX32\n",
cde46304e0c614aad7fd63abacb0180e4e83f24cvboxsync LogRel(("TestOhciReads: Error! Register %s failed: %s; uInitialValue=%08RX32 u32B=%08RX32\n",
cde46304e0c614aad7fd63abacb0180e4e83f24cvboxsync g_apszRegNms[iReg], pszError, uInitialValue, u32B));
cde46304e0c614aad7fd63abacb0180e4e83f24cvboxsync LogRel(("tstOhciRegisterAccess: HCPhysOHCI=%RHp\n", HCPhysOHCI));
cde46304e0c614aad7fd63abacb0180e4e83f24cvboxsync * Map the OHCI registers so we can access them.
cde46304e0c614aad7fd63abacb0180e4e83f24cvboxsync int rc = RTR0MemObjEnterPhys(&hMemObj, HCPhysOHCI, PAGE_SIZE, RTMEM_CACHE_POLICY_MMIO);
cde46304e0c614aad7fd63abacb0180e4e83f24cvboxsync LogRel(("tstOhciRegisterAccess: Failed to enter OHCI memory at %RHp: %Rrc\n", HCPhysOHCI, rc));
cde46304e0c614aad7fd63abacb0180e4e83f24cvboxsync rc = RTR0MemObjMapKernel(&hMapObj, hMemObj, (void *)-1, 0 /*uAlignment*/, RTMEM_PROT_READ | RTMEM_PROT_WRITE);
cde46304e0c614aad7fd63abacb0180e4e83f24cvboxsync uPtr.pv = (void volatile *)RTR0MemObjAddress(hMapObj);
cde46304e0c614aad7fd63abacb0180e4e83f24cvboxsync LogRel(("tstOhciRegisterAccess: mapping address %p\n", uPtr.pv));
cde46304e0c614aad7fd63abacb0180e4e83f24cvboxsync LogRel(("tstOhciRegisterAccess: HcRevision=%#x\n", *uPtr.pu32));
cde46304e0c614aad7fd63abacb0180e4e83f24cvboxsync * Do the access tests.
cde46304e0c614aad7fd63abacb0180e4e83f24cvboxsync * Clean up.
cde46304e0c614aad7fd63abacb0180e4e83f24cvboxsync LogRel(("tstOhciRegisterAccess: Failed to map OHCI memory at %RHp: %Rrc\n", HCPhysOHCI, rc));
cde46304e0c614aad7fd63abacb0180e4e83f24cvboxsync LogRel(("tstOhciRegisterAccess: returns %Rrc\n", rc));