#define LOG_GROUP LOG_GROUP_DEV_BUSLOGIC

#include <VBox/vmm/pdmdev.h>

#include <VBox/vmm/pdmifs.h>

#include <VBox/vmm/pdmcritsect.h>

#include <VBox/scsi.h>

#include <iprt/asm.h>

#include <iprt/assert.h>

#include <iprt/string.h>

#include <iprt/log.h>

#ifdef IN_RING3

# include <iprt/alloc.h>

# include <iprt/memcache.h>

# include <iprt/param.h>

# include <iprt/uuid.h>

#endif

#include "VBoxSCSI.h"

#include "VBoxDD.h"

#define BUSLOGIC_MAX_DEVICES 16

#define BUSLOGIC_MAX_SCATTER_GATHER_LIST_SIZE 128

#define BUSLOGIC_COMMAND_SIZE_MAX 5

#define BUSLOGIC_REPLY_SIZE_MAX 64

#define BUSLOGIC_BIOS_IO_PORT 0x330

#define BUSLOGIC_SAVED_STATE_MINOR_VERSION 2

#define BUSLOGIC_SAVED_STATE_MINOR_PRE_ERROR_HANDLING 1

#define BUSLOGIC_RESET_DURATION_NS (500*1000*1000UL)

typedef struct BUSLOGICDEVICE

{

/** Pointer to the owning buslogic device instance. - R3 pointer */

R3PTRTYPE(struct BUSLOGIC *) pBusLogicR3;

/** Pointer to the owning buslogic device instance. - R0 pointer */

R0PTRTYPE(struct BUSLOGIC *) pBusLogicR0;

/** Pointer to the owning buslogic device instance. - RC pointer */

RCPTRTYPE(struct BUSLOGIC *) pBusLogicRC;

/** Flag whether device is present. */

bool fPresent;

/** LUN of the device. */

RTUINT iLUN;

#if HC_ARCH_BITS == 64

uint32_t Alignment0;

#endif

/** Our base interface. */

PDMIBASE IBase;

/** SCSI port interface. */

PDMISCSIPORT ISCSIPort;

/** Led interface. */

PDMILEDPORTS ILed;

/** Pointer to the attached driver's base interface. */

R3PTRTYPE(PPDMIBASE) pDrvBase;

/** Pointer to the underlying SCSI connector interface. */

R3PTRTYPE(PPDMISCSICONNECTOR) pDrvSCSIConnector;

/** The status LED state for this device. */

PDMLED Led;

#if HC_ARCH_BITS == 64

uint32_t Alignment1;

#endif

/** Number of outstanding tasks on the port. */

volatile uint32_t cOutstandingRequests;

} BUSLOGICDEVICE, *PBUSLOGICDEVICE;

enum BUSLOGICCOMMAND

{

BUSLOGICCOMMAND_TEST_CMDC_INTERRUPT = 0x00,

BUSLOGICCOMMAND_INITIALIZE_MAILBOX = 0x01,

BUSLOGICCOMMAND_EXECUTE_MAILBOX_COMMAND = 0x02,

BUSLOGICCOMMAND_EXECUTE_BIOS_COMMAND = 0x03,

BUSLOGICCOMMAND_INQUIRE_BOARD_ID = 0x04,

BUSLOGICCOMMAND_ENABLE_OUTGOING_MAILBOX_AVAILABLE_INTERRUPT = 0x05,

BUSLOGICCOMMAND_SET_SCSI_SELECTION_TIMEOUT = 0x06,

BUSLOGICCOMMAND_SET_PREEMPT_TIME_ON_BUS = 0x07,

BUSLOGICCOMMAND_SET_TIME_OFF_BUS = 0x08,

BUSLOGICCOMMAND_SET_BUS_TRANSFER_RATE = 0x09,

BUSLOGICCOMMAND_INQUIRE_INSTALLED_DEVICES_ID_0_TO_7 = 0x0a,

BUSLOGICCOMMAND_INQUIRE_CONFIGURATION = 0x0b,

BUSLOGICCOMMAND_ENABLE_TARGET_MODE = 0x0c,

BUSLOGICCOMMAND_INQUIRE_SETUP_INFORMATION = 0x0d,

BUSLOGICCOMMAND_WRITE_ADAPTER_LOCAL_RAM = 0x1a,

BUSLOGICCOMMAND_READ_ADAPTER_LOCAL_RAM = 0x1b,

BUSLOGICCOMMAND_WRITE_BUSMASTER_CHIP_FIFO = 0x1c,

BUSLOGICCOMMAND_READ_BUSMASTER_CHIP_FIFO = 0x1d,

BUSLOGICCOMMAND_ECHO_COMMAND_DATA = 0x1f,

BUSLOGICCOMMAND_HOST_ADAPTER_DIAGNOSTIC = 0x20,

BUSLOGICCOMMAND_SET_ADAPTER_OPTIONS = 0x21,

BUSLOGICCOMMAND_INQUIRE_INSTALLED_DEVICES_ID_8_TO_15 = 0x23,

BUSLOGICCOMMAND_INQUIRE_TARGET_DEVICES = 0x24,

BUSLOGICCOMMAND_DISABLE_HOST_ADAPTER_INTERRUPT = 0x25,

BUSLOGICCOMMAND_EXT_BIOS_INFO = 0x28,

BUSLOGICCOMMAND_UNLOCK_MAILBOX = 0x29,

BUSLOGICCOMMAND_INITIALIZE_EXTENDED_MAILBOX = 0x81,

BUSLOGICCOMMAND_EXECUTE_SCSI_COMMAND = 0x83,

BUSLOGICCOMMAND_INQUIRE_FIRMWARE_VERSION_3RD_LETTER = 0x84,

BUSLOGICCOMMAND_INQUIRE_FIRMWARE_VERSION_LETTER = 0x85,

BUSLOGICCOMMAND_INQUIRE_PCI_HOST_ADAPTER_INFORMATION = 0x86,

BUSLOGICCOMMAND_INQUIRE_HOST_ADAPTER_MODEL_NUMBER = 0x8b,

BUSLOGICCOMMAND_INQUIRE_SYNCHRONOUS_PERIOD = 0x8c,

BUSLOGICCOMMAND_INQUIRE_EXTENDED_SETUP_INFORMATION = 0x8d,

BUSLOGICCOMMAND_ENABLE_STRICT_ROUND_ROBIN_MODE = 0x8f,

BUSLOGICCOMMAND_STORE_HOST_ADAPTER_LOCAL_RAM = 0x90,

BUSLOGICCOMMAND_FETCH_HOST_ADAPTER_LOCAL_RAM = 0x91,

BUSLOGICCOMMAND_STORE_LOCAL_DATA_IN_EEPROM = 0x92,

BUSLOGICCOMMAND_UPLOAD_AUTO_SCSI_CODE = 0x94,

BUSLOGICCOMMAND_MODIFY_IO_ADDRESS = 0x95,

BUSLOGICCOMMAND_SET_CCB_FORMAT = 0x96,

BUSLOGICCOMMAND_WRITE_INQUIRY_BUFFER = 0x9a,

BUSLOGICCOMMAND_READ_INQUIRY_BUFFER = 0x9b,

BUSLOGICCOMMAND_FLASH_ROM_UPLOAD_DOWNLOAD = 0xa7,

BUSLOGICCOMMAND_READ_SCAM_DATA = 0xa8,

BUSLOGICCOMMAND_WRITE_SCAM_DATA = 0xa9

} BUSLOGICCOMMAND;

#pragma pack(1)

typedef struct AutoSCSIRam

{

uint8_t aInternalSignature[2];

uint8_t cbInformation;

uint8_t aHostAdaptertype[6];

uint8_t uReserved1;

bool fFloppyEnabled: 1;

bool fFloppySecondary: 1;

bool fLevelSensitiveInterrupt: 1;

unsigned char uReserved2: 2;

unsigned char uSystemRAMAreForBIOS: 3;

unsigned char uDMAChannel: 7;

bool fDMAAutoConfiguration: 1;

unsigned char uIrqChannel: 7;

bool fIrqAutoConfiguration: 1;

uint8_t uDMATransferRate;

uint8_t uSCSIId;

bool fLowByteTerminated: 1;

bool fParityCheckingEnabled: 1;

bool fHighByteTerminated: 1;

bool fNoisyCablingEnvironment: 1;

bool fFastSynchronousNeogtiation: 1;

bool fBusResetEnabled: 1;

bool fReserved3: 1;

bool fActiveNegotiationEnabled: 1;

uint8_t uBusOnDelay;

uint8_t uBusOffDelay;

bool fHostAdapterBIOSEnabled: 1;

bool fBIOSRedirectionOfInt19: 1;

bool fExtendedTranslation: 1;

bool fMapRemovableAsFixed: 1;

bool fReserved4: 1;

bool fBIOSSupportsMoreThan2Drives: 1;

bool fBIOSInterruptMode: 1;

bool fFlopticalSupport: 1;

uint16_t u16DeviceEnabledMask;

uint16_t u16WidePermittedMask;

uint16_t u16FastPermittedMask;

uint16_t u16SynchronousPermittedMask;

uint16_t u16DisconnectPermittedMask;

uint16_t u16SendStartUnitCommandMask;

uint16_t u16IgnoreInBIOSScanMask;

unsigned char uPCIInterruptPin: 2;

unsigned char uHostAdapterIoPortAddress: 2;

bool fStrictRoundRobinMode: 1;

bool fVesaBusSpeedGreaterThan33MHz: 1;

bool fVesaBurstWrite: 1;

bool fVesaBurstRead: 1;

uint16_t u16UltraPermittedMask;

uint32_t uReserved5;

uint8_t uReserved6;

uint8_t uAutoSCSIMaximumLUN;

bool fReserved7: 1;

bool fSCAMDominant: 1;

bool fSCAMenabled: 1;

bool fSCAMLevel2: 1;

unsigned char uReserved8: 4;

bool fInt13Extension: 1;

bool fReserved9: 1;

bool fCDROMBoot: 1;

unsigned char uReserved10: 5;

unsigned char uBootTargetId: 4;

unsigned char uBootChannel: 4;

bool fForceBusDeviceScanningOrder: 1;

unsigned char uReserved11: 7;

uint16_t u16NonTaggedToAlternateLunPermittedMask;

uint16_t u16RenegotiateSyncAfterCheckConditionMask;

uint8_t aReserved12[10];

uint8_t aManufacturingDiagnostic[2];

uint16_t u16Checksum;

} AutoSCSIRam, *PAutoSCSIRam;

AssertCompileSize(AutoSCSIRam, 64);

#pragma pack()

typedef union HostAdapterLocalRam

{

/* Byte view. */

uint8_t u8View[256];

/* Structured view. */

struct

{

/** Offset 0 - 63 is for BIOS. */

uint8_t u8Bios[64];

/** Auto SCSI structure. */

AutoSCSIRam autoSCSIData;

} structured;

} HostAdapterLocalRam, *PHostAdapterLocalRam;

AssertCompileSize(HostAdapterLocalRam, 256);

#define NUM_ISA_BASES 8

#define MAX_ISA_BASE (NUM_ISA_BASES - 1)

#define ISA_BASE_DISABLED 6

static uint16_t aISABases[NUM_ISA_BASES] = {

0x330, 0x334, 0x230, 0x234, 0x130, 0x134, 0, 0

};

typedef struct BUSLOGICTASKSTATE *PBUSLOGICTASKSTATE;

typedef struct BUSLOGIC

{

/** The PCI device structure. */

PCIDEVICE dev;

/** Pointer to the device instance - HC ptr */

PPDMDEVINSR3 pDevInsR3;

/** Pointer to the device instance - R0 ptr */

PPDMDEVINSR0 pDevInsR0;

/** Pointer to the device instance - RC ptr. */

PPDMDEVINSRC pDevInsRC;

/** Whether R0 is enabled. */

bool fR0Enabled;

/** Whether RC is enabled. */

bool fGCEnabled;

/** Base address of the I/O ports. */

RTIOPORT IOPortBase;

/** Base address of the memory mapping. */

RTGCPHYS MMIOBase;

/** Status register - Readonly. */

volatile uint8_t regStatus;

/** Interrupt register - Readonly. */

volatile uint8_t regInterrupt;

/** Geometry register - Readonly. */

volatile uint8_t regGeometry;

/** Pending (delayed) interrupt. */

uint8_t uPendingIntr;

/** Local RAM for the fetch hostadapter local RAM request.

HostAdapterLocalRam LocalRam;

/** Command code the guest issued. */

uint8_t uOperationCode;

/** Buffer for the command parameters the adapter is currently receiving from the guest.

uint8_t aCommandBuffer[BUSLOGIC_COMMAND_SIZE_MAX]; /* Size of the biggest request. */

/** Current position in the command buffer. */

uint8_t iParameter;

/** Parameters left until the command is complete. */

uint8_t cbCommandParametersLeft;

/** Whether we are using the RAM or reply buffer. */

bool fUseLocalRam;

/** Buffer to store reply data from the controller to the guest. */

uint8_t aReplyBuffer[BUSLOGIC_REPLY_SIZE_MAX]; /* Size of the biggest reply. */

/** Position in the buffer we are reading next. */

uint8_t iReply;

/** Bytes left until the reply buffer is empty. */

uint8_t cbReplyParametersLeft;

/** Flag whether IRQs are enabled. */

bool fIRQEnabled;

/** Flag whether the ISA I/O port range is disabled

bool fISAEnabled; //@todo: unused, to be removed

/** Flag whether 24-bit mailboxes are in use (default is 32-bit). */

bool fMbxIs24Bit; //@todo: save?

/** ISA I/O port base (encoded in FW-compatible format). */

uint8_t uISABaseCode;

/** ISA I/O port base (disabled if zero). */

RTIOPORT IOISABase;

/** Default ISA I/O port base in FW-compatible format. */

uint8_t uDefaultISABaseCode;

/** Number of mailboxes the guest set up. */

uint32_t cMailbox;

#if HC_ARCH_BITS == 64

uint32_t Alignment0;

#endif

/** Time when HBA reset was last initiated. */ //@todo: does this need to be saved?

uint64_t u64ResetTime;

/** Physical base address of the outgoing mailboxes. */

RTGCPHYS GCPhysAddrMailboxOutgoingBase;

/** Current outgoing mailbox position. */

uint32_t uMailboxOutgoingPositionCurrent;

/** Number of mailboxes ready. */

volatile uint32_t cMailboxesReady;

/** Whether a notification to R3 was send. */

volatile bool fNotificationSend;

#if HC_ARCH_BITS == 64

uint32_t Alignment1;

#endif

/** Physical base address of the incoming mailboxes. */

RTGCPHYS GCPhysAddrMailboxIncomingBase;

/** Current incoming mailbox position. */

uint32_t uMailboxIncomingPositionCurrent;

/** Whether strict round robin is enabled. */

bool fStrictRoundRobinMode;

/** Whether the extended LUN CCB format is enabled for 32 possible logical units. */

bool fExtendedLunCCBFormat;

/** Queue to send tasks to R3. - HC ptr */

R3PTRTYPE(PPDMQUEUE) pNotifierQueueR3;

/** Queue to send tasks to R3. - HC ptr */

R0PTRTYPE(PPDMQUEUE) pNotifierQueueR0;

/** Queue to send tasks to R3. - RC ptr */

RCPTRTYPE(PPDMQUEUE) pNotifierQueueRC;

uint32_t Alignment2;

/** Critical section protecting access to the interrupt status register. */

PDMCRITSECT CritSectIntr;

/** Cache for task states. */

R3PTRTYPE(RTMEMCACHE) hTaskCache;

/** Device state for BIOS access. */

VBOXSCSI VBoxSCSI;

/** BusLogic device states. */

BUSLOGICDEVICE aDeviceStates[BUSLOGIC_MAX_DEVICES];

/** The base interface.

PDMIBASE IBase;

/** Status Port - Leds interface. */

PDMILEDPORTS ILeds;

/** Partner of ILeds. */

R3PTRTYPE(PPDMILEDCONNECTORS) pLedsConnector;

#if HC_ARCH_BITS == 64

uint32_t Alignment3;

#endif

/** Indicates that PDMDevHlpAsyncNotificationCompleted should be called when

bool volatile fSignalIdle;

/** Flag whether we have tasks which need to be processed again. */

bool volatile fRedo;

/** List of tasks which can be redone. */

R3PTRTYPE(volatile PBUSLOGICTASKSTATE) pTasksRedoHead;

#ifdef LOG_ENABLED

# if HC_ARCH_BITS == 64

uint32_t Alignment4;

# endif

volatile uint32_t cInMailboxesReady;

#endif

} BUSLOGIC, *PBUSLOGIC;

#define BUSLOGIC_REGISTER_CONTROL 0 /* Writeonly */

# define BUSLOGIC_REGISTER_CONTROL_SCSI_BUSRESET RT_BIT(4)

# define BUSLOGIC_REGISTER_CONTROL_INTERRUPT_RESET RT_BIT(5)

# define BUSLOGIC_REGISTER_CONTROL_SOFT_RESET RT_BIT(6)

# define BUSLOGIC_REGISTER_CONTROL_HARD_RESET RT_BIT(7)

#define BUSLOGIC_REGISTER_STATUS 0 /* Readonly */

# define BUSLOGIC_REGISTER_STATUS_COMMAND_INVALID RT_BIT(0)

# define BUSLOGIC_REGISTER_STATUS_DATA_IN_REGISTER_READY RT_BIT(2)

# define BUSLOGIC_REGISTER_STATUS_COMMAND_PARAMETER_REGISTER_BUSY RT_BIT(3)

# define BUSLOGIC_REGISTER_STATUS_HOST_ADAPTER_READY RT_BIT(4)

# define BUSLOGIC_REGISTER_STATUS_INITIALIZATION_REQUIRED RT_BIT(5)

# define BUSLOGIC_REGISTER_STATUS_DIAGNOSTIC_FAILURE RT_BIT(6)

# define BUSLOGIC_REGISTER_STATUS_DIAGNOSTIC_ACTIVE RT_BIT(7)

#define BUSLOGIC_REGISTER_COMMAND 1 /* Writeonly */

#define BUSLOGIC_REGISTER_DATAIN 1 /* Readonly */

#define BUSLOGIC_REGISTER_INTERRUPT 2 /* Readonly */

# define BUSLOGIC_REGISTER_INTERRUPT_INCOMING_MAILBOX_LOADED RT_BIT(0)

# define BUSLOGIC_REGISTER_INTERRUPT_OUTGOING_MAILBOX_AVAILABLE RT_BIT(1)

# define BUSLOGIC_REGISTER_INTERRUPT_COMMAND_COMPLETE RT_BIT(2)

# define BUSLOGIC_REGISTER_INTERRUPT_EXTERNAL_BUS_RESET RT_BIT(3)

# define BUSLOGIC_REGISTER_INTERRUPT_INTERRUPT_VALID RT_BIT(7)

#define BUSLOGIC_REGISTER_GEOMETRY 3 /* Readonly */

# define BUSLOGIC_REGISTER_GEOMETRY_EXTENTED_TRANSLATION_ENABLED RT_BIT(7)

typedef struct ReplyInquirePCIHostAdapterInformation

{

uint8_t IsaIOPort;

uint8_t IRQ;

unsigned char LowByteTerminated:1;

unsigned char HighByteTerminated:1;

unsigned char uReserved:2; /* Reserved. */

unsigned char JP1:1; /* Whatever that means. */

unsigned char JP2:1; /* Whatever that means. */

unsigned char JP3:1; /* Whatever that means. */

/** Whether the provided info is valid. */

unsigned char InformationIsValid: 1;

uint8_t uReserved2; /* Reserved. */

} ReplyInquirePCIHostAdapterInformation, *PReplyInquirePCIHostAdapterInformation;

AssertCompileSize(ReplyInquirePCIHostAdapterInformation, 4);

typedef struct ReplyInquireConfiguration

{

unsigned char uReserved1: 5;

bool fDmaChannel5: 1;

bool fDmaChannel6: 1;

bool fDmaChannel7: 1;

bool fIrqChannel9: 1;

bool fIrqChannel10: 1;

bool fIrqChannel11: 1;

bool fIrqChannel12: 1;

unsigned char uReserved2: 1;

bool fIrqChannel14: 1;

bool fIrqChannel15: 1;

unsigned char uReserved3: 1;

unsigned char uHostAdapterId: 4;

unsigned char uReserved4: 4;

} ReplyInquireConfiguration, *PReplyInquireConfiguration;

AssertCompileSize(ReplyInquireConfiguration, 3);

typedef struct ReplyInquireSetupInformationSynchronousValue

{

unsigned char uOffset: 4;

unsigned char uTransferPeriod: 3;

bool fSynchronous: 1;

}ReplyInquireSetupInformationSynchronousValue, *PReplyInquireSetupInformationSynchronousValue;

AssertCompileSize(ReplyInquireSetupInformationSynchronousValue, 1);

typedef struct ReplyInquireSetupInformation

{

bool fSynchronousInitiationEnabled: 1;

bool fParityCheckingEnabled: 1;

unsigned char uReserved1: 6;

uint8_t uBusTransferRate;

uint8_t uPreemptTimeOnBus;

uint8_t uTimeOffBus;

uint8_t cMailbox;

uint8_t MailboxAddress[3];

ReplyInquireSetupInformationSynchronousValue SynchronousValuesId0To7[8];

uint8_t uDisconnectPermittedId0To7;

uint8_t uSignature;

uint8_t uCharacterD;

uint8_t uHostBusType;

uint8_t uWideTransferPermittedId0To7;

uint8_t uWideTransfersActiveId0To7;

ReplyInquireSetupInformationSynchronousValue SynchronousValuesId8To15[8];

uint8_t uDisconnectPermittedId8To15;

uint8_t uReserved2;

uint8_t uWideTransferPermittedId8To15;

uint8_t uWideTransfersActiveId8To15;

} ReplyInquireSetupInformation, *PReplyInquireSetupInformation;

AssertCompileSize(ReplyInquireSetupInformation, 34);

#pragma pack(1)

typedef struct ReplyInquireExtendedSetupInformation

{

uint8_t uBusType;

uint8_t uBiosAddress;

uint16_t u16ScatterGatherLimit;

uint8_t cMailbox;

uint32_t uMailboxAddressBase;

unsigned char uReserved1: 2;

bool fFastEISA: 1;

unsigned char uReserved2: 3;

bool fLevelSensitiveInterrupt: 1;

unsigned char uReserved3: 1;

unsigned char aFirmwareRevision[3];

bool fHostWideSCSI: 1;

bool fHostDifferentialSCSI: 1;

bool fHostSupportsSCAM: 1;

bool fHostUltraSCSI: 1;

bool fHostSmartTermination: 1;

unsigned char uReserved4: 3;

} ReplyInquireExtendedSetupInformation, *PReplyInquireExtendedSetupInformation;

AssertCompileSize(ReplyInquireExtendedSetupInformation, 14);

#pragma pack()

#pragma pack(1)

typedef struct RequestInitializeExtendedMailbox

{

/** Number of mailboxes in guest memory. */

uint8_t cMailbox;

/** Physical address of the first mailbox. */

uint32_t uMailboxBaseAddress;

} RequestInitializeExtendedMailbox, *PRequestInitializeExtendedMailbox;

AssertCompileSize(RequestInitializeExtendedMailbox, 5);

#pragma pack()

#pragma pack(1)

typedef struct Mailbox

{

/** Physical address of the CCB structure in the guest memory. */

uint32_t u32PhysAddrCCB;

/** Type specific data. */

union

{

/** For outgoing mailboxes. */

struct

{

/** Reserved */

uint8_t uReserved[3];

/** Action code. */

uint8_t uActionCode;

} out;

/** For incoming mailboxes. */

struct

{

/** The host adapter status after finishing the request. */

uint8_t uHostAdapterStatus;

/** The status of the device which executed the request after executing it. */

uint8_t uTargetDeviceStatus;

/** Reserved. */

uint8_t uReserved;

/** The completion status code of the request. */

uint8_t uCompletionCode;

} in;

} u;

} Mailbox, *PMailbox;

AssertCompileSize(Mailbox, 8);

#pragma pack()

enum BUSLOGIC_MAILBOX_OUTGOING_ACTION

{

BUSLOGIC_MAILBOX_OUTGOING_ACTION_FREE = 0x00,

BUSLOGIC_MAILBOX_OUTGOING_ACTION_START_COMMAND = 0x01,

BUSLOGIC_MAILBOX_OUTGOING_ACTION_ABORT_COMMAND = 0x02

};

enum BUSLOGIC_MAILBOX_INCOMING_COMPLETION

{

BUSLOGIC_MAILBOX_INCOMING_COMPLETION_FREE = 0x00,

BUSLOGIC_MAILBOX_INCOMING_COMPLETION_WITHOUT_ERROR = 0x01,

BUSLOGIC_MAILBOX_INCOMING_COMPLETION_ABORTED = 0x02,

BUSLOGIC_MAILBOX_INCOMING_COMPLETION_ABORTED_NOT_FOUND = 0x03,

BUSLOGIC_MAILBOX_INCOMING_COMPLETION_WITH_ERROR = 0x04,

BUSLOGIC_MAILBOX_INCOMING_COMPLETION_INVALID_CCB = 0x05

};

enum BUSLOGIC_MAILBOX_INCOMING_ADAPTER_STATUS

{

BUSLOGIC_MAILBOX_INCOMING_ADAPTER_STATUS_CMD_COMPLETED = 0x00,

BUSLOGIC_MAILBOX_INCOMING_ADAPTER_STATUS_LINKED_CMD_COMPLETED = 0x0a,

BUSLOGIC_MAILBOX_INCOMING_ADAPTER_STATUS_LINKED_CMD_COMPLETED_WITH_FLAG = 0x0b,

BUSLOGIC_MAILBOX_INCOMING_ADAPTER_STATUS_DATA_UNDERUN = 0x0c,

BUSLOGIC_MAILBOX_INCOMING_ADAPTER_STATUS_SCSI_SELECTION_TIMEOUT = 0x11,

BUSLOGIC_MAILBOX_INCOMING_ADAPTER_STATUS_DATA_OVERRUN = 0x12,

BUSLOGIC_MAILBOX_INCOMING_ADAPTER_STATUS_UNEXPECTED_BUS_FREE = 0x13,

BUSLOGIC_MAILBOX_INCOMING_ADAPTER_STATUS_INVALID_BUS_PHASE_REQUESTED = 0x14,

BUSLOGIC_MAILBOX_INCOMING_ADAPTER_STATUS_INVALID_OUTGOING_MAILBOX_ACTION_CODE = 0x15,

BUSLOGIC_MAILBOX_INCOMING_ADAPTER_STATUS_INVALID_COMMAND_OPERATION_CODE = 0x16,

BUSLOGIC_MAILBOX_INCOMING_ADAPTER_STATUS_LINKED_CCB_HAS_INVALID_LUN = 0x17,

BUSLOGIC_MAILBOX_INCOMING_ADAPTER_STATUS_INVALID_COMMAND_PARAMETER = 0x1a,

BUSLOGIC_MAILBOX_INCOMING_ADAPTER_STATUS_AUTO_REQUEST_SENSE_FAILED = 0x1b,

BUSLOGIC_MAILBOX_INCOMING_ADAPTER_STATUS_TAGGED_QUEUING_MESSAGE_REJECTED = 0x1c,

BUSLOGIC_MAILBOX_INCOMING_ADAPTER_STATUS_UNSUPPORTED_MESSAGE_RECEIVED = 0x1d,

BUSLOGIC_MAILBOX_INCOMING_ADAPTER_STATUS_HOST_ADAPTER_HARDWARE_FAILED = 0x20,

BUSLOGIC_MAILBOX_INCOMING_ADAPTER_STATUS_TARGET_FAILED_RESPONSE_TO_ATN = 0x21,

BUSLOGIC_MAILBOX_INCOMING_ADAPTER_STATUS_HOST_ADAPTER_ASSERTED_RST = 0x22,

BUSLOGIC_MAILBOX_INCOMING_ADAPTER_STATUS_OTHER_DEVICE_ASSERTED_RST = 0x23,

BUSLOGIC_MAILBOX_INCOMING_ADAPTER_STATUS_TARGET_DEVICE_RECONNECTED_IMPROPERLY = 0x24,

BUSLOGIC_MAILBOX_INCOMING_ADAPTER_STATUS_HOST_ADAPTER_ASSERTED_BUS_DEVICE_RESET = 0x25,

BUSLOGIC_MAILBOX_INCOMING_ADAPTER_STATUS_ABORT_QUEUE_GENERATED = 0x26,

BUSLOGIC_MAILBOX_INCOMING_ADAPTER_STATUS_HOST_ADAPTER_SOFTWARE_ERROR = 0x27,

BUSLOGIC_MAILBOX_INCOMING_ADAPTER_STATUS_HOST_ADAPTER_HARDWARE_TIMEOUT_ERROR = 0x30,

BUSLOGIC_MAILBOX_INCOMING_ADAPTER_STATUS_SCSI_PARITY_ERROR_DETECTED = 0x34

};

enum BUSLOGIC_MAILBOX_INCOMING_DEVICE_STATUS

{

BUSLOGIC_MAILBOX_INCOMING_DEVICE_STATUS_OPERATION_GOOD = 0x00,

BUSLOGIC_MAILBOX_INCOMING_DEVICE_STATUS_CHECK_CONDITION = 0x02,

BUSLOGIC_MAILBOX_INCOMING_DEVICE_STATUS_DEVICE_BUSY = 0x08

};

enum BUSLOGIC_CCB_OPCODE

{

BUSLOGIC_CCB_OPCODE_INITIATOR_CCB = 0x00,

BUSLOGIC_CCB_OPCODE_TARGET_CCB = 0x01,

BUSLOGIC_CCB_OPCODE_INITIATOR_CCB_SCATTER_GATHER = 0x02,

BUSLOGIC_CCB_OPCODE_INITIATOR_CCB_RESIDUAL_DATA_LENGTH = 0x03,

BUSLOGIC_CCB_OPCODE_INITIATOR_CCB_RESIDUAL_SCATTER_GATHER = 0x04,

BUSLOGIC_CCB_OPCODE_BUS_DEVICE_RESET = 0x81

};

enum BUSLOGIC_CCB_DIRECTION

{

BUSLOGIC_CCB_DIRECTION_UNKNOWN = 0x00,

BUSLOGIC_CCB_DIRECTION_IN = 0x01,

BUSLOGIC_CCB_DIRECTION_OUT = 0x02,

BUSLOGIC_CCB_DIRECTION_NO_DATA = 0x03

};

#pragma pack(1)

typedef struct CommandControlBlock

{

/** Opcode. */

uint8_t uOpcode;

/** Reserved */

unsigned char uReserved1: 3;

/** Data direction for the request. */

unsigned char uDataDirection: 2;

/** Whether the request is tag queued. */

bool fTagQueued: 1;

/** Queue tag mode. */

unsigned char uQueueTag: 2;

/** Length of the SCSI CDB. */

uint8_t cbCDB;

/** Sense data length. */

uint8_t cbSenseData;

/** Data length. */

uint32_t cbData;

/** Data pointer.

uint32_t u32PhysAddrData;

/** Reserved. */

uint8_t uReserved2[2];

/** Host adapter status. */

uint8_t uHostAdapterStatus;

/** Device adapter status. */

uint8_t uDeviceStatus;

/** The device the request is sent to. */

uint8_t uTargetId;

/**The LUN in the device. */

unsigned char uLogicalUnit: 5;

/** Legacy tag. */

bool fLegacyTagEnable: 1;

/** Legacy queue tag. */

unsigned char uLegacyQueueTag: 2;

/** The SCSI CDB. */

uint8_t aCDB[12]; /* A CDB can be 12 bytes long. */

/** Reserved. */

uint8_t uReserved3[6];

/** Sense data pointer. */

uint32_t u32PhysAddrSenseData;

} CommandControlBlock, *PCommandControlBlock;

AssertCompileSize(CommandControlBlock, 40);

#pragma pack()

#pragma pack(1)

typedef struct ScatterGatherEntry

{

uint32_t cbSegment;

uint32_t u32PhysAddrSegmentBase;

} ScatterGatherEntry, *PScatterGatherEntry;

AssertCompileSize(ScatterGatherEntry, 8);

#pragma pack()

typedef struct BUSLOGICTASKSTATE

{

/** Next in the redo list. */

PBUSLOGICTASKSTATE pRedoNext;

/** Device this task is assigned to. */

R3PTRTYPE(PBUSLOGICDEVICE) pTargetDeviceR3;

/** The command control block from the guest. */

CommandControlBlock CommandControlBlockGuest;

/** Mailbox read from guest memory. */

Mailbox MailboxGuest;

/** The SCSI request we pass to the underlying SCSI engine. */

PDMSCSIREQUEST PDMScsiRequest;

/** Data buffer segment */

RTSGSEG DataSeg;

/** Pointer to the R3 sense buffer. */

uint8_t *pbSenseBuffer;

/** Flag whether this is a request from the BIOS. */

bool fBIOS;

} BUSLOGICTASKSTATE;

#ifndef VBOX_DEVICE_STRUCT_TESTCASE

#define PDMIBASE_2_PBUSLOGICDEVICE(pInterface) ( (PBUSLOGICDEVICE)((uintptr_t)(pInterface) - RT_OFFSETOF(BUSLOGICDEVICE, IBase)) )

#define PDMISCSIPORT_2_PBUSLOGICDEVICE(pInterface) ( (PBUSLOGICDEVICE)((uintptr_t)(pInterface) - RT_OFFSETOF(BUSLOGICDEVICE, ISCSIPort)) )

#define PDMILEDPORTS_2_PBUSLOGICDEVICE(pInterface) ( (PBUSLOGICDEVICE)((uintptr_t)(pInterface) - RT_OFFSETOF(BUSLOGICDEVICE, ILed)) )

#define PDMIBASE_2_PBUSLOGIC(pInterface) ( (PBUSLOGIC)((uintptr_t)(pInterface) - RT_OFFSETOF(BUSLOGIC, IBase)) )

#define PDMILEDPORTS_2_PBUSLOGIC(pInterface) ( (PBUSLOGIC)((uintptr_t)(pInterface) - RT_OFFSETOF(BUSLOGIC, ILeds)) )

static int buslogicRegisterISARange(PBUSLOGIC pBusLogic, uint8_t uBaseCode);

static void buslogicSetInterrupt(PBUSLOGIC pBusLogic, bool fSuppressIrq, uint8_t uIrqType)

{

LogFlowFunc(("pBusLogic=%#p\n", pBusLogic));

/* The CMDC interrupt has priority over IMBL and MBOR. */

if (uIrqType & (BUSLOGIC_REGISTER_INTERRUPT_INCOMING_MAILBOX_LOADED | BUSLOGIC_REGISTER_INTERRUPT_OUTGOING_MAILBOX_AVAILABLE))

{

if (!(pBusLogic->regInterrupt & BUSLOGIC_REGISTER_INTERRUPT_COMMAND_COMPLETE))

pBusLogic->regInterrupt |= uIrqType; /* Report now. */

else

pBusLogic->uPendingIntr |= uIrqType; /* Report later. */

}

else if (uIrqType & BUSLOGIC_REGISTER_INTERRUPT_COMMAND_COMPLETE)

{

Assert(!pBusLogic->regInterrupt);

pBusLogic->regInterrupt |= uIrqType;

}

else

AssertMsgFailed(("Invalid interrupt state!\n"));

pBusLogic->regInterrupt |= BUSLOGIC_REGISTER_INTERRUPT_INTERRUPT_VALID;

if (pBusLogic->fIRQEnabled && !fSuppressIrq)

PDMDevHlpPCISetIrq(pBusLogic->CTX_SUFF(pDevIns), 0, 1);

}

static void buslogicClearInterrupt(PBUSLOGIC pBusLogic)

{

LogFlowFunc(("pBusLogic=%#p\n", pBusLogic));

pBusLogic->regInterrupt = 0;

PDMDevHlpPCISetIrq(pBusLogic->CTX_SUFF(pDevIns), 0, 0);

/* If there's another pending interrupt, report it now. */

if (pBusLogic->uPendingIntr)

{

buslogicSetInterrupt(pBusLogic, false, pBusLogic->uPendingIntr);

pBusLogic->uPendingIntr = 0;

}

}

#if defined(IN_RING3)

DECLINLINE(void) buslogicOutgoingMailboxAdvance(PBUSLOGIC pBusLogic)

{

pBusLogic->uMailboxOutgoingPositionCurrent = (pBusLogic->uMailboxOutgoingPositionCurrent + 1) % pBusLogic->cMailbox;

}

DECLINLINE(RTGCPHYS) buslogicOutgoingMailboxGetGCPhys(PBUSLOGIC pBusLogic)

{

return pBusLogic->GCPhysAddrMailboxOutgoingBase + (pBusLogic->uMailboxOutgoingPositionCurrent * sizeof(Mailbox));

}

static void buslogicInitializeLocalRam(PBUSLOGIC pBusLogic)

{

/*

memset(pBusLogic->LocalRam.u8View, 0, sizeof(HostAdapterLocalRam));

pBusLogic->LocalRam.structured.autoSCSIData.fLevelSensitiveInterrupt = true;

pBusLogic->LocalRam.structured.autoSCSIData.fParityCheckingEnabled = true;

pBusLogic->LocalRam.structured.autoSCSIData.fExtendedTranslation = true; /* Same as in geometry register. */

pBusLogic->LocalRam.structured.autoSCSIData.u16DeviceEnabledMask = ~0; /* All enabled. Maybe mask out non present devices? */

pBusLogic->LocalRam.structured.autoSCSIData.u16WidePermittedMask = ~0;

pBusLogic->LocalRam.structured.autoSCSIData.u16FastPermittedMask = ~0;

pBusLogic->LocalRam.structured.autoSCSIData.u16SynchronousPermittedMask = ~0;

pBusLogic->LocalRam.structured.autoSCSIData.u16DisconnectPermittedMask = ~0;

pBusLogic->LocalRam.structured.autoSCSIData.fStrictRoundRobinMode = pBusLogic->fStrictRoundRobinMode;

pBusLogic->LocalRam.structured.autoSCSIData.u16UltraPermittedMask = ~0;

/* @todo calculate checksum? */

}

static int buslogicHwReset(PBUSLOGIC pBusLogic, bool fResetIO)

{

LogFlowFunc(("pBusLogic=%#p\n", pBusLogic));

/* Reset registers to default value. */

pBusLogic->regStatus = BUSLOGIC_REGISTER_STATUS_HOST_ADAPTER_READY | BUSLOGIC_REGISTER_STATUS_INITIALIZATION_REQUIRED;

pBusLogic->regInterrupt = 0;

pBusLogic->uPendingIntr = 0;

pBusLogic->regGeometry = BUSLOGIC_REGISTER_GEOMETRY_EXTENTED_TRANSLATION_ENABLED;

pBusLogic->uOperationCode = 0xff; /* No command executing. */

pBusLogic->iParameter = 0;

pBusLogic->cbCommandParametersLeft = 0;

pBusLogic->fIRQEnabled = true;

pBusLogic->uMailboxOutgoingPositionCurrent = 0;

pBusLogic->uMailboxIncomingPositionCurrent = 0;

/* Guest-initiated HBA reset does not affect ISA port I/O. */

if (fResetIO)

{

buslogicRegisterISARange(pBusLogic, pBusLogic->uDefaultISABaseCode);

}

buslogicInitializeLocalRam(pBusLogic);

vboxscsiInitialize(&pBusLogic->VBoxSCSI);

return VINF_SUCCESS;

}

#endif

static void buslogicCommandComplete(PBUSLOGIC pBusLogic, bool fSuppressIrq)

{

LogFlowFunc(("pBusLogic=%#p\n", pBusLogic));

pBusLogic->fUseLocalRam = false;

pBusLogic->regStatus |= BUSLOGIC_REGISTER_STATUS_HOST_ADAPTER_READY;

pBusLogic->iReply = 0;

/* Modify I/O address does not generate an interrupt. */

if (pBusLogic->uOperationCode != BUSLOGICCOMMAND_EXECUTE_MAILBOX_COMMAND)

{

/* Notify that the command is complete. */

pBusLogic->regStatus &= ~BUSLOGIC_REGISTER_STATUS_DATA_IN_REGISTER_READY;

buslogicSetInterrupt(pBusLogic, fSuppressIrq, BUSLOGIC_REGISTER_INTERRUPT_COMMAND_COMPLETE);

}

pBusLogic->uOperationCode = 0xff;

pBusLogic->iParameter = 0;

}

#if defined(IN_RING3)

static void buslogicInitiateReset(PBUSLOGIC pBusLogic, bool fHardReset)

{

LogFlowFunc(("pBusLogic=%#p fHardReset=%d\n", pBusLogic, fHardReset));

buslogicHwReset(pBusLogic, fHardReset);

if (fHardReset)

{

/* Set the diagnostic active bit in the status register and clear the ready state. */

pBusLogic->regStatus |= BUSLOGIC_REGISTER_STATUS_DIAGNOSTIC_ACTIVE;

pBusLogic->regStatus &= ~BUSLOGIC_REGISTER_STATUS_HOST_ADAPTER_READY;

/* Remember when the guest initiated a reset (after we're done resetting). */

pBusLogic->u64ResetTime = PDMDevHlpTMTimeVirtGetNano(pBusLogic->CTX_SUFF(pDevIns));

}

}

static void buslogicSendIncomingMailbox(PBUSLOGIC pBusLogic, PBUSLOGICTASKSTATE pTaskState,

uint8_t uHostAdapterStatus, uint8_t uDeviceStatus,

uint8_t uMailboxCompletionCode)

{

pTaskState->MailboxGuest.u.in.uHostAdapterStatus = uHostAdapterStatus;

pTaskState->MailboxGuest.u.in.uTargetDeviceStatus = uDeviceStatus;

pTaskState->MailboxGuest.u.in.uCompletionCode = uMailboxCompletionCode;

int rc = PDMCritSectEnter(&pBusLogic->CritSectIntr, VINF_SUCCESS);

AssertRC(rc);

RTGCPHYS GCPhysAddrMailboxIncoming = pBusLogic->GCPhysAddrMailboxIncomingBase + (pBusLogic->uMailboxIncomingPositionCurrent * sizeof(Mailbox));

RTGCPHYS GCPhysAddrCCB = (RTGCPHYS)pTaskState->MailboxGuest.u32PhysAddrCCB;

LogFlowFunc(("Completing CCB %RGp\n", GCPhysAddrCCB));

/* Update CCB. */

pTaskState->CommandControlBlockGuest.uHostAdapterStatus = uHostAdapterStatus;

pTaskState->CommandControlBlockGuest.uDeviceStatus = uDeviceStatus;

/* @todo: this is wrong - writing too much! */

PDMDevHlpPhysWrite(pBusLogic->CTX_SUFF(pDevIns), GCPhysAddrCCB, &pTaskState->CommandControlBlockGuest, sizeof(CommandControlBlock));

#ifdef RT_STRICT

Mailbox Tmp;

PDMDevHlpPhysRead(pBusLogic->CTX_SUFF(pDevIns), GCPhysAddrMailboxIncoming, &Tmp, sizeof(Mailbox));

Assert(Tmp.u.in.uCompletionCode == BUSLOGIC_MAILBOX_INCOMING_COMPLETION_FREE);

#endif

/* Update mailbox. */

PDMDevHlpPhysWrite(pBusLogic->CTX_SUFF(pDevIns), GCPhysAddrMailboxIncoming, &pTaskState->MailboxGuest, sizeof(Mailbox));

/* Advance to next mailbox position. */

pBusLogic->uMailboxIncomingPositionCurrent++;

if (pBusLogic->uMailboxIncomingPositionCurrent >= pBusLogic->cMailbox)

pBusLogic->uMailboxIncomingPositionCurrent = 0;

#ifdef LOG_ENABLED

ASMAtomicIncU32(&pBusLogic->cInMailboxesReady);

#endif

buslogicSetInterrupt(pBusLogic, false, BUSLOGIC_REGISTER_INTERRUPT_INCOMING_MAILBOX_LOADED);

PDMCritSectLeave(&pBusLogic->CritSectIntr);

}

#if defined(DEBUG)

static void buslogicDumpMailboxInfo(PMailbox pMailbox, bool fOutgoing)

{

Log(("%s: Dump for %s mailbox:\n", __FUNCTION__, fOutgoing ? "outgoing" : "incoming"));

Log(("%s: u32PhysAddrCCB=%#x\n", __FUNCTION__, pMailbox->u32PhysAddrCCB));

if (fOutgoing)

{

Log(("%s: uActionCode=%u\n", __FUNCTION__, pMailbox->u.out.uActionCode));

}

else

{

Log(("%s: uHostAdapterStatus=%u\n", __FUNCTION__, pMailbox->u.in.uHostAdapterStatus));

Log(("%s: uTargetDeviceStatus=%u\n", __FUNCTION__, pMailbox->u.in.uTargetDeviceStatus));

Log(("%s: uCompletionCode=%u\n", __FUNCTION__, pMailbox->u.in.uCompletionCode));

}

}

static void buslogicDumpCCBInfo(PCommandControlBlock pCCB)

{

Log(("%s: Dump for Command Control Block:\n", __FUNCTION__));

Log(("%s: uOpCode=%#x\n", __FUNCTION__, pCCB->uOpcode));

Log(("%s: uDataDirection=%u\n", __FUNCTION__, pCCB->uDataDirection));

Log(("%s: fTagQueued=%d\n", __FUNCTION__, pCCB->fTagQueued));

Log(("%s: uQueueTag=%u\n", __FUNCTION__, pCCB->uQueueTag));

Log(("%s: cbCDB=%u\n", __FUNCTION__, pCCB->cbCDB));

Log(("%s: cbSenseData=%u\n", __FUNCTION__, pCCB->cbSenseData));

Log(("%s: cbData=%u\n", __FUNCTION__, pCCB->cbData));

Log(("%s: u32PhysAddrData=%#x\n", __FUNCTION__, pCCB->u32PhysAddrData));

Log(("%s: uHostAdapterStatus=%u\n", __FUNCTION__, pCCB->uHostAdapterStatus));

Log(("%s: uDeviceStatus=%u\n", __FUNCTION__, pCCB->uDeviceStatus));

Log(("%s: uTargetId=%u\n", __FUNCTION__, pCCB->uTargetId));

Log(("%s: uLogicalUnit=%u\n", __FUNCTION__, pCCB->uLogicalUnit));

Log(("%s: fLegacyTagEnable=%u\n", __FUNCTION__, pCCB->fLegacyTagEnable));

Log(("%s: uLegacyQueueTag=%u\n", __FUNCTION__, pCCB->uLegacyQueueTag));

Log(("%s: uCDB[0]=%#x\n", __FUNCTION__, pCCB->aCDB[0]));

for (int i = 1; i < pCCB->cbCDB; i++)

Log(("%s: uCDB[%d]=%u\n", __FUNCTION__, i, pCCB->aCDB[i]));

Log(("%s: u32PhysAddrSenseData=%#x\n", __FUNCTION__, pCCB->u32PhysAddrSenseData));

}

#endif

static int buslogicDataBufferAlloc(PBUSLOGICTASKSTATE pTaskState)

{

PPDMDEVINS pDevIns = pTaskState->CTX_SUFF(pTargetDevice)->CTX_SUFF(pBusLogic)->CTX_SUFF(pDevIns);

if ( (pTaskState->CommandControlBlockGuest.uDataDirection != BUSLOGIC_CCB_DIRECTION_NO_DATA)

&& (pTaskState->CommandControlBlockGuest.cbData > 0))

{

/*

if ( (pTaskState->CommandControlBlockGuest.uOpcode == BUSLOGIC_CCB_OPCODE_INITIATOR_CCB_SCATTER_GATHER)

|| (pTaskState->CommandControlBlockGuest.uOpcode == BUSLOGIC_CCB_OPCODE_INITIATOR_CCB_RESIDUAL_SCATTER_GATHER))

{

uint32_t cScatterGatherGCRead;

uint32_t iScatterGatherEntry;

ScatterGatherEntry aScatterGatherReadGC[32]; /* Number of scatter gather list entries read from guest memory. */

uint32_t cScatterGatherGCLeft = pTaskState->CommandControlBlockGuest.cbData / sizeof(ScatterGatherEntry);

RTGCPHYS GCPhysAddrScatterGatherCurrent = (RTGCPHYS)pTaskState->CommandControlBlockGuest.u32PhysAddrData;

size_t cbDataToTransfer = 0;

/* Count number of bytes to transfer. */

do

{

cScatterGatherGCRead = (cScatterGatherGCLeft < RT_ELEMENTS(aScatterGatherReadGC))

? cScatterGatherGCLeft

: RT_ELEMENTS(aScatterGatherReadGC);

cScatterGatherGCLeft -= cScatterGatherGCRead;

/* Read the SG entries. */

PDMDevHlpPhysRead(pDevIns, GCPhysAddrScatterGatherCurrent, &aScatterGatherReadGC[0],

cScatterGatherGCRead * sizeof(ScatterGatherEntry));

for (iScatterGatherEntry = 0; iScatterGatherEntry < cScatterGatherGCRead; iScatterGatherEntry++)

{

RTGCPHYS GCPhysAddrDataBase;

Log(("%s: iScatterGatherEntry=%u\n", __FUNCTION__, iScatterGatherEntry));

GCPhysAddrDataBase = (RTGCPHYS)aScatterGatherReadGC[iScatterGatherEntry].u32PhysAddrSegmentBase;

cbDataToTransfer += aScatterGatherReadGC[iScatterGatherEntry].cbSegment;

Log(("%s: GCPhysAddrDataBase=%RGp cbDataToTransfer=%u\n",

__FUNCTION__, GCPhysAddrDataBase,

aScatterGatherReadGC[iScatterGatherEntry].cbSegment));

}

/* Set address to the next entries to read. */

GCPhysAddrScatterGatherCurrent += cScatterGatherGCRead * sizeof(ScatterGatherEntry);

} while (cScatterGatherGCLeft > 0);

Log(("%s: cbDataToTransfer=%d\n", __FUNCTION__, cbDataToTransfer));

/* Allocate buffer */

pTaskState->DataSeg.cbSeg = cbDataToTransfer;

pTaskState->DataSeg.pvSeg = RTMemAlloc(pTaskState->DataSeg.cbSeg);

if (!pTaskState->DataSeg.pvSeg)

return VERR_NO_MEMORY;

/* Copy the data if needed */

if (pTaskState->CommandControlBlockGuest.uDataDirection == BUSLOGIC_CCB_DIRECTION_OUT)

{

cScatterGatherGCLeft = pTaskState->CommandControlBlockGuest.cbData / sizeof(ScatterGatherEntry);

GCPhysAddrScatterGatherCurrent = (RTGCPHYS)pTaskState->CommandControlBlockGuest.u32PhysAddrData;

uint8_t *pbData = (uint8_t *)pTaskState->DataSeg.pvSeg;

do

{

cScatterGatherGCRead = (cScatterGatherGCLeft < RT_ELEMENTS(aScatterGatherReadGC))

? cScatterGatherGCLeft

: RT_ELEMENTS(aScatterGatherReadGC);

cScatterGatherGCLeft -= cScatterGatherGCRead;

/* Read the SG entries. */

PDMDevHlpPhysRead(pDevIns, GCPhysAddrScatterGatherCurrent, &aScatterGatherReadGC[0],

cScatterGatherGCRead * sizeof(ScatterGatherEntry));

for (iScatterGatherEntry = 0; iScatterGatherEntry < cScatterGatherGCRead; iScatterGatherEntry++)

{

RTGCPHYS GCPhysAddrDataBase;

Log(("%s: iScatterGatherEntry=%u\n", __FUNCTION__, iScatterGatherEntry));

GCPhysAddrDataBase = (RTGCPHYS)aScatterGatherReadGC[iScatterGatherEntry].u32PhysAddrSegmentBase;

cbDataToTransfer = aScatterGatherReadGC[iScatterGatherEntry].cbSegment;

Log(("%s: GCPhysAddrDataBase=%RGp cbDataToTransfer=%u\n", __FUNCTION__, GCPhysAddrDataBase, cbDataToTransfer));

PDMDevHlpPhysRead(pDevIns, GCPhysAddrDataBase, pbData, cbDataToTransfer);

pbData += cbDataToTransfer;

}

/* Set address to the next entries to read. */

GCPhysAddrScatterGatherCurrent += cScatterGatherGCRead * sizeof(ScatterGatherEntry);

} while (cScatterGatherGCLeft > 0);

}

}

else if ( pTaskState->CommandControlBlockGuest.uOpcode == BUSLOGIC_CCB_OPCODE_INITIATOR_CCB

|| pTaskState->CommandControlBlockGuest.uOpcode == BUSLOGIC_CCB_OPCODE_INITIATOR_CCB_RESIDUAL_DATA_LENGTH)

{

/* The buffer is not scattered. */

RTGCPHYS GCPhysAddrDataBase = (RTGCPHYS)pTaskState->CommandControlBlockGuest.u32PhysAddrData;

AssertMsg(GCPhysAddrDataBase != 0, ("Physical address is 0\n"));

pTaskState->DataSeg.cbSeg = pTaskState->CommandControlBlockGuest.cbData;

pTaskState->DataSeg.pvSeg = RTMemAlloc(pTaskState->DataSeg.cbSeg);

if (!pTaskState->DataSeg.pvSeg)

return VERR_NO_MEMORY;

Log(("Non scattered buffer:\n"));

Log(("u32PhysAddrData=%#x\n", pTaskState->CommandControlBlockGuest.u32PhysAddrData));

Log(("cbData=%u\n", pTaskState->CommandControlBlockGuest.cbData));

Log(("GCPhysAddrDataBase=0x%RGp\n", GCPhysAddrDataBase));

/* Copy the data into the buffer. */

PDMDevHlpPhysRead(pDevIns, GCPhysAddrDataBase, pTaskState->DataSeg.pvSeg, pTaskState->DataSeg.cbSeg);

}

}

return VINF_SUCCESS;

}

static void buslogicDataBufferFree(PBUSLOGICTASKSTATE pTaskState)

{

PPDMDEVINS pDevIns = pTaskState->CTX_SUFF(pTargetDevice)->CTX_SUFF(pBusLogic)->CTX_SUFF(pDevIns);

if ( (pTaskState->CommandControlBlockGuest.cbData > 0)

&& ( (pTaskState->CommandControlBlockGuest.uDataDirection == BUSLOGIC_CCB_DIRECTION_IN)

|| (pTaskState->CommandControlBlockGuest.uDataDirection == BUSLOGIC_CCB_DIRECTION_UNKNOWN)))

{

if ( (pTaskState->CommandControlBlockGuest.uOpcode == BUSLOGIC_CCB_OPCODE_INITIATOR_CCB_SCATTER_GATHER)

|| (pTaskState->CommandControlBlockGuest.uOpcode == BUSLOGIC_CCB_OPCODE_INITIATOR_CCB_RESIDUAL_SCATTER_GATHER))

{

uint32_t cScatterGatherGCRead;

uint32_t iScatterGatherEntry;

ScatterGatherEntry aScatterGatherReadGC[32]; /* Number of scatter gather list entries read from guest memory. */

uint32_t cScatterGatherGCLeft = pTaskState->CommandControlBlockGuest.cbData / sizeof(ScatterGatherEntry);

RTGCPHYS GCPhysAddrScatterGatherCurrent = (RTGCPHYS)pTaskState->CommandControlBlockGuest.u32PhysAddrData;

uint8_t *pbData = (uint8_t *)pTaskState->DataSeg.pvSeg;

do

{

cScatterGatherGCRead = (cScatterGatherGCLeft < RT_ELEMENTS(aScatterGatherReadGC))

? cScatterGatherGCLeft

: RT_ELEMENTS(aScatterGatherReadGC);

cScatterGatherGCLeft -= cScatterGatherGCRead;

/* Read the SG entries. */

PDMDevHlpPhysRead(pDevIns, GCPhysAddrScatterGatherCurrent, &aScatterGatherReadGC[0],

cScatterGatherGCRead * sizeof(ScatterGatherEntry));

for (iScatterGatherEntry = 0; iScatterGatherEntry < cScatterGatherGCRead; iScatterGatherEntry++)

{

RTGCPHYS GCPhysAddrDataBase;

size_t cbDataToTransfer;

Log(("%s: iScatterGatherEntry=%u\n", __FUNCTION__, iScatterGatherEntry));

GCPhysAddrDataBase = (RTGCPHYS)aScatterGatherReadGC[iScatterGatherEntry].u32PhysAddrSegmentBase;

cbDataToTransfer = aScatterGatherReadGC[iScatterGatherEntry].cbSegment;

Log(("%s: GCPhysAddrDataBase=%RGp cbDataToTransfer=%u\n", __FUNCTION__, GCPhysAddrDataBase, cbDataToTransfer));

PDMDevHlpPhysWrite(pDevIns, GCPhysAddrDataBase, pbData, cbDataToTransfer);

pbData += cbDataToTransfer;

}

/* Set address to the next entries to read. */

GCPhysAddrScatterGatherCurrent += cScatterGatherGCRead * sizeof(ScatterGatherEntry);

} while (cScatterGatherGCLeft > 0);

}

else if ( pTaskState->CommandControlBlockGuest.uOpcode == BUSLOGIC_CCB_OPCODE_INITIATOR_CCB

|| pTaskState->CommandControlBlockGuest.uOpcode == BUSLOGIC_CCB_OPCODE_INITIATOR_CCB_RESIDUAL_DATA_LENGTH)

{

/* The buffer is not scattered. */

RTGCPHYS GCPhysAddrDataBase = (RTGCPHYS)pTaskState->CommandControlBlockGuest.u32PhysAddrData;

AssertMsg(GCPhysAddrDataBase != 0, ("Physical address is 0\n"));

Log(("Non scattered buffer:\n"));

Log(("u32PhysAddrData=%#x\n", pTaskState->CommandControlBlockGuest.u32PhysAddrData));

Log(("cbData=%u\n", pTaskState->CommandControlBlockGuest.cbData));

Log(("GCPhysAddrDataBase=0x%RGp\n", GCPhysAddrDataBase));

/* Copy the data into the guest memory. */

PDMDevHlpPhysWrite(pDevIns, GCPhysAddrDataBase, pTaskState->DataSeg.pvSeg, pTaskState->DataSeg.cbSeg);

}

}

RTMemFree(pTaskState->DataSeg.pvSeg);

pTaskState->DataSeg.pvSeg = NULL;

pTaskState->DataSeg.cbSeg = 0;

}

static uint32_t buslogicConvertSenseBufferLength(uint32_t cbSense)

{

/* Convert special sense buffer length values. */

if (cbSense == 0)

cbSense = 14; /* 0 means standard 14-byte buffer. */

else if (cbSense == 1)

cbSense = 0; /* 1 means no sense data. */

else if (cbSense < 8)

AssertMsgFailed(("Reserved cbSense value of %d used!\n", cbSense));

return cbSense;

}

static void buslogicSenseBufferFree(PBUSLOGICTASKSTATE pTaskState, bool fCopy)

{

uint32_t cbSenseBuffer;

cbSenseBuffer = buslogicConvertSenseBufferLength(pTaskState->CommandControlBlockGuest.cbSenseData);

/* Copy the sense buffer into guest memory if requested. */

if (fCopy && cbSenseBuffer)

{

PPDMDEVINS pDevIns = pTaskState->CTX_SUFF(pTargetDevice)->CTX_SUFF(pBusLogic)->CTX_SUFF(pDevIns);

RTGCPHYS GCPhysAddrSenseBuffer = (RTGCPHYS)pTaskState->CommandControlBlockGuest.u32PhysAddrSenseData;

PDMDevHlpPhysWrite(pDevIns, GCPhysAddrSenseBuffer, pTaskState->pbSenseBuffer, cbSenseBuffer);

}

RTMemFree(pTaskState->pbSenseBuffer);

pTaskState->pbSenseBuffer = NULL;

}

static int buslogicSenseBufferAlloc(PBUSLOGICTASKSTATE pTaskState)

{

PPDMDEVINS pDevIns = pTaskState->CTX_SUFF(pTargetDevice)->CTX_SUFF(pBusLogic)->CTX_SUFF(pDevIns);

uint32_t cbSenseBuffer;

pTaskState->pbSenseBuffer = NULL;

cbSenseBuffer = buslogicConvertSenseBufferLength(pTaskState->CommandControlBlockGuest.cbSenseData);

if (cbSenseBuffer)

{

pTaskState->pbSenseBuffer = (uint8_t *)RTMemAllocZ(cbSenseBuffer);

if (!pTaskState->pbSenseBuffer)

return VERR_NO_MEMORY;

}

return VINF_SUCCESS;

}

#endif /* IN_RING3 */

static int buslogicProcessCommand(PBUSLOGIC pBusLogic)

{

int rc = VINF_SUCCESS;

bool fSuppressIrq = false;

LogFlowFunc(("pBusLogic=%#p\n", pBusLogic));

AssertMsg(pBusLogic->uOperationCode != 0xff, ("There is no command to execute\n"));

switch (pBusLogic->uOperationCode)

{

case BUSLOGICCOMMAND_TEST_CMDC_INTERRUPT:

/* Valid command, no reply. */

pBusLogic->cbReplyParametersLeft = 0;

break;

case BUSLOGICCOMMAND_INQUIRE_PCI_HOST_ADAPTER_INFORMATION:

{

PReplyInquirePCIHostAdapterInformation pReply = (PReplyInquirePCIHostAdapterInformation)pBusLogic->aReplyBuffer;

memset(pReply, 0, sizeof(ReplyInquirePCIHostAdapterInformation));

/* It seems VMware does not provide valid information here too, lets do the same :) */

pReply->InformationIsValid = 0;

pReply->IsaIOPort = pBusLogic->uISABaseCode;

pReply->IRQ = PCIDevGetInterruptLine(&pBusLogic->dev);

pBusLogic->cbReplyParametersLeft = sizeof(ReplyInquirePCIHostAdapterInformation);

break;

}

case BUSLOGICCOMMAND_MODIFY_IO_ADDRESS:

{

/* Modify the ISA-compatible I/O port base. Note that this technically

#ifdef IN_RING3

Log(("ISA I/O for PCI (code %x)\n", pBusLogic->aCommandBuffer[0]));

buslogicRegisterISARange(pBusLogic, pBusLogic->aCommandBuffer[0]);

pBusLogic->cbReplyParametersLeft = 0;

fSuppressIrq = true;

break;

#else

AssertMsgFailed(("Must never get here!\n"));

#endif

}

case BUSLOGICCOMMAND_INQUIRE_BOARD_ID:

{

/* The special option byte is important: If it is '0' or 'B', Windows NT drivers

pBusLogic->aReplyBuffer[0] = 'A'; /* Firmware option bytes */

pBusLogic->aReplyBuffer[1] = 'A'; /* Special option byte */

/* We report version 5.07B. This reply will provide the first two digits. */

pBusLogic->aReplyBuffer[2] = '5'; /* Major version 5 */

pBusLogic->aReplyBuffer[3] = '0'; /* Minor version 0 */

pBusLogic->cbReplyParametersLeft = 4; /* Reply is 4 bytes long */

break;

}

case BUSLOGICCOMMAND_INQUIRE_FIRMWARE_VERSION_3RD_LETTER:

{

pBusLogic->aReplyBuffer[0] = '7';

pBusLogic->cbReplyParametersLeft = 1;

break;

}

case BUSLOGICCOMMAND_INQUIRE_FIRMWARE_VERSION_LETTER:

{

pBusLogic->aReplyBuffer[0] = 'B';

pBusLogic->cbReplyParametersLeft = 1;

break;

}

case BUSLOGICCOMMAND_SET_ADAPTER_OPTIONS:

/* The parameter list length is determined by the first byte of the command buffer. */

if (pBusLogic->iParameter == 1)

{

/* First pass - set the number of following parameter bytes. */

pBusLogic->cbCommandParametersLeft = pBusLogic->aCommandBuffer[0];

Log(("Set HA options: %u bytes follow\n", pBusLogic->cbCommandParametersLeft));

}

else

{

/* Second pass - process received data. */

Log(("Set HA options: received %u bytes\n", pBusLogic->aCommandBuffer[0]));

/* We ignore the data - it only concerns the SCSI hardware protocol. */

}

pBusLogic->cbReplyParametersLeft = 0;

break;

case BUSLOGICCOMMAND_INQUIRE_HOST_ADAPTER_MODEL_NUMBER:

{

/* The reply length is set by the guest and is found in the first byte of the command buffer. */

pBusLogic->cbReplyParametersLeft = pBusLogic->aCommandBuffer[0];

memset(pBusLogic->aReplyBuffer, ' ', pBusLogic->cbReplyParametersLeft);

const char aModelName[] = "958";

int cCharsToTransfer = (pBusLogic->cbReplyParametersLeft <= (sizeof(aModelName) - 1))

? pBusLogic->cbReplyParametersLeft

: sizeof(aModelName) - 1;

for (int i = 0; i < cCharsToTransfer; i++)

pBusLogic->aReplyBuffer[i] = aModelName[i];

break;

}

case BUSLOGICCOMMAND_INQUIRE_CONFIGURATION:

{

uint8_t uPciIrq = PCIDevGetInterruptLine(&pBusLogic->dev);

pBusLogic->cbReplyParametersLeft = sizeof(ReplyInquireConfiguration);

PReplyInquireConfiguration pReply = (PReplyInquireConfiguration)pBusLogic->aReplyBuffer;

memset(pReply, 0, sizeof(ReplyInquireConfiguration));

pReply->uHostAdapterId = 7; /* The controller has always 7 as ID. */

pReply->fDmaChannel6 = 1; /* DMA channel 6 is a good default. */

/* The PCI IRQ is not necessarily representable in this structure.

switch (uPciIrq) {

case 9: pReply->fIrqChannel9 = 1; break;

case 10: pReply->fIrqChannel10 = 1; break;

case 11: pReply->fIrqChannel11 = 1; break;

case 12: pReply->fIrqChannel12 = 1; break;

case 14: pReply->fIrqChannel14 = 1; break;

case 15: pReply->fIrqChannel15 = 1; break;

default:

LogRel(("Warning: PCI IRQ %d cannot be represented as ISA!\n", uPciIrq));

break;

}

break;

}

case BUSLOGICCOMMAND_INQUIRE_EXTENDED_SETUP_INFORMATION:

{

/* Some Adaptec AHA-154x drivers (e.g. OS/2) execute this command and expect

/* The reply length is set by the guest and is found in the first byte of the command buffer. */

pBusLogic->cbReplyParametersLeft = pBusLogic->aCommandBuffer[0];

PReplyInquireExtendedSetupInformation pReply = (PReplyInquireExtendedSetupInformation)pBusLogic->aReplyBuffer;

memset(pReply, 0, sizeof(ReplyInquireExtendedSetupInformation));

//@todo: should this reflect the RAM contents (AutoSCSIRam)?

pReply->uBusType = 'E'; /* EISA style */

pReply->u16ScatterGatherLimit = 8192;

pReply->cMailbox = pBusLogic->cMailbox;

pReply->uMailboxAddressBase = (uint32_t)pBusLogic->GCPhysAddrMailboxOutgoingBase;

pReply->fLevelSensitiveInterrupt = true;

pReply->fHostWideSCSI = true;

pReply->fHostUltraSCSI = true;

memcpy(pReply->aFirmwareRevision, "07B", sizeof(pReply->aFirmwareRevision));

break;

}

case BUSLOGICCOMMAND_INQUIRE_SETUP_INFORMATION:

{

/* The reply length is set by the guest and is found in the first byte of the command buffer. */

pBusLogic->cbReplyParametersLeft = pBusLogic->aCommandBuffer[0];

PReplyInquireSetupInformation pReply = (PReplyInquireSetupInformation)pBusLogic->aReplyBuffer;

memset(pReply, 0, sizeof(ReplyInquireSetupInformation));

pReply->fSynchronousInitiationEnabled = true;

pReply->fParityCheckingEnabled = true;

pReply->cMailbox = pBusLogic->cMailbox;

pReply->uSignature = 'B';

/* The 'D' signature prevents Adaptec's OS/2 drivers from getting too

pReply->uCharacterD = 'D'; /* BusLogic model. */

pReply->uHostBusType = 'F'; /* PCI bus. */

break;

}

case BUSLOGICCOMMAND_FETCH_HOST_ADAPTER_LOCAL_RAM:

{

/*

uint8_t uOffset = pBusLogic->aCommandBuffer[0];

pBusLogic->cbReplyParametersLeft = pBusLogic->aCommandBuffer[1];

pBusLogic->fUseLocalRam = true;

pBusLogic->iReply = uOffset;

break;

}

case BUSLOGICCOMMAND_INITIALIZE_EXTENDED_MAILBOX:

{

PRequestInitializeExtendedMailbox pRequest = (PRequestInitializeExtendedMailbox)pBusLogic->aCommandBuffer;

pBusLogic->cMailbox = pRequest->cMailbox;

pBusLogic->GCPhysAddrMailboxOutgoingBase = (RTGCPHYS)pRequest->uMailboxBaseAddress;

/* The area for incoming mailboxes is right after the last entry of outgoing mailboxes. */

pBusLogic->GCPhysAddrMailboxIncomingBase = (RTGCPHYS)pRequest->uMailboxBaseAddress + (pBusLogic->cMailbox * sizeof(Mailbox));

Log(("GCPhysAddrMailboxOutgoingBase=%RGp\n", pBusLogic->GCPhysAddrMailboxOutgoingBase));

Log(("GCPhysAddrMailboxIncomingBase=%RGp\n", pBusLogic->GCPhysAddrMailboxIncomingBase));

Log(("cMailboxes=%u (32-bit mode)\n", pBusLogic->cMailbox));

LogRel(("Initialized 32-bit mailbox, %d entries at %08x\n", pRequest->cMailbox, pRequest->uMailboxBaseAddress));

pBusLogic->regStatus &= ~BUSLOGIC_REGISTER_STATUS_INITIALIZATION_REQUIRED;

pBusLogic->cbReplyParametersLeft = 0;

break;

}

case BUSLOGICCOMMAND_ENABLE_STRICT_ROUND_ROBIN_MODE:

{

if (pBusLogic->aCommandBuffer[0] == 0)

pBusLogic->fStrictRoundRobinMode = false;

else if (pBusLogic->aCommandBuffer[0] == 1)

pBusLogic->fStrictRoundRobinMode = true;

else

AssertMsgFailed(("Invalid round robin mode %d\n", pBusLogic->aCommandBuffer[0]));

pBusLogic->cbReplyParametersLeft = 0;

break;

}

case BUSLOGICCOMMAND_SET_CCB_FORMAT:

{

if (pBusLogic->aCommandBuffer[0] == 0)

pBusLogic->fExtendedLunCCBFormat = false;

else if (pBusLogic->aCommandBuffer[0] == 1)

pBusLogic->fExtendedLunCCBFormat = true;

else

AssertMsgFailed(("Invalid CCB format %d\n", pBusLogic->aCommandBuffer[0]));

pBusLogic->cbReplyParametersLeft = 0;

break;

}

case BUSLOGICCOMMAND_INQUIRE_INSTALLED_DEVICES_ID_0_TO_7:

/* This is supposed to send TEST UNIT READY to each target/LUN.

memset(pBusLogic->aReplyBuffer, 0, 8);

for (int i = 0; i < 8; ++i)

{

if (pBusLogic->aDeviceStates[i].fPresent)

pBusLogic->aReplyBuffer[i] = 1;

}

pBusLogic->aReplyBuffer[7] = 0; /* HA hardcoded at ID 7. */

pBusLogic->cbReplyParametersLeft = 8;

break;

case BUSLOGICCOMMAND_INQUIRE_INSTALLED_DEVICES_ID_8_TO_15:

/* See note about cheating above. */

memset(pBusLogic->aReplyBuffer, 0, 8);

for (int i = 0; i < 8; ++i)

{

if (pBusLogic->aDeviceStates[i + 8].fPresent)

pBusLogic->aReplyBuffer[i] = 1;

}

pBusLogic->cbReplyParametersLeft = 8;

break;

case BUSLOGICCOMMAND_INQUIRE_TARGET_DEVICES:

{

/* Each bit which is set in the 16bit wide variable means a present device. */

uint16_t u16TargetsPresentMask = 0;

for (uint8_t i = 0; i < RT_ELEMENTS(pBusLogic->aDeviceStates); i++)

{

if (pBusLogic->aDeviceStates[i].fPresent)

u16TargetsPresentMask |= (1 << i);

}

pBusLogic->aReplyBuffer[0] = (uint8_t)u16TargetsPresentMask;

pBusLogic->aReplyBuffer[1] = (uint8_t)(u16TargetsPresentMask >> 8);

pBusLogic->cbReplyParametersLeft = 2;

break;

}

case BUSLOGICCOMMAND_INQUIRE_SYNCHRONOUS_PERIOD:

{

pBusLogic->cbReplyParametersLeft = pBusLogic->aCommandBuffer[0];

for (uint8_t i = 0; i < pBusLogic->cbReplyParametersLeft; i++)

pBusLogic->aReplyBuffer[i] = 0; /* @todo Figure if we need something other here. It's not needed for the linux driver */

break;

}

case BUSLOGICCOMMAND_DISABLE_HOST_ADAPTER_INTERRUPT:

{

if (pBusLogic->aCommandBuffer[0] == 0)

pBusLogic->fIRQEnabled = false;

else

pBusLogic->fIRQEnabled = true;

/* No interrupt signaled regardless of enable/disable. */

fSuppressIrq = true;

break;

}

case BUSLOGICCOMMAND_ECHO_COMMAND_DATA:

{

pBusLogic->aReplyBuffer[0] = pBusLogic->aCommandBuffer[0];

pBusLogic->cbReplyParametersLeft = 1;

break;

}

case BUSLOGICCOMMAND_SET_PREEMPT_TIME_ON_BUS:

{

pBusLogic->cbReplyParametersLeft = 0;

pBusLogic->LocalRam.structured.autoSCSIData.uBusOnDelay = pBusLogic->aCommandBuffer[0];

Log(("Bus-on time: %d\n", pBusLogic->aCommandBuffer[0]));

break;

}

case BUSLOGICCOMMAND_SET_TIME_OFF_BUS:

{

pBusLogic->cbReplyParametersLeft = 0;

pBusLogic->LocalRam.structured.autoSCSIData.uBusOffDelay = pBusLogic->aCommandBuffer[0];

Log(("Bus-off time: %d\n", pBusLogic->aCommandBuffer[0]));

break;

}

case BUSLOGICCOMMAND_SET_BUS_TRANSFER_RATE:

{

pBusLogic->cbReplyParametersLeft = 0;

pBusLogic->LocalRam.structured.autoSCSIData.uDMATransferRate = pBusLogic->aCommandBuffer[0];

Log(("Bus transfer rate: %02X\n", pBusLogic->aCommandBuffer[0]));

break;

}

default:

AssertMsgFailed(("Invalid command %#x\n", pBusLogic->uOperationCode));

case BUSLOGICCOMMAND_EXT_BIOS_INFO:

case BUSLOGICCOMMAND_UNLOCK_MAILBOX:

/* Commands valid for Adaptec 154xC which we don't handle since

Log(("Command %#x not valid for this adapter\n", pBusLogic->uOperationCode));

pBusLogic->cbReplyParametersLeft = 0;

pBusLogic->regStatus |= BUSLOGIC_REGISTER_STATUS_COMMAND_INVALID;

break;

case BUSLOGICCOMMAND_EXECUTE_MAILBOX_COMMAND: /* Should be handled already. */

AssertMsgFailed(("Invalid mailbox execute state!\n"));

}

Log(("uOperationCode=%#x, cbReplyParametersLeft=%d\n", pBusLogic->uOperationCode, pBusLogic->cbReplyParametersLeft));

/* Set the data in ready bit in the status register in case the command has a reply. */

if (pBusLogic->cbReplyParametersLeft)

pBusLogic->regStatus |= BUSLOGIC_REGISTER_STATUS_DATA_IN_REGISTER_READY;

else if (!pBusLogic->cbCommandParametersLeft)

buslogicCommandComplete(pBusLogic, fSuppressIrq);

return rc;

}

static int buslogicRegisterRead(PBUSLOGIC pBusLogic, unsigned iRegister, uint32_t *pu32)

{

int rc = VINF_SUCCESS;

switch (iRegister)

{

case BUSLOGIC_REGISTER_STATUS:

{

*pu32 = pBusLogic->regStatus;

/* If the diagnostic active bit is set, we are in a guest-initiated

if (pBusLogic->regStatus & BUSLOGIC_REGISTER_STATUS_DIAGNOSTIC_ACTIVE)

{

uint64_t u64AccessTime = PDMDevHlpTMTimeVirtGetNano(pBusLogic->CTX_SUFF(pDevIns));

pBusLogic->regStatus &= ~BUSLOGIC_REGISTER_STATUS_DIAGNOSTIC_ACTIVE;

pBusLogic->regStatus |= BUSLOGIC_REGISTER_STATUS_HOST_ADAPTER_READY;

if (u64AccessTime - pBusLogic->u64ResetTime > BUSLOGIC_RESET_DURATION_NS)

{

/* If reset already expired, let the guest see that right away. */

*pu32 = pBusLogic->regStatus;

pBusLogic->u64ResetTime = 0;

}

}

break;

}

case BUSLOGIC_REGISTER_DATAIN:

{

if (pBusLogic->fUseLocalRam)

*pu32 = pBusLogic->LocalRam.u8View[pBusLogic->iReply];

else

*pu32 = pBusLogic->aReplyBuffer[pBusLogic->iReply];

/* Careful about underflow - guest can read data register even if

if (pBusLogic->cbReplyParametersLeft)

{

pBusLogic->iReply++;

pBusLogic->cbReplyParametersLeft--;

if (!pBusLogic->cbReplyParametersLeft)

{

/*

buslogicCommandComplete(pBusLogic, false);

}

}

LogFlowFunc(("data=%02x, iReply=%d, cbReplyParametersLeft=%u\n", *pu32,

pBusLogic->iReply, pBusLogic->cbReplyParametersLeft));

break;

}

case BUSLOGIC_REGISTER_INTERRUPT:

{

*pu32 = pBusLogic->regInterrupt;

break;

}

case BUSLOGIC_REGISTER_GEOMETRY:

{

*pu32 = pBusLogic->regGeometry;

break;

}

default:

*pu32 = UINT32_C(0xffffffff);

}

Log2(("%s: pu32=%p:{%.*Rhxs} iRegister=%d rc=%Rrc\n",

__FUNCTION__, pu32, 1, pu32, iRegister, rc));

return rc;

}

static int buslogicRegisterWrite(PBUSLOGIC pBusLogic, unsigned iRegister, uint8_t uVal)

{

int rc = VINF_SUCCESS;

switch (iRegister)

{

case BUSLOGIC_REGISTER_CONTROL:

{

if ((uVal & BUSLOGIC_REGISTER_CONTROL_HARD_RESET) || (uVal & BUSLOGIC_REGISTER_CONTROL_SOFT_RESET))

{

#ifdef IN_RING3

bool fHardReset = !!(uVal & BUSLOGIC_REGISTER_CONTROL_HARD_RESET);

LogRel(("BusLogic: %s reset\n", fHardReset ? "hard" : "soft"));

buslogicInitiateReset(pBusLogic, fHardReset);

#else

rc = VINF_IOM_R3_IOPORT_WRITE;

#endif

break;

}

rc = PDMCritSectEnter(&pBusLogic->CritSectIntr, VINF_IOM_R3_IOPORT_WRITE);

if (rc != VINF_SUCCESS)

return rc;

#ifdef LOG_ENABLED

uint32_t cMailboxesReady = ASMAtomicXchgU32(&pBusLogic->cInMailboxesReady, 0);

Log(("%u incoming mailboxes were ready when this interrupt was cleared\n", cMailboxesReady));

#endif

if (uVal & BUSLOGIC_REGISTER_CONTROL_INTERRUPT_RESET)

buslogicClearInterrupt(pBusLogic);

PDMCritSectLeave(&pBusLogic->CritSectIntr);

break;

}

case BUSLOGIC_REGISTER_COMMAND:

{

/* Fast path for mailbox execution command. */

if ((uVal == BUSLOGICCOMMAND_EXECUTE_MAILBOX_COMMAND) && (pBusLogic->uOperationCode == 0xff))

{

ASMAtomicIncU32(&pBusLogic->cMailboxesReady);

if (!ASMAtomicXchgBool(&pBusLogic->fNotificationSend, true))

{

/* Send new notification to the queue. */

PPDMQUEUEITEMCORE pItem = PDMQueueAlloc(pBusLogic->CTX_SUFF(pNotifierQueue));

AssertMsg(pItem, ("Allocating item for queue failed\n"));

PDMQueueInsert(pBusLogic->CTX_SUFF(pNotifierQueue), (PPDMQUEUEITEMCORE)pItem);

}

return rc;

}

/*

if (pBusLogic->uOperationCode == 0xff)

{

pBusLogic->uOperationCode = uVal;

pBusLogic->iParameter = 0;

/* Mark host adapter as busy and clear the invalid status bit. */

pBusLogic->regStatus &= ~(BUSLOGIC_REGISTER_STATUS_HOST_ADAPTER_READY | BUSLOGIC_REGISTER_STATUS_COMMAND_INVALID);

/* Get the number of bytes for parameters from the command code. */

switch (pBusLogic->uOperationCode)

{

case BUSLOGICCOMMAND_TEST_CMDC_INTERRUPT:

case BUSLOGICCOMMAND_INQUIRE_FIRMWARE_VERSION_LETTER:

case BUSLOGICCOMMAND_INQUIRE_BOARD_ID:

case BUSLOGICCOMMAND_INQUIRE_FIRMWARE_VERSION_3RD_LETTER:

case BUSLOGICCOMMAND_INQUIRE_PCI_HOST_ADAPTER_INFORMATION:

case BUSLOGICCOMMAND_INQUIRE_CONFIGURATION:

case BUSLOGICCOMMAND_INQUIRE_INSTALLED_DEVICES_ID_0_TO_7:

case BUSLOGICCOMMAND_INQUIRE_INSTALLED_DEVICES_ID_8_TO_15:

case BUSLOGICCOMMAND_INQUIRE_TARGET_DEVICES:

pBusLogic->cbCommandParametersLeft = 0;

break;

case BUSLOGICCOMMAND_MODIFY_IO_ADDRESS:

case BUSLOGICCOMMAND_INQUIRE_EXTENDED_SETUP_INFORMATION:

case BUSLOGICCOMMAND_INQUIRE_SETUP_INFORMATION:

case BUSLOGICCOMMAND_INQUIRE_HOST_ADAPTER_MODEL_NUMBER:

case BUSLOGICCOMMAND_ENABLE_STRICT_ROUND_ROBIN_MODE:

case BUSLOGICCOMMAND_SET_CCB_FORMAT:

case BUSLOGICCOMMAND_INQUIRE_SYNCHRONOUS_PERIOD:

case BUSLOGICCOMMAND_DISABLE_HOST_ADAPTER_INTERRUPT:

case BUSLOGICCOMMAND_ECHO_COMMAND_DATA:

case BUSLOGICCOMMAND_SET_PREEMPT_TIME_ON_BUS:

case BUSLOGICCOMMAND_SET_TIME_OFF_BUS:

case BUSLOGICCOMMAND_SET_BUS_TRANSFER_RATE:

pBusLogic->cbCommandParametersLeft = 1;

break;

case BUSLOGICCOMMAND_FETCH_HOST_ADAPTER_LOCAL_RAM:

pBusLogic->cbCommandParametersLeft = 2;

break;

case BUSLOGICCOMMAND_INITIALIZE_EXTENDED_MAILBOX:

pBusLogic->cbCommandParametersLeft = sizeof(RequestInitializeExtendedMailbox);

break;

case BUSLOGICCOMMAND_SET_ADAPTER_OPTIONS:

/* There must be at least one byte following this command. */

pBusLogic->cbCommandParametersLeft = 1;

break;

case BUSLOGICCOMMAND_EXT_BIOS_INFO:

case BUSLOGICCOMMAND_UNLOCK_MAILBOX:

/* Invalid commands. */

pBusLogic->cbCommandParametersLeft = 0;

break;

case BUSLOGICCOMMAND_EXECUTE_MAILBOX_COMMAND: /* Should not come here anymore. */

default:

AssertMsgFailed(("Invalid operation code %#x\n", uVal));

}

}

else

{

#ifndef IN_RING3

/* This command must be executed in R3 as it rehooks the ISA I/O port. */

if (pBusLogic->uOperationCode == BUSLOGICCOMMAND_MODIFY_IO_ADDRESS)

{

rc = VINF_IOM_R3_IOPORT_WRITE;

break;

}

#endif

/*

pBusLogic->aCommandBuffer[pBusLogic->iParameter] = uVal;

pBusLogic->iParameter++;

pBusLogic->cbCommandParametersLeft--;

}

/* Start execution of command if there are no parameters left. */

if (!pBusLogic->cbCommandParametersLeft)

{

rc = buslogicProcessCommand(pBusLogic);

AssertMsgRC(rc, ("Processing command failed rc=%Rrc\n", rc));

}

break;

}

/* On BusLogic adapters, the interrupt and geometry registers are R/W.

case BUSLOGIC_REGISTER_INTERRUPT:

pBusLogic->regInterrupt = uVal;

break;

case BUSLOGIC_REGISTER_GEOMETRY:

pBusLogic->regGeometry = uVal;

break;

default:

AssertMsgFailed(("Register not available\n"));

rc = VERR_IOM_IOPORT_UNUSED;

}

return rc;

}

PDMBOTHCBDECL(int) buslogicMMIORead(PPDMDEVINS pDevIns, void *pvUser,

RTGCPHYS GCPhysAddr, void *pv, unsigned cb)

{

/* the linux driver does not make use of the MMIO area. */

AssertMsgFailed(("MMIO Read\n"));

return VINF_SUCCESS;

}

PDMBOTHCBDECL(int) buslogicMMIOWrite(PPDMDEVINS pDevIns, void *pvUser,

RTGCPHYS GCPhysAddr, void const *pv, unsigned cb)

{

/* the linux driver does not make use of the MMIO area. */

AssertMsgFailed(("MMIO Write\n"));

return VINF_SUCCESS;

}

PDMBOTHCBDECL(int) buslogicIOPortRead (PPDMDEVINS pDevIns, void *pvUser,

RTIOPORT Port, uint32_t *pu32, unsigned cb)

{

PBUSLOGIC pBusLogic = PDMINS_2_DATA(pDevIns, PBUSLOGIC);

unsigned iRegister = Port % 4;

Assert(cb == 1);

return buslogicRegisterRead(pBusLogic, iRegister, pu32);

}

PDMBOTHCBDECL(int) buslogicIOPortWrite (PPDMDEVINS pDevIns, void *pvUser,

RTIOPORT Port, uint32_t u32, unsigned cb)

{

PBUSLOGIC pBusLogic = PDMINS_2_DATA(pDevIns, PBUSLOGIC);

int rc = VINF_SUCCESS;

unsigned iRegister = Port % 4;

uint8_t uVal = (uint8_t)u32;

Assert(cb == 1);

rc = buslogicRegisterWrite(pBusLogic, iRegister, (uint8_t)uVal);

Log2(("#%d %s: pvUser=%#p cb=%d u32=%#x Port=%#x rc=%Rrc\n",

pDevIns->iInstance, __FUNCTION__, pvUser, cb, u32, Port, rc));

return rc;

}

#ifdef IN_RING3

static int buslogicPrepareBIOSSCSIRequest(PBUSLOGIC pBusLogic)

{

int rc;

PBUSLOGICTASKSTATE pTaskState;

uint32_t uTargetDevice;

rc = RTMemCacheAllocEx(pBusLogic->hTaskCache, (void **)&pTaskState);

AssertMsgRCReturn(rc, ("Getting task from cache failed rc=%Rrc\n", rc), rc);

pTaskState->fBIOS = true;

rc = vboxscsiSetupRequest(&pBusLogic->VBoxSCSI, &pTaskState->PDMScsiRequest, &uTargetDevice);

AssertMsgRCReturn(rc, ("Setting up SCSI request failed rc=%Rrc\n", rc), rc);

pTaskState->PDMScsiRequest.pvUser = pTaskState;

pTaskState->CTX_SUFF(pTargetDevice) = &pBusLogic->aDeviceStates[uTargetDevice];

if (!pTaskState->CTX_SUFF(pTargetDevice)->fPresent)

{

/* Device is not present. */

AssertMsg(pTaskState->PDMScsiRequest.pbCDB[0] == SCSI_INQUIRY,

("Device is not present but command is not inquiry\n"));

SCSIINQUIRYDATA ScsiInquiryData;

memset(&ScsiInquiryData, 0, sizeof(SCSIINQUIRYDATA));

ScsiInquiryData.u5PeripheralDeviceType = SCSI_INQUIRY_DATA_PERIPHERAL_DEVICE_TYPE_UNKNOWN;

ScsiInquiryData.u3PeripheralQualifier = SCSI_INQUIRY_DATA_PERIPHERAL_QUALIFIER_NOT_CONNECTED_NOT_SUPPORTED;

memcpy(pBusLogic->VBoxSCSI.pBuf, &ScsiInquiryData, 5);

rc = vboxscsiRequestFinished(&pBusLogic->VBoxSCSI, &pTaskState->PDMScsiRequest, SCSI_STATUS_OK);

AssertMsgRCReturn(rc, ("Finishing BIOS SCSI request failed rc=%Rrc\n", rc), rc);

RTMemCacheFree(pBusLogic->hTaskCache, pTaskState);

}

else

{

LogFlowFunc(("before increment %u\n", pTaskState->CTX_SUFF(pTargetDevice)->cOutstandingRequests));

ASMAtomicIncU32(&pTaskState->CTX_SUFF(pTargetDevice)->cOutstandingRequests);

LogFlowFunc(("after increment %u\n", pTaskState->CTX_SUFF(pTargetDevice)->cOutstandingRequests));

rc = pTaskState->CTX_SUFF(pTargetDevice)->pDrvSCSIConnector->pfnSCSIRequestSend(pTaskState->CTX_SUFF(pTargetDevice)->pDrvSCSIConnector,

&pTaskState->PDMScsiRequest);

AssertMsgRC(rc, ("Sending request to SCSI layer failed rc=%Rrc\n", rc));

}

return rc;

}

static int buslogicBIOSIOPortRead(PPDMDEVINS pDevIns, void *pvUser,

RTIOPORT Port, uint32_t *pu32, unsigned cb)

{

int rc;

PBUSLOGIC pBusLogic = PDMINS_2_DATA(pDevIns, PBUSLOGIC);

Assert(cb == 1);

rc = vboxscsiReadRegister(&pBusLogic->VBoxSCSI, (Port - BUSLOGIC_BIOS_IO_PORT), pu32);

//Log2(("%s: pu32=%p:{%.*Rhxs} iRegister=%d rc=%Rrc\n",

// __FUNCTION__, pu32, 1, pu32, (Port - BUSLOGIC_BIOS_IO_PORT), rc));

return rc;

}

static int buslogicBIOSIOPortWrite(PPDMDEVINS pDevIns, void *pvUser,

RTIOPORT Port, uint32_t u32, unsigned cb)

{

int rc;

PBUSLOGIC pBusLogic = PDMINS_2_DATA(pDevIns, PBUSLOGIC);

Log2(("#%d %s: pvUser=%#p cb=%d u32=%#x Port=%#x\n",

pDevIns->iInstance, __FUNCTION__, pvUser, cb, u32, Port));

Assert(cb == 1);

rc = vboxscsiWriteRegister(&pBusLogic->VBoxSCSI, (Port - BUSLOGIC_BIOS_IO_PORT), (uint8_t)u32);

if (rc == VERR_MORE_DATA)

{

rc = buslogicPrepareBIOSSCSIRequest(pBusLogic);

AssertRC(rc);

}

else if (RT_FAILURE(rc))

AssertMsgFailed(("Writing BIOS register failed %Rrc\n", rc));

return VINF_SUCCESS;

}

static DECLCALLBACK(int) buslogicBIOSIOPortWriteStr(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, RTGCPTR *pGCPtrSrc, PRTGCUINTREG pcTransfer, unsigned cb)

{

PBUSLOGIC pBusLogic = PDMINS_2_DATA(pDevIns, PBUSLOGIC);

int rc;

Log2(("#%d %s: pvUser=%#p cb=%d Port=%#x\n",

pDevIns->iInstance, __FUNCTION__, pvUser, cb, Port));

rc = vboxscsiWriteString(pDevIns, &pBusLogic->VBoxSCSI, (Port - BUSLOGIC_BIOS_IO_PORT),

pGCPtrSrc, pcTransfer, cb);

if (rc == VERR_MORE_DATA)

{

rc = buslogicPrepareBIOSSCSIRequest(pBusLogic);

AssertRC(rc);

}

else if (RT_FAILURE(rc))

AssertMsgFailed(("Writing BIOS register failed %Rrc\n", rc));

return rc;

}

static DECLCALLBACK(int) buslogicBIOSIOPortReadStr(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, RTGCPTR *pGCPtrDst, PRTGCUINTREG pcTransfer, unsigned cb)

{

PBUSLOGIC pBusLogic = PDMINS_2_DATA(pDevIns, PBUSLOGIC);

LogFlowFunc(("#%d %s: pvUser=%#p cb=%d Port=%#x\n",

pDevIns->iInstance, __FUNCTION__, pvUser, cb, Port));

return vboxscsiReadString(pDevIns, &pBusLogic->VBoxSCSI, (Port - BUSLOGIC_BIOS_IO_PORT),

pGCPtrDst, pcTransfer, cb);

}

static int buslogicRegisterISARange(PBUSLOGIC pBusLogic, uint8_t uBaseCode)

{

uint8_t uCode = uBaseCode & MAX_ISA_BASE;

uint16_t uNewBase = aISABases[uCode];

int rc = VINF_SUCCESS;

LogFlowFunc(("ISA I/O code %02X, new base %X\n", uBaseCode, uNewBase));

/* Check if the same port range is already registered. */

if (uNewBase != pBusLogic->IOISABase)

{

/* Unregister the old range, if any. */

if (pBusLogic->IOISABase)

rc = PDMDevHlpIOPortDeregister(pBusLogic->CTX_SUFF(pDevIns), pBusLogic->IOISABase, 4);

if (RT_SUCCESS(rc))

{

pBusLogic->IOISABase = 0; /* First mark as unregistered. */

pBusLogic->uISABaseCode = ISA_BASE_DISABLED;

if (uNewBase)

{

/* Register the new range if requested. */

rc = PDMDevHlpIOPortRegister(pBusLogic->CTX_SUFF(pDevIns), uNewBase, 4, NULL,

buslogicIOPortWrite, buslogicIOPortRead,

NULL, NULL,

"BusLogic ISA");

if (RT_SUCCESS(rc))

{

pBusLogic->IOISABase = uNewBase;

pBusLogic->uISABaseCode = uCode;

}

}

}

if (RT_SUCCESS(rc))

{

if (uNewBase)

{

Log(("ISA I/O base: %x\n", uNewBase));

LogRel(("BusLogic: ISA I/O base: %x\n", uNewBase));

}

else

{

Log(("Disabling ISA I/O ports.\n"));

LogRel(("BusLogic: ISA I/O disabled\n"));

}

}

}

return rc;

}

static void buslogicWarningDiskFull(PPDMDEVINS pDevIns)

{

int rc;

LogRel(("BusLogic#%d: Host disk full\n", pDevIns->iInstance));

rc = PDMDevHlpVMSetRuntimeError(pDevIns, VMSETRTERR_FLAGS_SUSPEND | VMSETRTERR_FLAGS_NO_WAIT, "DevBusLogic_DISKFULL",

N_("Host system reported disk full. VM execution is suspended. You can resume after freeing some space"));

AssertRC(rc);

}

static void buslogicWarningFileTooBig(PPDMDEVINS pDevIns)

{

int rc;

LogRel(("BusLogic#%d: File too big\n", pDevIns->iInstance));

rc = PDMDevHlpVMSetRuntimeError(pDevIns, VMSETRTERR_FLAGS_SUSPEND | VMSETRTERR_FLAGS_NO_WAIT, "DevBusLogic_FILETOOBIG",

N_("Host system reported that the file size limit of the host file system has been exceeded. VM execution is suspended. You need to move your virtual hard disk to a filesystem which allows bigger files"));

AssertRC(rc);

}

static void buslogicWarningISCSI(PPDMDEVINS pDevIns)

{

int rc;

LogRel(("BusLogic#%d: iSCSI target unavailable\n", pDevIns->iInstance));

rc = PDMDevHlpVMSetRuntimeError(pDevIns, VMSETRTERR_FLAGS_SUSPEND | VMSETRTERR_FLAGS_NO_WAIT, "DevBusLogic_ISCSIDOWN",

N_("The iSCSI target has stopped responding. VM execution is suspended. You can resume when it is available again"));

AssertRC(rc);

}

static void buslogicWarningUnknown(PPDMDEVINS pDevIns, int rc)

{

int rc2;

LogRel(("BusLogic#%d: Unknown but recoverable error has occurred (rc=%Rrc)\n", pDevIns->iInstance, rc));

rc2 = PDMDevHlpVMSetRuntimeError(pDevIns, VMSETRTERR_FLAGS_SUSPEND | VMSETRTERR_FLAGS_NO_WAIT, "DevBusLogic_UNKNOWN",

N_("An unknown but recoverable I/O error has occurred (rc=%Rrc). VM execution is suspended. You can resume when the error is fixed"), rc);

AssertRC(rc2);

}

static void buslogicRedoSetWarning(PBUSLOGIC pThis, int rc)

{

if (rc == VERR_DISK_FULL)

buslogicWarningDiskFull(pThis->CTX_SUFF(pDevIns));

else if (rc == VERR_FILE_TOO_BIG)

buslogicWarningFileTooBig(pThis->CTX_SUFF(pDevIns));

else if (rc == VERR_BROKEN_PIPE || rc == VERR_NET_CONNECTION_REFUSED)

{

/* iSCSI connection abort (first error) or failure to reestablish

buslogicWarningISCSI(pThis->CTX_SUFF(pDevIns));

}

else

buslogicWarningUnknown(pThis->CTX_SUFF(pDevIns), rc);

}

static DECLCALLBACK(int) buslogicMMIOMap(PPCIDEVICE pPciDev, /*unsigned*/ int iRegion,

RTGCPHYS GCPhysAddress, uint32_t cb,

PCIADDRESSSPACE enmType)

{

PPDMDEVINS pDevIns = pPciDev->pDevIns;

PBUSLOGIC pThis = PDMINS_2_DATA(pDevIns, PBUSLOGIC);

int rc = VINF_SUCCESS;

Log2(("%s: registering MMIO area at GCPhysAddr=%RGp cb=%u\n", __FUNCTION__, GCPhysAddress, cb));

Assert(cb >= 32);

if (enmType == PCI_ADDRESS_SPACE_MEM)

{

/* We use the assigned size here, because we currently only support page aligned MMIO ranges. */

rc = PDMDevHlpMMIORegister(pDevIns, GCPhysAddress, cb, NULL /*pvUser*/,

IOMMMIO_FLAGS_READ_PASSTHRU | IOMMMIO_FLAGS_WRITE_PASSTHRU,

buslogicMMIOWrite, buslogicMMIORead, "BusLogic MMIO");

if (RT_FAILURE(rc))

return rc;

if (pThis->fR0Enabled)

{

rc = PDMDevHlpMMIORegisterR0(pDevIns, GCPhysAddress, cb, NIL_RTR0PTR /*pvUser*/,

"buslogicMMIOWrite", "buslogicMMIORead");

if (RT_FAILURE(rc))

return rc;

}

if (pThis->fGCEnabled)

{

rc = PDMDevHlpMMIORegisterRC(pDevIns, GCPhysAddress, cb, NIL_RTRCPTR /*pvUser*/,

"buslogicMMIOWrite", "buslogicMMIORead");

if (RT_FAILURE(rc))

return rc;

}

pThis->MMIOBase = GCPhysAddress;

}

else if (enmType == PCI_ADDRESS_SPACE_IO)

{

rc = PDMDevHlpIOPortRegister(pDevIns, (RTIOPORT)GCPhysAddress, 32,

NULL, buslogicIOPortWrite, buslogicIOPortRead, NULL, NULL, "BusLogic PCI");

if (RT_FAILURE(rc))

return rc;

if (pThis->fR0Enabled)

{

rc = PDMDevHlpIOPortRegisterR0(pDevIns, (RTIOPORT)GCPhysAddress, 32,

0, "buslogicIOPortWrite", "buslogicIOPortRead", NULL, NULL, "BusLogic PCI");

if (RT_FAILURE(rc))

return rc;

}

if (pThis->fGCEnabled)

{

rc = PDMDevHlpIOPortRegisterRC(pDevIns, (RTIOPORT)GCPhysAddress, 32,

0, "buslogicIOPortWrite", "buslogicIOPortRead", NULL, NULL, "BusLogic PCI");

if (RT_FAILURE(rc))

return rc;

}

pThis->IOPortBase = (RTIOPORT)GCPhysAddress;

}

else

AssertMsgFailed(("Invalid enmType=%d\n", enmType));

return rc;

}

static DECLCALLBACK(int) buslogicDeviceSCSIRequestCompleted(PPDMISCSIPORT pInterface, PPDMSCSIREQUEST pSCSIRequest,

int rcCompletion, bool fRedo, int rcReq)

{

int rc;

PBUSLOGICTASKSTATE pTaskState = (PBUSLOGICTASKSTATE)pSCSIRequest->pvUser;

PBUSLOGICDEVICE pBusLogicDevice = pTaskState->CTX_SUFF(pTargetDevice);

PBUSLOGIC pBusLogic = pBusLogicDevice->CTX_SUFF(pBusLogic);

LogFlowFunc(("before decrement %u\n", pBusLogicDevice->cOutstandingRequests));

ASMAtomicDecU32(&pBusLogicDevice->cOutstandingRequests);

LogFlowFunc(("after decrement %u\n", pBusLogicDevice->cOutstandingRequests));

if (fRedo)

{

if (!pTaskState->fBIOS)

{

buslogicDataBufferFree(pTaskState);

if (pTaskState->pbSenseBuffer)

buslogicSenseBufferFree(pTaskState, false /* fCopy */);

}

/* Add to the list. */

do

{

pTaskState->pRedoNext = ASMAtomicReadPtrT(&pBusLogic->pTasksRedoHead, PBUSLOGICTASKSTATE);

} while (!ASMAtomicCmpXchgPtr(&pBusLogic->pTasksRedoHead, pTaskState, pTaskState->pRedoNext));

/* Suspend the VM if not done already. */

if (!ASMAtomicXchgBool(&pBusLogic->fRedo, true))

buslogicRedoSetWarning(pBusLogic, rcReq);

}

else

{

if (pTaskState->fBIOS)

{

rc = vboxscsiRequestFinished(&pBusLogic->VBoxSCSI, pSCSIRequest, rcCompletion);

AssertMsgRC(rc, ("Finishing BIOS SCSI request failed rc=%Rrc\n", rc));

}

else

{

buslogicDataBufferFree(pTaskState);

if (pTaskState->pbSenseBuffer)

buslogicSenseBufferFree(pTaskState, (rcCompletion != SCSI_STATUS_OK));

if (rcCompletion == SCSI_STATUS_OK)

buslogicSendIncomingMailbox(pBusLogic, pTaskState,

BUSLOGIC_MAILBOX_INCOMING_ADAPTER_STATUS_CMD_COMPLETED,

BUSLOGIC_MAILBOX_INCOMING_DEVICE_STATUS_OPERATION_GOOD,

BUSLOGIC_MAILBOX_INCOMING_COMPLETION_WITHOUT_ERROR);

else if (rcCompletion == SCSI_STATUS_CHECK_CONDITION)

buslogicSendIncomingMailbox(pBusLogic, pTaskState,

BUSLOGIC_MAILBOX_INCOMING_ADAPTER_STATUS_CMD_COMPLETED,

BUSLOGIC_MAILBOX_INCOMING_DEVICE_STATUS_CHECK_CONDITION,

BUSLOGIC_MAILBOX_INCOMING_COMPLETION_WITH_ERROR);

else

AssertMsgFailed(("invalid completion status %d\n", rcCompletion));

}

#ifdef DEBUG

buslogicDumpCCBInfo(&pTaskState->CommandControlBlockGuest);

#endif

/* Remove task from the cache. */

RTMemCacheFree(pBusLogic->hTaskCache, pTaskState);

}

if (pBusLogicDevice->cOutstandingRequests == 0 && pBusLogic->fSignalIdle)

PDMDevHlpAsyncNotificationCompleted(pBusLogic->pDevInsR3);

return VINF_SUCCESS;

}

static DECLCALLBACK(int) buslogicQueryDeviceLocation(PPDMISCSIPORT pInterface, const char **ppcszController,

uint32_t *piInstance, uint32_t *piLUN)

{

PBUSLOGICDEVICE pBusLogicDevice = PDMISCSIPORT_2_PBUSLOGICDEVICE(pInterface);

PPDMDEVINS pDevIns = pBusLogicDevice->CTX_SUFF(pBusLogic)->CTX_SUFF(pDevIns);

AssertPtrReturn(ppcszController, VERR_INVALID_POINTER);

AssertPtrReturn(piInstance, VERR_INVALID_POINTER);

AssertPtrReturn(piLUN, VERR_INVALID_POINTER);

*ppcszController = pDevIns->pReg->szName;

*piInstance = pDevIns->iInstance;

*piLUN = pBusLogicDevice->iLUN;

return VINF_SUCCESS;

}

static int buslogicDeviceSCSIRequestSetup(PBUSLOGIC pBusLogic, PBUSLOGICTASKSTATE pTaskState)

{

int rc = VINF_SUCCESS;

/* Fetch the CCB from guest memory. */

RTGCPHYS GCPhysAddrCCB = (RTGCPHYS)pTaskState->MailboxGuest.u32PhysAddrCCB;

PDMDevHlpPhysRead(pBusLogic->CTX_SUFF(pDevIns), GCPhysAddrCCB,

&pTaskState->CommandControlBlockGuest, sizeof(CommandControlBlock));

PBUSLOGICDEVICE pTargetDevice = &pBusLogic->aDeviceStates[pTaskState->CommandControlBlockGuest.uTargetId];

pTaskState->CTX_SUFF(pTargetDevice) = pTargetDevice;

#ifdef DEBUG

buslogicDumpCCBInfo(&pTaskState->CommandControlBlockGuest);

#endif

/* Alloc required buffers. */

rc = buslogicDataBufferAlloc(pTaskState);

AssertMsgRC(rc, ("Alloc failed rc=%Rrc\n", rc));

rc = buslogicSenseBufferAlloc(pTaskState);

AssertMsgRC(rc, ("Mapping sense buffer failed rc=%Rrc\n", rc));

/* Check if device is present on bus. If not return error immediately and don't process this further. */

if (!pBusLogic->aDeviceStates[pTaskState->CommandControlBlockGuest.uTargetId].fPresent)

{

buslogicDataBufferFree(pTaskState);

if (pTaskState->pbSenseBuffer)

buslogicSenseBufferFree(pTaskState, true);

buslogicSendIncomingMailbox(pBusLogic, pTaskState,

BUSLOGIC_MAILBOX_INCOMING_ADAPTER_STATUS_SCSI_SELECTION_TIMEOUT,

BUSLOGIC_MAILBOX_INCOMING_DEVICE_STATUS_OPERATION_GOOD,

BUSLOGIC_MAILBOX_INCOMING_COMPLETION_WITH_ERROR);

RTMemCacheFree(pBusLogic->hTaskCache, pTaskState);

}

else

{

/* Setup SCSI request. */

pTaskState->PDMScsiRequest.uLogicalUnit = pTaskState->CommandControlBlockGuest.uLogicalUnit;

if (pTaskState->CommandControlBlockGuest.uDataDirection == BUSLOGIC_CCB_DIRECTION_UNKNOWN)

pTaskState->PDMScsiRequest.uDataDirection = PDMSCSIREQUESTTXDIR_UNKNOWN;

else if (pTaskState->CommandControlBlockGuest.uDataDirection == BUSLOGIC_CCB_DIRECTION_IN)

pTaskState->PDMScsiRequest.uDataDirection = PDMSCSIREQUESTTXDIR_FROM_DEVICE;

else if (pTaskState->CommandControlBlockGuest.uDataDirection == BUSLOGIC_CCB_DIRECTION_OUT)

pTaskState->PDMScsiRequest.uDataDirection = PDMSCSIREQUESTTXDIR_TO_DEVICE;

else if (pTaskState->CommandControlBlockGuest.uDataDirection == BUSLOGIC_CCB_DIRECTION_NO_DATA)

pTaskState->PDMScsiRequest.uDataDirection = PDMSCSIREQUESTTXDIR_NONE;

else

AssertMsgFailed(("Invalid data direction type %d\n", pTaskState->CommandControlBlockGuest.uDataDirection));

pTaskState->PDMScsiRequest.cbCDB = pTaskState->CommandControlBlockGuest.cbCDB;

pTaskState->PDMScsiRequest.pbCDB = pTaskState->CommandControlBlockGuest.aCDB;

if (pTaskState->DataSeg.cbSeg)

{

pTaskState->PDMScsiRequest.cbScatterGather = pTaskState->DataSeg.cbSeg;

pTaskState->PDMScsiRequest.cScatterGatherEntries = 1;

pTaskState->PDMScsiRequest.paScatterGatherHead = &pTaskState->DataSeg;

}

else

{

pTaskState->PDMScsiRequest.cbScatterGather = 0;

pTaskState->PDMScsiRequest.cScatterGatherEntries = 0;

pTaskState->PDMScsiRequest.paScatterGatherHead = NULL;

}

pTaskState->PDMScsiRequest.cbSenseBuffer = buslogicConvertSenseBufferLength(pTaskState->CommandControlBlockGuest.cbSenseData);

pTaskState->PDMScsiRequest.pbSenseBuffer = pTaskState->pbSenseBuffer;

pTaskState->PDMScsiRequest.pvUser = pTaskState;

ASMAtomicIncU32(&pTargetDevice->cOutstandingRequests);

rc = pTargetDevice->pDrvSCSIConnector->pfnSCSIRequestSend(pTargetDevice->pDrvSCSIConnector, &pTaskState->PDMScsiRequest);

AssertMsgRC(rc, ("Sending request to SCSI layer failed rc=%Rrc\n", rc));

}

return rc;

}

static int buslogicProcessMailboxNext(PBUSLOGIC pBusLogic)

{

PBUSLOGICTASKSTATE pTaskState = NULL;

RTGCPHYS GCPhysAddrMailboxCurrent;

int rc;

rc = RTMemCacheAllocEx(pBusLogic->hTaskCache, (void **)&pTaskState);

AssertMsgReturn(RT_SUCCESS(rc) && (pTaskState != NULL), ("Failed to get task state from cache\n"), rc);

pTaskState->fBIOS = false;

if (!pBusLogic->fStrictRoundRobinMode)

{

/* Search for a filled mailbox - stop if we have scanned all mailboxes. */

uint8_t uMailboxPosCur = pBusLogic->uMailboxOutgoingPositionCurrent;

do

{

/* Fetch mailbox from guest memory. */

GCPhysAddrMailboxCurrent = buslogicOutgoingMailboxGetGCPhys(pBusLogic);

PDMDevHlpPhysRead(pBusLogic->CTX_SUFF(pDevIns), GCPhysAddrMailboxCurrent,

&pTaskState->MailboxGuest, sizeof(Mailbox));

/* Check the next mailbox. */

buslogicOutgoingMailboxAdvance(pBusLogic);

} while ( pTaskState->MailboxGuest.u.out.uActionCode == BUSLOGIC_MAILBOX_OUTGOING_ACTION_FREE

&& uMailboxPosCur != pBusLogic->uMailboxOutgoingPositionCurrent);

}

else

{

/* Fetch mailbox from guest memory. */

GCPhysAddrMailboxCurrent = buslogicOutgoingMailboxGetGCPhys(pBusLogic);

PDMDevHlpPhysRead(pBusLogic->CTX_SUFF(pDevIns), GCPhysAddrMailboxCurrent,

&pTaskState->MailboxGuest, sizeof(Mailbox));

}

/*

if (pTaskState->MailboxGuest.u.out.uActionCode == BUSLOGIC_MAILBOX_OUTGOING_ACTION_FREE)

{

Log(("No loaded mailbox left\n"));

RTMemCacheFree(pBusLogic->hTaskCache, pTaskState);

return VERR_NO_DATA;

}

LogFlow(("Got loaded mailbox at slot %u, CCB phys %RGp\n", pBusLogic->uMailboxOutgoingPositionCurrent, (RTGCPHYS)pTaskState->MailboxGuest.u32PhysAddrCCB));

#ifdef DEBUG

buslogicDumpMailboxInfo(&pTaskState->MailboxGuest, true);

#endif

/* We got the mailbox, mark it as free in the guest. */

uint8_t uActionCode = BUSLOGIC_MAILBOX_OUTGOING_ACTION_FREE;

PDMDevHlpPhysWrite(pBusLogic->CTX_SUFF(pDevIns), GCPhysAddrMailboxCurrent + RT_OFFSETOF(Mailbox, u.out.uActionCode), &uActionCode, sizeof(uActionCode));

if (pTaskState->MailboxGuest.u.out.uActionCode == BUSLOGIC_MAILBOX_OUTGOING_ACTION_START_COMMAND)

rc = buslogicDeviceSCSIRequestSetup(pBusLogic, pTaskState);

else if (pTaskState->MailboxGuest.u.out.uActionCode == BUSLOGIC_MAILBOX_OUTGOING_ACTION_ABORT_COMMAND)