DevATA.cpp revision 954c328a44c68ccd408d540218239ff31973bace
29099c2d04b11e614f1fa399fab9e9162f2788b9vboxsync/* $Id$ */
29099c2d04b11e614f1fa399fab9e9162f2788b9vboxsync/** @file
661bfa5aae55ac2f94fa1cb131ea2323e5f6e633vboxsync * VBox storage devices: ATA/ATAPI controller device (disk and cdrom).
29099c2d04b11e614f1fa399fab9e9162f2788b9vboxsync */
29099c2d04b11e614f1fa399fab9e9162f2788b9vboxsync
29099c2d04b11e614f1fa399fab9e9162f2788b9vboxsync/*
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync * Copyright (C) 2006-2008 Sun Microsystems, Inc.
29099c2d04b11e614f1fa399fab9e9162f2788b9vboxsync *
29099c2d04b11e614f1fa399fab9e9162f2788b9vboxsync * This file is part of VirtualBox Open Source Edition (OSE), as
29099c2d04b11e614f1fa399fab9e9162f2788b9vboxsync * available from http://www.virtualbox.org. This file is free software;
29099c2d04b11e614f1fa399fab9e9162f2788b9vboxsync * you can redistribute it and/or modify it under the terms of the GNU
29099c2d04b11e614f1fa399fab9e9162f2788b9vboxsync * General Public License (GPL) as published by the Free Software
29099c2d04b11e614f1fa399fab9e9162f2788b9vboxsync * Foundation, in version 2 as it comes in the "COPYING" file of the
29099c2d04b11e614f1fa399fab9e9162f2788b9vboxsync * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
29099c2d04b11e614f1fa399fab9e9162f2788b9vboxsync * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
29099c2d04b11e614f1fa399fab9e9162f2788b9vboxsync *
29099c2d04b11e614f1fa399fab9e9162f2788b9vboxsync * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
29099c2d04b11e614f1fa399fab9e9162f2788b9vboxsync * Clara, CA 95054 USA or visit http://www.sun.com if you need
29099c2d04b11e614f1fa399fab9e9162f2788b9vboxsync * additional information or have any questions.
29099c2d04b11e614f1fa399fab9e9162f2788b9vboxsync */
29099c2d04b11e614f1fa399fab9e9162f2788b9vboxsync
661bfa5aae55ac2f94fa1cb131ea2323e5f6e633vboxsync/*******************************************************************************
661bfa5aae55ac2f94fa1cb131ea2323e5f6e633vboxsync* Defined Constants And Macros *
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync*******************************************************************************/
29099c2d04b11e614f1fa399fab9e9162f2788b9vboxsync/** Temporary instrumentation for tracking down potential virtual disk
29099c2d04b11e614f1fa399fab9e9162f2788b9vboxsync * write performance issues. */
29099c2d04b11e614f1fa399fab9e9162f2788b9vboxsync#undef VBOX_INSTRUMENT_DMA_WRITES
29099c2d04b11e614f1fa399fab9e9162f2788b9vboxsync
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync/**
29099c2d04b11e614f1fa399fab9e9162f2788b9vboxsync * The SSM saved state versions.
29099c2d04b11e614f1fa399fab9e9162f2788b9vboxsync */
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync#define ATA_SAVED_STATE_VERSION 18
29099c2d04b11e614f1fa399fab9e9162f2788b9vboxsync#define ATA_SAVED_STATE_VERSION_WITHOUT_FULL_SENSE 16
29099c2d04b11e614f1fa399fab9e9162f2788b9vboxsync#define ATA_SAVED_STATE_VERSION_WITHOUT_EVENT_STATUS 17
66b58af085e22ee26be57f98127fb49ee2e91790vboxsync
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync
29099c2d04b11e614f1fa399fab9e9162f2788b9vboxsync/*******************************************************************************
29099c2d04b11e614f1fa399fab9e9162f2788b9vboxsync* Header Files *
29099c2d04b11e614f1fa399fab9e9162f2788b9vboxsync*******************************************************************************/
29099c2d04b11e614f1fa399fab9e9162f2788b9vboxsync#define LOG_GROUP LOG_GROUP_DEV_IDE
29099c2d04b11e614f1fa399fab9e9162f2788b9vboxsync#include <VBox/pdmdev.h>
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync#include <iprt/assert.h>
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync#include <iprt/string.h>
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync#ifdef IN_RING3
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync# include <iprt/uuid.h>
5c4d7e2aae42bbf39793dfa686925f076a56b4d5vboxsync# include <iprt/semaphore.h>
5c4d7e2aae42bbf39793dfa686925f076a56b4d5vboxsync# include <iprt/thread.h>
5c4d7e2aae42bbf39793dfa686925f076a56b4d5vboxsync# include <iprt/time.h>
5c4d7e2aae42bbf39793dfa686925f076a56b4d5vboxsync# include <iprt/alloc.h>
5c4d7e2aae42bbf39793dfa686925f076a56b4d5vboxsync#endif /* IN_RING3 */
5c4d7e2aae42bbf39793dfa686925f076a56b4d5vboxsync#include <iprt/critsect.h>
5c4d7e2aae42bbf39793dfa686925f076a56b4d5vboxsync#include <iprt/asm.h>
5c4d7e2aae42bbf39793dfa686925f076a56b4d5vboxsync#include <VBox/stam.h>
5c4d7e2aae42bbf39793dfa686925f076a56b4d5vboxsync#include <VBox/mm.h>
5c4d7e2aae42bbf39793dfa686925f076a56b4d5vboxsync#include <VBox/pgm.h>
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync
29099c2d04b11e614f1fa399fab9e9162f2788b9vboxsync#include <VBox/scsi.h>
5c4d7e2aae42bbf39793dfa686925f076a56b4d5vboxsync
e250515922582e0410c9bcb6d24b0f17bef083a0vboxsync#include "PIIX3ATABmDma.h"
0c94a8282c9042b02f022302a3d987746140eab9vboxsync#include "ide.h"
e250515922582e0410c9bcb6d24b0f17bef083a0vboxsync#include "../Builtins.h"
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync/*******************************************************************************
29099c2d04b11e614f1fa399fab9e9162f2788b9vboxsync* Defined Constants And Macros *
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync*******************************************************************************/
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync/**
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync * Maximum number of sectors to transfer in a READ/WRITE MULTIPLE request.
fdb40b7d2efa84fc6f03b7a695cb4b2e035c30c7vboxsync * Set to 1 to disable multi-sector read support. According to the ATA
fdb40b7d2efa84fc6f03b7a695cb4b2e035c30c7vboxsync * specification this must be a power of 2 and it must fit in an 8 bit
5c4d7e2aae42bbf39793dfa686925f076a56b4d5vboxsync * value. Thus the only valid values are 1, 2, 4, 8, 16, 32, 64 and 128.
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync */
e250515922582e0410c9bcb6d24b0f17bef083a0vboxsync#define ATA_MAX_MULT_SECTORS 128
19320d55d1417c39b3b5673a53aaa5ef177242c8vboxsync
19320d55d1417c39b3b5673a53aaa5ef177242c8vboxsync/**
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync * Fastest PIO mode supported by the drive.
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync */
29099c2d04b11e614f1fa399fab9e9162f2788b9vboxsync#define ATA_PIO_MODE_MAX 4
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync/**
29099c2d04b11e614f1fa399fab9e9162f2788b9vboxsync * Fastest MDMA mode supported by the drive.
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync */
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync#define ATA_MDMA_MODE_MAX 2
5c4d7e2aae42bbf39793dfa686925f076a56b4d5vboxsync/**
c66c4413faa5a72ce047742f9acfa85e94dec8afvboxsync * Fastest UDMA mode supported by the drive.
c66c4413faa5a72ce047742f9acfa85e94dec8afvboxsync */
c66c4413faa5a72ce047742f9acfa85e94dec8afvboxsync#define ATA_UDMA_MODE_MAX 6
5c4d7e2aae42bbf39793dfa686925f076a56b4d5vboxsync
5c4d7e2aae42bbf39793dfa686925f076a56b4d5vboxsync/** ATAPI sense info size. */
5c4d7e2aae42bbf39793dfa686925f076a56b4d5vboxsync#define ATAPI_SENSE_SIZE 64
5c4d7e2aae42bbf39793dfa686925f076a56b4d5vboxsync
5c4d7e2aae42bbf39793dfa686925f076a56b4d5vboxsync/** The maximum number of release log entries per device. */
5c4d7e2aae42bbf39793dfa686925f076a56b4d5vboxsync#define MAX_LOG_REL_ERRORS 1024
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync/* MediaEventStatus */
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync#define ATA_EVENT_STATUS_UNCHANGED 0 /**< medium event status not changed */
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync#define ATA_EVENT_STATUS_MEDIA_NEW 1 /**< new medium inserted */
0c94a8282c9042b02f022302a3d987746140eab9vboxsync#define ATA_EVENT_STATUS_MEDIA_REMOVED 2 /**< medium removed */
0c94a8282c9042b02f022302a3d987746140eab9vboxsync#define ATA_EVENT_STATUS_MEDIA_CHANGED 3 /**< medium was removed + new medium was inserted */
0c94a8282c9042b02f022302a3d987746140eab9vboxsync
0c94a8282c9042b02f022302a3d987746140eab9vboxsync
0c94a8282c9042b02f022302a3d987746140eab9vboxsync/*******************************************************************************
0c94a8282c9042b02f022302a3d987746140eab9vboxsync* Structures and Typedefs *
0c94a8282c9042b02f022302a3d987746140eab9vboxsync*******************************************************************************/
0c94a8282c9042b02f022302a3d987746140eab9vboxsynctypedef struct ATADevState {
0c94a8282c9042b02f022302a3d987746140eab9vboxsync /** Flag indicating whether the current command uses LBA48 mode. */
0c94a8282c9042b02f022302a3d987746140eab9vboxsync bool fLBA48;
0c94a8282c9042b02f022302a3d987746140eab9vboxsync /** Flag indicating whether this drive implements the ATAPI command set. */
0c94a8282c9042b02f022302a3d987746140eab9vboxsync bool fATAPI;
0c94a8282c9042b02f022302a3d987746140eab9vboxsync /** Set if this interface has asserted the IRQ. */
0c94a8282c9042b02f022302a3d987746140eab9vboxsync bool fIrqPending;
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync /** Currently configured number of sectors in a multi-sector transfer. */
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync uint8_t cMultSectors;
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync /** PCHS disk geometry. */
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync PDMMEDIAGEOMETRY PCHSGeometry;
0c94a8282c9042b02f022302a3d987746140eab9vboxsync /** Total number of sectors on this disk. */
0c94a8282c9042b02f022302a3d987746140eab9vboxsync uint64_t cTotalSectors;
0c94a8282c9042b02f022302a3d987746140eab9vboxsync /** Number of sectors to transfer per IRQ. */
0c94a8282c9042b02f022302a3d987746140eab9vboxsync uint32_t cSectorsPerIRQ;
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync /** ATA/ATAPI register 1: feature (write-only). */
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync uint8_t uATARegFeature;
e250515922582e0410c9bcb6d24b0f17bef083a0vboxsync /** ATA/ATAPI register 1: feature, high order byte. */
e250515922582e0410c9bcb6d24b0f17bef083a0vboxsync uint8_t uATARegFeatureHOB;
e250515922582e0410c9bcb6d24b0f17bef083a0vboxsync /** ATA/ATAPI register 1: error (read-only). */
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync uint8_t uATARegError;
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync /** ATA/ATAPI register 2: sector count (read/write). */
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync uint8_t uATARegNSector;
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync /** ATA/ATAPI register 2: sector count, high order byte. */
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync uint8_t uATARegNSectorHOB;
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync /** ATA/ATAPI register 3: sector (read/write). */
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync uint8_t uATARegSector;
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync /** ATA/ATAPI register 3: sector, high order byte. */
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync uint8_t uATARegSectorHOB;
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync /** ATA/ATAPI register 4: cylinder low (read/write). */
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync uint8_t uATARegLCyl;
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync /** ATA/ATAPI register 4: cylinder low, high order byte. */
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync uint8_t uATARegLCylHOB;
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync /** ATA/ATAPI register 5: cylinder high (read/write). */
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync uint8_t uATARegHCyl;
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync /** ATA/ATAPI register 5: cylinder high, high order byte. */
19320d55d1417c39b3b5673a53aaa5ef177242c8vboxsync uint8_t uATARegHCylHOB;
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync /** ATA/ATAPI register 6: select drive/head (read/write). */
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync uint8_t uATARegSelect;
82e3a4017d20f44c30ff909e6b825ff78139cbbbvboxsync /** ATA/ATAPI register 7: status (read-only). */
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync uint8_t uATARegStatus;
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync /** ATA/ATAPI register 7: command (write-only). */
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync uint8_t uATARegCommand;
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync /** ATA/ATAPI drive control register (write-only). */
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync uint8_t uATARegDevCtl;
82e3a4017d20f44c30ff909e6b825ff78139cbbbvboxsync
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync /** Currently active transfer mode (MDMA/UDMA) and speed. */
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync uint8_t uATATransferMode;
f9cdd92d151d9c28eb0f1aed25863fc04f85691dvboxsync /** Current transfer direction. */
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync uint8_t uTxDir;
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync /** Index of callback for begin transfer. */
82e3a4017d20f44c30ff909e6b825ff78139cbbbvboxsync uint8_t iBeginTransfer;
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync /** Index of callback for source/sink of data. */
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync uint8_t iSourceSink;
f9cdd92d151d9c28eb0f1aed25863fc04f85691dvboxsync /** Flag indicating whether the current command transfers data in DMA mode. */
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync bool fDMA;
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync /** Set to indicate that ATAPI transfer semantics must be used. */
82e3a4017d20f44c30ff909e6b825ff78139cbbbvboxsync bool fATAPITransfer;
82e3a4017d20f44c30ff909e6b825ff78139cbbbvboxsync
82e3a4017d20f44c30ff909e6b825ff78139cbbbvboxsync /** Total ATA/ATAPI transfer size, shared PIO/DMA. */
82e3a4017d20f44c30ff909e6b825ff78139cbbbvboxsync uint32_t cbTotalTransfer;
82e3a4017d20f44c30ff909e6b825ff78139cbbbvboxsync /** Elementary ATA/ATAPI transfer size, shared PIO/DMA. */
82e3a4017d20f44c30ff909e6b825ff78139cbbbvboxsync uint32_t cbElementaryTransfer;
82e3a4017d20f44c30ff909e6b825ff78139cbbbvboxsync /** Current read/write buffer position, shared PIO/DMA. */
82e3a4017d20f44c30ff909e6b825ff78139cbbbvboxsync uint32_t iIOBufferCur;
82e3a4017d20f44c30ff909e6b825ff78139cbbbvboxsync /** First element beyond end of valid buffer content, shared PIO/DMA. */
82e3a4017d20f44c30ff909e6b825ff78139cbbbvboxsync uint32_t iIOBufferEnd;
82e3a4017d20f44c30ff909e6b825ff78139cbbbvboxsync
82e3a4017d20f44c30ff909e6b825ff78139cbbbvboxsync /** ATA/ATAPI current PIO read/write transfer position. Not shared with DMA for safety reasons. */
82e3a4017d20f44c30ff909e6b825ff78139cbbbvboxsync uint32_t iIOBufferPIODataStart;
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync /** ATA/ATAPI current PIO read/write transfer end. Not shared with DMA for safety reasons. */
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync uint32_t iIOBufferPIODataEnd;
19320d55d1417c39b3b5673a53aaa5ef177242c8vboxsync
19320d55d1417c39b3b5673a53aaa5ef177242c8vboxsync /** ATAPI current LBA position. */
19320d55d1417c39b3b5673a53aaa5ef177242c8vboxsync uint32_t iATAPILBA;
19320d55d1417c39b3b5673a53aaa5ef177242c8vboxsync /** ATAPI current sector size. */
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync uint32_t cbATAPISector;
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync /** ATAPI current command. */
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync uint8_t aATAPICmd[ATAPI_PACKET_SIZE];
1969e98a26e5b56b67fbe3b6bfa007f8f09e86ebvboxsync /** ATAPI sense data. */
44372afb953dc9f1f1ec71943f5f561a607c0307vboxsync uint8_t abATAPISense[ATAPI_SENSE_SIZE];
81614fc60e096e714022d10d38b70a36b9b21d48vboxsync /** HACK: Countdown till we report a newly unmounted drive as mounted. */
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync uint8_t cNotifiedMediaChange;
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync /** The same for GET_EVENT_STATUS for mechanism */
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync volatile uint32_t MediaEventStatus;
e250515922582e0410c9bcb6d24b0f17bef083a0vboxsync
e250515922582e0410c9bcb6d24b0f17bef083a0vboxsync uint32_t Alignment0;
0c94a8282c9042b02f022302a3d987746140eab9vboxsync
0c94a8282c9042b02f022302a3d987746140eab9vboxsync /** The status LED state for this drive. */
0c94a8282c9042b02f022302a3d987746140eab9vboxsync PDMLED Led;
0c94a8282c9042b02f022302a3d987746140eab9vboxsync
0c94a8282c9042b02f022302a3d987746140eab9vboxsync /** Size of I/O buffer. */
0c94a8282c9042b02f022302a3d987746140eab9vboxsync uint32_t cbIOBuffer;
0c94a8282c9042b02f022302a3d987746140eab9vboxsync /** Pointer to the I/O buffer. */
0c94a8282c9042b02f022302a3d987746140eab9vboxsync R3PTRTYPE(uint8_t *) pbIOBufferR3;
0c94a8282c9042b02f022302a3d987746140eab9vboxsync /** Pointer to the I/O buffer. */
0c94a8282c9042b02f022302a3d987746140eab9vboxsync R0PTRTYPE(uint8_t *) pbIOBufferR0;
0c94a8282c9042b02f022302a3d987746140eab9vboxsync /** Pointer to the I/O buffer. */
0c94a8282c9042b02f022302a3d987746140eab9vboxsync RCPTRTYPE(uint8_t *) pbIOBufferRC;
0c94a8282c9042b02f022302a3d987746140eab9vboxsync
0c94a8282c9042b02f022302a3d987746140eab9vboxsync RTRCPTR Aligmnent1; /**< Align the statistics at an 8-byte boundrary. */
0c94a8282c9042b02f022302a3d987746140eab9vboxsync
0c94a8282c9042b02f022302a3d987746140eab9vboxsync /*
0c94a8282c9042b02f022302a3d987746140eab9vboxsync * No data that is part of the saved state after this point!!!!!
0c94a8282c9042b02f022302a3d987746140eab9vboxsync */
0c94a8282c9042b02f022302a3d987746140eab9vboxsync
0c94a8282c9042b02f022302a3d987746140eab9vboxsync /* Release statistics: number of ATA DMA commands. */
0c94a8282c9042b02f022302a3d987746140eab9vboxsync STAMCOUNTER StatATADMA;
0c94a8282c9042b02f022302a3d987746140eab9vboxsync /* Release statistics: number of ATA PIO commands. */
0c94a8282c9042b02f022302a3d987746140eab9vboxsync STAMCOUNTER StatATAPIO;
0c94a8282c9042b02f022302a3d987746140eab9vboxsync /* Release statistics: number of ATAPI PIO commands. */
0c94a8282c9042b02f022302a3d987746140eab9vboxsync STAMCOUNTER StatATAPIDMA;
0c94a8282c9042b02f022302a3d987746140eab9vboxsync /* Release statistics: number of ATAPI PIO commands. */
0c94a8282c9042b02f022302a3d987746140eab9vboxsync STAMCOUNTER StatATAPIPIO;
0c94a8282c9042b02f022302a3d987746140eab9vboxsync#ifdef VBOX_INSTRUMENT_DMA_WRITES
0c94a8282c9042b02f022302a3d987746140eab9vboxsync /* Release statistics: number of DMA sector writes and the time spent. */
0c94a8282c9042b02f022302a3d987746140eab9vboxsync STAMPROFILEADV StatInstrVDWrites;
0c94a8282c9042b02f022302a3d987746140eab9vboxsync#endif
0c94a8282c9042b02f022302a3d987746140eab9vboxsync
19320d55d1417c39b3b5673a53aaa5ef177242c8vboxsync /** Statistics: number of read operations and the time spent reading. */
19320d55d1417c39b3b5673a53aaa5ef177242c8vboxsync STAMPROFILEADV StatReads;
19320d55d1417c39b3b5673a53aaa5ef177242c8vboxsync /** Statistics: number of bytes read. */
19320d55d1417c39b3b5673a53aaa5ef177242c8vboxsync STAMCOUNTER StatBytesRead;
19320d55d1417c39b3b5673a53aaa5ef177242c8vboxsync /** Statistics: number of write operations and the time spent writing. */
19320d55d1417c39b3b5673a53aaa5ef177242c8vboxsync STAMPROFILEADV StatWrites;
19320d55d1417c39b3b5673a53aaa5ef177242c8vboxsync /** Statistics: number of bytes written. */
19320d55d1417c39b3b5673a53aaa5ef177242c8vboxsync STAMCOUNTER StatBytesWritten;
19320d55d1417c39b3b5673a53aaa5ef177242c8vboxsync /** Statistics: number of flush operations and the time spend flushing. */
19320d55d1417c39b3b5673a53aaa5ef177242c8vboxsync STAMPROFILE StatFlushes;
19320d55d1417c39b3b5673a53aaa5ef177242c8vboxsync
19320d55d1417c39b3b5673a53aaa5ef177242c8vboxsync /** Enable passing through commands directly to the ATAPI drive. */
19320d55d1417c39b3b5673a53aaa5ef177242c8vboxsync bool fATAPIPassthrough;
19320d55d1417c39b3b5673a53aaa5ef177242c8vboxsync /** Number of errors we've reported to the release log.
c66c4413faa5a72ce047742f9acfa85e94dec8afvboxsync * This is to prevent flooding caused by something going horribly wrong.
c66c4413faa5a72ce047742f9acfa85e94dec8afvboxsync * this value against MAX_LOG_REL_ERRORS in places likely to cause floods
c66c4413faa5a72ce047742f9acfa85e94dec8afvboxsync * like the ones we currently seeing on the linux smoke tests (2006-11-10). */
c66c4413faa5a72ce047742f9acfa85e94dec8afvboxsync uint32_t cErrors;
c66c4413faa5a72ce047742f9acfa85e94dec8afvboxsync /** Timestamp of last started command. 0 if no command pending. */
c66c4413faa5a72ce047742f9acfa85e94dec8afvboxsync uint64_t u64CmdTS;
c66c4413faa5a72ce047742f9acfa85e94dec8afvboxsync
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync /** Pointer to the attached driver's base interface. */
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync R3PTRTYPE(PPDMIBASE) pDrvBase;
19320d55d1417c39b3b5673a53aaa5ef177242c8vboxsync /** Pointer to the attached driver's block interface. */
19320d55d1417c39b3b5673a53aaa5ef177242c8vboxsync R3PTRTYPE(PPDMIBLOCK) pDrvBlock;
19320d55d1417c39b3b5673a53aaa5ef177242c8vboxsync /** Pointer to the attached driver's block bios interface. */
19320d55d1417c39b3b5673a53aaa5ef177242c8vboxsync R3PTRTYPE(PPDMIBLOCKBIOS) pDrvBlockBios;
19320d55d1417c39b3b5673a53aaa5ef177242c8vboxsync /** Pointer to the attached driver's mount interface.
19320d55d1417c39b3b5673a53aaa5ef177242c8vboxsync * This is NULL if the driver isn't a removable unit. */
19320d55d1417c39b3b5673a53aaa5ef177242c8vboxsync R3PTRTYPE(PPDMIMOUNT) pDrvMount;
19320d55d1417c39b3b5673a53aaa5ef177242c8vboxsync /** The base interface. */
19320d55d1417c39b3b5673a53aaa5ef177242c8vboxsync PDMIBASE IBase;
19320d55d1417c39b3b5673a53aaa5ef177242c8vboxsync /** The block port interface. */
19320d55d1417c39b3b5673a53aaa5ef177242c8vboxsync PDMIBLOCKPORT IPort;
19320d55d1417c39b3b5673a53aaa5ef177242c8vboxsync /** The mount notify interface. */
19320d55d1417c39b3b5673a53aaa5ef177242c8vboxsync PDMIMOUNTNOTIFY IMountNotify;
19320d55d1417c39b3b5673a53aaa5ef177242c8vboxsync /** The LUN #. */
19320d55d1417c39b3b5673a53aaa5ef177242c8vboxsync RTUINT iLUN;
19320d55d1417c39b3b5673a53aaa5ef177242c8vboxsync#if HC_ARCH_BITS == 64
19320d55d1417c39b3b5673a53aaa5ef177242c8vboxsync RTUINT Alignment2; /**< Align pDevInsR3 correctly. */
19320d55d1417c39b3b5673a53aaa5ef177242c8vboxsync#endif
19320d55d1417c39b3b5673a53aaa5ef177242c8vboxsync /** Pointer to device instance. */
19320d55d1417c39b3b5673a53aaa5ef177242c8vboxsync PPDMDEVINSR3 pDevInsR3;
19320d55d1417c39b3b5673a53aaa5ef177242c8vboxsync /** Pointer to controller instance. */
19320d55d1417c39b3b5673a53aaa5ef177242c8vboxsync R3PTRTYPE(struct ATACONTROLLER *) pControllerR3;
19320d55d1417c39b3b5673a53aaa5ef177242c8vboxsync /** Pointer to device instance. */
19320d55d1417c39b3b5673a53aaa5ef177242c8vboxsync PPDMDEVINSR0 pDevInsR0;
19320d55d1417c39b3b5673a53aaa5ef177242c8vboxsync /** Pointer to controller instance. */
19320d55d1417c39b3b5673a53aaa5ef177242c8vboxsync R0PTRTYPE(struct ATACONTROLLER *) pControllerR0;
19320d55d1417c39b3b5673a53aaa5ef177242c8vboxsync /** Pointer to device instance. */
19320d55d1417c39b3b5673a53aaa5ef177242c8vboxsync PPDMDEVINSRC pDevInsRC;
19320d55d1417c39b3b5673a53aaa5ef177242c8vboxsync /** Pointer to controller instance. */
19320d55d1417c39b3b5673a53aaa5ef177242c8vboxsync RCPTRTYPE(struct ATACONTROLLER *) pControllerRC;
19320d55d1417c39b3b5673a53aaa5ef177242c8vboxsync
19320d55d1417c39b3b5673a53aaa5ef177242c8vboxsync /** The serial numnber to use for IDENTIFY DEVICE commands. */
19320d55d1417c39b3b5673a53aaa5ef177242c8vboxsync int8_t abSerialNumber[20];
82e3a4017d20f44c30ff909e6b825ff78139cbbbvboxsync /** The firmware revision to use for IDENTIFY DEVICE commands. */
82e3a4017d20f44c30ff909e6b825ff78139cbbbvboxsync int8_t abFirmwareRevision[8];
82e3a4017d20f44c30ff909e6b825ff78139cbbbvboxsync /** The model number to use for IDENTIFY DEVICE commands. */
82e3a4017d20f44c30ff909e6b825ff78139cbbbvboxsync int8_t abModelNumber[40];
82e3a4017d20f44c30ff909e6b825ff78139cbbbvboxsync
19320d55d1417c39b3b5673a53aaa5ef177242c8vboxsync#if HC_ARCH_BITS == 64
19320d55d1417c39b3b5673a53aaa5ef177242c8vboxsync uint32_t Alignment1;
19320d55d1417c39b3b5673a53aaa5ef177242c8vboxsync#endif
19320d55d1417c39b3b5673a53aaa5ef177242c8vboxsync} ATADevState;
19320d55d1417c39b3b5673a53aaa5ef177242c8vboxsync
19320d55d1417c39b3b5673a53aaa5ef177242c8vboxsync
19320d55d1417c39b3b5673a53aaa5ef177242c8vboxsynctypedef struct ATATransferRequest
19320d55d1417c39b3b5673a53aaa5ef177242c8vboxsync{
19320d55d1417c39b3b5673a53aaa5ef177242c8vboxsync uint8_t iIf;
19320d55d1417c39b3b5673a53aaa5ef177242c8vboxsync uint8_t iBeginTransfer;
19320d55d1417c39b3b5673a53aaa5ef177242c8vboxsync uint8_t iSourceSink;
19320d55d1417c39b3b5673a53aaa5ef177242c8vboxsync uint32_t cbTotalTransfer;
19320d55d1417c39b3b5673a53aaa5ef177242c8vboxsync uint8_t uTxDir;
19320d55d1417c39b3b5673a53aaa5ef177242c8vboxsync} ATATransferRequest;
19320d55d1417c39b3b5673a53aaa5ef177242c8vboxsync
19320d55d1417c39b3b5673a53aaa5ef177242c8vboxsync
19320d55d1417c39b3b5673a53aaa5ef177242c8vboxsynctypedef struct ATAAbortRequest
19320d55d1417c39b3b5673a53aaa5ef177242c8vboxsync{
19320d55d1417c39b3b5673a53aaa5ef177242c8vboxsync uint8_t iIf;
38745c55f37c31ba8b78cc728d2f08ea6eec38d6vboxsync bool fResetDrive;
19320d55d1417c39b3b5673a53aaa5ef177242c8vboxsync} ATAAbortRequest;
19320d55d1417c39b3b5673a53aaa5ef177242c8vboxsync
19320d55d1417c39b3b5673a53aaa5ef177242c8vboxsync
19320d55d1417c39b3b5673a53aaa5ef177242c8vboxsynctypedef enum
19320d55d1417c39b3b5673a53aaa5ef177242c8vboxsync{
19320d55d1417c39b3b5673a53aaa5ef177242c8vboxsync /** Begin a new transfer. */
19320d55d1417c39b3b5673a53aaa5ef177242c8vboxsync ATA_AIO_NEW = 0,
19320d55d1417c39b3b5673a53aaa5ef177242c8vboxsync /** Continue a DMA transfer. */
19320d55d1417c39b3b5673a53aaa5ef177242c8vboxsync ATA_AIO_DMA,
19320d55d1417c39b3b5673a53aaa5ef177242c8vboxsync /** Continue a PIO transfer. */
c66c4413faa5a72ce047742f9acfa85e94dec8afvboxsync ATA_AIO_PIO,
19320d55d1417c39b3b5673a53aaa5ef177242c8vboxsync /** Reset the drives on current controller, stop all transfer activity. */
c66c4413faa5a72ce047742f9acfa85e94dec8afvboxsync ATA_AIO_RESET_ASSERTED,
c66c4413faa5a72ce047742f9acfa85e94dec8afvboxsync /** Reset the drives on current controller, resume operation. */
19320d55d1417c39b3b5673a53aaa5ef177242c8vboxsync ATA_AIO_RESET_CLEARED,
19320d55d1417c39b3b5673a53aaa5ef177242c8vboxsync /** Abort the current transfer of a particular drive. */
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync ATA_AIO_ABORT
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync} ATAAIO;
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync
c66c4413faa5a72ce047742f9acfa85e94dec8afvboxsync
c66c4413faa5a72ce047742f9acfa85e94dec8afvboxsynctypedef struct ATARequest
c66c4413faa5a72ce047742f9acfa85e94dec8afvboxsync{
c66c4413faa5a72ce047742f9acfa85e94dec8afvboxsync ATAAIO ReqType;
c66c4413faa5a72ce047742f9acfa85e94dec8afvboxsync union
c66c4413faa5a72ce047742f9acfa85e94dec8afvboxsync {
c66c4413faa5a72ce047742f9acfa85e94dec8afvboxsync ATATransferRequest t;
c66c4413faa5a72ce047742f9acfa85e94dec8afvboxsync ATAAbortRequest a;
c66c4413faa5a72ce047742f9acfa85e94dec8afvboxsync } u;
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync} ATARequest;
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsynctypedef struct ATACONTROLLER
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync{
29099c2d04b11e614f1fa399fab9e9162f2788b9vboxsync /** The base of the first I/O Port range. */
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync RTIOPORT IOPortBase1;
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync /** The base of the second I/O Port range. (0 if none) */
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync RTIOPORT IOPortBase2;
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync /** The assigned IRQ. */
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync RTUINT irq;
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync /** Access critical section */
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync PDMCRITSECT lock;
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync /** Selected drive. */
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync uint8_t iSelectedIf;
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync /** The interface on which to handle async I/O. */
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync uint8_t iAIOIf;
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync /** The state of the async I/O thread. */
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync uint8_t uAsyncIOState;
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync /** Flag indicating whether the next transfer is part of the current command. */
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync bool fChainedTransfer;
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync /** Set when the reset processing is currently active on this controller. */
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync bool fReset;
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync /** Flag whether the current transfer needs to be redone. */
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync bool fRedo;
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync /** Flag whether the redo suspend has been finished. */
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync bool fRedoIdle;
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync /** Flag whether the DMA operation to be redone is the final transfer. */
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync bool fRedoDMALastDesc;
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync /** The BusMaster DMA state. */
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync BMDMAState BmDma;
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync /** Pointer to first DMA descriptor. */
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync RTGCPHYS32 pFirstDMADesc;
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync /** Pointer to last DMA descriptor. */
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync RTGCPHYS32 pLastDMADesc;
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync /** Pointer to current DMA buffer (for redo operations). */
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync RTGCPHYS32 pRedoDMABuffer;
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync /** Size of current DMA buffer (for redo operations). */
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync uint32_t cbRedoDMABuffer;
c66c4413faa5a72ce047742f9acfa85e94dec8afvboxsync
c66c4413faa5a72ce047742f9acfa85e94dec8afvboxsync /** The ATA/ATAPI interfaces of this controller. */
c66c4413faa5a72ce047742f9acfa85e94dec8afvboxsync ATADevState aIfs[2];
c66c4413faa5a72ce047742f9acfa85e94dec8afvboxsync
c66c4413faa5a72ce047742f9acfa85e94dec8afvboxsync /** Pointer to device instance. */
c66c4413faa5a72ce047742f9acfa85e94dec8afvboxsync PPDMDEVINSR3 pDevInsR3;
c66c4413faa5a72ce047742f9acfa85e94dec8afvboxsync /** Pointer to device instance. */
c66c4413faa5a72ce047742f9acfa85e94dec8afvboxsync PPDMDEVINSR0 pDevInsR0;
c66c4413faa5a72ce047742f9acfa85e94dec8afvboxsync /** Pointer to device instance. */
c66c4413faa5a72ce047742f9acfa85e94dec8afvboxsync PPDMDEVINSRC pDevInsRC;
66b58af085e22ee26be57f98127fb49ee2e91790vboxsync
66b58af085e22ee26be57f98127fb49ee2e91790vboxsync /** Set when the destroying the device instance and the thread must exit. */
66b58af085e22ee26be57f98127fb49ee2e91790vboxsync uint32_t volatile fShutdown;
66b58af085e22ee26be57f98127fb49ee2e91790vboxsync /** The async I/O thread handle. NIL_RTTHREAD if no thread. */
66b58af085e22ee26be57f98127fb49ee2e91790vboxsync RTTHREAD AsyncIOThread;
66b58af085e22ee26be57f98127fb49ee2e91790vboxsync /** The event semaphore the thread is waiting on for requests. */
66b58af085e22ee26be57f98127fb49ee2e91790vboxsync RTSEMEVENT AsyncIOSem;
66b58af085e22ee26be57f98127fb49ee2e91790vboxsync /** The request queue for the AIO thread. One element is always unused. */
66b58af085e22ee26be57f98127fb49ee2e91790vboxsync ATARequest aAsyncIORequests[4];
66b58af085e22ee26be57f98127fb49ee2e91790vboxsync /** The position at which to insert a new request for the AIO thread. */
66b58af085e22ee26be57f98127fb49ee2e91790vboxsync uint8_t AsyncIOReqHead;
66b58af085e22ee26be57f98127fb49ee2e91790vboxsync /** The position at which to get a new request for the AIO thread. */
66b58af085e22ee26be57f98127fb49ee2e91790vboxsync uint8_t AsyncIOReqTail;
66b58af085e22ee26be57f98127fb49ee2e91790vboxsync uint8_t Alignment3[2]; /**< Explicit padding of the 2 byte gap. */
c66c4413faa5a72ce047742f9acfa85e94dec8afvboxsync /** Magic delay before triggering interrupts in DMA mode. */
c66c4413faa5a72ce047742f9acfa85e94dec8afvboxsync uint32_t DelayIRQMillies;
c66c4413faa5a72ce047742f9acfa85e94dec8afvboxsync /** The mutex protecting the request queue. */
c66c4413faa5a72ce047742f9acfa85e94dec8afvboxsync RTSEMMUTEX AsyncIORequestMutex;
c66c4413faa5a72ce047742f9acfa85e94dec8afvboxsync /** The event semaphore the thread is waiting on during suspended I/O. */
c66c4413faa5a72ce047742f9acfa85e94dec8afvboxsync RTSEMEVENT SuspendIOSem;
c66c4413faa5a72ce047742f9acfa85e94dec8afvboxsync#if 0 /*HC_ARCH_BITS == 32*/
c66c4413faa5a72ce047742f9acfa85e94dec8afvboxsync uint32_t Alignment0;
c66c4413faa5a72ce047742f9acfa85e94dec8afvboxsync#endif
c66c4413faa5a72ce047742f9acfa85e94dec8afvboxsync
66b58af085e22ee26be57f98127fb49ee2e91790vboxsync /* Statistics */
66b58af085e22ee26be57f98127fb49ee2e91790vboxsync STAMCOUNTER StatAsyncOps;
66b58af085e22ee26be57f98127fb49ee2e91790vboxsync uint64_t StatAsyncMinWait;
66b58af085e22ee26be57f98127fb49ee2e91790vboxsync uint64_t StatAsyncMaxWait;
66b58af085e22ee26be57f98127fb49ee2e91790vboxsync STAMCOUNTER StatAsyncTimeUS;
66b58af085e22ee26be57f98127fb49ee2e91790vboxsync STAMPROFILEADV StatAsyncTime;
66b58af085e22ee26be57f98127fb49ee2e91790vboxsync STAMPROFILE StatLockWait;
66b58af085e22ee26be57f98127fb49ee2e91790vboxsync} ATACONTROLLER, *PATACONTROLLER;
66b58af085e22ee26be57f98127fb49ee2e91790vboxsync
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsynctypedef struct PCIATAState {
0c94a8282c9042b02f022302a3d987746140eab9vboxsync PCIDEVICE dev;
0c94a8282c9042b02f022302a3d987746140eab9vboxsync /** The controllers. */
0c94a8282c9042b02f022302a3d987746140eab9vboxsync ATACONTROLLER aCts[2];
0c94a8282c9042b02f022302a3d987746140eab9vboxsync /** Pointer to device instance. */
0c94a8282c9042b02f022302a3d987746140eab9vboxsync PPDMDEVINSR3 pDevIns;
0c94a8282c9042b02f022302a3d987746140eab9vboxsync /** Status Port - Base interface. */
0c94a8282c9042b02f022302a3d987746140eab9vboxsync PDMIBASE IBase;
0c94a8282c9042b02f022302a3d987746140eab9vboxsync /** Status Port - Leds interface. */
0c94a8282c9042b02f022302a3d987746140eab9vboxsync PDMILEDPORTS ILeds;
38745c55f37c31ba8b78cc728d2f08ea6eec38d6vboxsync /** Partner of ILeds. */
0c94a8282c9042b02f022302a3d987746140eab9vboxsync R3PTRTYPE(PPDMILEDCONNECTORS) pLedsConnector;
0c94a8282c9042b02f022302a3d987746140eab9vboxsync /** Flag whether GC is enabled. */
0c94a8282c9042b02f022302a3d987746140eab9vboxsync bool fGCEnabled;
0c94a8282c9042b02f022302a3d987746140eab9vboxsync /** Flag whether R0 is enabled. */
0c94a8282c9042b02f022302a3d987746140eab9vboxsync bool fR0Enabled;
0c94a8282c9042b02f022302a3d987746140eab9vboxsync /** Flag indicating whether PIIX4 or PIIX3 is being emulated. */
0c94a8282c9042b02f022302a3d987746140eab9vboxsync bool fPIIX4;
0c94a8282c9042b02f022302a3d987746140eab9vboxsync bool Alignment0[HC_ARCH_BITS == 64 ? 5 : 1]; /**< Align the struct size. */
c66c4413faa5a72ce047742f9acfa85e94dec8afvboxsync} PCIATAState;
c66c4413faa5a72ce047742f9acfa85e94dec8afvboxsync
c66c4413faa5a72ce047742f9acfa85e94dec8afvboxsync#define PDMIBASE_2_PCIATASTATE(pInterface) ( (PCIATAState *)((uintptr_t)(pInterface) - RT_OFFSETOF(PCIATAState, IBase)) )
c66c4413faa5a72ce047742f9acfa85e94dec8afvboxsync#define PDMILEDPORTS_2_PCIATASTATE(pInterface) ( (PCIATAState *)((uintptr_t)(pInterface) - RT_OFFSETOF(PCIATAState, ILeds)) )
c66c4413faa5a72ce047742f9acfa85e94dec8afvboxsync#define PDMIBLOCKPORT_2_ATASTATE(pInterface) ( (ATADevState *)((uintptr_t)(pInterface) - RT_OFFSETOF(ATADevState, IPort)) )
c66c4413faa5a72ce047742f9acfa85e94dec8afvboxsync#define PDMIMOUNT_2_ATASTATE(pInterface) ( (ATADevState *)((uintptr_t)(pInterface) - RT_OFFSETOF(ATADevState, IMount)) )
c66c4413faa5a72ce047742f9acfa85e94dec8afvboxsync#define PDMIMOUNTNOTIFY_2_ATASTATE(pInterface) ( (ATADevState *)((uintptr_t)(pInterface) - RT_OFFSETOF(ATADevState, IMountNotify)) )
c66c4413faa5a72ce047742f9acfa85e94dec8afvboxsync#define PCIDEV_2_PCIATASTATE(pPciDev) ( (PCIATAState *)(pPciDev) )
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync#define ATACONTROLLER_IDX(pController) ( (pController) - PDMINS_2_DATA(CONTROLLER_2_DEVINS(pController), PCIATAState *)->aCts )
c66c4413faa5a72ce047742f9acfa85e94dec8afvboxsync
c66c4413faa5a72ce047742f9acfa85e94dec8afvboxsync#define ATADEVSTATE_2_CONTROLLER(pIf) ( (pIf)->CTX_SUFF(pController) )
c66c4413faa5a72ce047742f9acfa85e94dec8afvboxsync#define ATADEVSTATE_2_DEVINS(pIf) ( (pIf)->CTX_SUFF(pDevIns) )
c66c4413faa5a72ce047742f9acfa85e94dec8afvboxsync#define CONTROLLER_2_DEVINS(pController) ( (pController)->CTX_SUFF(pDevIns) )
c66c4413faa5a72ce047742f9acfa85e94dec8afvboxsync#define PDMIBASE_2_ATASTATE(pInterface) ( (ATADevState *)((uintptr_t)(pInterface) - RT_OFFSETOF(ATADevState, IBase)) )
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync#ifndef VBOX_DEVICE_STRUCT_TESTCASE
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync/*******************************************************************************
66b58af085e22ee26be57f98127fb49ee2e91790vboxsync * Internal Functions *
66b58af085e22ee26be57f98127fb49ee2e91790vboxsync ******************************************************************************/
66b58af085e22ee26be57f98127fb49ee2e91790vboxsync__BEGIN_DECLS
66b58af085e22ee26be57f98127fb49ee2e91790vboxsyncPDMBOTHCBDECL(int) ataIOPortWrite1(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb);
66b58af085e22ee26be57f98127fb49ee2e91790vboxsyncPDMBOTHCBDECL(int) ataIOPortRead1(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t *u32, unsigned cb);
66b58af085e22ee26be57f98127fb49ee2e91790vboxsyncPDMBOTHCBDECL(int) ataIOPortWriteStr1(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, RTGCPTR *pGCPtrSrc, PRTGCUINTREG pcTransfer, unsigned cb);
66b58af085e22ee26be57f98127fb49ee2e91790vboxsyncPDMBOTHCBDECL(int) ataIOPortReadStr1(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, RTGCPTR *pGCPtrDst, PRTGCUINTREG pcTransfer, unsigned cb);
66b58af085e22ee26be57f98127fb49ee2e91790vboxsyncPDMBOTHCBDECL(int) ataIOPortWrite2(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb);
66b58af085e22ee26be57f98127fb49ee2e91790vboxsyncPDMBOTHCBDECL(int) ataIOPortRead2(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t *u32, unsigned cb);
19320d55d1417c39b3b5673a53aaa5ef177242c8vboxsyncPDMBOTHCBDECL(int) ataBMDMAIOPortWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb);
19320d55d1417c39b3b5673a53aaa5ef177242c8vboxsyncPDMBOTHCBDECL(int) ataBMDMAIOPortRead(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t *pu32, unsigned cb);
19320d55d1417c39b3b5673a53aaa5ef177242c8vboxsync__END_DECLS
19320d55d1417c39b3b5673a53aaa5ef177242c8vboxsync
f9cdd92d151d9c28eb0f1aed25863fc04f85691dvboxsync
f9cdd92d151d9c28eb0f1aed25863fc04f85691dvboxsync
f9cdd92d151d9c28eb0f1aed25863fc04f85691dvboxsyncDECLINLINE(void) ataSetStatusValue(ATADevState *s, uint8_t stat)
f9cdd92d151d9c28eb0f1aed25863fc04f85691dvboxsync{
f9cdd92d151d9c28eb0f1aed25863fc04f85691dvboxsync PATACONTROLLER pCtl = ATADEVSTATE_2_CONTROLLER(s);
19320d55d1417c39b3b5673a53aaa5ef177242c8vboxsync
19320d55d1417c39b3b5673a53aaa5ef177242c8vboxsync /* Freeze status register contents while processing RESET. */
661bfa5aae55ac2f94fa1cb131ea2323e5f6e633vboxsync if (!pCtl->fReset)
661bfa5aae55ac2f94fa1cb131ea2323e5f6e633vboxsync {
661bfa5aae55ac2f94fa1cb131ea2323e5f6e633vboxsync s->uATARegStatus = stat;
661bfa5aae55ac2f94fa1cb131ea2323e5f6e633vboxsync Log2(("%s: LUN#%d status %#04x\n", __FUNCTION__, s->iLUN, s->uATARegStatus));
19320d55d1417c39b3b5673a53aaa5ef177242c8vboxsync }
661bfa5aae55ac2f94fa1cb131ea2323e5f6e633vboxsync}
19320d55d1417c39b3b5673a53aaa5ef177242c8vboxsync
661bfa5aae55ac2f94fa1cb131ea2323e5f6e633vboxsync
661bfa5aae55ac2f94fa1cb131ea2323e5f6e633vboxsyncDECLINLINE(void) ataSetStatus(ATADevState *s, uint8_t stat)
661bfa5aae55ac2f94fa1cb131ea2323e5f6e633vboxsync{
661bfa5aae55ac2f94fa1cb131ea2323e5f6e633vboxsync PATACONTROLLER pCtl = ATADEVSTATE_2_CONTROLLER(s);
82e3a4017d20f44c30ff909e6b825ff78139cbbbvboxsync
661bfa5aae55ac2f94fa1cb131ea2323e5f6e633vboxsync /* Freeze status register contents while processing RESET. */
19320d55d1417c39b3b5673a53aaa5ef177242c8vboxsync if (!pCtl->fReset)
661bfa5aae55ac2f94fa1cb131ea2323e5f6e633vboxsync {
661bfa5aae55ac2f94fa1cb131ea2323e5f6e633vboxsync s->uATARegStatus |= stat;
661bfa5aae55ac2f94fa1cb131ea2323e5f6e633vboxsync Log2(("%s: LUN#%d status %#04x\n", __FUNCTION__, s->iLUN, s->uATARegStatus));
661bfa5aae55ac2f94fa1cb131ea2323e5f6e633vboxsync }
38745c55f37c31ba8b78cc728d2f08ea6eec38d6vboxsync}
1379dfd407ada5fab15655776896f13b61a951fdvboxsync
38745c55f37c31ba8b78cc728d2f08ea6eec38d6vboxsync
38745c55f37c31ba8b78cc728d2f08ea6eec38d6vboxsyncDECLINLINE(void) ataUnsetStatus(ATADevState *s, uint8_t stat)
38745c55f37c31ba8b78cc728d2f08ea6eec38d6vboxsync{
38745c55f37c31ba8b78cc728d2f08ea6eec38d6vboxsync PATACONTROLLER pCtl = ATADEVSTATE_2_CONTROLLER(s);
1379dfd407ada5fab15655776896f13b61a951fdvboxsync
38745c55f37c31ba8b78cc728d2f08ea6eec38d6vboxsync /* Freeze status register contents while processing RESET. */
f9cdd92d151d9c28eb0f1aed25863fc04f85691dvboxsync if (!pCtl->fReset)
19320d55d1417c39b3b5673a53aaa5ef177242c8vboxsync {
661bfa5aae55ac2f94fa1cb131ea2323e5f6e633vboxsync s->uATARegStatus &= ~stat;
661bfa5aae55ac2f94fa1cb131ea2323e5f6e633vboxsync Log2(("%s: LUN#%d status %#04x\n", __FUNCTION__, s->iLUN, s->uATARegStatus));
661bfa5aae55ac2f94fa1cb131ea2323e5f6e633vboxsync }
661bfa5aae55ac2f94fa1cb131ea2323e5f6e633vboxsync}
1379dfd407ada5fab15655776896f13b61a951fdvboxsync
661bfa5aae55ac2f94fa1cb131ea2323e5f6e633vboxsync#ifdef IN_RING3
1379dfd407ada5fab15655776896f13b61a951fdvboxsync
1379dfd407ada5fab15655776896f13b61a951fdvboxsynctypedef void (*PBeginTransferFunc)(ATADevState *);
661bfa5aae55ac2f94fa1cb131ea2323e5f6e633vboxsynctypedef bool (*PSourceSinkFunc)(ATADevState *);
661bfa5aae55ac2f94fa1cb131ea2323e5f6e633vboxsync
661bfa5aae55ac2f94fa1cb131ea2323e5f6e633vboxsyncstatic void ataReadWriteSectorsBT(ATADevState *);
19320d55d1417c39b3b5673a53aaa5ef177242c8vboxsyncstatic void ataPacketBT(ATADevState *);
19320d55d1417c39b3b5673a53aaa5ef177242c8vboxsyncstatic void atapiCmdBT(ATADevState *);
19320d55d1417c39b3b5673a53aaa5ef177242c8vboxsyncstatic void atapiPassthroughCmdBT(ATADevState *);
66b58af085e22ee26be57f98127fb49ee2e91790vboxsync
661bfa5aae55ac2f94fa1cb131ea2323e5f6e633vboxsyncstatic bool ataIdentifySS(ATADevState *);
661bfa5aae55ac2f94fa1cb131ea2323e5f6e633vboxsyncstatic bool ataFlushSS(ATADevState *);
661bfa5aae55ac2f94fa1cb131ea2323e5f6e633vboxsyncstatic bool ataReadSectorsSS(ATADevState *);
661bfa5aae55ac2f94fa1cb131ea2323e5f6e633vboxsyncstatic bool ataWriteSectorsSS(ATADevState *);
20f21077abf35d7b7b618acb159267933907407fvboxsyncstatic bool ataExecuteDeviceDiagnosticSS(ATADevState *);
661bfa5aae55ac2f94fa1cb131ea2323e5f6e633vboxsyncstatic bool ataPacketSS(ATADevState *);
661bfa5aae55ac2f94fa1cb131ea2323e5f6e633vboxsyncstatic bool atapiGetConfigurationSS(ATADevState *);
661bfa5aae55ac2f94fa1cb131ea2323e5f6e633vboxsyncstatic bool atapiGetEventStatusNotificationSS(ATADevState *);
661bfa5aae55ac2f94fa1cb131ea2323e5f6e633vboxsyncstatic bool atapiIdentifySS(ATADevState *);
661bfa5aae55ac2f94fa1cb131ea2323e5f6e633vboxsyncstatic bool atapiInquirySS(ATADevState *);
661bfa5aae55ac2f94fa1cb131ea2323e5f6e633vboxsyncstatic bool atapiMechanismStatusSS(ATADevState *);
661bfa5aae55ac2f94fa1cb131ea2323e5f6e633vboxsyncstatic bool atapiModeSenseErrorRecoverySS(ATADevState *);
661bfa5aae55ac2f94fa1cb131ea2323e5f6e633vboxsyncstatic bool atapiModeSenseCDStatusSS(ATADevState *);
661bfa5aae55ac2f94fa1cb131ea2323e5f6e633vboxsyncstatic bool atapiReadSS(ATADevState *);
661bfa5aae55ac2f94fa1cb131ea2323e5f6e633vboxsyncstatic bool atapiReadCapacitySS(ATADevState *);
661bfa5aae55ac2f94fa1cb131ea2323e5f6e633vboxsyncstatic bool atapiReadDiscInformationSS(ATADevState *);
661bfa5aae55ac2f94fa1cb131ea2323e5f6e633vboxsyncstatic bool atapiReadTOCNormalSS(ATADevState *);
82e3a4017d20f44c30ff909e6b825ff78139cbbbvboxsyncstatic bool atapiReadTOCMultiSS(ATADevState *);
82e3a4017d20f44c30ff909e6b825ff78139cbbbvboxsyncstatic bool atapiReadTOCRawSS(ATADevState *);
82e3a4017d20f44c30ff909e6b825ff78139cbbbvboxsyncstatic bool atapiReadTrackInformationSS(ATADevState *);
82e3a4017d20f44c30ff909e6b825ff78139cbbbvboxsyncstatic bool atapiRequestSenseSS(ATADevState *);
82e3a4017d20f44c30ff909e6b825ff78139cbbbvboxsyncstatic bool atapiPassthroughSS(ATADevState *);
82e3a4017d20f44c30ff909e6b825ff78139cbbbvboxsync
661bfa5aae55ac2f94fa1cb131ea2323e5f6e633vboxsync/**
661bfa5aae55ac2f94fa1cb131ea2323e5f6e633vboxsync * Begin of transfer function indexes for g_apfnBeginTransFuncs.
82e3a4017d20f44c30ff909e6b825ff78139cbbbvboxsync */
19320d55d1417c39b3b5673a53aaa5ef177242c8vboxsynctypedef enum ATAFNBT
19320d55d1417c39b3b5673a53aaa5ef177242c8vboxsync{
19320d55d1417c39b3b5673a53aaa5ef177242c8vboxsync ATAFN_BT_NULL = 0,
19320d55d1417c39b3b5673a53aaa5ef177242c8vboxsync ATAFN_BT_READ_WRITE_SECTORS,
66b58af085e22ee26be57f98127fb49ee2e91790vboxsync ATAFN_BT_PACKET,
661bfa5aae55ac2f94fa1cb131ea2323e5f6e633vboxsync ATAFN_BT_ATAPI_CMD,
66b58af085e22ee26be57f98127fb49ee2e91790vboxsync ATAFN_BT_ATAPI_PASSTHROUGH_CMD,
0c94a8282c9042b02f022302a3d987746140eab9vboxsync ATAFN_BT_MAX
19320d55d1417c39b3b5673a53aaa5ef177242c8vboxsync} ATAFNBT;
19320d55d1417c39b3b5673a53aaa5ef177242c8vboxsync
19320d55d1417c39b3b5673a53aaa5ef177242c8vboxsync/**
19320d55d1417c39b3b5673a53aaa5ef177242c8vboxsync * Array of end transfer functions, the index is ATAFNET.
19320d55d1417c39b3b5673a53aaa5ef177242c8vboxsync * Make sure ATAFNET and this array match!
19320d55d1417c39b3b5673a53aaa5ef177242c8vboxsync */
19320d55d1417c39b3b5673a53aaa5ef177242c8vboxsyncstatic const PBeginTransferFunc g_apfnBeginTransFuncs[ATAFN_BT_MAX] =
19320d55d1417c39b3b5673a53aaa5ef177242c8vboxsync{
661bfa5aae55ac2f94fa1cb131ea2323e5f6e633vboxsync NULL,
19320d55d1417c39b3b5673a53aaa5ef177242c8vboxsync ataReadWriteSectorsBT,
c66c4413faa5a72ce047742f9acfa85e94dec8afvboxsync ataPacketBT,
c66c4413faa5a72ce047742f9acfa85e94dec8afvboxsync atapiCmdBT,
19320d55d1417c39b3b5673a53aaa5ef177242c8vboxsync atapiPassthroughCmdBT,
c66c4413faa5a72ce047742f9acfa85e94dec8afvboxsync};
19320d55d1417c39b3b5673a53aaa5ef177242c8vboxsync
19320d55d1417c39b3b5673a53aaa5ef177242c8vboxsync/**
661bfa5aae55ac2f94fa1cb131ea2323e5f6e633vboxsync * Source/sink function indexes for g_apfnSourceSinkFuncs.
19320d55d1417c39b3b5673a53aaa5ef177242c8vboxsync */
fdb40b7d2efa84fc6f03b7a695cb4b2e035c30c7vboxsynctypedef enum ATAFNSS
c66c4413faa5a72ce047742f9acfa85e94dec8afvboxsync{
19320d55d1417c39b3b5673a53aaa5ef177242c8vboxsync ATAFN_SS_NULL = 0,
19320d55d1417c39b3b5673a53aaa5ef177242c8vboxsync ATAFN_SS_IDENTIFY,
661bfa5aae55ac2f94fa1cb131ea2323e5f6e633vboxsync ATAFN_SS_FLUSH,
c66c4413faa5a72ce047742f9acfa85e94dec8afvboxsync ATAFN_SS_READ_SECTORS,
c66c4413faa5a72ce047742f9acfa85e94dec8afvboxsync ATAFN_SS_WRITE_SECTORS,
19320d55d1417c39b3b5673a53aaa5ef177242c8vboxsync ATAFN_SS_EXECUTE_DEVICE_DIAGNOSTIC,
19320d55d1417c39b3b5673a53aaa5ef177242c8vboxsync ATAFN_SS_PACKET,
19320d55d1417c39b3b5673a53aaa5ef177242c8vboxsync ATAFN_SS_ATAPI_GET_CONFIGURATION,
0c94a8282c9042b02f022302a3d987746140eab9vboxsync ATAFN_SS_ATAPI_GET_EVENT_STATUS_NOTIFICATION,
0c94a8282c9042b02f022302a3d987746140eab9vboxsync ATAFN_SS_ATAPI_IDENTIFY,
c66c4413faa5a72ce047742f9acfa85e94dec8afvboxsync ATAFN_SS_ATAPI_INQUIRY,
0c94a8282c9042b02f022302a3d987746140eab9vboxsync ATAFN_SS_ATAPI_MECHANISM_STATUS,
0c94a8282c9042b02f022302a3d987746140eab9vboxsync ATAFN_SS_ATAPI_MODE_SENSE_ERROR_RECOVERY,
0c94a8282c9042b02f022302a3d987746140eab9vboxsync ATAFN_SS_ATAPI_MODE_SENSE_CD_STATUS,
661bfa5aae55ac2f94fa1cb131ea2323e5f6e633vboxsync ATAFN_SS_ATAPI_READ,
0c94a8282c9042b02f022302a3d987746140eab9vboxsync ATAFN_SS_ATAPI_READ_CAPACITY,
0c94a8282c9042b02f022302a3d987746140eab9vboxsync ATAFN_SS_ATAPI_READ_DISC_INFORMATION,
0c94a8282c9042b02f022302a3d987746140eab9vboxsync ATAFN_SS_ATAPI_READ_TOC_NORMAL,
661bfa5aae55ac2f94fa1cb131ea2323e5f6e633vboxsync ATAFN_SS_ATAPI_READ_TOC_MULTI,
0c94a8282c9042b02f022302a3d987746140eab9vboxsync ATAFN_SS_ATAPI_READ_TOC_RAW,
66b58af085e22ee26be57f98127fb49ee2e91790vboxsync ATAFN_SS_ATAPI_READ_TRACK_INFORMATION,
19320d55d1417c39b3b5673a53aaa5ef177242c8vboxsync ATAFN_SS_ATAPI_REQUEST_SENSE,
66b58af085e22ee26be57f98127fb49ee2e91790vboxsync ATAFN_SS_ATAPI_PASSTHROUGH,
66b58af085e22ee26be57f98127fb49ee2e91790vboxsync ATAFN_SS_MAX
c66c4413faa5a72ce047742f9acfa85e94dec8afvboxsync} ATAFNSS;
66b58af085e22ee26be57f98127fb49ee2e91790vboxsync
19320d55d1417c39b3b5673a53aaa5ef177242c8vboxsync/**
66b58af085e22ee26be57f98127fb49ee2e91790vboxsync * Array of source/sink functions, the index is ATAFNSS.
661bfa5aae55ac2f94fa1cb131ea2323e5f6e633vboxsync * Make sure ATAFNSS and this array match!
19320d55d1417c39b3b5673a53aaa5ef177242c8vboxsync */
c66c4413faa5a72ce047742f9acfa85e94dec8afvboxsyncstatic const PSourceSinkFunc g_apfnSourceSinkFuncs[ATAFN_SS_MAX] =
66b58af085e22ee26be57f98127fb49ee2e91790vboxsync{
c66c4413faa5a72ce047742f9acfa85e94dec8afvboxsync NULL,
66b58af085e22ee26be57f98127fb49ee2e91790vboxsync ataIdentifySS,
19320d55d1417c39b3b5673a53aaa5ef177242c8vboxsync ataFlushSS,
19320d55d1417c39b3b5673a53aaa5ef177242c8vboxsync ataReadSectorsSS,
19320d55d1417c39b3b5673a53aaa5ef177242c8vboxsync ataWriteSectorsSS,
19320d55d1417c39b3b5673a53aaa5ef177242c8vboxsync ataExecuteDeviceDiagnosticSS,
19320d55d1417c39b3b5673a53aaa5ef177242c8vboxsync ataPacketSS,
66b58af085e22ee26be57f98127fb49ee2e91790vboxsync atapiGetConfigurationSS,
19320d55d1417c39b3b5673a53aaa5ef177242c8vboxsync atapiGetEventStatusNotificationSS,
20f21077abf35d7b7b618acb159267933907407fvboxsync atapiIdentifySS,
20f21077abf35d7b7b618acb159267933907407fvboxsync atapiInquirySS,
20f21077abf35d7b7b618acb159267933907407fvboxsync atapiMechanismStatusSS,
0d8c2135d15345cc68111eea91052cdf5518d7e3vboxsync atapiModeSenseErrorRecoverySS,
19320d55d1417c39b3b5673a53aaa5ef177242c8vboxsync atapiModeSenseCDStatusSS,
19320d55d1417c39b3b5673a53aaa5ef177242c8vboxsync atapiReadSS,
19320d55d1417c39b3b5673a53aaa5ef177242c8vboxsync atapiReadCapacitySS,
19320d55d1417c39b3b5673a53aaa5ef177242c8vboxsync atapiReadDiscInformationSS,
20f21077abf35d7b7b618acb159267933907407fvboxsync atapiReadTOCNormalSS,
e250515922582e0410c9bcb6d24b0f17bef083a0vboxsync atapiReadTOCMultiSS,
e250515922582e0410c9bcb6d24b0f17bef083a0vboxsync atapiReadTOCRawSS,
e250515922582e0410c9bcb6d24b0f17bef083a0vboxsync atapiReadTrackInformationSS,
19320d55d1417c39b3b5673a53aaa5ef177242c8vboxsync atapiRequestSenseSS,
19320d55d1417c39b3b5673a53aaa5ef177242c8vboxsync atapiPassthroughSS
19320d55d1417c39b3b5673a53aaa5ef177242c8vboxsync};
19320d55d1417c39b3b5673a53aaa5ef177242c8vboxsync
19320d55d1417c39b3b5673a53aaa5ef177242c8vboxsync
19320d55d1417c39b3b5673a53aaa5ef177242c8vboxsyncstatic const ATARequest ataDMARequest = { ATA_AIO_DMA, };
19320d55d1417c39b3b5673a53aaa5ef177242c8vboxsyncstatic const ATARequest ataPIORequest = { ATA_AIO_PIO, };
19320d55d1417c39b3b5673a53aaa5ef177242c8vboxsyncstatic const ATARequest ataResetARequest = { ATA_AIO_RESET_ASSERTED, };
c66c4413faa5a72ce047742f9acfa85e94dec8afvboxsyncstatic const ATARequest ataResetCRequest = { ATA_AIO_RESET_CLEARED, };
19320d55d1417c39b3b5673a53aaa5ef177242c8vboxsync
19320d55d1417c39b3b5673a53aaa5ef177242c8vboxsync
19320d55d1417c39b3b5673a53aaa5ef177242c8vboxsyncstatic void ataAsyncIOClearRequests(PATACONTROLLER pCtl)
19320d55d1417c39b3b5673a53aaa5ef177242c8vboxsync{
19320d55d1417c39b3b5673a53aaa5ef177242c8vboxsync int rc;
19320d55d1417c39b3b5673a53aaa5ef177242c8vboxsync
19320d55d1417c39b3b5673a53aaa5ef177242c8vboxsync rc = RTSemMutexRequest(pCtl->AsyncIORequestMutex, RT_INDEFINITE_WAIT);
19320d55d1417c39b3b5673a53aaa5ef177242c8vboxsync AssertRC(rc);
19320d55d1417c39b3b5673a53aaa5ef177242c8vboxsync pCtl->AsyncIOReqHead = 0;
19320d55d1417c39b3b5673a53aaa5ef177242c8vboxsync pCtl->AsyncIOReqTail = 0;
19320d55d1417c39b3b5673a53aaa5ef177242c8vboxsync rc = RTSemMutexRelease(pCtl->AsyncIORequestMutex);
dcb99408dc4f7a2a640ec18b7f9df885bef1f154vboxsync AssertRC(rc);
dcb99408dc4f7a2a640ec18b7f9df885bef1f154vboxsync}
19320d55d1417c39b3b5673a53aaa5ef177242c8vboxsync
19320d55d1417c39b3b5673a53aaa5ef177242c8vboxsync
19320d55d1417c39b3b5673a53aaa5ef177242c8vboxsyncstatic void ataAsyncIOPutRequest(PATACONTROLLER pCtl, const ATARequest *pReq)
19320d55d1417c39b3b5673a53aaa5ef177242c8vboxsync{
19320d55d1417c39b3b5673a53aaa5ef177242c8vboxsync int rc;
19320d55d1417c39b3b5673a53aaa5ef177242c8vboxsync
19320d55d1417c39b3b5673a53aaa5ef177242c8vboxsync rc = RTSemMutexRequest(pCtl->AsyncIORequestMutex, RT_INDEFINITE_WAIT);
19320d55d1417c39b3b5673a53aaa5ef177242c8vboxsync AssertRC(rc);
19320d55d1417c39b3b5673a53aaa5ef177242c8vboxsync Assert((pCtl->AsyncIOReqHead + 1) % RT_ELEMENTS(pCtl->aAsyncIORequests) != pCtl->AsyncIOReqTail);
66b58af085e22ee26be57f98127fb49ee2e91790vboxsync memcpy(&pCtl->aAsyncIORequests[pCtl->AsyncIOReqHead], pReq, sizeof(*pReq));
66b58af085e22ee26be57f98127fb49ee2e91790vboxsync pCtl->AsyncIOReqHead++;
19320d55d1417c39b3b5673a53aaa5ef177242c8vboxsync pCtl->AsyncIOReqHead %= RT_ELEMENTS(pCtl->aAsyncIORequests);
661bfa5aae55ac2f94fa1cb131ea2323e5f6e633vboxsync rc = RTSemMutexRelease(pCtl->AsyncIORequestMutex);
19320d55d1417c39b3b5673a53aaa5ef177242c8vboxsync AssertRC(rc);
66b58af085e22ee26be57f98127fb49ee2e91790vboxsync LogBird(("ata: %x: signalling\n", pCtl->IOPortBase1));
66b58af085e22ee26be57f98127fb49ee2e91790vboxsync rc = PDMR3CritSectScheduleExitEvent(&pCtl->lock, pCtl->AsyncIOSem);
c66c4413faa5a72ce047742f9acfa85e94dec8afvboxsync if (RT_FAILURE(rc))
66b58af085e22ee26be57f98127fb49ee2e91790vboxsync {
66b58af085e22ee26be57f98127fb49ee2e91790vboxsync LogBird(("ata: %x: schedule failed, rc=%Rrc\n", pCtl->IOPortBase1, rc));
66b58af085e22ee26be57f98127fb49ee2e91790vboxsync rc = RTSemEventSignal(pCtl->AsyncIOSem);
66b58af085e22ee26be57f98127fb49ee2e91790vboxsync AssertRC(rc);
19320d55d1417c39b3b5673a53aaa5ef177242c8vboxsync }
66b58af085e22ee26be57f98127fb49ee2e91790vboxsync}
661bfa5aae55ac2f94fa1cb131ea2323e5f6e633vboxsync
66b58af085e22ee26be57f98127fb49ee2e91790vboxsync
c66c4413faa5a72ce047742f9acfa85e94dec8afvboxsyncstatic const ATARequest *ataAsyncIOGetCurrentRequest(PATACONTROLLER pCtl)
19320d55d1417c39b3b5673a53aaa5ef177242c8vboxsync{
c66c4413faa5a72ce047742f9acfa85e94dec8afvboxsync int rc;
66b58af085e22ee26be57f98127fb49ee2e91790vboxsync const ATARequest *pReq;
c66c4413faa5a72ce047742f9acfa85e94dec8afvboxsync
c66c4413faa5a72ce047742f9acfa85e94dec8afvboxsync rc = RTSemMutexRequest(pCtl->AsyncIORequestMutex, RT_INDEFINITE_WAIT);
66b58af085e22ee26be57f98127fb49ee2e91790vboxsync AssertRC(rc);
19320d55d1417c39b3b5673a53aaa5ef177242c8vboxsync if (pCtl->AsyncIOReqHead != pCtl->AsyncIOReqTail)
661bfa5aae55ac2f94fa1cb131ea2323e5f6e633vboxsync pReq = &pCtl->aAsyncIORequests[pCtl->AsyncIOReqTail];
19320d55d1417c39b3b5673a53aaa5ef177242c8vboxsync else
19320d55d1417c39b3b5673a53aaa5ef177242c8vboxsync pReq = NULL;
82e3a4017d20f44c30ff909e6b825ff78139cbbbvboxsync rc = RTSemMutexRelease(pCtl->AsyncIORequestMutex);
c66c4413faa5a72ce047742f9acfa85e94dec8afvboxsync AssertRC(rc);
20f21077abf35d7b7b618acb159267933907407fvboxsync return pReq;
20f21077abf35d7b7b618acb159267933907407fvboxsync}
20f21077abf35d7b7b618acb159267933907407fvboxsync
19320d55d1417c39b3b5673a53aaa5ef177242c8vboxsync
fdb40b7d2efa84fc6f03b7a695cb4b2e035c30c7vboxsync/**
fdb40b7d2efa84fc6f03b7a695cb4b2e035c30c7vboxsync * Remove the request with the given type, as it's finished. The request
19320d55d1417c39b3b5673a53aaa5ef177242c8vboxsync * is not removed blindly, as this could mean a RESET request that is not
fdb40b7d2efa84fc6f03b7a695cb4b2e035c30c7vboxsync * yet processed (but has cleared the request queue) is lost.
20f21077abf35d7b7b618acb159267933907407fvboxsync *
20f21077abf35d7b7b618acb159267933907407fvboxsync * @param pCtl Controller for which to remove the request.
20f21077abf35d7b7b618acb159267933907407fvboxsync * @param ReqType Type of the request to remove.
19320d55d1417c39b3b5673a53aaa5ef177242c8vboxsync */
19320d55d1417c39b3b5673a53aaa5ef177242c8vboxsyncstatic void ataAsyncIORemoveCurrentRequest(PATACONTROLLER pCtl, ATAAIO ReqType)
66b58af085e22ee26be57f98127fb49ee2e91790vboxsync{
c66c4413faa5a72ce047742f9acfa85e94dec8afvboxsync int rc;
c66c4413faa5a72ce047742f9acfa85e94dec8afvboxsync
66b58af085e22ee26be57f98127fb49ee2e91790vboxsync rc = RTSemMutexRequest(pCtl->AsyncIORequestMutex, RT_INDEFINITE_WAIT);
661bfa5aae55ac2f94fa1cb131ea2323e5f6e633vboxsync AssertRC(rc);
19320d55d1417c39b3b5673a53aaa5ef177242c8vboxsync if (pCtl->AsyncIOReqHead != pCtl->AsyncIOReqTail && pCtl->aAsyncIORequests[pCtl->AsyncIOReqTail].ReqType == ReqType)
19320d55d1417c39b3b5673a53aaa5ef177242c8vboxsync {
19320d55d1417c39b3b5673a53aaa5ef177242c8vboxsync pCtl->AsyncIOReqTail++;
19320d55d1417c39b3b5673a53aaa5ef177242c8vboxsync pCtl->AsyncIOReqTail %= RT_ELEMENTS(pCtl->aAsyncIORequests);
19320d55d1417c39b3b5673a53aaa5ef177242c8vboxsync }
19320d55d1417c39b3b5673a53aaa5ef177242c8vboxsync rc = RTSemMutexRelease(pCtl->AsyncIORequestMutex);
19320d55d1417c39b3b5673a53aaa5ef177242c8vboxsync AssertRC(rc);
19320d55d1417c39b3b5673a53aaa5ef177242c8vboxsync}
19320d55d1417c39b3b5673a53aaa5ef177242c8vboxsync
661bfa5aae55ac2f94fa1cb131ea2323e5f6e633vboxsync
c66c4413faa5a72ce047742f9acfa85e94dec8afvboxsync/**
c66c4413faa5a72ce047742f9acfa85e94dec8afvboxsync * Dump the request queue for a particular controller. First dump the queue
19320d55d1417c39b3b5673a53aaa5ef177242c8vboxsync * contents, then the already processed entries, as long as they haven't been
19320d55d1417c39b3b5673a53aaa5ef177242c8vboxsync * overwritten.
c66c4413faa5a72ce047742f9acfa85e94dec8afvboxsync *
19320d55d1417c39b3b5673a53aaa5ef177242c8vboxsync * @param pCtl Controller for which to dump the queue.
c66c4413faa5a72ce047742f9acfa85e94dec8afvboxsync */
c66c4413faa5a72ce047742f9acfa85e94dec8afvboxsyncstatic void ataAsyncIODumpRequests(PATACONTROLLER pCtl)
c66c4413faa5a72ce047742f9acfa85e94dec8afvboxsync{
c66c4413faa5a72ce047742f9acfa85e94dec8afvboxsync int rc;
c66c4413faa5a72ce047742f9acfa85e94dec8afvboxsync uint8_t curr;
c66c4413faa5a72ce047742f9acfa85e94dec8afvboxsync
c66c4413faa5a72ce047742f9acfa85e94dec8afvboxsync rc = RTSemMutexRequest(pCtl->AsyncIORequestMutex, RT_INDEFINITE_WAIT);
c66c4413faa5a72ce047742f9acfa85e94dec8afvboxsync AssertRC(rc);
19320d55d1417c39b3b5673a53aaa5ef177242c8vboxsync LogRel(("PIIX3 ATA: Ctl#%d: request queue dump (topmost is current):\n", ATACONTROLLER_IDX(pCtl)));
c66c4413faa5a72ce047742f9acfa85e94dec8afvboxsync curr = pCtl->AsyncIOReqTail;
c66c4413faa5a72ce047742f9acfa85e94dec8afvboxsync do
c66c4413faa5a72ce047742f9acfa85e94dec8afvboxsync {
c66c4413faa5a72ce047742f9acfa85e94dec8afvboxsync if (curr == pCtl->AsyncIOReqHead)
c66c4413faa5a72ce047742f9acfa85e94dec8afvboxsync LogRel(("PIIX3 ATA: Ctl#%d: processed requests (topmost is oldest):\n", ATACONTROLLER_IDX(pCtl)));
c66c4413faa5a72ce047742f9acfa85e94dec8afvboxsync switch (pCtl->aAsyncIORequests[curr].ReqType)
c66c4413faa5a72ce047742f9acfa85e94dec8afvboxsync {
c66c4413faa5a72ce047742f9acfa85e94dec8afvboxsync case ATA_AIO_NEW:
c66c4413faa5a72ce047742f9acfa85e94dec8afvboxsync LogRel(("new transfer request, iIf=%d iBeginTransfer=%d iSourceSink=%d cbTotalTransfer=%d uTxDir=%d\n", pCtl->aAsyncIORequests[curr].u.t.iIf, pCtl->aAsyncIORequests[curr].u.t.iBeginTransfer, pCtl->aAsyncIORequests[curr].u.t.iSourceSink, pCtl->aAsyncIORequests[curr].u.t.cbTotalTransfer, pCtl->aAsyncIORequests[curr].u.t.uTxDir));
19320d55d1417c39b3b5673a53aaa5ef177242c8vboxsync break;
19320d55d1417c39b3b5673a53aaa5ef177242c8vboxsync case ATA_AIO_DMA:
661bfa5aae55ac2f94fa1cb131ea2323e5f6e633vboxsync LogRel(("dma transfer finished\n"));
19320d55d1417c39b3b5673a53aaa5ef177242c8vboxsync break;
19320d55d1417c39b3b5673a53aaa5ef177242c8vboxsync case ATA_AIO_PIO:
19320d55d1417c39b3b5673a53aaa5ef177242c8vboxsync LogRel(("pio transfer finished\n"));
19320d55d1417c39b3b5673a53aaa5ef177242c8vboxsync break;
9b1d52365befbce1af8f32d53c2e563ee9169501vboxsync case ATA_AIO_RESET_ASSERTED:
9b1d52365befbce1af8f32d53c2e563ee9169501vboxsync LogRel(("reset asserted request\n"));
9b1d52365befbce1af8f32d53c2e563ee9169501vboxsync break;
c66c4413faa5a72ce047742f9acfa85e94dec8afvboxsync case ATA_AIO_RESET_CLEARED:
c66c4413faa5a72ce047742f9acfa85e94dec8afvboxsync LogRel(("reset cleared request\n"));
c66c4413faa5a72ce047742f9acfa85e94dec8afvboxsync break;
c66c4413faa5a72ce047742f9acfa85e94dec8afvboxsync case ATA_AIO_ABORT:
c66c4413faa5a72ce047742f9acfa85e94dec8afvboxsync LogRel(("abort request, iIf=%d fResetDrive=%d\n", pCtl->aAsyncIORequests[curr].u.a.iIf, pCtl->aAsyncIORequests[curr].u.a.fResetDrive));
c66c4413faa5a72ce047742f9acfa85e94dec8afvboxsync break;
9c9db71d639cf066ed41d49629d46d48bff4be2fvboxsync default:
44372afb953dc9f1f1ec71943f5f561a607c0307vboxsync LogRel(("unknown request %d\n", pCtl->aAsyncIORequests[curr].ReqType));
44372afb953dc9f1f1ec71943f5f561a607c0307vboxsync }
81614fc60e096e714022d10d38b70a36b9b21d48vboxsync curr = (curr + 1) % RT_ELEMENTS(pCtl->aAsyncIORequests);
9b1d52365befbce1af8f32d53c2e563ee9169501vboxsync } while (curr != pCtl->AsyncIOReqTail);
9b1d52365befbce1af8f32d53c2e563ee9169501vboxsync rc = RTSemMutexRelease(pCtl->AsyncIORequestMutex);
9b1d52365befbce1af8f32d53c2e563ee9169501vboxsync AssertRC(rc);
9b1d52365befbce1af8f32d53c2e563ee9169501vboxsync}
9b1d52365befbce1af8f32d53c2e563ee9169501vboxsync
c66c4413faa5a72ce047742f9acfa85e94dec8afvboxsync
c66c4413faa5a72ce047742f9acfa85e94dec8afvboxsync/**
c66c4413faa5a72ce047742f9acfa85e94dec8afvboxsync * Checks whether the request queue for a particular controller is empty
c66c4413faa5a72ce047742f9acfa85e94dec8afvboxsync * or whether a particular controller is idle.
c66c4413faa5a72ce047742f9acfa85e94dec8afvboxsync *
c66c4413faa5a72ce047742f9acfa85e94dec8afvboxsync * @param pCtl Controller for which to check the queue.
661bfa5aae55ac2f94fa1cb131ea2323e5f6e633vboxsync * @param fStrict If set then the controller is checked to be idle.
fdb40b7d2efa84fc6f03b7a695cb4b2e035c30c7vboxsync */
c66c4413faa5a72ce047742f9acfa85e94dec8afvboxsyncstatic bool ataAsyncIOIsIdle(PATACONTROLLER pCtl, bool fStrict)
c66c4413faa5a72ce047742f9acfa85e94dec8afvboxsync{
c66c4413faa5a72ce047742f9acfa85e94dec8afvboxsync int rc;
c66c4413faa5a72ce047742f9acfa85e94dec8afvboxsync bool fIdle;
c66c4413faa5a72ce047742f9acfa85e94dec8afvboxsync
c66c4413faa5a72ce047742f9acfa85e94dec8afvboxsync rc = RTSemMutexRequest(pCtl->AsyncIORequestMutex, RT_INDEFINITE_WAIT);
c66c4413faa5a72ce047742f9acfa85e94dec8afvboxsync AssertRC(rc);
c66c4413faa5a72ce047742f9acfa85e94dec8afvboxsync fIdle = pCtl->fRedoIdle;
c66c4413faa5a72ce047742f9acfa85e94dec8afvboxsync if (!fIdle)
c66c4413faa5a72ce047742f9acfa85e94dec8afvboxsync fIdle = (pCtl->AsyncIOReqHead == pCtl->AsyncIOReqTail);
c66c4413faa5a72ce047742f9acfa85e94dec8afvboxsync if (fStrict)
c66c4413faa5a72ce047742f9acfa85e94dec8afvboxsync fIdle &= (pCtl->uAsyncIOState == ATA_AIO_NEW);
c66c4413faa5a72ce047742f9acfa85e94dec8afvboxsync rc = RTSemMutexRelease(pCtl->AsyncIORequestMutex);
c66c4413faa5a72ce047742f9acfa85e94dec8afvboxsync AssertRC(rc);
c66c4413faa5a72ce047742f9acfa85e94dec8afvboxsync return fIdle;
c66c4413faa5a72ce047742f9acfa85e94dec8afvboxsync}
c66c4413faa5a72ce047742f9acfa85e94dec8afvboxsync
c66c4413faa5a72ce047742f9acfa85e94dec8afvboxsync
c66c4413faa5a72ce047742f9acfa85e94dec8afvboxsync/**
c66c4413faa5a72ce047742f9acfa85e94dec8afvboxsync * Send a transfer request to the async I/O thread.
c66c4413faa5a72ce047742f9acfa85e94dec8afvboxsync *
c66c4413faa5a72ce047742f9acfa85e94dec8afvboxsync * @param s Pointer to the ATA device state data.
c66c4413faa5a72ce047742f9acfa85e94dec8afvboxsync * @param cbTotalTransfer Data transfer size.
c66c4413faa5a72ce047742f9acfa85e94dec8afvboxsync * @param uTxDir Data transfer direction.
8865793e4f3435f5e2c728d9e6739cd24d08c0devboxsync * @param iBeginTransfer Index of BeginTransfer callback.
8865793e4f3435f5e2c728d9e6739cd24d08c0devboxsync * @param iSourceSink Index of SourceSink callback.
8865793e4f3435f5e2c728d9e6739cd24d08c0devboxsync * @param fChainedTransfer Whether this is a transfer that is part of the previous command/transfer.
8865793e4f3435f5e2c728d9e6739cd24d08c0devboxsync */
81614fc60e096e714022d10d38b70a36b9b21d48vboxsyncstatic void ataStartTransfer(ATADevState *s, uint32_t cbTotalTransfer, uint8_t uTxDir, ATAFNBT iBeginTransfer, ATAFNSS iSourceSink, bool fChainedTransfer)
81614fc60e096e714022d10d38b70a36b9b21d48vboxsync{
81614fc60e096e714022d10d38b70a36b9b21d48vboxsync PATACONTROLLER pCtl = ATADEVSTATE_2_CONTROLLER(s);
81614fc60e096e714022d10d38b70a36b9b21d48vboxsync ATARequest Req;
81614fc60e096e714022d10d38b70a36b9b21d48vboxsync
81614fc60e096e714022d10d38b70a36b9b21d48vboxsync Assert(PDMCritSectIsOwner(&pCtl->lock));
81614fc60e096e714022d10d38b70a36b9b21d48vboxsync
81614fc60e096e714022d10d38b70a36b9b21d48vboxsync /* Do not issue new requests while the RESET line is asserted. */
81614fc60e096e714022d10d38b70a36b9b21d48vboxsync if (pCtl->fReset)
81614fc60e096e714022d10d38b70a36b9b21d48vboxsync {
8865793e4f3435f5e2c728d9e6739cd24d08c0devboxsync Log2(("%s: Ctl#%d: suppressed new request as RESET is active\n", __FUNCTION__, ATACONTROLLER_IDX(pCtl)));
8865793e4f3435f5e2c728d9e6739cd24d08c0devboxsync return;
8865793e4f3435f5e2c728d9e6739cd24d08c0devboxsync }
8865793e4f3435f5e2c728d9e6739cd24d08c0devboxsync
44372afb953dc9f1f1ec71943f5f561a607c0307vboxsync /* If the controller is already doing something else right now, ignore
8865793e4f3435f5e2c728d9e6739cd24d08c0devboxsync * the command that is being submitted. Some broken guests issue commands
8865793e4f3435f5e2c728d9e6739cd24d08c0devboxsync * twice (e.g. the Linux kernel that comes with Acronis True Image 8). */
8865793e4f3435f5e2c728d9e6739cd24d08c0devboxsync if (!fChainedTransfer && !ataAsyncIOIsIdle(pCtl, true))
8865793e4f3435f5e2c728d9e6739cd24d08c0devboxsync {
8865793e4f3435f5e2c728d9e6739cd24d08c0devboxsync Log(("%s: Ctl#%d: ignored command %#04x, controller state %d\n", __FUNCTION__, ATACONTROLLER_IDX(pCtl), s->uATARegCommand, pCtl->uAsyncIOState));
8865793e4f3435f5e2c728d9e6739cd24d08c0devboxsync LogRel(("PIIX3 IDE: guest issued command %#04x while controller busy\n", s->uATARegCommand));
8865793e4f3435f5e2c728d9e6739cd24d08c0devboxsync return;
9b1d52365befbce1af8f32d53c2e563ee9169501vboxsync }
9b1d52365befbce1af8f32d53c2e563ee9169501vboxsync
9b1d52365befbce1af8f32d53c2e563ee9169501vboxsync Req.ReqType = ATA_AIO_NEW;
8865793e4f3435f5e2c728d9e6739cd24d08c0devboxsync if (fChainedTransfer)
81614fc60e096e714022d10d38b70a36b9b21d48vboxsync Req.u.t.iIf = pCtl->iAIOIf;
81614fc60e096e714022d10d38b70a36b9b21d48vboxsync else
81614fc60e096e714022d10d38b70a36b9b21d48vboxsync Req.u.t.iIf = pCtl->iSelectedIf;
81614fc60e096e714022d10d38b70a36b9b21d48vboxsync Req.u.t.cbTotalTransfer = cbTotalTransfer;
8865793e4f3435f5e2c728d9e6739cd24d08c0devboxsync Req.u.t.uTxDir = uTxDir;
8865793e4f3435f5e2c728d9e6739cd24d08c0devboxsync Req.u.t.iBeginTransfer = iBeginTransfer;
8865793e4f3435f5e2c728d9e6739cd24d08c0devboxsync Req.u.t.iSourceSink = iSourceSink;
8865793e4f3435f5e2c728d9e6739cd24d08c0devboxsync ataSetStatusValue(s, ATA_STAT_BUSY);
c66c4413faa5a72ce047742f9acfa85e94dec8afvboxsync pCtl->fChainedTransfer = fChainedTransfer;
c66c4413faa5a72ce047742f9acfa85e94dec8afvboxsync
c66c4413faa5a72ce047742f9acfa85e94dec8afvboxsync /*
c66c4413faa5a72ce047742f9acfa85e94dec8afvboxsync * Kick the worker thread into action.
c66c4413faa5a72ce047742f9acfa85e94dec8afvboxsync */
c66c4413faa5a72ce047742f9acfa85e94dec8afvboxsync Log2(("%s: Ctl#%d: message to async I/O thread, new request\n", __FUNCTION__, ATACONTROLLER_IDX(pCtl)));
c66c4413faa5a72ce047742f9acfa85e94dec8afvboxsync ataAsyncIOPutRequest(pCtl, &Req);
66b58af085e22ee26be57f98127fb49ee2e91790vboxsync}
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync/**
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync * Send an abort command request to the async I/O thread.
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync *
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync * @param s Pointer to the ATA device state data.
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync * @param fResetDrive Whether to reset the drive or just abort a command.
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync */
66b58af085e22ee26be57f98127fb49ee2e91790vboxsyncstatic void ataAbortCurrentCommand(ATADevState *s, bool fResetDrive)
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync{
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync PATACONTROLLER pCtl = ATADEVSTATE_2_CONTROLLER(s);
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync ATARequest Req;
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync Assert(PDMCritSectIsOwner(&pCtl->lock));
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync /* Do not issue new requests while the RESET line is asserted. */
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync if (pCtl->fReset)
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync {
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync Log2(("%s: Ctl#%d: suppressed aborting command as RESET is active\n", __FUNCTION__, ATACONTROLLER_IDX(pCtl)));
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync return;
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync }
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync Req.ReqType = ATA_AIO_ABORT;
66b58af085e22ee26be57f98127fb49ee2e91790vboxsync Req.u.a.iIf = pCtl->iSelectedIf;
66b58af085e22ee26be57f98127fb49ee2e91790vboxsync Req.u.a.fResetDrive = fResetDrive;
66b58af085e22ee26be57f98127fb49ee2e91790vboxsync ataSetStatus(s, ATA_STAT_BUSY);
66b58af085e22ee26be57f98127fb49ee2e91790vboxsync Log2(("%s: Ctl#%d: message to async I/O thread, abort command on LUN#%d\n", __FUNCTION__, ATACONTROLLER_IDX(pCtl), s->iLUN));
66b58af085e22ee26be57f98127fb49ee2e91790vboxsync ataAsyncIOPutRequest(pCtl, &Req);
66b58af085e22ee26be57f98127fb49ee2e91790vboxsync}
66b58af085e22ee26be57f98127fb49ee2e91790vboxsync
66b58af085e22ee26be57f98127fb49ee2e91790vboxsync
66b58af085e22ee26be57f98127fb49ee2e91790vboxsyncstatic void ataSetIRQ(ATADevState *s)
66b58af085e22ee26be57f98127fb49ee2e91790vboxsync{
66b58af085e22ee26be57f98127fb49ee2e91790vboxsync PATACONTROLLER pCtl = ATADEVSTATE_2_CONTROLLER(s);
66b58af085e22ee26be57f98127fb49ee2e91790vboxsync PPDMDEVINS pDevIns = ATADEVSTATE_2_DEVINS(s);
66b58af085e22ee26be57f98127fb49ee2e91790vboxsync
66b58af085e22ee26be57f98127fb49ee2e91790vboxsync if (!(s->uATARegDevCtl & ATA_DEVCTL_DISABLE_IRQ))
66b58af085e22ee26be57f98127fb49ee2e91790vboxsync {
66b58af085e22ee26be57f98127fb49ee2e91790vboxsync Log2(("%s: LUN#%d asserting IRQ\n", __FUNCTION__, s->iLUN));
66b58af085e22ee26be57f98127fb49ee2e91790vboxsync /* The BMDMA unit unconditionally sets BM_STATUS_INT if the interrupt
66b58af085e22ee26be57f98127fb49ee2e91790vboxsync * line is asserted. It monitors the line for a rising edge. */
66b58af085e22ee26be57f98127fb49ee2e91790vboxsync if (!s->fIrqPending)
66b58af085e22ee26be57f98127fb49ee2e91790vboxsync pCtl->BmDma.u8Status |= BM_STATUS_INT;
66b58af085e22ee26be57f98127fb49ee2e91790vboxsync /* Only actually set the IRQ line if updating the currently selected drive. */
66b58af085e22ee26be57f98127fb49ee2e91790vboxsync if (s == &pCtl->aIfs[pCtl->iSelectedIf])
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync {
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync /** @todo experiment with adaptive IRQ delivery: for reads it is
66b58af085e22ee26be57f98127fb49ee2e91790vboxsync * better to wait for IRQ delivery, as it reduces latency. */
66b58af085e22ee26be57f98127fb49ee2e91790vboxsync if (pCtl->irq == 16)
66b58af085e22ee26be57f98127fb49ee2e91790vboxsync PDMDevHlpPCISetIrqNoWait(pDevIns, 0, 1);
66b58af085e22ee26be57f98127fb49ee2e91790vboxsync else
66b58af085e22ee26be57f98127fb49ee2e91790vboxsync PDMDevHlpISASetIrqNoWait(pDevIns, pCtl->irq, 1);
66b58af085e22ee26be57f98127fb49ee2e91790vboxsync }
66b58af085e22ee26be57f98127fb49ee2e91790vboxsync }
66b58af085e22ee26be57f98127fb49ee2e91790vboxsync s->fIrqPending = true;
66b58af085e22ee26be57f98127fb49ee2e91790vboxsync}
66b58af085e22ee26be57f98127fb49ee2e91790vboxsync
66b58af085e22ee26be57f98127fb49ee2e91790vboxsync#endif /* IN_RING3 */
66b58af085e22ee26be57f98127fb49ee2e91790vboxsync
66b58af085e22ee26be57f98127fb49ee2e91790vboxsyncstatic void ataUnsetIRQ(ATADevState *s)
66b58af085e22ee26be57f98127fb49ee2e91790vboxsync{
66b58af085e22ee26be57f98127fb49ee2e91790vboxsync PATACONTROLLER pCtl = ATADEVSTATE_2_CONTROLLER(s);
66b58af085e22ee26be57f98127fb49ee2e91790vboxsync PPDMDEVINS pDevIns = ATADEVSTATE_2_DEVINS(s);
66b58af085e22ee26be57f98127fb49ee2e91790vboxsync
66b58af085e22ee26be57f98127fb49ee2e91790vboxsync if (!(s->uATARegDevCtl & ATA_DEVCTL_DISABLE_IRQ))
66b58af085e22ee26be57f98127fb49ee2e91790vboxsync {
66b58af085e22ee26be57f98127fb49ee2e91790vboxsync Log2(("%s: LUN#%d deasserting IRQ\n", __FUNCTION__, s->iLUN));
66b58af085e22ee26be57f98127fb49ee2e91790vboxsync /* Only actually unset the IRQ line if updating the currently selected drive. */
66b58af085e22ee26be57f98127fb49ee2e91790vboxsync if (s == &pCtl->aIfs[pCtl->iSelectedIf])
66b58af085e22ee26be57f98127fb49ee2e91790vboxsync {
66b58af085e22ee26be57f98127fb49ee2e91790vboxsync if (pCtl->irq == 16)
66b58af085e22ee26be57f98127fb49ee2e91790vboxsync PDMDevHlpPCISetIrqNoWait(pDevIns, 0, 0);
66b58af085e22ee26be57f98127fb49ee2e91790vboxsync else
66b58af085e22ee26be57f98127fb49ee2e91790vboxsync PDMDevHlpISASetIrqNoWait(pDevIns, pCtl->irq, 0);
66b58af085e22ee26be57f98127fb49ee2e91790vboxsync }
66b58af085e22ee26be57f98127fb49ee2e91790vboxsync }
66b58af085e22ee26be57f98127fb49ee2e91790vboxsync s->fIrqPending = false;
66b58af085e22ee26be57f98127fb49ee2e91790vboxsync}
66b58af085e22ee26be57f98127fb49ee2e91790vboxsync
66b58af085e22ee26be57f98127fb49ee2e91790vboxsync#ifdef IN_RING3
661bfa5aae55ac2f94fa1cb131ea2323e5f6e633vboxsync
66b58af085e22ee26be57f98127fb49ee2e91790vboxsyncstatic void ataPIOTransferStart(ATADevState *s, uint32_t start, uint32_t size)
661bfa5aae55ac2f94fa1cb131ea2323e5f6e633vboxsync{
66b58af085e22ee26be57f98127fb49ee2e91790vboxsync Log2(("%s: LUN#%d start %d size %d\n", __FUNCTION__, s->iLUN, start, size));
661bfa5aae55ac2f94fa1cb131ea2323e5f6e633vboxsync s->iIOBufferPIODataStart = start;
66b58af085e22ee26be57f98127fb49ee2e91790vboxsync s->iIOBufferPIODataEnd = start + size;
38745c55f37c31ba8b78cc728d2f08ea6eec38d6vboxsync ataSetStatus(s, ATA_STAT_DRQ);
38745c55f37c31ba8b78cc728d2f08ea6eec38d6vboxsync}
38745c55f37c31ba8b78cc728d2f08ea6eec38d6vboxsync
38745c55f37c31ba8b78cc728d2f08ea6eec38d6vboxsync
38745c55f37c31ba8b78cc728d2f08ea6eec38d6vboxsyncstatic void ataPIOTransferStop(ATADevState *s)
66b58af085e22ee26be57f98127fb49ee2e91790vboxsync{
66b58af085e22ee26be57f98127fb49ee2e91790vboxsync Log2(("%s: LUN#%d\n", __FUNCTION__, s->iLUN));
66b58af085e22ee26be57f98127fb49ee2e91790vboxsync if (s->fATAPITransfer)
66b58af085e22ee26be57f98127fb49ee2e91790vboxsync {
66b58af085e22ee26be57f98127fb49ee2e91790vboxsync s->uATARegNSector = (s->uATARegNSector & ~7) | ATAPI_INT_REASON_IO | ATAPI_INT_REASON_CD;
66b58af085e22ee26be57f98127fb49ee2e91790vboxsync Log2(("%s: interrupt reason %#04x\n", __FUNCTION__, s->uATARegNSector));
66b58af085e22ee26be57f98127fb49ee2e91790vboxsync ataSetIRQ(s);
66b58af085e22ee26be57f98127fb49ee2e91790vboxsync s->fATAPITransfer = false;
66b58af085e22ee26be57f98127fb49ee2e91790vboxsync }
661bfa5aae55ac2f94fa1cb131ea2323e5f6e633vboxsync s->cbTotalTransfer = 0;
661bfa5aae55ac2f94fa1cb131ea2323e5f6e633vboxsync s->cbElementaryTransfer = 0;
66b58af085e22ee26be57f98127fb49ee2e91790vboxsync s->iIOBufferPIODataStart = 0;
66b58af085e22ee26be57f98127fb49ee2e91790vboxsync s->iIOBufferPIODataEnd = 0;
66b58af085e22ee26be57f98127fb49ee2e91790vboxsync s->iBeginTransfer = ATAFN_BT_NULL;
66b58af085e22ee26be57f98127fb49ee2e91790vboxsync s->iSourceSink = ATAFN_SS_NULL;
66b58af085e22ee26be57f98127fb49ee2e91790vboxsync}
66b58af085e22ee26be57f98127fb49ee2e91790vboxsync
66b58af085e22ee26be57f98127fb49ee2e91790vboxsync
661bfa5aae55ac2f94fa1cb131ea2323e5f6e633vboxsyncstatic void ataPIOTransferLimitATAPI(ATADevState *s)
fdb40b7d2efa84fc6f03b7a695cb4b2e035c30c7vboxsync{
fdb40b7d2efa84fc6f03b7a695cb4b2e035c30c7vboxsync uint32_t cbLimit, cbTransfer;
fdb40b7d2efa84fc6f03b7a695cb4b2e035c30c7vboxsync
66b58af085e22ee26be57f98127fb49ee2e91790vboxsync cbLimit = s->uATARegLCyl | (s->uATARegHCyl << 8);
66b58af085e22ee26be57f98127fb49ee2e91790vboxsync /* Use maximum transfer size if the guest requested 0. Avoids a hang. */
66b58af085e22ee26be57f98127fb49ee2e91790vboxsync if (cbLimit == 0)
66b58af085e22ee26be57f98127fb49ee2e91790vboxsync cbLimit = 0xfffe;
fdb40b7d2efa84fc6f03b7a695cb4b2e035c30c7vboxsync Log2(("%s: byte count limit=%d\n", __FUNCTION__, cbLimit));
66b58af085e22ee26be57f98127fb49ee2e91790vboxsync if (cbLimit == 0xffff)
66b58af085e22ee26be57f98127fb49ee2e91790vboxsync cbLimit--;
661bfa5aae55ac2f94fa1cb131ea2323e5f6e633vboxsync cbTransfer = RT_MIN(s->cbTotalTransfer, s->iIOBufferEnd - s->iIOBufferCur);
66b58af085e22ee26be57f98127fb49ee2e91790vboxsync if (cbTransfer > cbLimit)
661bfa5aae55ac2f94fa1cb131ea2323e5f6e633vboxsync {
66b58af085e22ee26be57f98127fb49ee2e91790vboxsync /* Byte count limit for clipping must be even in this case */
fdb40b7d2efa84fc6f03b7a695cb4b2e035c30c7vboxsync if (cbLimit & 1)
66b58af085e22ee26be57f98127fb49ee2e91790vboxsync cbLimit--;
66b58af085e22ee26be57f98127fb49ee2e91790vboxsync cbTransfer = cbLimit;
66b58af085e22ee26be57f98127fb49ee2e91790vboxsync }
66b58af085e22ee26be57f98127fb49ee2e91790vboxsync s->uATARegLCyl = cbTransfer;
66b58af085e22ee26be57f98127fb49ee2e91790vboxsync s->uATARegHCyl = cbTransfer >> 8;
66b58af085e22ee26be57f98127fb49ee2e91790vboxsync s->cbElementaryTransfer = cbTransfer;
66b58af085e22ee26be57f98127fb49ee2e91790vboxsync}
66b58af085e22ee26be57f98127fb49ee2e91790vboxsync
66b58af085e22ee26be57f98127fb49ee2e91790vboxsync
66b58af085e22ee26be57f98127fb49ee2e91790vboxsyncstatic uint32_t ataGetNSectors(ATADevState *s)
66b58af085e22ee26be57f98127fb49ee2e91790vboxsync{
661bfa5aae55ac2f94fa1cb131ea2323e5f6e633vboxsync /* 0 means either 256 (LBA28) or 65536 (LBA48) sectors. */
66b58af085e22ee26be57f98127fb49ee2e91790vboxsync if (s->fLBA48)
661bfa5aae55ac2f94fa1cb131ea2323e5f6e633vboxsync {
2cf9be9fb8dd19b4e5695e3f70c864390c500eb0vboxsync if (!s->uATARegNSector && !s->uATARegNSectorHOB)
c66c4413faa5a72ce047742f9acfa85e94dec8afvboxsync return 65536;
fdb40b7d2efa84fc6f03b7a695cb4b2e035c30c7vboxsync else
fdb40b7d2efa84fc6f03b7a695cb4b2e035c30c7vboxsync return s->uATARegNSectorHOB << 8 | s->uATARegNSector;
fdb40b7d2efa84fc6f03b7a695cb4b2e035c30c7vboxsync }
66b58af085e22ee26be57f98127fb49ee2e91790vboxsync else
66b58af085e22ee26be57f98127fb49ee2e91790vboxsync {
66b58af085e22ee26be57f98127fb49ee2e91790vboxsync if (!s->uATARegNSector)
66b58af085e22ee26be57f98127fb49ee2e91790vboxsync return 256;
66b58af085e22ee26be57f98127fb49ee2e91790vboxsync else
c66c4413faa5a72ce047742f9acfa85e94dec8afvboxsync return s->uATARegNSector;
e70bda5438c3582164d26f171a8bc8d3d7da1e12vboxsync }
e70bda5438c3582164d26f171a8bc8d3d7da1e12vboxsync}
e250515922582e0410c9bcb6d24b0f17bef083a0vboxsync
c66c4413faa5a72ce047742f9acfa85e94dec8afvboxsync
c66c4413faa5a72ce047742f9acfa85e94dec8afvboxsyncstatic void ataPadString(uint8_t *pbDst, const char *pbSrc, uint32_t cbSize)
20f21077abf35d7b7b618acb159267933907407fvboxsync{
20f21077abf35d7b7b618acb159267933907407fvboxsync for (uint32_t i = 0; i < cbSize; i++)
20f21077abf35d7b7b618acb159267933907407fvboxsync {
20f21077abf35d7b7b618acb159267933907407fvboxsync if (*pbSrc)
20f21077abf35d7b7b618acb159267933907407fvboxsync pbDst[i ^ 1] = *pbSrc++;
20f21077abf35d7b7b618acb159267933907407fvboxsync else
20f21077abf35d7b7b618acb159267933907407fvboxsync pbDst[i ^ 1] = ' ';
20f21077abf35d7b7b618acb159267933907407fvboxsync }
20f21077abf35d7b7b618acb159267933907407fvboxsync}
20f21077abf35d7b7b618acb159267933907407fvboxsync
20f21077abf35d7b7b618acb159267933907407fvboxsync
20f21077abf35d7b7b618acb159267933907407fvboxsyncstatic void ataSCSIPadStr(uint8_t *pbDst, const char *pbSrc, uint32_t cbSize)
e250515922582e0410c9bcb6d24b0f17bef083a0vboxsync{
c66c4413faa5a72ce047742f9acfa85e94dec8afvboxsync for (uint32_t i = 0; i < cbSize; i++)
c66c4413faa5a72ce047742f9acfa85e94dec8afvboxsync {
e70bda5438c3582164d26f171a8bc8d3d7da1e12vboxsync if (*pbSrc)
66b58af085e22ee26be57f98127fb49ee2e91790vboxsync pbDst[i] = *pbSrc++;
66b58af085e22ee26be57f98127fb49ee2e91790vboxsync else
66b58af085e22ee26be57f98127fb49ee2e91790vboxsync pbDst[i] = ' ';
66b58af085e22ee26be57f98127fb49ee2e91790vboxsync }
66b58af085e22ee26be57f98127fb49ee2e91790vboxsync}
661bfa5aae55ac2f94fa1cb131ea2323e5f6e633vboxsync
661bfa5aae55ac2f94fa1cb131ea2323e5f6e633vboxsync
661bfa5aae55ac2f94fa1cb131ea2323e5f6e633vboxsyncDECLINLINE(void) ataH2BE_U16(uint8_t *pbBuf, uint16_t val)
661bfa5aae55ac2f94fa1cb131ea2323e5f6e633vboxsync{
661bfa5aae55ac2f94fa1cb131ea2323e5f6e633vboxsync pbBuf[0] = val >> 8;
661bfa5aae55ac2f94fa1cb131ea2323e5f6e633vboxsync pbBuf[1] = val;
661bfa5aae55ac2f94fa1cb131ea2323e5f6e633vboxsync}
661bfa5aae55ac2f94fa1cb131ea2323e5f6e633vboxsync
fdb40b7d2efa84fc6f03b7a695cb4b2e035c30c7vboxsync
661bfa5aae55ac2f94fa1cb131ea2323e5f6e633vboxsyncDECLINLINE(void) ataH2BE_U24(uint8_t *pbBuf, uint32_t val)
661bfa5aae55ac2f94fa1cb131ea2323e5f6e633vboxsync{
661bfa5aae55ac2f94fa1cb131ea2323e5f6e633vboxsync pbBuf[0] = val >> 16;
661bfa5aae55ac2f94fa1cb131ea2323e5f6e633vboxsync pbBuf[1] = val >> 8;
661bfa5aae55ac2f94fa1cb131ea2323e5f6e633vboxsync pbBuf[2] = val;
661bfa5aae55ac2f94fa1cb131ea2323e5f6e633vboxsync}
661bfa5aae55ac2f94fa1cb131ea2323e5f6e633vboxsync
661bfa5aae55ac2f94fa1cb131ea2323e5f6e633vboxsync
661bfa5aae55ac2f94fa1cb131ea2323e5f6e633vboxsyncDECLINLINE(void) ataH2BE_U32(uint8_t *pbBuf, uint32_t val)
661bfa5aae55ac2f94fa1cb131ea2323e5f6e633vboxsync{
661bfa5aae55ac2f94fa1cb131ea2323e5f6e633vboxsync pbBuf[0] = val >> 24;
661bfa5aae55ac2f94fa1cb131ea2323e5f6e633vboxsync pbBuf[1] = val >> 16;
661bfa5aae55ac2f94fa1cb131ea2323e5f6e633vboxsync pbBuf[2] = val >> 8;
661bfa5aae55ac2f94fa1cb131ea2323e5f6e633vboxsync pbBuf[3] = val;
661bfa5aae55ac2f94fa1cb131ea2323e5f6e633vboxsync}
661bfa5aae55ac2f94fa1cb131ea2323e5f6e633vboxsync
66b58af085e22ee26be57f98127fb49ee2e91790vboxsync
661bfa5aae55ac2f94fa1cb131ea2323e5f6e633vboxsyncDECLINLINE(uint16_t) ataBE2H_U16(const uint8_t *pbBuf)
661bfa5aae55ac2f94fa1cb131ea2323e5f6e633vboxsync{
66b58af085e22ee26be57f98127fb49ee2e91790vboxsync return (pbBuf[0] << 8) | pbBuf[1];
66b58af085e22ee26be57f98127fb49ee2e91790vboxsync}
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsyncDECLINLINE(uint32_t) ataBE2H_U24(const uint8_t *pbBuf)
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync{
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync return (pbBuf[0] << 16) | (pbBuf[1] << 8) | pbBuf[2];
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync}
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsyncDECLINLINE(uint32_t) ataBE2H_U32(const uint8_t *pbBuf)
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync{
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync return (pbBuf[0] << 24) | (pbBuf[1] << 16) | (pbBuf[2] << 8) | pbBuf[3];
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync}
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsyncDECLINLINE(void) ataLBA2MSF(uint8_t *pbBuf, uint32_t iATAPILBA)
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync{
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync iATAPILBA += 150;
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync pbBuf[0] = (iATAPILBA / 75) / 60;
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync pbBuf[1] = (iATAPILBA / 75) % 60;
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync pbBuf[2] = iATAPILBA % 75;
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync}
5c4d7e2aae42bbf39793dfa686925f076a56b4d5vboxsync
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsyncDECLINLINE(uint32_t) ataMSF2LBA(const uint8_t *pbBuf)
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync{
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync return (pbBuf[0] * 60 + pbBuf[1]) * 75 + pbBuf[2];
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync}
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsyncstatic void ataCmdOK(ATADevState *s, uint8_t status)
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync{
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync s->uATARegError = 0; /* Not needed by ATA spec, but cannot hurt. */
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync ataSetStatusValue(s, ATA_STAT_READY | status);
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync}
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsyncstatic void ataCmdError(ATADevState *s, uint8_t uErrorCode)
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync{
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync Log(("%s: code=%#x\n", __FUNCTION__, uErrorCode));
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync s->uATARegError = uErrorCode;
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync ataSetStatusValue(s, ATA_STAT_READY | ATA_STAT_ERR);
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync s->cbTotalTransfer = 0;
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync s->cbElementaryTransfer = 0;
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync s->iIOBufferCur = 0;
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync s->iIOBufferEnd = 0;
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync s->uTxDir = PDMBLOCKTXDIR_NONE;
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync s->iBeginTransfer = ATAFN_BT_NULL;
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync s->iSourceSink = ATAFN_SS_NULL;
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync}
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsyncstatic bool ataIdentifySS(ATADevState *s)
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync{
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync uint16_t *p;
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync char aSerial[20];
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync int rc;
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync RTUUID Uuid;
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync Assert(s->uTxDir == PDMBLOCKTXDIR_FROM_DEVICE);
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync Assert(s->cbElementaryTransfer == 512);
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync p = (uint16_t *)s->CTX_SUFF(pbIOBuffer);
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync memset(p, 0, 512);
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync p[0] = RT_H2LE_U16(0x0040);
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync p[1] = RT_H2LE_U16(RT_MIN(s->PCHSGeometry.cCylinders, 16383));
8f7ee9e453c60b3b699799538a45950b35266665vboxsync p[3] = RT_H2LE_U16(s->PCHSGeometry.cHeads);
8f7ee9e453c60b3b699799538a45950b35266665vboxsync /* Block size; obsolete, but required for the BIOS. */
8f7ee9e453c60b3b699799538a45950b35266665vboxsync p[5] = RT_H2LE_U16(512);
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync p[6] = RT_H2LE_U16(s->PCHSGeometry.cSectors);
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync ataPadString((uint8_t *)(p + 10), (const char *)s->abSerialNumber, 20); /* serial number */
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync p[20] = RT_H2LE_U16(3); /* XXX: retired, cache type */
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync p[21] = RT_H2LE_U16(512); /* XXX: retired, cache size in sectors */
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync p[22] = RT_H2LE_U16(0); /* ECC bytes per sector */
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync ataPadString((uint8_t *)(p + 23), (const char *)s->abFirmwareRevision, 8); /* firmware version */
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync ataPadString((uint8_t *)(p + 27), (const char *)s->abModelNumber, 40); /* model */
38745c55f37c31ba8b78cc728d2f08ea6eec38d6vboxsync#if ATA_MAX_MULT_SECTORS > 1
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync p[47] = RT_H2LE_U16(0x8000 | ATA_MAX_MULT_SECTORS);
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync#endif
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync p[48] = RT_H2LE_U16(1); /* dword I/O, used by the BIOS */
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync p[49] = RT_H2LE_U16(1 << 11 | 1 << 9 | 1 << 8); /* DMA and LBA supported */
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync p[50] = RT_H2LE_U16(1 << 14); /* No drive specific standby timer minimum */
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync p[51] = RT_H2LE_U16(240); /* PIO transfer cycle */
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync p[52] = RT_H2LE_U16(240); /* DMA transfer cycle */
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync p[53] = RT_H2LE_U16(1 | 1 << 1 | 1 << 2); /* words 54-58,64-70,88 valid */
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync p[54] = RT_H2LE_U16(RT_MIN(s->PCHSGeometry.cCylinders, 16383));
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync p[55] = RT_H2LE_U16(s->PCHSGeometry.cHeads);
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync p[56] = RT_H2LE_U16(s->PCHSGeometry.cSectors);
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync p[57] = RT_H2LE_U16( RT_MIN(s->PCHSGeometry.cCylinders, 16383)
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync * s->PCHSGeometry.cHeads
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync * s->PCHSGeometry.cSectors);
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync p[58] = RT_H2LE_U16( RT_MIN(s->PCHSGeometry.cCylinders, 16383)
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync * s->PCHSGeometry.cHeads
88e56f700a3b8dfdf1646f96320f335e22339caavboxsync * s->PCHSGeometry.cSectors >> 16);
88e56f700a3b8dfdf1646f96320f335e22339caavboxsync if (s->cMultSectors)
88e56f700a3b8dfdf1646f96320f335e22339caavboxsync p[59] = RT_H2LE_U16(0x100 | s->cMultSectors);
88e56f700a3b8dfdf1646f96320f335e22339caavboxsync if (s->cTotalSectors <= (1 << 28) - 1)
88e56f700a3b8dfdf1646f96320f335e22339caavboxsync {
88e56f700a3b8dfdf1646f96320f335e22339caavboxsync p[60] = RT_H2LE_U16(s->cTotalSectors);
88e56f700a3b8dfdf1646f96320f335e22339caavboxsync p[61] = RT_H2LE_U16(s->cTotalSectors >> 16);
88e56f700a3b8dfdf1646f96320f335e22339caavboxsync }
88e56f700a3b8dfdf1646f96320f335e22339caavboxsync else
88e56f700a3b8dfdf1646f96320f335e22339caavboxsync {
88e56f700a3b8dfdf1646f96320f335e22339caavboxsync /* Report maximum number of sectors possible with LBA28 */
88e56f700a3b8dfdf1646f96320f335e22339caavboxsync p[60] = RT_H2LE_U16(((1 << 28) - 1) & 0xffff);
8f7ee9e453c60b3b699799538a45950b35266665vboxsync p[61] = RT_H2LE_U16(((1 << 28) - 1) >> 16);
8f7ee9e453c60b3b699799538a45950b35266665vboxsync }
8f7ee9e453c60b3b699799538a45950b35266665vboxsync p[63] = RT_H2LE_U16(ATA_TRANSFER_ID(ATA_MODE_MDMA, ATA_MDMA_MODE_MAX, s->uATATransferMode)); /* MDMA modes supported / mode enabled */
88e56f700a3b8dfdf1646f96320f335e22339caavboxsync p[64] = RT_H2LE_U16(ATA_PIO_MODE_MAX > 2 ? (1 << (ATA_PIO_MODE_MAX - 2)) - 1 : 0); /* PIO modes beyond PIO2 supported */
88e56f700a3b8dfdf1646f96320f335e22339caavboxsync p[65] = RT_H2LE_U16(120); /* minimum DMA multiword tx cycle time */
88e56f700a3b8dfdf1646f96320f335e22339caavboxsync p[66] = RT_H2LE_U16(120); /* recommended DMA multiword tx cycle time */
88e56f700a3b8dfdf1646f96320f335e22339caavboxsync p[67] = RT_H2LE_U16(120); /* minimum PIO cycle time without flow control */
88e56f700a3b8dfdf1646f96320f335e22339caavboxsync p[68] = RT_H2LE_U16(120); /* minimum PIO cycle time with IORDY flow control */
88e56f700a3b8dfdf1646f96320f335e22339caavboxsync p[80] = RT_H2LE_U16(0x7e); /* support everything up to ATA/ATAPI-6 */
88e56f700a3b8dfdf1646f96320f335e22339caavboxsync p[81] = RT_H2LE_U16(0x22); /* conforms to ATA/ATAPI-6 */
38745c55f37c31ba8b78cc728d2f08ea6eec38d6vboxsync p[82] = RT_H2LE_U16(1 << 3 | 1 << 5 | 1 << 6); /* supports power management, write cache and look-ahead */
88e56f700a3b8dfdf1646f96320f335e22339caavboxsync if (s->cTotalSectors <= (1 << 28) - 1)
88e56f700a3b8dfdf1646f96320f335e22339caavboxsync p[83] = RT_H2LE_U16(1 << 14 | 1 << 12); /* supports FLUSH CACHE */
88e56f700a3b8dfdf1646f96320f335e22339caavboxsync else
88e56f700a3b8dfdf1646f96320f335e22339caavboxsync p[83] = RT_H2LE_U16(1 << 14 | 1 << 10 | 1 << 12 | 1 << 13); /* supports LBA48, FLUSH CACHE and FLUSH CACHE EXT */
88e56f700a3b8dfdf1646f96320f335e22339caavboxsync p[84] = RT_H2LE_U16(1 << 14);
88e56f700a3b8dfdf1646f96320f335e22339caavboxsync p[85] = RT_H2LE_U16(1 << 3 | 1 << 5 | 1 << 6); /* enabled power management, write cache and look-ahead */
88e56f700a3b8dfdf1646f96320f335e22339caavboxsync if (s->cTotalSectors <= (1 << 28) - 1)
88e56f700a3b8dfdf1646f96320f335e22339caavboxsync p[86] = RT_H2LE_U16(1 << 12); /* enabled FLUSH CACHE */
88e56f700a3b8dfdf1646f96320f335e22339caavboxsync else
88e56f700a3b8dfdf1646f96320f335e22339caavboxsync p[86] = RT_H2LE_U16(1 << 10 | 1 << 12 | 1 << 13); /* enabled LBA48, FLUSH CACHE and FLUSH CACHE EXT */
88e56f700a3b8dfdf1646f96320f335e22339caavboxsync p[87] = RT_H2LE_U16(1 << 14);
88e56f700a3b8dfdf1646f96320f335e22339caavboxsync p[88] = RT_H2LE_U16(ATA_TRANSFER_ID(ATA_MODE_UDMA, ATA_UDMA_MODE_MAX, s->uATATransferMode)); /* UDMA modes supported / mode enabled */
88e56f700a3b8dfdf1646f96320f335e22339caavboxsync p[93] = RT_H2LE_U16((1 | 1 << 1) << ((s->iLUN & 1) == 0 ? 0 : 8) | 1 << 13 | 1 << 14);
88e56f700a3b8dfdf1646f96320f335e22339caavboxsync if (s->cTotalSectors > (1 << 28) - 1)
88e56f700a3b8dfdf1646f96320f335e22339caavboxsync {
88e56f700a3b8dfdf1646f96320f335e22339caavboxsync p[100] = RT_H2LE_U16(s->cTotalSectors);
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync p[101] = RT_H2LE_U16(s->cTotalSectors >> 16);
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync p[102] = RT_H2LE_U16(s->cTotalSectors >> 32);
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync p[103] = RT_H2LE_U16(s->cTotalSectors >> 48);
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync }
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync s->iSourceSink = ATAFN_SS_NULL;
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync ataCmdOK(s, ATA_STAT_SEEK);
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync return false;
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync}
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsyncstatic bool ataFlushSS(ATADevState *s)
5c4d7e2aae42bbf39793dfa686925f076a56b4d5vboxsync{
38745c55f37c31ba8b78cc728d2f08ea6eec38d6vboxsync PATACONTROLLER pCtl = ATADEVSTATE_2_CONTROLLER(s);
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync int rc;
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync Assert(s->uTxDir == PDMBLOCKTXDIR_NONE);
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync Assert(!s->cbElementaryTransfer);
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync
5c4d7e2aae42bbf39793dfa686925f076a56b4d5vboxsync PDMCritSectLeave(&pCtl->lock);
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync STAM_PROFILE_START(&s->StatFlushes, f);
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync rc = s->pDrvBlock->pfnFlush(s->pDrvBlock);
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync AssertRC(rc);
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync STAM_PROFILE_STOP(&s->StatFlushes, f);
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync STAM_PROFILE_START(&pCtl->StatLockWait, a);
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync PDMCritSectEnter(&pCtl->lock, VINF_SUCCESS);
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync STAM_PROFILE_STOP(&pCtl->StatLockWait, a);
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync ataCmdOK(s, 0);
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync return false;
49a6b09abb20015b0af3e618a1f92b7e26785e90vboxsync}
49a6b09abb20015b0af3e618a1f92b7e26785e90vboxsync
49a6b09abb20015b0af3e618a1f92b7e26785e90vboxsync
49a6b09abb20015b0af3e618a1f92b7e26785e90vboxsyncstatic bool atapiIdentifySS(ATADevState *s)
49a6b09abb20015b0af3e618a1f92b7e26785e90vboxsync{
49a6b09abb20015b0af3e618a1f92b7e26785e90vboxsync uint16_t *p;
49a6b09abb20015b0af3e618a1f92b7e26785e90vboxsync char aSerial[20];
49a6b09abb20015b0af3e618a1f92b7e26785e90vboxsync RTUUID Uuid;
49a6b09abb20015b0af3e618a1f92b7e26785e90vboxsync int rc;
49a6b09abb20015b0af3e618a1f92b7e26785e90vboxsync
49a6b09abb20015b0af3e618a1f92b7e26785e90vboxsync Assert(s->uTxDir == PDMBLOCKTXDIR_FROM_DEVICE);
49a6b09abb20015b0af3e618a1f92b7e26785e90vboxsync Assert(s->cbElementaryTransfer == 512);
49a6b09abb20015b0af3e618a1f92b7e26785e90vboxsync rc = s->pDrvBlock ? s->pDrvBlock->pfnGetUuid(s->pDrvBlock, &Uuid) : RTUuidClear(&Uuid);
49a6b09abb20015b0af3e618a1f92b7e26785e90vboxsync if (RT_FAILURE(rc) || RTUuidIsNull(&Uuid))
49a6b09abb20015b0af3e618a1f92b7e26785e90vboxsync {
49a6b09abb20015b0af3e618a1f92b7e26785e90vboxsync PATACONTROLLER pCtl = ATADEVSTATE_2_CONTROLLER(s);
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync /* Generate a predictable serial for drives which don't have a UUID. */
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync RTStrPrintf(aSerial, sizeof(aSerial), "VB%x-%04x%04x",
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync s->iLUN + ATADEVSTATE_2_DEVINS(s)->iInstance * 32,
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync pCtl->IOPortBase1, pCtl->IOPortBase2);
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync }
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync else
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync RTStrPrintf(aSerial, sizeof(aSerial), "VB%08x-%08x", Uuid.au32[0], Uuid.au32[3]);
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync p = (uint16_t *)s->CTX_SUFF(pbIOBuffer);
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync memset(p, 0, 512);
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync /* Removable CDROM, 50us response, 12 byte packets */
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync p[0] = RT_H2LE_U16(2 << 14 | 5 << 8 | 1 << 7 | 2 << 5 | 0 << 0);
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync ataPadString((uint8_t *)(p + 10), aSerial, 20); /* serial number */
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync p[20] = RT_H2LE_U16(3); /* XXX: retired, cache type */
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync p[21] = RT_H2LE_U16(512); /* XXX: retired, cache size in sectors */
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync ataPadString((uint8_t *)(p + 23), "1.0", 8); /* firmware version */
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync ataPadString((uint8_t *)(p + 27), "VBOX CD-ROM", 40); /* model */
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync p[49] = RT_H2LE_U16(1 << 11 | 1 << 9 | 1 << 8); /* DMA and LBA supported */
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync p[50] = RT_H2LE_U16(1 << 14); /* No drive specific standby timer minimum */
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync p[51] = RT_H2LE_U16(240); /* PIO transfer cycle */
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync p[52] = RT_H2LE_U16(240); /* DMA transfer cycle */
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync p[53] = RT_H2LE_U16(1 << 1 | 1 << 2); /* words 64-70,88 are valid */
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync p[63] = RT_H2LE_U16(ATA_TRANSFER_ID(ATA_MODE_MDMA, ATA_MDMA_MODE_MAX, s->uATATransferMode)); /* MDMA modes supported / mode enabled */
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync p[64] = RT_H2LE_U16(ATA_PIO_MODE_MAX > 2 ? (1 << (ATA_PIO_MODE_MAX - 2)) - 1 : 0); /* PIO modes beyond PIO2 supported */
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync p[65] = RT_H2LE_U16(120); /* minimum DMA multiword tx cycle time */
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync p[66] = RT_H2LE_U16(120); /* recommended DMA multiword tx cycle time */
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync p[67] = RT_H2LE_U16(120); /* minimum PIO cycle time without flow control */
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync p[68] = RT_H2LE_U16(120); /* minimum PIO cycle time with IORDY flow control */
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync p[73] = RT_H2LE_U16(0x003e); /* ATAPI CDROM major */
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync p[74] = RT_H2LE_U16(9); /* ATAPI CDROM minor */
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync p[75] = RT_H2LE_U16(1); /* queue depth 1 */
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync p[80] = RT_H2LE_U16(0x7e); /* support everything up to ATA/ATAPI-6 */
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync p[81] = RT_H2LE_U16(0x22); /* conforms to ATA/ATAPI-6 */
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync p[82] = RT_H2LE_U16(1 << 4 | 1 << 9); /* supports packet command set and DEVICE RESET */
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync p[83] = RT_H2LE_U16(1 << 14);
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync p[84] = RT_H2LE_U16(1 << 14);
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync p[85] = RT_H2LE_U16(1 << 4 | 1 << 9); /* enabled packet command set and DEVICE RESET */
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync p[86] = RT_H2LE_U16(0);
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync p[87] = RT_H2LE_U16(1 << 14);
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync p[88] = RT_H2LE_U16(ATA_TRANSFER_ID(ATA_MODE_UDMA, ATA_UDMA_MODE_MAX, s->uATATransferMode)); /* UDMA modes supported / mode enabled */
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync p[93] = RT_H2LE_U16((1 | 1 << 1) << ((s->iLUN & 1) == 0 ? 0 : 8) | 1 << 13 | 1 << 14);
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync s->iSourceSink = ATAFN_SS_NULL;
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync ataCmdOK(s, ATA_STAT_SEEK);
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync return false;
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync}
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsyncstatic void ataSetSignature(ATADevState *s)
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync{
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync s->uATARegSelect &= 0xf0; /* clear head */
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync /* put signature */
5c4d7e2aae42bbf39793dfa686925f076a56b4d5vboxsync s->uATARegNSector = 1;
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync s->uATARegSector = 1;
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync if (s->fATAPI)
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync {
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync s->uATARegLCyl = 0x14;
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync s->uATARegHCyl = 0xeb;
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync }
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync else if (s->pDrvBlock)
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync {
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync s->uATARegLCyl = 0;
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync s->uATARegHCyl = 0;
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync }
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync else
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync {
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync s->uATARegLCyl = 0xff;
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync s->uATARegHCyl = 0xff;
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync }
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync}
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync
49a6b09abb20015b0af3e618a1f92b7e26785e90vboxsyncstatic uint64_t ataGetSector(ATADevState *s)
49a6b09abb20015b0af3e618a1f92b7e26785e90vboxsync{
49a6b09abb20015b0af3e618a1f92b7e26785e90vboxsync uint64_t iLBA;
49a6b09abb20015b0af3e618a1f92b7e26785e90vboxsync if (s->uATARegSelect & 0x40)
49a6b09abb20015b0af3e618a1f92b7e26785e90vboxsync {
49a6b09abb20015b0af3e618a1f92b7e26785e90vboxsync /* any LBA variant */
49a6b09abb20015b0af3e618a1f92b7e26785e90vboxsync if (s->fLBA48)
49a6b09abb20015b0af3e618a1f92b7e26785e90vboxsync {
49a6b09abb20015b0af3e618a1f92b7e26785e90vboxsync /* LBA48 */
49a6b09abb20015b0af3e618a1f92b7e26785e90vboxsync iLBA = ((uint64_t)s->uATARegHCylHOB << 40) |
49a6b09abb20015b0af3e618a1f92b7e26785e90vboxsync ((uint64_t)s->uATARegLCylHOB << 32) |
49a6b09abb20015b0af3e618a1f92b7e26785e90vboxsync ((uint64_t)s->uATARegSectorHOB << 24) |
49a6b09abb20015b0af3e618a1f92b7e26785e90vboxsync ((uint64_t)s->uATARegHCyl << 16) |
49a6b09abb20015b0af3e618a1f92b7e26785e90vboxsync ((uint64_t)s->uATARegLCyl << 8) |
49a6b09abb20015b0af3e618a1f92b7e26785e90vboxsync s->uATARegSector;
49a6b09abb20015b0af3e618a1f92b7e26785e90vboxsync }
49a6b09abb20015b0af3e618a1f92b7e26785e90vboxsync else
49a6b09abb20015b0af3e618a1f92b7e26785e90vboxsync {
49a6b09abb20015b0af3e618a1f92b7e26785e90vboxsync /* LBA */
49a6b09abb20015b0af3e618a1f92b7e26785e90vboxsync iLBA = ((s->uATARegSelect & 0x0f) << 24) | (s->uATARegHCyl << 16) |
49a6b09abb20015b0af3e618a1f92b7e26785e90vboxsync (s->uATARegLCyl << 8) | s->uATARegSector;
49a6b09abb20015b0af3e618a1f92b7e26785e90vboxsync }
49a6b09abb20015b0af3e618a1f92b7e26785e90vboxsync }
49a6b09abb20015b0af3e618a1f92b7e26785e90vboxsync else
49a6b09abb20015b0af3e618a1f92b7e26785e90vboxsync {
49a6b09abb20015b0af3e618a1f92b7e26785e90vboxsync /* CHS */
49a6b09abb20015b0af3e618a1f92b7e26785e90vboxsync iLBA = ((s->uATARegHCyl << 8) | s->uATARegLCyl) * s->PCHSGeometry.cHeads * s->PCHSGeometry.cSectors +
49a6b09abb20015b0af3e618a1f92b7e26785e90vboxsync (s->uATARegSelect & 0x0f) * s->PCHSGeometry.cSectors +
49a6b09abb20015b0af3e618a1f92b7e26785e90vboxsync (s->uATARegSector - 1);
49a6b09abb20015b0af3e618a1f92b7e26785e90vboxsync }
49a6b09abb20015b0af3e618a1f92b7e26785e90vboxsync return iLBA;
49a6b09abb20015b0af3e618a1f92b7e26785e90vboxsync}
49a6b09abb20015b0af3e618a1f92b7e26785e90vboxsync
49a6b09abb20015b0af3e618a1f92b7e26785e90vboxsyncstatic void ataSetSector(ATADevState *s, uint64_t iLBA)
5c4d7e2aae42bbf39793dfa686925f076a56b4d5vboxsync{
5c4d7e2aae42bbf39793dfa686925f076a56b4d5vboxsync uint32_t cyl, r;
5c4d7e2aae42bbf39793dfa686925f076a56b4d5vboxsync if (s->uATARegSelect & 0x40)
5c4d7e2aae42bbf39793dfa686925f076a56b4d5vboxsync {
5c4d7e2aae42bbf39793dfa686925f076a56b4d5vboxsync /* any LBA variant */
5c4d7e2aae42bbf39793dfa686925f076a56b4d5vboxsync if (s->fLBA48)
5c4d7e2aae42bbf39793dfa686925f076a56b4d5vboxsync {
5c4d7e2aae42bbf39793dfa686925f076a56b4d5vboxsync /* LBA48 */
5c4d7e2aae42bbf39793dfa686925f076a56b4d5vboxsync s->uATARegHCylHOB = iLBA >> 40;
5c4d7e2aae42bbf39793dfa686925f076a56b4d5vboxsync s->uATARegLCylHOB = iLBA >> 32;
5c4d7e2aae42bbf39793dfa686925f076a56b4d5vboxsync s->uATARegSectorHOB = iLBA >> 24;
5c4d7e2aae42bbf39793dfa686925f076a56b4d5vboxsync s->uATARegHCyl = iLBA >> 16;
5c4d7e2aae42bbf39793dfa686925f076a56b4d5vboxsync s->uATARegLCyl = iLBA >> 8;
5c4d7e2aae42bbf39793dfa686925f076a56b4d5vboxsync s->uATARegSector = iLBA;
5c4d7e2aae42bbf39793dfa686925f076a56b4d5vboxsync }
5c4d7e2aae42bbf39793dfa686925f076a56b4d5vboxsync else
5c4d7e2aae42bbf39793dfa686925f076a56b4d5vboxsync {
5c4d7e2aae42bbf39793dfa686925f076a56b4d5vboxsync /* LBA */
5c4d7e2aae42bbf39793dfa686925f076a56b4d5vboxsync s->uATARegSelect = (s->uATARegSelect & 0xf0) | (iLBA >> 24);
5c4d7e2aae42bbf39793dfa686925f076a56b4d5vboxsync s->uATARegHCyl = (iLBA >> 16);
5c4d7e2aae42bbf39793dfa686925f076a56b4d5vboxsync s->uATARegLCyl = (iLBA >> 8);
5c4d7e2aae42bbf39793dfa686925f076a56b4d5vboxsync s->uATARegSector = (iLBA);
5c4d7e2aae42bbf39793dfa686925f076a56b4d5vboxsync }
5c4d7e2aae42bbf39793dfa686925f076a56b4d5vboxsync }
5c4d7e2aae42bbf39793dfa686925f076a56b4d5vboxsync else
5c4d7e2aae42bbf39793dfa686925f076a56b4d5vboxsync {
5c4d7e2aae42bbf39793dfa686925f076a56b4d5vboxsync /* CHS */
5c4d7e2aae42bbf39793dfa686925f076a56b4d5vboxsync cyl = iLBA / (s->PCHSGeometry.cHeads * s->PCHSGeometry.cSectors);
5c4d7e2aae42bbf39793dfa686925f076a56b4d5vboxsync r = iLBA % (s->PCHSGeometry.cHeads * s->PCHSGeometry.cSectors);
5c4d7e2aae42bbf39793dfa686925f076a56b4d5vboxsync s->uATARegHCyl = cyl >> 8;
5c4d7e2aae42bbf39793dfa686925f076a56b4d5vboxsync s->uATARegLCyl = cyl;
5c4d7e2aae42bbf39793dfa686925f076a56b4d5vboxsync s->uATARegSelect = (s->uATARegSelect & 0xf0) | ((r / s->PCHSGeometry.cSectors) & 0x0f);
5c4d7e2aae42bbf39793dfa686925f076a56b4d5vboxsync s->uATARegSector = (r % s->PCHSGeometry.cSectors) + 1;
5c4d7e2aae42bbf39793dfa686925f076a56b4d5vboxsync }
5c4d7e2aae42bbf39793dfa686925f076a56b4d5vboxsync}
5c4d7e2aae42bbf39793dfa686925f076a56b4d5vboxsync
5c4d7e2aae42bbf39793dfa686925f076a56b4d5vboxsync
5c4d7e2aae42bbf39793dfa686925f076a56b4d5vboxsyncstatic int ataReadSectors(ATADevState *s, uint64_t u64Sector, void *pvBuf, uint32_t cSectors)
5c4d7e2aae42bbf39793dfa686925f076a56b4d5vboxsync{
5c4d7e2aae42bbf39793dfa686925f076a56b4d5vboxsync PATACONTROLLER pCtl = ATADEVSTATE_2_CONTROLLER(s);
88e56f700a3b8dfdf1646f96320f335e22339caavboxsync int rc;
88e56f700a3b8dfdf1646f96320f335e22339caavboxsync
88e56f700a3b8dfdf1646f96320f335e22339caavboxsync PDMCritSectLeave(&pCtl->lock);
88e56f700a3b8dfdf1646f96320f335e22339caavboxsync
88e56f700a3b8dfdf1646f96320f335e22339caavboxsync STAM_PROFILE_ADV_START(&s->StatReads, r);
88e56f700a3b8dfdf1646f96320f335e22339caavboxsync s->Led.Asserted.s.fReading = s->Led.Actual.s.fReading = 1;
88e56f700a3b8dfdf1646f96320f335e22339caavboxsync rc = s->pDrvBlock->pfnRead(s->pDrvBlock, u64Sector * 512, pvBuf, cSectors * 512);
88e56f700a3b8dfdf1646f96320f335e22339caavboxsync s->Led.Actual.s.fReading = 0;
88e56f700a3b8dfdf1646f96320f335e22339caavboxsync STAM_PROFILE_ADV_STOP(&s->StatReads, r);
88e56f700a3b8dfdf1646f96320f335e22339caavboxsync
88e56f700a3b8dfdf1646f96320f335e22339caavboxsync STAM_REL_COUNTER_ADD(&s->StatBytesRead, cSectors * 512);
88e56f700a3b8dfdf1646f96320f335e22339caavboxsync
88e56f700a3b8dfdf1646f96320f335e22339caavboxsync STAM_PROFILE_START(&pCtl->StatLockWait, a);
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync PDMCritSectEnter(&pCtl->lock, VINF_SUCCESS);
88e56f700a3b8dfdf1646f96320f335e22339caavboxsync STAM_PROFILE_STOP(&pCtl->StatLockWait, a);
5c4d7e2aae42bbf39793dfa686925f076a56b4d5vboxsync return rc;
5c4d7e2aae42bbf39793dfa686925f076a56b4d5vboxsync}
5c4d7e2aae42bbf39793dfa686925f076a56b4d5vboxsync
5c4d7e2aae42bbf39793dfa686925f076a56b4d5vboxsync
5c4d7e2aae42bbf39793dfa686925f076a56b4d5vboxsyncstatic int ataWriteSectors(ATADevState *s, uint64_t u64Sector, const void *pvBuf, uint32_t cSectors)
5c4d7e2aae42bbf39793dfa686925f076a56b4d5vboxsync{
5c4d7e2aae42bbf39793dfa686925f076a56b4d5vboxsync PATACONTROLLER pCtl = ATADEVSTATE_2_CONTROLLER(s);
5c4d7e2aae42bbf39793dfa686925f076a56b4d5vboxsync int rc;
5c4d7e2aae42bbf39793dfa686925f076a56b4d5vboxsync
5c4d7e2aae42bbf39793dfa686925f076a56b4d5vboxsync PDMCritSectLeave(&pCtl->lock);
5c4d7e2aae42bbf39793dfa686925f076a56b4d5vboxsync
5c4d7e2aae42bbf39793dfa686925f076a56b4d5vboxsync STAM_PROFILE_ADV_START(&s->StatWrites, w);
5c4d7e2aae42bbf39793dfa686925f076a56b4d5vboxsync s->Led.Asserted.s.fWriting = s->Led.Actual.s.fWriting = 1;
5c4d7e2aae42bbf39793dfa686925f076a56b4d5vboxsync#ifdef VBOX_INSTRUMENT_DMA_WRITES
5c4d7e2aae42bbf39793dfa686925f076a56b4d5vboxsync if (s->fDMA)
5c4d7e2aae42bbf39793dfa686925f076a56b4d5vboxsync STAM_PROFILE_ADV_START(&s->StatInstrVDWrites, vw);
5c4d7e2aae42bbf39793dfa686925f076a56b4d5vboxsync#endif
5c4d7e2aae42bbf39793dfa686925f076a56b4d5vboxsync rc = s->pDrvBlock->pfnWrite(s->pDrvBlock, u64Sector * 512, pvBuf, cSectors * 512);
5c4d7e2aae42bbf39793dfa686925f076a56b4d5vboxsync#ifdef VBOX_INSTRUMENT_DMA_WRITES
5c4d7e2aae42bbf39793dfa686925f076a56b4d5vboxsync if (s->fDMA)
5c4d7e2aae42bbf39793dfa686925f076a56b4d5vboxsync STAM_PROFILE_ADV_STOP(&s->StatInstrVDWrites, vw);
5c4d7e2aae42bbf39793dfa686925f076a56b4d5vboxsync#endif
5c4d7e2aae42bbf39793dfa686925f076a56b4d5vboxsync s->Led.Actual.s.fWriting = 0;
5c4d7e2aae42bbf39793dfa686925f076a56b4d5vboxsync STAM_PROFILE_ADV_STOP(&s->StatWrites, w);
5c4d7e2aae42bbf39793dfa686925f076a56b4d5vboxsync
5c4d7e2aae42bbf39793dfa686925f076a56b4d5vboxsync STAM_REL_COUNTER_ADD(&s->StatBytesWritten, cSectors * 512);
5c4d7e2aae42bbf39793dfa686925f076a56b4d5vboxsync
5c4d7e2aae42bbf39793dfa686925f076a56b4d5vboxsync STAM_PROFILE_START(&pCtl->StatLockWait, a);
5c4d7e2aae42bbf39793dfa686925f076a56b4d5vboxsync PDMCritSectEnter(&pCtl->lock, VINF_SUCCESS);
5c4d7e2aae42bbf39793dfa686925f076a56b4d5vboxsync STAM_PROFILE_STOP(&pCtl->StatLockWait, a);
5c4d7e2aae42bbf39793dfa686925f076a56b4d5vboxsync return rc;
5c4d7e2aae42bbf39793dfa686925f076a56b4d5vboxsync}
5c4d7e2aae42bbf39793dfa686925f076a56b4d5vboxsync
5c4d7e2aae42bbf39793dfa686925f076a56b4d5vboxsync
5c4d7e2aae42bbf39793dfa686925f076a56b4d5vboxsyncstatic void ataReadWriteSectorsBT(ATADevState *s)
5c4d7e2aae42bbf39793dfa686925f076a56b4d5vboxsync{
5c4d7e2aae42bbf39793dfa686925f076a56b4d5vboxsync uint32_t cSectors;
5c4d7e2aae42bbf39793dfa686925f076a56b4d5vboxsync
5c4d7e2aae42bbf39793dfa686925f076a56b4d5vboxsync cSectors = s->cbTotalTransfer / 512;
5c4d7e2aae42bbf39793dfa686925f076a56b4d5vboxsync if (cSectors > s->cSectorsPerIRQ)
5c4d7e2aae42bbf39793dfa686925f076a56b4d5vboxsync s->cbElementaryTransfer = s->cSectorsPerIRQ * 512;
5c4d7e2aae42bbf39793dfa686925f076a56b4d5vboxsync else
5c4d7e2aae42bbf39793dfa686925f076a56b4d5vboxsync s->cbElementaryTransfer = cSectors * 512;
5c4d7e2aae42bbf39793dfa686925f076a56b4d5vboxsync if (s->uTxDir == PDMBLOCKTXDIR_TO_DEVICE)
5c4d7e2aae42bbf39793dfa686925f076a56b4d5vboxsync ataCmdOK(s, 0);
5c4d7e2aae42bbf39793dfa686925f076a56b4d5vboxsync}
5c4d7e2aae42bbf39793dfa686925f076a56b4d5vboxsync
5c4d7e2aae42bbf39793dfa686925f076a56b4d5vboxsync
5c4d7e2aae42bbf39793dfa686925f076a56b4d5vboxsyncstatic void ataWarningDiskFull(PPDMDEVINS pDevIns)
5c4d7e2aae42bbf39793dfa686925f076a56b4d5vboxsync{
5c4d7e2aae42bbf39793dfa686925f076a56b4d5vboxsync int rc;
5c4d7e2aae42bbf39793dfa686925f076a56b4d5vboxsync LogRel(("PIIX3 ATA: Host disk full\n"));
5c4d7e2aae42bbf39793dfa686925f076a56b4d5vboxsync rc = VMSetRuntimeError(PDMDevHlpGetVM(pDevIns),
5c4d7e2aae42bbf39793dfa686925f076a56b4d5vboxsync false, "DevATA_DISKFULL",
5c4d7e2aae42bbf39793dfa686925f076a56b4d5vboxsync N_("Host system reported disk full. VM execution is suspended. You can resume after freeing some space"));
5c4d7e2aae42bbf39793dfa686925f076a56b4d5vboxsync AssertRC(rc);
5c4d7e2aae42bbf39793dfa686925f076a56b4d5vboxsync}
5c4d7e2aae42bbf39793dfa686925f076a56b4d5vboxsync
5c4d7e2aae42bbf39793dfa686925f076a56b4d5vboxsync
5c4d7e2aae42bbf39793dfa686925f076a56b4d5vboxsyncstatic void ataWarningFileTooBig(PPDMDEVINS pDevIns)
5c4d7e2aae42bbf39793dfa686925f076a56b4d5vboxsync{
5c4d7e2aae42bbf39793dfa686925f076a56b4d5vboxsync int rc;
5c4d7e2aae42bbf39793dfa686925f076a56b4d5vboxsync LogRel(("PIIX3 ATA: File too big\n"));
5c4d7e2aae42bbf39793dfa686925f076a56b4d5vboxsync rc = VMSetRuntimeError(PDMDevHlpGetVM(pDevIns),
5c4d7e2aae42bbf39793dfa686925f076a56b4d5vboxsync false, "DevATA_FILETOOBIG",
5c4d7e2aae42bbf39793dfa686925f076a56b4d5vboxsync N_("Host system reported that the file size limit of the host file system has been exceeded. VM execution is suspended. You need to move your virtual hard disk to a filesystem which allows bigger files"));
5c4d7e2aae42bbf39793dfa686925f076a56b4d5vboxsync AssertRC(rc);
5c4d7e2aae42bbf39793dfa686925f076a56b4d5vboxsync}
5c4d7e2aae42bbf39793dfa686925f076a56b4d5vboxsync
5c4d7e2aae42bbf39793dfa686925f076a56b4d5vboxsync
5c4d7e2aae42bbf39793dfa686925f076a56b4d5vboxsyncstatic void ataWarningISCSI(PPDMDEVINS pDevIns)
5c4d7e2aae42bbf39793dfa686925f076a56b4d5vboxsync{
5c4d7e2aae42bbf39793dfa686925f076a56b4d5vboxsync int rc;
5c4d7e2aae42bbf39793dfa686925f076a56b4d5vboxsync LogRel(("PIIX3 ATA: iSCSI target unavailable\n"));
5c4d7e2aae42bbf39793dfa686925f076a56b4d5vboxsync rc = VMSetRuntimeError(PDMDevHlpGetVM(pDevIns),
5c4d7e2aae42bbf39793dfa686925f076a56b4d5vboxsync false, "DevATA_ISCSIDOWN",
5c4d7e2aae42bbf39793dfa686925f076a56b4d5vboxsync N_("The iSCSI target has stopped responding. VM execution is suspended. You can resume when it is available again"));
5c4d7e2aae42bbf39793dfa686925f076a56b4d5vboxsync AssertRC(rc);
5c4d7e2aae42bbf39793dfa686925f076a56b4d5vboxsync}
5c4d7e2aae42bbf39793dfa686925f076a56b4d5vboxsync
5c4d7e2aae42bbf39793dfa686925f076a56b4d5vboxsync
5c4d7e2aae42bbf39793dfa686925f076a56b4d5vboxsyncstatic bool ataReadSectorsSS(ATADevState *s)
5c4d7e2aae42bbf39793dfa686925f076a56b4d5vboxsync{
5c4d7e2aae42bbf39793dfa686925f076a56b4d5vboxsync int rc;
5c4d7e2aae42bbf39793dfa686925f076a56b4d5vboxsync uint32_t cSectors;
5c4d7e2aae42bbf39793dfa686925f076a56b4d5vboxsync uint64_t iLBA;
5c4d7e2aae42bbf39793dfa686925f076a56b4d5vboxsync
5c4d7e2aae42bbf39793dfa686925f076a56b4d5vboxsync cSectors = s->cbElementaryTransfer / 512;
5c4d7e2aae42bbf39793dfa686925f076a56b4d5vboxsync Assert(cSectors);
5c4d7e2aae42bbf39793dfa686925f076a56b4d5vboxsync iLBA = ataGetSector(s);
5c4d7e2aae42bbf39793dfa686925f076a56b4d5vboxsync Log(("%s: %d sectors at LBA %d\n", __FUNCTION__, cSectors, iLBA));
5c4d7e2aae42bbf39793dfa686925f076a56b4d5vboxsync rc = ataReadSectors(s, iLBA, s->CTX_SUFF(pbIOBuffer), cSectors);
5c4d7e2aae42bbf39793dfa686925f076a56b4d5vboxsync if (RT_SUCCESS(rc))
5c4d7e2aae42bbf39793dfa686925f076a56b4d5vboxsync {
5c4d7e2aae42bbf39793dfa686925f076a56b4d5vboxsync ataSetSector(s, iLBA + cSectors);
5c4d7e2aae42bbf39793dfa686925f076a56b4d5vboxsync if (s->cbElementaryTransfer == s->cbTotalTransfer)
5c4d7e2aae42bbf39793dfa686925f076a56b4d5vboxsync s->iSourceSink = ATAFN_SS_NULL;
5c4d7e2aae42bbf39793dfa686925f076a56b4d5vboxsync ataCmdOK(s, ATA_STAT_SEEK);
5c4d7e2aae42bbf39793dfa686925f076a56b4d5vboxsync }
5c4d7e2aae42bbf39793dfa686925f076a56b4d5vboxsync else
5c4d7e2aae42bbf39793dfa686925f076a56b4d5vboxsync {
5c4d7e2aae42bbf39793dfa686925f076a56b4d5vboxsync if (rc == VERR_DISK_FULL)
5c4d7e2aae42bbf39793dfa686925f076a56b4d5vboxsync {
5c4d7e2aae42bbf39793dfa686925f076a56b4d5vboxsync ataWarningDiskFull(ATADEVSTATE_2_DEVINS(s));
5c4d7e2aae42bbf39793dfa686925f076a56b4d5vboxsync return true;
5c4d7e2aae42bbf39793dfa686925f076a56b4d5vboxsync }
5c4d7e2aae42bbf39793dfa686925f076a56b4d5vboxsync if (rc == VERR_FILE_TOO_BIG)
5c4d7e2aae42bbf39793dfa686925f076a56b4d5vboxsync {
5c4d7e2aae42bbf39793dfa686925f076a56b4d5vboxsync ataWarningFileTooBig(ATADEVSTATE_2_DEVINS(s));
5c4d7e2aae42bbf39793dfa686925f076a56b4d5vboxsync return true;
5c4d7e2aae42bbf39793dfa686925f076a56b4d5vboxsync }
5c4d7e2aae42bbf39793dfa686925f076a56b4d5vboxsync if (rc == VERR_BROKEN_PIPE || rc == VERR_NET_CONNECTION_REFUSED)
5c4d7e2aae42bbf39793dfa686925f076a56b4d5vboxsync {
5c4d7e2aae42bbf39793dfa686925f076a56b4d5vboxsync /* iSCSI connection abort (first error) or failure to reestablish
5c4d7e2aae42bbf39793dfa686925f076a56b4d5vboxsync * connection (second error). Pause VM. On resume we'll retry. */
5c4d7e2aae42bbf39793dfa686925f076a56b4d5vboxsync ataWarningISCSI(ATADEVSTATE_2_DEVINS(s));
5c4d7e2aae42bbf39793dfa686925f076a56b4d5vboxsync return true;
5c4d7e2aae42bbf39793dfa686925f076a56b4d5vboxsync }
5c4d7e2aae42bbf39793dfa686925f076a56b4d5vboxsync if (s->cErrors++ < MAX_LOG_REL_ERRORS)
5c4d7e2aae42bbf39793dfa686925f076a56b4d5vboxsync LogRel(("PIIX3 ATA: LUN#%d: disk read error (rc=%Rrc iSector=%#RX64 cSectors=%#RX32)\n",
5c4d7e2aae42bbf39793dfa686925f076a56b4d5vboxsync s->iLUN, rc, iLBA, cSectors));
5c4d7e2aae42bbf39793dfa686925f076a56b4d5vboxsync ataCmdError(s, ID_ERR);
5c4d7e2aae42bbf39793dfa686925f076a56b4d5vboxsync }
5c4d7e2aae42bbf39793dfa686925f076a56b4d5vboxsync /** @todo implement redo for iSCSI */
5c4d7e2aae42bbf39793dfa686925f076a56b4d5vboxsync return false;
5c4d7e2aae42bbf39793dfa686925f076a56b4d5vboxsync}
5c4d7e2aae42bbf39793dfa686925f076a56b4d5vboxsync
5c4d7e2aae42bbf39793dfa686925f076a56b4d5vboxsync
5c4d7e2aae42bbf39793dfa686925f076a56b4d5vboxsyncstatic bool ataWriteSectorsSS(ATADevState *s)
5c4d7e2aae42bbf39793dfa686925f076a56b4d5vboxsync{
5c4d7e2aae42bbf39793dfa686925f076a56b4d5vboxsync int rc;
5c4d7e2aae42bbf39793dfa686925f076a56b4d5vboxsync uint32_t cSectors;
5c4d7e2aae42bbf39793dfa686925f076a56b4d5vboxsync uint64_t iLBA;
5c4d7e2aae42bbf39793dfa686925f076a56b4d5vboxsync
5c4d7e2aae42bbf39793dfa686925f076a56b4d5vboxsync cSectors = s->cbElementaryTransfer / 512;
5c4d7e2aae42bbf39793dfa686925f076a56b4d5vboxsync Assert(cSectors);
5c4d7e2aae42bbf39793dfa686925f076a56b4d5vboxsync iLBA = ataGetSector(s);
5c4d7e2aae42bbf39793dfa686925f076a56b4d5vboxsync Log(("%s: %d sectors at LBA %d\n", __FUNCTION__, cSectors, iLBA));
5c4d7e2aae42bbf39793dfa686925f076a56b4d5vboxsync rc = ataWriteSectors(s, iLBA, s->CTX_SUFF(pbIOBuffer), cSectors);
5c4d7e2aae42bbf39793dfa686925f076a56b4d5vboxsync if (RT_SUCCESS(rc))
661bfa5aae55ac2f94fa1cb131ea2323e5f6e633vboxsync {
5c4d7e2aae42bbf39793dfa686925f076a56b4d5vboxsync ataSetSector(s, iLBA + cSectors);
5c4d7e2aae42bbf39793dfa686925f076a56b4d5vboxsync if (!s->cbTotalTransfer)
5c4d7e2aae42bbf39793dfa686925f076a56b4d5vboxsync s->iSourceSink = ATAFN_SS_NULL;
5c4d7e2aae42bbf39793dfa686925f076a56b4d5vboxsync ataCmdOK(s, ATA_STAT_SEEK);
5c4d7e2aae42bbf39793dfa686925f076a56b4d5vboxsync }
5c4d7e2aae42bbf39793dfa686925f076a56b4d5vboxsync else
5c4d7e2aae42bbf39793dfa686925f076a56b4d5vboxsync {
5c4d7e2aae42bbf39793dfa686925f076a56b4d5vboxsync if (rc == VERR_DISK_FULL)
5c4d7e2aae42bbf39793dfa686925f076a56b4d5vboxsync {
5c4d7e2aae42bbf39793dfa686925f076a56b4d5vboxsync ataWarningDiskFull(ATADEVSTATE_2_DEVINS(s));
5c4d7e2aae42bbf39793dfa686925f076a56b4d5vboxsync return true;
5c4d7e2aae42bbf39793dfa686925f076a56b4d5vboxsync }
5c4d7e2aae42bbf39793dfa686925f076a56b4d5vboxsync if (rc == VERR_FILE_TOO_BIG)
5c4d7e2aae42bbf39793dfa686925f076a56b4d5vboxsync {
5c4d7e2aae42bbf39793dfa686925f076a56b4d5vboxsync ataWarningFileTooBig(ATADEVSTATE_2_DEVINS(s));
5c4d7e2aae42bbf39793dfa686925f076a56b4d5vboxsync return true;
5c4d7e2aae42bbf39793dfa686925f076a56b4d5vboxsync }
5c4d7e2aae42bbf39793dfa686925f076a56b4d5vboxsync if (rc == VERR_BROKEN_PIPE || rc == VERR_NET_CONNECTION_REFUSED)
5c4d7e2aae42bbf39793dfa686925f076a56b4d5vboxsync {
5c4d7e2aae42bbf39793dfa686925f076a56b4d5vboxsync /* iSCSI connection abort (first error) or failure to reestablish
5c4d7e2aae42bbf39793dfa686925f076a56b4d5vboxsync * connection (second error). Pause VM. On resume we'll retry. */
5c4d7e2aae42bbf39793dfa686925f076a56b4d5vboxsync ataWarningISCSI(ATADEVSTATE_2_DEVINS(s));
5c4d7e2aae42bbf39793dfa686925f076a56b4d5vboxsync return true;
5c4d7e2aae42bbf39793dfa686925f076a56b4d5vboxsync }
5c4d7e2aae42bbf39793dfa686925f076a56b4d5vboxsync if (s->cErrors++ < MAX_LOG_REL_ERRORS)
5c4d7e2aae42bbf39793dfa686925f076a56b4d5vboxsync LogRel(("PIIX3 ATA: LUN#%d: disk write error (rc=%Rrc iSector=%#RX64 cSectors=%#RX32)\n",
5c4d7e2aae42bbf39793dfa686925f076a56b4d5vboxsync s->iLUN, rc, iLBA, cSectors));
5c4d7e2aae42bbf39793dfa686925f076a56b4d5vboxsync ataCmdError(s, ID_ERR);
5c4d7e2aae42bbf39793dfa686925f076a56b4d5vboxsync }
5c4d7e2aae42bbf39793dfa686925f076a56b4d5vboxsync /** @todo implement redo for iSCSI */
5c4d7e2aae42bbf39793dfa686925f076a56b4d5vboxsync return false;
5c4d7e2aae42bbf39793dfa686925f076a56b4d5vboxsync}
5c4d7e2aae42bbf39793dfa686925f076a56b4d5vboxsync
5c4d7e2aae42bbf39793dfa686925f076a56b4d5vboxsync
5c4d7e2aae42bbf39793dfa686925f076a56b4d5vboxsyncstatic void atapiCmdOK(ATADevState *s)
5c4d7e2aae42bbf39793dfa686925f076a56b4d5vboxsync{
5c4d7e2aae42bbf39793dfa686925f076a56b4d5vboxsync s->uATARegError = 0;
5c4d7e2aae42bbf39793dfa686925f076a56b4d5vboxsync ataSetStatusValue(s, ATA_STAT_READY);
5c4d7e2aae42bbf39793dfa686925f076a56b4d5vboxsync s->uATARegNSector = (s->uATARegNSector & ~7)
5c4d7e2aae42bbf39793dfa686925f076a56b4d5vboxsync | ((s->uTxDir != PDMBLOCKTXDIR_TO_DEVICE) ? ATAPI_INT_REASON_IO : 0)
5c4d7e2aae42bbf39793dfa686925f076a56b4d5vboxsync | (!s->cbTotalTransfer ? ATAPI_INT_REASON_CD : 0);
5c4d7e2aae42bbf39793dfa686925f076a56b4d5vboxsync Log2(("%s: interrupt reason %#04x\n", __FUNCTION__, s->uATARegNSector));
5c4d7e2aae42bbf39793dfa686925f076a56b4d5vboxsync
5c4d7e2aae42bbf39793dfa686925f076a56b4d5vboxsync memset(s->abATAPISense, '\0', sizeof(s->abATAPISense));
5c4d7e2aae42bbf39793dfa686925f076a56b4d5vboxsync s->abATAPISense[0] = 0x70 | (1 << 7);
5c4d7e2aae42bbf39793dfa686925f076a56b4d5vboxsync s->abATAPISense[7] = 10;
5c4d7e2aae42bbf39793dfa686925f076a56b4d5vboxsync}
5c4d7e2aae42bbf39793dfa686925f076a56b4d5vboxsync
5c4d7e2aae42bbf39793dfa686925f076a56b4d5vboxsync
5c4d7e2aae42bbf39793dfa686925f076a56b4d5vboxsyncstatic void atapiCmdError(ATADevState *s, const uint8_t *pabATAPISense, size_t cbATAPISense)
5c4d7e2aae42bbf39793dfa686925f076a56b4d5vboxsync{
5c4d7e2aae42bbf39793dfa686925f076a56b4d5vboxsync Log(("%s: sense=%#x (%s) asc=%#x ascq=%#x (%s)\n", __FUNCTION__, pabATAPISense[2] & 0x0f, SCSISenseText(pabATAPISense[2] & 0x0f),
5c4d7e2aae42bbf39793dfa686925f076a56b4d5vboxsync pabATAPISense[12], pabATAPISense[13], SCSISenseExtText(pabATAPISense[12], pabATAPISense[13])));
5c4d7e2aae42bbf39793dfa686925f076a56b4d5vboxsync s->uATARegError = pabATAPISense[2] << 4;
5c4d7e2aae42bbf39793dfa686925f076a56b4d5vboxsync ataSetStatusValue(s, ATA_STAT_READY | ATA_STAT_ERR);
5c4d7e2aae42bbf39793dfa686925f076a56b4d5vboxsync s->uATARegNSector = (s->uATARegNSector & ~7) | ATAPI_INT_REASON_IO | ATAPI_INT_REASON_CD;
5c4d7e2aae42bbf39793dfa686925f076a56b4d5vboxsync Log2(("%s: interrupt reason %#04x\n", __FUNCTION__, s->uATARegNSector));
5c4d7e2aae42bbf39793dfa686925f076a56b4d5vboxsync memset(s->abATAPISense, '\0', sizeof(s->abATAPISense));
5c4d7e2aae42bbf39793dfa686925f076a56b4d5vboxsync memcpy(s->abATAPISense, pabATAPISense, RT_MIN(cbATAPISense, sizeof(s->abATAPISense)));
5c4d7e2aae42bbf39793dfa686925f076a56b4d5vboxsync s->cbTotalTransfer = 0;
5c4d7e2aae42bbf39793dfa686925f076a56b4d5vboxsync s->cbElementaryTransfer = 0;
e250515922582e0410c9bcb6d24b0f17bef083a0vboxsync s->iIOBufferCur = 0;
e250515922582e0410c9bcb6d24b0f17bef083a0vboxsync s->iIOBufferEnd = 0;
e250515922582e0410c9bcb6d24b0f17bef083a0vboxsync s->uTxDir = PDMBLOCKTXDIR_NONE;
e250515922582e0410c9bcb6d24b0f17bef083a0vboxsync s->iBeginTransfer = ATAFN_BT_NULL;
e250515922582e0410c9bcb6d24b0f17bef083a0vboxsync s->iSourceSink = ATAFN_SS_NULL;
e250515922582e0410c9bcb6d24b0f17bef083a0vboxsync}
e250515922582e0410c9bcb6d24b0f17bef083a0vboxsync
e250515922582e0410c9bcb6d24b0f17bef083a0vboxsync
e250515922582e0410c9bcb6d24b0f17bef083a0vboxsync/** @todo deprecated function - doesn't provide enough info. Replace by direct
e250515922582e0410c9bcb6d24b0f17bef083a0vboxsync * calls to atapiCmdError() with full data. */
e250515922582e0410c9bcb6d24b0f17bef083a0vboxsyncstatic void atapiCmdErrorSimple(ATADevState *s, uint8_t uATAPISenseKey, uint8_t uATAPIASC)
e250515922582e0410c9bcb6d24b0f17bef083a0vboxsync{
e250515922582e0410c9bcb6d24b0f17bef083a0vboxsync uint8_t abATAPISense[ATAPI_SENSE_SIZE];
e250515922582e0410c9bcb6d24b0f17bef083a0vboxsync memset(abATAPISense, '\0', sizeof(abATAPISense));
e250515922582e0410c9bcb6d24b0f17bef083a0vboxsync abATAPISense[0] = 0x70 | (1 << 7);
e250515922582e0410c9bcb6d24b0f17bef083a0vboxsync abATAPISense[2] = uATAPISenseKey & 0x0f;
e250515922582e0410c9bcb6d24b0f17bef083a0vboxsync abATAPISense[7] = 10;
e250515922582e0410c9bcb6d24b0f17bef083a0vboxsync abATAPISense[12] = uATAPIASC;
e250515922582e0410c9bcb6d24b0f17bef083a0vboxsync atapiCmdError(s, abATAPISense, sizeof(abATAPISense));
e250515922582e0410c9bcb6d24b0f17bef083a0vboxsync}
e250515922582e0410c9bcb6d24b0f17bef083a0vboxsync
e250515922582e0410c9bcb6d24b0f17bef083a0vboxsync
e250515922582e0410c9bcb6d24b0f17bef083a0vboxsyncstatic void atapiCmdBT(ATADevState *s)
e250515922582e0410c9bcb6d24b0f17bef083a0vboxsync{
e250515922582e0410c9bcb6d24b0f17bef083a0vboxsync s->fATAPITransfer = true;
e250515922582e0410c9bcb6d24b0f17bef083a0vboxsync s->cbElementaryTransfer = s->cbTotalTransfer;
f40cc8247b1da75ce42e73e6c557ec29b8f830a5vboxsync if (s->uTxDir == PDMBLOCKTXDIR_TO_DEVICE)
f40cc8247b1da75ce42e73e6c557ec29b8f830a5vboxsync atapiCmdOK(s);
f40cc8247b1da75ce42e73e6c557ec29b8f830a5vboxsync}
f40cc8247b1da75ce42e73e6c557ec29b8f830a5vboxsync
e250515922582e0410c9bcb6d24b0f17bef083a0vboxsync
e250515922582e0410c9bcb6d24b0f17bef083a0vboxsyncstatic void atapiPassthroughCmdBT(ATADevState *s)
e250515922582e0410c9bcb6d24b0f17bef083a0vboxsync{
e250515922582e0410c9bcb6d24b0f17bef083a0vboxsync /* @todo implement an algorithm for correctly determining the read and
e250515922582e0410c9bcb6d24b0f17bef083a0vboxsync * write sector size without sending additional commands to the drive.
e250515922582e0410c9bcb6d24b0f17bef083a0vboxsync * This should be doable by saving processing the configuration requests
e250515922582e0410c9bcb6d24b0f17bef083a0vboxsync * and replies. */
e250515922582e0410c9bcb6d24b0f17bef083a0vboxsync#if 0
e250515922582e0410c9bcb6d24b0f17bef083a0vboxsync if (s->uTxDir == PDMBLOCKTXDIR_TO_DEVICE)
e250515922582e0410c9bcb6d24b0f17bef083a0vboxsync {
e250515922582e0410c9bcb6d24b0f17bef083a0vboxsync uint8_t cmd = s->aATAPICmd[0];
e250515922582e0410c9bcb6d24b0f17bef083a0vboxsync if (cmd == SCSI_WRITE_10 || cmd == SCSI_WRITE_12 || cmd == SCSI_WRITE_AND_VERIFY_10)
e250515922582e0410c9bcb6d24b0f17bef083a0vboxsync {
e250515922582e0410c9bcb6d24b0f17bef083a0vboxsync uint8_t aModeSenseCmd[10];
e250515922582e0410c9bcb6d24b0f17bef083a0vboxsync uint8_t aModeSenseResult[16];
e250515922582e0410c9bcb6d24b0f17bef083a0vboxsync uint8_t uDummySense;
e250515922582e0410c9bcb6d24b0f17bef083a0vboxsync uint32_t cbTransfer;
e250515922582e0410c9bcb6d24b0f17bef083a0vboxsync int rc;
f40cc8247b1da75ce42e73e6c557ec29b8f830a5vboxsync
e250515922582e0410c9bcb6d24b0f17bef083a0vboxsync cbTransfer = sizeof(aModeSenseResult);
e250515922582e0410c9bcb6d24b0f17bef083a0vboxsync aModeSenseCmd[0] = SCSI_MODE_SENSE_10;
e250515922582e0410c9bcb6d24b0f17bef083a0vboxsync aModeSenseCmd[1] = 0x08; /* disable block descriptor = 1 */
e250515922582e0410c9bcb6d24b0f17bef083a0vboxsync aModeSenseCmd[2] = (SCSI_PAGECONTROL_CURRENT << 6) | SCSI_MODEPAGE_WRITE_PARAMETER;
e250515922582e0410c9bcb6d24b0f17bef083a0vboxsync aModeSenseCmd[3] = 0; /* subpage code */
e250515922582e0410c9bcb6d24b0f17bef083a0vboxsync aModeSenseCmd[4] = 0; /* reserved */
e250515922582e0410c9bcb6d24b0f17bef083a0vboxsync aModeSenseCmd[5] = 0; /* reserved */
e250515922582e0410c9bcb6d24b0f17bef083a0vboxsync aModeSenseCmd[6] = 0; /* reserved */
e250515922582e0410c9bcb6d24b0f17bef083a0vboxsync aModeSenseCmd[7] = cbTransfer >> 8;
e250515922582e0410c9bcb6d24b0f17bef083a0vboxsync aModeSenseCmd[8] = cbTransfer & 0xff;
e250515922582e0410c9bcb6d24b0f17bef083a0vboxsync aModeSenseCmd[9] = 0; /* control */
e250515922582e0410c9bcb6d24b0f17bef083a0vboxsync rc = s->pDrvBlock->pfnSendCmd(s->pDrvBlock, aModeSenseCmd, PDMBLOCKTXDIR_FROM_DEVICE, aModeSenseResult, &cbTransfer, &uDummySense, 500);
e250515922582e0410c9bcb6d24b0f17bef083a0vboxsync if (RT_FAILURE(rc))
e250515922582e0410c9bcb6d24b0f17bef083a0vboxsync {
e250515922582e0410c9bcb6d24b0f17bef083a0vboxsync atapiCmdErrorSimple(s, SCSI_SENSE_ILLEGAL_REQUEST, SCSI_ASC_NONE);
e250515922582e0410c9bcb6d24b0f17bef083a0vboxsync return;
e250515922582e0410c9bcb6d24b0f17bef083a0vboxsync }
e250515922582e0410c9bcb6d24b0f17bef083a0vboxsync /* Select sector size based on the current data block type. */
e250515922582e0410c9bcb6d24b0f17bef083a0vboxsync switch (aModeSenseResult[12] & 0x0f)
e250515922582e0410c9bcb6d24b0f17bef083a0vboxsync {
e250515922582e0410c9bcb6d24b0f17bef083a0vboxsync case 0:
e250515922582e0410c9bcb6d24b0f17bef083a0vboxsync s->cbATAPISector = 2352;
e250515922582e0410c9bcb6d24b0f17bef083a0vboxsync break;
e250515922582e0410c9bcb6d24b0f17bef083a0vboxsync case 1:
e250515922582e0410c9bcb6d24b0f17bef083a0vboxsync s->cbATAPISector = 2368;
e250515922582e0410c9bcb6d24b0f17bef083a0vboxsync break;
e250515922582e0410c9bcb6d24b0f17bef083a0vboxsync case 2:
e250515922582e0410c9bcb6d24b0f17bef083a0vboxsync case 3:
e250515922582e0410c9bcb6d24b0f17bef083a0vboxsync s->cbATAPISector = 2448;
e250515922582e0410c9bcb6d24b0f17bef083a0vboxsync break;
e250515922582e0410c9bcb6d24b0f17bef083a0vboxsync case 8:
e250515922582e0410c9bcb6d24b0f17bef083a0vboxsync case 10:
e250515922582e0410c9bcb6d24b0f17bef083a0vboxsync s->cbATAPISector = 2048;
e250515922582e0410c9bcb6d24b0f17bef083a0vboxsync break;
e250515922582e0410c9bcb6d24b0f17bef083a0vboxsync case 9:
e250515922582e0410c9bcb6d24b0f17bef083a0vboxsync s->cbATAPISector = 2336;
e250515922582e0410c9bcb6d24b0f17bef083a0vboxsync break;
e250515922582e0410c9bcb6d24b0f17bef083a0vboxsync case 11:
e250515922582e0410c9bcb6d24b0f17bef083a0vboxsync s->cbATAPISector = 2056;
e250515922582e0410c9bcb6d24b0f17bef083a0vboxsync break;
e250515922582e0410c9bcb6d24b0f17bef083a0vboxsync case 12:
e250515922582e0410c9bcb6d24b0f17bef083a0vboxsync s->cbATAPISector = 2324;
e250515922582e0410c9bcb6d24b0f17bef083a0vboxsync break;
e250515922582e0410c9bcb6d24b0f17bef083a0vboxsync case 13:
e250515922582e0410c9bcb6d24b0f17bef083a0vboxsync s->cbATAPISector = 2332;
e250515922582e0410c9bcb6d24b0f17bef083a0vboxsync break;
e250515922582e0410c9bcb6d24b0f17bef083a0vboxsync default:
e250515922582e0410c9bcb6d24b0f17bef083a0vboxsync s->cbATAPISector = 0;
e250515922582e0410c9bcb6d24b0f17bef083a0vboxsync }
e250515922582e0410c9bcb6d24b0f17bef083a0vboxsync Log2(("%s: sector size %d\n", __FUNCTION__, s->cbATAPISector));
e250515922582e0410c9bcb6d24b0f17bef083a0vboxsync s->cbTotalTransfer *= s->cbATAPISector;
e250515922582e0410c9bcb6d24b0f17bef083a0vboxsync if (s->cbTotalTransfer == 0)
e250515922582e0410c9bcb6d24b0f17bef083a0vboxsync s->uTxDir = PDMBLOCKTXDIR_NONE;
e250515922582e0410c9bcb6d24b0f17bef083a0vboxsync }
e250515922582e0410c9bcb6d24b0f17bef083a0vboxsync }
e250515922582e0410c9bcb6d24b0f17bef083a0vboxsync#endif
e250515922582e0410c9bcb6d24b0f17bef083a0vboxsync atapiCmdBT(s);
e250515922582e0410c9bcb6d24b0f17bef083a0vboxsync}
e250515922582e0410c9bcb6d24b0f17bef083a0vboxsync
e250515922582e0410c9bcb6d24b0f17bef083a0vboxsync
e250515922582e0410c9bcb6d24b0f17bef083a0vboxsyncstatic bool atapiReadSS(ATADevState *s)
e250515922582e0410c9bcb6d24b0f17bef083a0vboxsync{
e250515922582e0410c9bcb6d24b0f17bef083a0vboxsync PATACONTROLLER pCtl = ATADEVSTATE_2_CONTROLLER(s);
e250515922582e0410c9bcb6d24b0f17bef083a0vboxsync int rc = VINF_SUCCESS;
e250515922582e0410c9bcb6d24b0f17bef083a0vboxsync uint32_t cbTransfer, cSectors;
e250515922582e0410c9bcb6d24b0f17bef083a0vboxsync
e250515922582e0410c9bcb6d24b0f17bef083a0vboxsync Assert(s->uTxDir == PDMBLOCKTXDIR_FROM_DEVICE);
e250515922582e0410c9bcb6d24b0f17bef083a0vboxsync cbTransfer = RT_MIN(s->cbTotalTransfer, s->cbIOBuffer);
e250515922582e0410c9bcb6d24b0f17bef083a0vboxsync cSectors = cbTransfer / s->cbATAPISector;
e250515922582e0410c9bcb6d24b0f17bef083a0vboxsync Assert(cSectors * s->cbATAPISector <= cbTransfer);
e250515922582e0410c9bcb6d24b0f17bef083a0vboxsync Log(("%s: %d sectors at LBA %d\n", __FUNCTION__, cSectors, s->iATAPILBA));
e250515922582e0410c9bcb6d24b0f17bef083a0vboxsync
e250515922582e0410c9bcb6d24b0f17bef083a0vboxsync PDMCritSectLeave(&pCtl->lock);
e250515922582e0410c9bcb6d24b0f17bef083a0vboxsync
e250515922582e0410c9bcb6d24b0f17bef083a0vboxsync STAM_PROFILE_ADV_START(&s->StatReads, r);
e250515922582e0410c9bcb6d24b0f17bef083a0vboxsync s->Led.Asserted.s.fReading = s->Led.Actual.s.fReading = 1;
e250515922582e0410c9bcb6d24b0f17bef083a0vboxsync switch (s->cbATAPISector)
e250515922582e0410c9bcb6d24b0f17bef083a0vboxsync {
e250515922582e0410c9bcb6d24b0f17bef083a0vboxsync case 2048:
e250515922582e0410c9bcb6d24b0f17bef083a0vboxsync rc = s->pDrvBlock->pfnRead(s->pDrvBlock, (uint64_t)s->iATAPILBA * s->cbATAPISector, s->CTX_SUFF(pbIOBuffer), s->cbATAPISector * cSectors);
e250515922582e0410c9bcb6d24b0f17bef083a0vboxsync break;
e250515922582e0410c9bcb6d24b0f17bef083a0vboxsync case 2352:
e250515922582e0410c9bcb6d24b0f17bef083a0vboxsync {
e250515922582e0410c9bcb6d24b0f17bef083a0vboxsync uint8_t *pbBuf = s->CTX_SUFF(pbIOBuffer);
e250515922582e0410c9bcb6d24b0f17bef083a0vboxsync
e250515922582e0410c9bcb6d24b0f17bef083a0vboxsync for (uint32_t i = s->iATAPILBA; i < s->iATAPILBA + cSectors; i++)
e250515922582e0410c9bcb6d24b0f17bef083a0vboxsync {
e250515922582e0410c9bcb6d24b0f17bef083a0vboxsync /* sync bytes */
e250515922582e0410c9bcb6d24b0f17bef083a0vboxsync *pbBuf++ = 0x00;
e250515922582e0410c9bcb6d24b0f17bef083a0vboxsync memset(pbBuf, 0xff, 11);
e250515922582e0410c9bcb6d24b0f17bef083a0vboxsync pbBuf += 11;
e250515922582e0410c9bcb6d24b0f17bef083a0vboxsync /* MSF */
e250515922582e0410c9bcb6d24b0f17bef083a0vboxsync ataLBA2MSF(pbBuf, i);
e250515922582e0410c9bcb6d24b0f17bef083a0vboxsync pbBuf += 3;
e250515922582e0410c9bcb6d24b0f17bef083a0vboxsync *pbBuf++ = 0x01; /* mode 1 data */
e250515922582e0410c9bcb6d24b0f17bef083a0vboxsync /* data */
e250515922582e0410c9bcb6d24b0f17bef083a0vboxsync rc = s->pDrvBlock->pfnRead(s->pDrvBlock, (uint64_t)i * 2048, pbBuf, 2048);
e250515922582e0410c9bcb6d24b0f17bef083a0vboxsync if (RT_FAILURE(rc))
fdb40b7d2efa84fc6f03b7a695cb4b2e035c30c7vboxsync break;
8f7ee9e453c60b3b699799538a45950b35266665vboxsync pbBuf += 2048;
8f7ee9e453c60b3b699799538a45950b35266665vboxsync /* ECC */
fdb40b7d2efa84fc6f03b7a695cb4b2e035c30c7vboxsync memset(pbBuf, 0, 288);
8f7ee9e453c60b3b699799538a45950b35266665vboxsync pbBuf += 288;
fdb40b7d2efa84fc6f03b7a695cb4b2e035c30c7vboxsync }
fdb40b7d2efa84fc6f03b7a695cb4b2e035c30c7vboxsync }
fdb40b7d2efa84fc6f03b7a695cb4b2e035c30c7vboxsync break;
fdb40b7d2efa84fc6f03b7a695cb4b2e035c30c7vboxsync default:
fdb40b7d2efa84fc6f03b7a695cb4b2e035c30c7vboxsync break;
fdb40b7d2efa84fc6f03b7a695cb4b2e035c30c7vboxsync }
fdb40b7d2efa84fc6f03b7a695cb4b2e035c30c7vboxsync STAM_PROFILE_ADV_STOP(&s->StatReads, r);
fdb40b7d2efa84fc6f03b7a695cb4b2e035c30c7vboxsync
fdb40b7d2efa84fc6f03b7a695cb4b2e035c30c7vboxsync STAM_PROFILE_START(&pCtl->StatLockWait, a);
fdb40b7d2efa84fc6f03b7a695cb4b2e035c30c7vboxsync PDMCritSectEnter(&pCtl->lock, VINF_SUCCESS);
fdb40b7d2efa84fc6f03b7a695cb4b2e035c30c7vboxsync STAM_PROFILE_STOP(&pCtl->StatLockWait, a);
fdb40b7d2efa84fc6f03b7a695cb4b2e035c30c7vboxsync
fdb40b7d2efa84fc6f03b7a695cb4b2e035c30c7vboxsync if (RT_SUCCESS(rc))
fdb40b7d2efa84fc6f03b7a695cb4b2e035c30c7vboxsync {
fdb40b7d2efa84fc6f03b7a695cb4b2e035c30c7vboxsync s->Led.Actual.s.fReading = 0;
fdb40b7d2efa84fc6f03b7a695cb4b2e035c30c7vboxsync STAM_REL_COUNTER_ADD(&s->StatBytesRead, s->cbATAPISector * cSectors);
fdb40b7d2efa84fc6f03b7a695cb4b2e035c30c7vboxsync
fdb40b7d2efa84fc6f03b7a695cb4b2e035c30c7vboxsync /* The initial buffer end value has been set up based on the total
fdb40b7d2efa84fc6f03b7a695cb4b2e035c30c7vboxsync * transfer size. But the I/O buffer size limits what can actually be
fdb40b7d2efa84fc6f03b7a695cb4b2e035c30c7vboxsync * done in one transfer, so set the actual value of the buffer end. */
fdb40b7d2efa84fc6f03b7a695cb4b2e035c30c7vboxsync s->cbElementaryTransfer = cbTransfer;
fdb40b7d2efa84fc6f03b7a695cb4b2e035c30c7vboxsync if (cbTransfer >= s->cbTotalTransfer)
fdb40b7d2efa84fc6f03b7a695cb4b2e035c30c7vboxsync s->iSourceSink = ATAFN_SS_NULL;
fdb40b7d2efa84fc6f03b7a695cb4b2e035c30c7vboxsync atapiCmdOK(s);
fdb40b7d2efa84fc6f03b7a695cb4b2e035c30c7vboxsync s->iATAPILBA += cSectors;
fdb40b7d2efa84fc6f03b7a695cb4b2e035c30c7vboxsync }
88e56f700a3b8dfdf1646f96320f335e22339caavboxsync else
88e56f700a3b8dfdf1646f96320f335e22339caavboxsync {
88e56f700a3b8dfdf1646f96320f335e22339caavboxsync if (s->cErrors++ < MAX_LOG_REL_ERRORS)
88e56f700a3b8dfdf1646f96320f335e22339caavboxsync LogRel(("PIIX3 ATA: LUN#%d: CD-ROM read error, %d sectors at LBA %d\n", s->iLUN, cSectors, s->iATAPILBA));
88e56f700a3b8dfdf1646f96320f335e22339caavboxsync atapiCmdErrorSimple(s, SCSI_SENSE_MEDIUM_ERROR, SCSI_ASC_READ_ERROR);
5c4d7e2aae42bbf39793dfa686925f076a56b4d5vboxsync }
88e56f700a3b8dfdf1646f96320f335e22339caavboxsync return false;
88e56f700a3b8dfdf1646f96320f335e22339caavboxsync}
88e56f700a3b8dfdf1646f96320f335e22339caavboxsync
88e56f700a3b8dfdf1646f96320f335e22339caavboxsync
88e56f700a3b8dfdf1646f96320f335e22339caavboxsyncstatic bool atapiPassthroughSS(ATADevState *s)
88e56f700a3b8dfdf1646f96320f335e22339caavboxsync{
88e56f700a3b8dfdf1646f96320f335e22339caavboxsync PATACONTROLLER pCtl = ATADEVSTATE_2_CONTROLLER(s);
88e56f700a3b8dfdf1646f96320f335e22339caavboxsync int rc = VINF_SUCCESS;
88e56f700a3b8dfdf1646f96320f335e22339caavboxsync uint8_t abATAPISense[ATAPI_SENSE_SIZE];
88e56f700a3b8dfdf1646f96320f335e22339caavboxsync size_t cbTransfer;
88e56f700a3b8dfdf1646f96320f335e22339caavboxsync PSTAMPROFILEADV pProf = NULL;
88e56f700a3b8dfdf1646f96320f335e22339caavboxsync
88e56f700a3b8dfdf1646f96320f335e22339caavboxsync cbTransfer = s->cbElementaryTransfer;
88e56f700a3b8dfdf1646f96320f335e22339caavboxsync
88e56f700a3b8dfdf1646f96320f335e22339caavboxsync if (s->uTxDir == PDMBLOCKTXDIR_TO_DEVICE)
88e56f700a3b8dfdf1646f96320f335e22339caavboxsync Log3(("ATAPI PT data write (%d): %.*Rhxs\n", cbTransfer, cbTransfer, s->CTX_SUFF(pbIOBuffer)));
88e56f700a3b8dfdf1646f96320f335e22339caavboxsync
88e56f700a3b8dfdf1646f96320f335e22339caavboxsync /* Simple heuristics: if there is at least one sector of data
88e56f700a3b8dfdf1646f96320f335e22339caavboxsync * to transfer, it's worth updating the LEDs. */
88e56f700a3b8dfdf1646f96320f335e22339caavboxsync if (cbTransfer >= 2048)
5c4d7e2aae42bbf39793dfa686925f076a56b4d5vboxsync {
88e56f700a3b8dfdf1646f96320f335e22339caavboxsync if (s->uTxDir != PDMBLOCKTXDIR_TO_DEVICE)
0d8c2135d15345cc68111eea91052cdf5518d7e3vboxsync {
fdb40b7d2efa84fc6f03b7a695cb4b2e035c30c7vboxsync s->Led.Asserted.s.fReading = s->Led.Actual.s.fReading = 1;
fdb40b7d2efa84fc6f03b7a695cb4b2e035c30c7vboxsync pProf = &s->StatReads;
88e56f700a3b8dfdf1646f96320f335e22339caavboxsync }
fdb40b7d2efa84fc6f03b7a695cb4b2e035c30c7vboxsync else
fdb40b7d2efa84fc6f03b7a695cb4b2e035c30c7vboxsync {
fdb40b7d2efa84fc6f03b7a695cb4b2e035c30c7vboxsync s->Led.Asserted.s.fWriting = s->Led.Actual.s.fWriting = 1;
8f7ee9e453c60b3b699799538a45950b35266665vboxsync pProf = &s->StatWrites;
88e56f700a3b8dfdf1646f96320f335e22339caavboxsync }
5c4d7e2aae42bbf39793dfa686925f076a56b4d5vboxsync }
88e56f700a3b8dfdf1646f96320f335e22339caavboxsync
5c4d7e2aae42bbf39793dfa686925f076a56b4d5vboxsync PDMCritSectLeave(&pCtl->lock);
5c4d7e2aae42bbf39793dfa686925f076a56b4d5vboxsync
0c94a8282c9042b02f022302a3d987746140eab9vboxsync if (pProf) { STAM_PROFILE_ADV_START(pProf, b); }
0c94a8282c9042b02f022302a3d987746140eab9vboxsync if (cbTransfer > 100 * _1K)
88e56f700a3b8dfdf1646f96320f335e22339caavboxsync {
88e56f700a3b8dfdf1646f96320f335e22339caavboxsync /* Linux accepts commands with up to 100KB of data, but expects
88e56f700a3b8dfdf1646f96320f335e22339caavboxsync * us to handle commands with up to 128KB of data. The usual
88e56f700a3b8dfdf1646f96320f335e22339caavboxsync * imbalance of powers. */
88e56f700a3b8dfdf1646f96320f335e22339caavboxsync uint8_t aATAPICmd[ATAPI_PACKET_SIZE];
88e56f700a3b8dfdf1646f96320f335e22339caavboxsync uint32_t iATAPILBA, cSectors, cReqSectors;
88e56f700a3b8dfdf1646f96320f335e22339caavboxsync size_t cbCurrTX;
88e56f700a3b8dfdf1646f96320f335e22339caavboxsync uint8_t *pbBuf = s->CTX_SUFF(pbIOBuffer);
5c4d7e2aae42bbf39793dfa686925f076a56b4d5vboxsync
5c4d7e2aae42bbf39793dfa686925f076a56b4d5vboxsync switch (s->aATAPICmd[0])
88e56f700a3b8dfdf1646f96320f335e22339caavboxsync {
5c4d7e2aae42bbf39793dfa686925f076a56b4d5vboxsync case SCSI_READ_10:
5c4d7e2aae42bbf39793dfa686925f076a56b4d5vboxsync case SCSI_WRITE_10:
9c9db71d639cf066ed41d49629d46d48bff4be2fvboxsync case SCSI_WRITE_AND_VERIFY_10:
9c9db71d639cf066ed41d49629d46d48bff4be2fvboxsync iATAPILBA = ataBE2H_U32(s->aATAPICmd + 2);
0c94a8282c9042b02f022302a3d987746140eab9vboxsync cSectors = ataBE2H_U16(s->aATAPICmd + 7);
e250515922582e0410c9bcb6d24b0f17bef083a0vboxsync break;
0c94a8282c9042b02f022302a3d987746140eab9vboxsync case SCSI_READ_12:
0c94a8282c9042b02f022302a3d987746140eab9vboxsync case SCSI_WRITE_12:
e250515922582e0410c9bcb6d24b0f17bef083a0vboxsync iATAPILBA = ataBE2H_U32(s->aATAPICmd + 2);
e250515922582e0410c9bcb6d24b0f17bef083a0vboxsync cSectors = ataBE2H_U32(s->aATAPICmd + 6);
e250515922582e0410c9bcb6d24b0f17bef083a0vboxsync break;
f40cc8247b1da75ce42e73e6c557ec29b8f830a5vboxsync case SCSI_READ_CD:
5c4d7e2aae42bbf39793dfa686925f076a56b4d5vboxsync iATAPILBA = ataBE2H_U32(s->aATAPICmd + 2);
0c94a8282c9042b02f022302a3d987746140eab9vboxsync cSectors = ataBE2H_U24(s->aATAPICmd + 6) / s->cbATAPISector;
88e56f700a3b8dfdf1646f96320f335e22339caavboxsync break;
5c4d7e2aae42bbf39793dfa686925f076a56b4d5vboxsync case SCSI_READ_CD_MSF:
88e56f700a3b8dfdf1646f96320f335e22339caavboxsync iATAPILBA = ataMSF2LBA(s->aATAPICmd + 3);
5c4d7e2aae42bbf39793dfa686925f076a56b4d5vboxsync cSectors = ataMSF2LBA(s->aATAPICmd + 6) - iATAPILBA;
5c4d7e2aae42bbf39793dfa686925f076a56b4d5vboxsync break;
5c4d7e2aae42bbf39793dfa686925f076a56b4d5vboxsync default:
5c4d7e2aae42bbf39793dfa686925f076a56b4d5vboxsync AssertMsgFailed(("Don't know how to split command %#04x\n", s->aATAPICmd[0]));
88e56f700a3b8dfdf1646f96320f335e22339caavboxsync if (s->cErrors++ < MAX_LOG_REL_ERRORS)
5c4d7e2aae42bbf39793dfa686925f076a56b4d5vboxsync LogRel(("PIIX3 ATA: LUN#%d: CD-ROM passthrough split error\n", s->iLUN));
88e56f700a3b8dfdf1646f96320f335e22339caavboxsync atapiCmdErrorSimple(s, SCSI_SENSE_ILLEGAL_REQUEST, SCSI_ASC_ILLEGAL_OPCODE);
88e56f700a3b8dfdf1646f96320f335e22339caavboxsync {
88e56f700a3b8dfdf1646f96320f335e22339caavboxsync STAM_PROFILE_START(&pCtl->StatLockWait, a);
88e56f700a3b8dfdf1646f96320f335e22339caavboxsync PDMCritSectEnter(&pCtl->lock, VINF_SUCCESS);
88e56f700a3b8dfdf1646f96320f335e22339caavboxsync STAM_PROFILE_STOP(&pCtl->StatLockWait, a);
88e56f700a3b8dfdf1646f96320f335e22339caavboxsync }
88e56f700a3b8dfdf1646f96320f335e22339caavboxsync return false;
88e56f700a3b8dfdf1646f96320f335e22339caavboxsync }
5c4d7e2aae42bbf39793dfa686925f076a56b4d5vboxsync memcpy(aATAPICmd, s->aATAPICmd, ATAPI_PACKET_SIZE);
5c4d7e2aae42bbf39793dfa686925f076a56b4d5vboxsync cReqSectors = 0;
5c4d7e2aae42bbf39793dfa686925f076a56b4d5vboxsync for (uint32_t i = cSectors; i > 0; i -= cReqSectors)
5c4d7e2aae42bbf39793dfa686925f076a56b4d5vboxsync {
5c4d7e2aae42bbf39793dfa686925f076a56b4d5vboxsync if (i * s->cbATAPISector > 100 * _1K)
5c4d7e2aae42bbf39793dfa686925f076a56b4d5vboxsync cReqSectors = (100 * _1K) / s->cbATAPISector;
5c4d7e2aae42bbf39793dfa686925f076a56b4d5vboxsync else
5c4d7e2aae42bbf39793dfa686925f076a56b4d5vboxsync cReqSectors = i;
5c4d7e2aae42bbf39793dfa686925f076a56b4d5vboxsync cbCurrTX = s->cbATAPISector * cReqSectors;
0c94a8282c9042b02f022302a3d987746140eab9vboxsync switch (s->aATAPICmd[0])
0c94a8282c9042b02f022302a3d987746140eab9vboxsync {
0c94a8282c9042b02f022302a3d987746140eab9vboxsync case SCSI_READ_10:
0c94a8282c9042b02f022302a3d987746140eab9vboxsync case SCSI_WRITE_10:
0c94a8282c9042b02f022302a3d987746140eab9vboxsync case SCSI_WRITE_AND_VERIFY_10:
5c4d7e2aae42bbf39793dfa686925f076a56b4d5vboxsync ataH2BE_U32(aATAPICmd + 2, iATAPILBA);
5c4d7e2aae42bbf39793dfa686925f076a56b4d5vboxsync ataH2BE_U16(aATAPICmd + 7, cReqSectors);
88e56f700a3b8dfdf1646f96320f335e22339caavboxsync break;
5c4d7e2aae42bbf39793dfa686925f076a56b4d5vboxsync case SCSI_READ_12:
0c94a8282c9042b02f022302a3d987746140eab9vboxsync case SCSI_WRITE_12:
0c94a8282c9042b02f022302a3d987746140eab9vboxsync ataH2BE_U32(aATAPICmd + 2, iATAPILBA);
0c94a8282c9042b02f022302a3d987746140eab9vboxsync ataH2BE_U32(aATAPICmd + 6, cReqSectors);
0c94a8282c9042b02f022302a3d987746140eab9vboxsync break;
0c94a8282c9042b02f022302a3d987746140eab9vboxsync case SCSI_READ_CD:
0c94a8282c9042b02f022302a3d987746140eab9vboxsync ataH2BE_U32(s->aATAPICmd + 2, iATAPILBA);
0c94a8282c9042b02f022302a3d987746140eab9vboxsync ataH2BE_U24(s->aATAPICmd + 6, cbCurrTX);
5c4d7e2aae42bbf39793dfa686925f076a56b4d5vboxsync break;
5c4d7e2aae42bbf39793dfa686925f076a56b4d5vboxsync case SCSI_READ_CD_MSF:
88e56f700a3b8dfdf1646f96320f335e22339caavboxsync ataLBA2MSF(aATAPICmd + 3, iATAPILBA);
88e56f700a3b8dfdf1646f96320f335e22339caavboxsync ataLBA2MSF(aATAPICmd + 6, iATAPILBA + cReqSectors);
88e56f700a3b8dfdf1646f96320f335e22339caavboxsync break;
88e56f700a3b8dfdf1646f96320f335e22339caavboxsync }
5c4d7e2aae42bbf39793dfa686925f076a56b4d5vboxsync rc = s->pDrvBlock->pfnSendCmd(s->pDrvBlock, aATAPICmd, (PDMBLOCKTXDIR)s->uTxDir, pbBuf, &cbCurrTX, abATAPISense, sizeof(abATAPISense), 30000 /**< @todo timeout */);
5c4d7e2aae42bbf39793dfa686925f076a56b4d5vboxsync if (rc != VINF_SUCCESS)
5c4d7e2aae42bbf39793dfa686925f076a56b4d5vboxsync break;
0c94a8282c9042b02f022302a3d987746140eab9vboxsync iATAPILBA += cReqSectors;
0c94a8282c9042b02f022302a3d987746140eab9vboxsync pbBuf += s->cbATAPISector * cReqSectors;
0c94a8282c9042b02f022302a3d987746140eab9vboxsync }
0c94a8282c9042b02f022302a3d987746140eab9vboxsync }
0c94a8282c9042b02f022302a3d987746140eab9vboxsync else
5c4d7e2aae42bbf39793dfa686925f076a56b4d5vboxsync rc = s->pDrvBlock->pfnSendCmd(s->pDrvBlock, s->aATAPICmd, (PDMBLOCKTXDIR)s->uTxDir, s->CTX_SUFF(pbIOBuffer), &cbTransfer, abATAPISense, sizeof(abATAPISense), 30000 /**< @todo timeout */);
88e56f700a3b8dfdf1646f96320f335e22339caavboxsync if (pProf) { STAM_PROFILE_ADV_STOP(pProf, b); }
5c4d7e2aae42bbf39793dfa686925f076a56b4d5vboxsync
88e56f700a3b8dfdf1646f96320f335e22339caavboxsync STAM_PROFILE_START(&pCtl->StatLockWait, a);
5c4d7e2aae42bbf39793dfa686925f076a56b4d5vboxsync PDMCritSectEnter(&pCtl->lock, VINF_SUCCESS);
5c4d7e2aae42bbf39793dfa686925f076a56b4d5vboxsync STAM_PROFILE_STOP(&pCtl->StatLockWait, a);
88e56f700a3b8dfdf1646f96320f335e22339caavboxsync
88e56f700a3b8dfdf1646f96320f335e22339caavboxsync /* Update the LEDs and the read/write statistics. */
88e56f700a3b8dfdf1646f96320f335e22339caavboxsync if (cbTransfer >= 2048)
88e56f700a3b8dfdf1646f96320f335e22339caavboxsync {
88e56f700a3b8dfdf1646f96320f335e22339caavboxsync if (s->uTxDir != PDMBLOCKTXDIR_TO_DEVICE)
88e56f700a3b8dfdf1646f96320f335e22339caavboxsync {
88e56f700a3b8dfdf1646f96320f335e22339caavboxsync s->Led.Actual.s.fReading = 0;
88e56f700a3b8dfdf1646f96320f335e22339caavboxsync STAM_REL_COUNTER_ADD(&s->StatBytesRead, cbTransfer);
88e56f700a3b8dfdf1646f96320f335e22339caavboxsync }
88e56f700a3b8dfdf1646f96320f335e22339caavboxsync else
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync {
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync s->Led.Actual.s.fWriting = 0;
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync STAM_REL_COUNTER_ADD(&s->StatBytesWritten, cbTransfer);
88e56f700a3b8dfdf1646f96320f335e22339caavboxsync }
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync }
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync if (RT_SUCCESS(rc))
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync {
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync if (s->uTxDir == PDMBLOCKTXDIR_FROM_DEVICE)
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync {
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync Assert(cbTransfer <= s->cbTotalTransfer);
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync /* Reply with the same amount of data as the real drive. */
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync s->cbTotalTransfer = cbTransfer;
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync /* The initial buffer end value has been set up based on the total
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync * transfer size. But the I/O buffer size limits what can actually be
49a6b09abb20015b0af3e618a1f92b7e26785e90vboxsync * done in one transfer, so set the actual value of the buffer end. */
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync s->cbElementaryTransfer = cbTransfer;
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync if (s->aATAPICmd[0] == SCSI_INQUIRY)
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync {
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync /* Make sure that the real drive cannot be identified.
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync * Motivation: changing the VM configuration should be as
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync * invisible as possible to the guest. */
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync Log3(("ATAPI PT inquiry data before (%d): %.*Rhxs\n", cbTransfer, cbTransfer, s->CTX_SUFF(pbIOBuffer)));
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync ataSCSIPadStr(s->CTX_SUFF(pbIOBuffer) + 8, "VBOX", 8);
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync ataSCSIPadStr(s->CTX_SUFF(pbIOBuffer) + 16, "CD-ROM", 16);
88e56f700a3b8dfdf1646f96320f335e22339caavboxsync ataSCSIPadStr(s->CTX_SUFF(pbIOBuffer) + 32, "1.0", 4);
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync }
0c94a8282c9042b02f022302a3d987746140eab9vboxsync if (cbTransfer)
49a6b09abb20015b0af3e618a1f92b7e26785e90vboxsync Log3(("ATAPI PT data read (%d): %.*Rhxs\n", cbTransfer, cbTransfer, s->CTX_SUFF(pbIOBuffer)));
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync }
29099c2d04b11e614f1fa399fab9e9162f2788b9vboxsync s->iSourceSink = ATAFN_SS_NULL;
29099c2d04b11e614f1fa399fab9e9162f2788b9vboxsync atapiCmdOK(s);
49a6b09abb20015b0af3e618a1f92b7e26785e90vboxsync }
29099c2d04b11e614f1fa399fab9e9162f2788b9vboxsync else
49a6b09abb20015b0af3e618a1f92b7e26785e90vboxsync {
49a6b09abb20015b0af3e618a1f92b7e26785e90vboxsync if (s->cErrors < MAX_LOG_REL_ERRORS)
49a6b09abb20015b0af3e618a1f92b7e26785e90vboxsync {
49a6b09abb20015b0af3e618a1f92b7e26785e90vboxsync uint8_t u8Cmd = s->aATAPICmd[0];
49a6b09abb20015b0af3e618a1f92b7e26785e90vboxsync do
49a6b09abb20015b0af3e618a1f92b7e26785e90vboxsync {
49a6b09abb20015b0af3e618a1f92b7e26785e90vboxsync /* don't log superflous errors */
88e56f700a3b8dfdf1646f96320f335e22339caavboxsync if ( rc == VERR_DEV_IO_ERROR
49a6b09abb20015b0af3e618a1f92b7e26785e90vboxsync && ( u8Cmd == SCSI_TEST_UNIT_READY
88e56f700a3b8dfdf1646f96320f335e22339caavboxsync || u8Cmd == SCSI_READ_CAPACITY
49a6b09abb20015b0af3e618a1f92b7e26785e90vboxsync || u8Cmd == SCSI_READ_DVD_STRUCTURE
49a6b09abb20015b0af3e618a1f92b7e26785e90vboxsync || u8Cmd == SCSI_READ_TOC_PMA_ATIP))
49a6b09abb20015b0af3e618a1f92b7e26785e90vboxsync break;
49a6b09abb20015b0af3e618a1f92b7e26785e90vboxsync s->cErrors++;
49a6b09abb20015b0af3e618a1f92b7e26785e90vboxsync LogRel(("PIIX3 ATA: LUN#%d: CD-ROM passthrough cmd=%#04x sense=%d ASC=%#02x ASCQ=%#02x %Rrc\n",
49a6b09abb20015b0af3e618a1f92b7e26785e90vboxsync s->iLUN, u8Cmd, abATAPISense[2] & 0x0f, abATAPISense[12], abATAPISense[13], rc));
88e56f700a3b8dfdf1646f96320f335e22339caavboxsync } while (0);
88e56f700a3b8dfdf1646f96320f335e22339caavboxsync }
88e56f700a3b8dfdf1646f96320f335e22339caavboxsync atapiCmdError(s, abATAPISense, sizeof(abATAPISense));
88e56f700a3b8dfdf1646f96320f335e22339caavboxsync }
49a6b09abb20015b0af3e618a1f92b7e26785e90vboxsync return false;
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync}
49a6b09abb20015b0af3e618a1f92b7e26785e90vboxsync
88e56f700a3b8dfdf1646f96320f335e22339caavboxsync
88e56f700a3b8dfdf1646f96320f335e22339caavboxsyncstatic bool atapiReadSectors(ATADevState *s, uint32_t iATAPILBA, uint32_t cSectors, uint32_t cbSector)
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync{
49a6b09abb20015b0af3e618a1f92b7e26785e90vboxsync Assert(cSectors > 0);
88e56f700a3b8dfdf1646f96320f335e22339caavboxsync s->iATAPILBA = iATAPILBA;
88e56f700a3b8dfdf1646f96320f335e22339caavboxsync s->cbATAPISector = cbSector;
49a6b09abb20015b0af3e618a1f92b7e26785e90vboxsync ataStartTransfer(s, cSectors * cbSector, PDMBLOCKTXDIR_FROM_DEVICE, ATAFN_BT_ATAPI_CMD, ATAFN_SS_ATAPI_READ, true);
88e56f700a3b8dfdf1646f96320f335e22339caavboxsync return false;
88e56f700a3b8dfdf1646f96320f335e22339caavboxsync}
49a6b09abb20015b0af3e618a1f92b7e26785e90vboxsync
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsyncstatic bool atapiReadCapacitySS(ATADevState *s)
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync{
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync uint8_t *pbBuf = s->CTX_SUFF(pbIOBuffer);
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync Assert(s->uTxDir == PDMBLOCKTXDIR_FROM_DEVICE);
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync Assert(s->cbElementaryTransfer <= 8);
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync ataH2BE_U32(pbBuf, s->cTotalSectors - 1);
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync ataH2BE_U32(pbBuf + 4, 2048);
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync s->iSourceSink = ATAFN_SS_NULL;
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync atapiCmdOK(s);
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync return false;
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync}
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsyncstatic bool atapiReadDiscInformationSS(ATADevState *s)
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync{
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync uint8_t *pbBuf = s->CTX_SUFF(pbIOBuffer);
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync Assert(s->uTxDir == PDMBLOCKTXDIR_FROM_DEVICE);
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync Assert(s->cbElementaryTransfer <= 34);
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync memset(pbBuf, '\0', 34);
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync ataH2BE_U16(pbBuf, 32);
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync pbBuf[2] = (0 << 4) | (3 << 2) | (2 << 0); /* not erasable, complete session, complete disc */
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync pbBuf[3] = 1; /* number of first track */
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync pbBuf[4] = 1; /* number of sessions (LSB) */
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync pbBuf[5] = 1; /* first track number in last session (LSB) */
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync pbBuf[6] = 1; /* last track number in last session (LSB) */
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync pbBuf[7] = (0 << 7) | (0 << 6) | (1 << 5) | (0 << 2) | (0 << 0); /* disc id not valid, disc bar code not valid, unrestricted use, not dirty, not RW medium */
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync pbBuf[8] = 0; /* disc type = CD-ROM */
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync pbBuf[9] = 0; /* number of sessions (MSB) */
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync pbBuf[10] = 0; /* number of sessions (MSB) */
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync pbBuf[11] = 0; /* number of sessions (MSB) */
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync ataH2BE_U32(pbBuf + 16, 0x00ffffff); /* last session lead-in start time is not available */
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync ataH2BE_U32(pbBuf + 20, 0x00ffffff); /* last possible start time for lead-out is not available */
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync s->iSourceSink = ATAFN_SS_NULL;
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync atapiCmdOK(s);
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync return false;
5c4d7e2aae42bbf39793dfa686925f076a56b4d5vboxsync}
5c4d7e2aae42bbf39793dfa686925f076a56b4d5vboxsync
5c4d7e2aae42bbf39793dfa686925f076a56b4d5vboxsync
38745c55f37c31ba8b78cc728d2f08ea6eec38d6vboxsyncstatic bool atapiReadTrackInformationSS(ATADevState *s)
5c4d7e2aae42bbf39793dfa686925f076a56b4d5vboxsync{
5c4d7e2aae42bbf39793dfa686925f076a56b4d5vboxsync uint8_t *pbBuf = s->CTX_SUFF(pbIOBuffer);
5c4d7e2aae42bbf39793dfa686925f076a56b4d5vboxsync
5c4d7e2aae42bbf39793dfa686925f076a56b4d5vboxsync Assert(s->uTxDir == PDMBLOCKTXDIR_FROM_DEVICE);
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync Assert(s->cbElementaryTransfer <= 36);
5c4d7e2aae42bbf39793dfa686925f076a56b4d5vboxsync /* Accept address/number type of 1 only, and only track 1 exists. */
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync if ((s->aATAPICmd[1] & 0x03) != 1 || ataBE2H_U32(&s->aATAPICmd[2]) != 1)
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync {
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync atapiCmdErrorSimple(s, SCSI_SENSE_ILLEGAL_REQUEST, SCSI_ASC_INV_FIELD_IN_CMD_PACKET);
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync return false;
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync }
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync memset(pbBuf, '\0', 36);
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync ataH2BE_U16(pbBuf, 34);
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync pbBuf[2] = 1; /* track number (LSB) */
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync pbBuf[3] = 1; /* session number (LSB) */
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync pbBuf[5] = (0 << 5) | (0 << 4) | (4 << 0); /* not damaged, primary copy, data track */
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync pbBuf[6] = (0 << 7) | (0 << 6) | (0 << 5) | (0 << 6) | (1 << 0); /* not reserved track, not blank, not packet writing, not fixed packet, data mode 1 */
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync pbBuf[7] = (0 << 1) | (0 << 0); /* last recorded address not valid, next recordable address not valid */
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync ataH2BE_U32(pbBuf + 8, 0); /* track start address is 0 */
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync ataH2BE_U32(pbBuf + 24, s->cTotalSectors); /* track size */
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync pbBuf[32] = 0; /* track number (MSB) */
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync pbBuf[33] = 0; /* session number (MSB) */
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync s->iSourceSink = ATAFN_SS_NULL;
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync atapiCmdOK(s);
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync return false;
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync}
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync
19320d55d1417c39b3b5673a53aaa5ef177242c8vboxsync
19320d55d1417c39b3b5673a53aaa5ef177242c8vboxsyncstatic bool atapiGetConfigurationSS(ATADevState *s)
19320d55d1417c39b3b5673a53aaa5ef177242c8vboxsync{
19320d55d1417c39b3b5673a53aaa5ef177242c8vboxsync uint8_t *pbBuf = s->CTX_SUFF(pbIOBuffer);
19320d55d1417c39b3b5673a53aaa5ef177242c8vboxsync uint16_t u16Sfn = ataBE2H_U16(&s->aATAPICmd[2]);
19320d55d1417c39b3b5673a53aaa5ef177242c8vboxsync
19320d55d1417c39b3b5673a53aaa5ef177242c8vboxsync Assert(s->uTxDir == PDMBLOCKTXDIR_FROM_DEVICE);
19320d55d1417c39b3b5673a53aaa5ef177242c8vboxsync Assert(s->cbElementaryTransfer <= 32);
19320d55d1417c39b3b5673a53aaa5ef177242c8vboxsync /* Accept valid request types only, and only starting feature 0. */
19320d55d1417c39b3b5673a53aaa5ef177242c8vboxsync if ((s->aATAPICmd[1] & 0x03) == 3 || u16Sfn != 0)
19320d55d1417c39b3b5673a53aaa5ef177242c8vboxsync {
19320d55d1417c39b3b5673a53aaa5ef177242c8vboxsync atapiCmdErrorSimple(s, SCSI_SENSE_ILLEGAL_REQUEST, SCSI_ASC_INV_FIELD_IN_CMD_PACKET);
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync return false;
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync }
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync memset(pbBuf, '\0', 32);
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync ataH2BE_U32(pbBuf, 16);
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync /** @todo implement switching between CD-ROM and DVD-ROM profile (the only
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync * way to differentiate them right now is based on the image size). Also
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync * implement signalling "no current profile" if no medium is loaded. */
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync ataH2BE_U16(pbBuf + 6, 0x08); /* current profile: read-only CD */
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync
81614fc60e096e714022d10d38b70a36b9b21d48vboxsync ataH2BE_U16(pbBuf + 8, 0); /* feature 0: list of profiles supported */
44372afb953dc9f1f1ec71943f5f561a607c0307vboxsync pbBuf[10] = (0 << 2) | (1 << 1) | (1 || 0); /* version 0, persistent, current */
44372afb953dc9f1f1ec71943f5f561a607c0307vboxsync pbBuf[11] = 8; /* additional bytes for profiles */
81614fc60e096e714022d10d38b70a36b9b21d48vboxsync /* The MMC-3 spec says that DVD-ROM read capability should be reported
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync * before CD-ROM read capability. */
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync ataH2BE_U16(pbBuf + 12, 0x10); /* profile: read-only DVD */
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync pbBuf[14] = (0 << 0); /* NOT current profile */
29099c2d04b11e614f1fa399fab9e9162f2788b9vboxsync ataH2BE_U16(pbBuf + 16, 0x08); /* profile: read only CD */
29099c2d04b11e614f1fa399fab9e9162f2788b9vboxsync pbBuf[18] = (1 << 0); /* current profile */
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync /* Other profiles we might want to add in the future: 0x40 (BD-ROM) and 0x50 (HDDVD-ROM) */
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync s->iSourceSink = ATAFN_SS_NULL;
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync atapiCmdOK(s);
29099c2d04b11e614f1fa399fab9e9162f2788b9vboxsync return false;
29099c2d04b11e614f1fa399fab9e9162f2788b9vboxsync}
29099c2d04b11e614f1fa399fab9e9162f2788b9vboxsync
29099c2d04b11e614f1fa399fab9e9162f2788b9vboxsync
29099c2d04b11e614f1fa399fab9e9162f2788b9vboxsyncstatic bool atapiGetEventStatusNotificationSS(ATADevState *s)
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync{
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync uint8_t *pbBuf = s->CTX_SUFF(pbIOBuffer);
29099c2d04b11e614f1fa399fab9e9162f2788b9vboxsync
29099c2d04b11e614f1fa399fab9e9162f2788b9vboxsync Assert(s->uTxDir == PDMBLOCKTXDIR_FROM_DEVICE);
29099c2d04b11e614f1fa399fab9e9162f2788b9vboxsync Assert(s->cbElementaryTransfer <= 8);
29099c2d04b11e614f1fa399fab9e9162f2788b9vboxsync
29099c2d04b11e614f1fa399fab9e9162f2788b9vboxsync if (!(s->aATAPICmd[1] & 1))
81614fc60e096e714022d10d38b70a36b9b21d48vboxsync {
44372afb953dc9f1f1ec71943f5f561a607c0307vboxsync /* no asynchronous operation supported */
81614fc60e096e714022d10d38b70a36b9b21d48vboxsync atapiCmdErrorSimple(s, SCSI_SENSE_ILLEGAL_REQUEST, SCSI_ASC_INV_FIELD_IN_CMD_PACKET);
81614fc60e096e714022d10d38b70a36b9b21d48vboxsync return false;
82e3a4017d20f44c30ff909e6b825ff78139cbbbvboxsync }
29099c2d04b11e614f1fa399fab9e9162f2788b9vboxsync
29099c2d04b11e614f1fa399fab9e9162f2788b9vboxsync uint32_t OldStatus, NewStatus;
29099c2d04b11e614f1fa399fab9e9162f2788b9vboxsync do
29099c2d04b11e614f1fa399fab9e9162f2788b9vboxsync {
19320d55d1417c39b3b5673a53aaa5ef177242c8vboxsync OldStatus = ASMAtomicReadU32(&s->MediaEventStatus);
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync NewStatus = ATA_EVENT_STATUS_UNCHANGED;
29099c2d04b11e614f1fa399fab9e9162f2788b9vboxsync switch (OldStatus)
19320d55d1417c39b3b5673a53aaa5ef177242c8vboxsync {
19320d55d1417c39b3b5673a53aaa5ef177242c8vboxsync case ATA_EVENT_STATUS_MEDIA_NEW:
19320d55d1417c39b3b5673a53aaa5ef177242c8vboxsync /* mount */
29099c2d04b11e614f1fa399fab9e9162f2788b9vboxsync ataH2BE_U16(pbBuf + 0, 6);
29099c2d04b11e614f1fa399fab9e9162f2788b9vboxsync pbBuf[2] = 0x04;
29099c2d04b11e614f1fa399fab9e9162f2788b9vboxsync pbBuf[3] = 0x5e;
29099c2d04b11e614f1fa399fab9e9162f2788b9vboxsync pbBuf[4] = 0x02;
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync pbBuf[5] = 0x02;
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync pbBuf[6] = 0x00;
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync pbBuf[7] = 0x00;
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync break;
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync
19320d55d1417c39b3b5673a53aaa5ef177242c8vboxsync case ATA_EVENT_STATUS_MEDIA_CHANGED:
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync case ATA_EVENT_STATUS_MEDIA_REMOVED:
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync /* umount */
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync ataH2BE_U16(pbBuf + 0, 6);
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync pbBuf[2] = 0x04;
19320d55d1417c39b3b5673a53aaa5ef177242c8vboxsync pbBuf[3] = 0x5e;
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync pbBuf[4] = 0x03;
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync pbBuf[5] = 0x00;
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync pbBuf[6] = 0x00;
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync pbBuf[7] = 0x00;
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync if (OldStatus == ATA_EVENT_STATUS_MEDIA_CHANGED)
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync NewStatus = ATA_EVENT_STATUS_MEDIA_NEW;
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync break;
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync case ATA_EVENT_STATUS_UNCHANGED:
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync default:
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync ataH2BE_U16(pbBuf + 0, 6);
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync pbBuf[2] = 0x01;
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync pbBuf[3] = 0x5e;
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync pbBuf[4] = 0x00;
29099c2d04b11e614f1fa399fab9e9162f2788b9vboxsync pbBuf[5] = 0x00;
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync pbBuf[6] = 0x00;
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync pbBuf[7] = 0x00;
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync break;
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync }
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync } while (!ASMAtomicCmpXchgU32(&s->MediaEventStatus, NewStatus, OldStatus));
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync s->iSourceSink = ATAFN_SS_NULL;
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync atapiCmdOK(s);
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync return false;
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync}
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsyncstatic bool atapiInquirySS(ATADevState *s)
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync{
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync uint8_t *pbBuf = s->CTX_SUFF(pbIOBuffer);
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync Assert(s->uTxDir == PDMBLOCKTXDIR_FROM_DEVICE);
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync Assert(s->cbElementaryTransfer <= 36);
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync pbBuf[0] = 0x05; /* CD-ROM */
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync pbBuf[1] = 0x80; /* removable */
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync#if 1/*ndef VBOX*/ /** @todo implement MESN + AENC. (async notification on removal and stuff.) */
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync pbBuf[2] = 0x00; /* ISO */
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync pbBuf[3] = 0x21; /* ATAPI-2 (XXX: put ATAPI-4 ?) */
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync#else
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync pbBuf[2] = 0x00; /* ISO */
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync pbBuf[3] = 0x91; /* format 1, MESN=1, AENC=9 ??? */
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync#endif
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync pbBuf[4] = 31; /* additional length */
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync pbBuf[5] = 0; /* reserved */
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync pbBuf[6] = 0; /* reserved */
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync pbBuf[7] = 0; /* reserved */
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync ataSCSIPadStr(pbBuf + 8, "VBOX", 8);
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync ataSCSIPadStr(pbBuf + 16, "CD-ROM", 16);
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync ataSCSIPadStr(pbBuf + 32, "1.0", 4);
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync s->iSourceSink = ATAFN_SS_NULL;
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync atapiCmdOK(s);
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync return false;
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync}
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync
29099c2d04b11e614f1fa399fab9e9162f2788b9vboxsync
29099c2d04b11e614f1fa399fab9e9162f2788b9vboxsyncstatic bool atapiModeSenseErrorRecoverySS(ATADevState *s)
29099c2d04b11e614f1fa399fab9e9162f2788b9vboxsync{
29099c2d04b11e614f1fa399fab9e9162f2788b9vboxsync uint8_t *pbBuf = s->CTX_SUFF(pbIOBuffer);
29099c2d04b11e614f1fa399fab9e9162f2788b9vboxsync
29099c2d04b11e614f1fa399fab9e9162f2788b9vboxsync Assert(s->uTxDir == PDMBLOCKTXDIR_FROM_DEVICE);
29099c2d04b11e614f1fa399fab9e9162f2788b9vboxsync Assert(s->cbElementaryTransfer <= 16);
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync ataH2BE_U16(&pbBuf[0], 16 + 6);
29099c2d04b11e614f1fa399fab9e9162f2788b9vboxsync pbBuf[2] = 0x70;
29099c2d04b11e614f1fa399fab9e9162f2788b9vboxsync pbBuf[3] = 0;
29099c2d04b11e614f1fa399fab9e9162f2788b9vboxsync pbBuf[4] = 0;
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync pbBuf[5] = 0;
29099c2d04b11e614f1fa399fab9e9162f2788b9vboxsync pbBuf[6] = 0;
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync pbBuf[7] = 0;
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync pbBuf[8] = 0x01;
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync pbBuf[9] = 0x06;
44372afb953dc9f1f1ec71943f5f561a607c0307vboxsync pbBuf[10] = 0x00;
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync pbBuf[11] = 0x05;
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync pbBuf[12] = 0x00;
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync pbBuf[13] = 0x00;
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync pbBuf[14] = 0x00;
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync pbBuf[15] = 0x00;
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync s->iSourceSink = ATAFN_SS_NULL;
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync atapiCmdOK(s);
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync return false;
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync}
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsyncstatic bool atapiModeSenseCDStatusSS(ATADevState *s)
29099c2d04b11e614f1fa399fab9e9162f2788b9vboxsync{
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync uint8_t *pbBuf = s->CTX_SUFF(pbIOBuffer);
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync Assert(s->uTxDir == PDMBLOCKTXDIR_FROM_DEVICE);
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync Assert(s->cbElementaryTransfer <= 40);
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync ataH2BE_U16(&pbBuf[0], 38);
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync pbBuf[2] = 0x70;
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync pbBuf[3] = 0;
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync pbBuf[4] = 0;
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync pbBuf[5] = 0;
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync pbBuf[6] = 0;
9c9db71d639cf066ed41d49629d46d48bff4be2fvboxsync pbBuf[7] = 0;
81614fc60e096e714022d10d38b70a36b9b21d48vboxsync
81614fc60e096e714022d10d38b70a36b9b21d48vboxsync pbBuf[8] = 0x2a;
81614fc60e096e714022d10d38b70a36b9b21d48vboxsync pbBuf[9] = 30; /* page length */
81614fc60e096e714022d10d38b70a36b9b21d48vboxsync pbBuf[10] = 0x08; /* DVD-ROM read support */
44372afb953dc9f1f1ec71943f5f561a607c0307vboxsync pbBuf[11] = 0x00; /* no write support */
44372afb953dc9f1f1ec71943f5f561a607c0307vboxsync /* The following claims we support audio play. This is obviously false,
44372afb953dc9f1f1ec71943f5f561a607c0307vboxsync * but the Linux generic CDROM support makes many features depend on this
44372afb953dc9f1f1ec71943f5f561a607c0307vboxsync * capability. If it's not set, this causes many things to be disabled. */
44372afb953dc9f1f1ec71943f5f561a607c0307vboxsync pbBuf[12] = 0x71; /* multisession support, mode 2 form 1/2 support, audio play */
81614fc60e096e714022d10d38b70a36b9b21d48vboxsync pbBuf[13] = 0x00; /* no subchannel reads supported */
81614fc60e096e714022d10d38b70a36b9b21d48vboxsync pbBuf[14] = (1 << 0) | (1 << 3) | (1 << 5); /* lock supported, eject supported, tray type loading mechanism */
81614fc60e096e714022d10d38b70a36b9b21d48vboxsync if (s->pDrvMount->pfnIsLocked(s->pDrvMount))
81614fc60e096e714022d10d38b70a36b9b21d48vboxsync pbBuf[14] |= 1 << 1; /* report lock state */
81614fc60e096e714022d10d38b70a36b9b21d48vboxsync pbBuf[15] = 0; /* no subchannel reads supported, no separate audio volume control, no changer etc. */
44372afb953dc9f1f1ec71943f5f561a607c0307vboxsync ataH2BE_U16(&pbBuf[16], 5632); /* (obsolete) claim 32x speed support */
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync ataH2BE_U16(&pbBuf[18], 2); /* number of audio volume levels */
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync ataH2BE_U16(&pbBuf[20], s->cbIOBuffer / _1K); /* buffer size supported in Kbyte */
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync ataH2BE_U16(&pbBuf[22], 5632); /* (obsolete) current read speed 32x */
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync pbBuf[24] = 0; /* reserved */
29099c2d04b11e614f1fa399fab9e9162f2788b9vboxsync pbBuf[25] = 0; /* reserved for digital audio (see idx 15) */
29099c2d04b11e614f1fa399fab9e9162f2788b9vboxsync ataH2BE_U16(&pbBuf[26], 0); /* (obsolete) maximum write speed */
29099c2d04b11e614f1fa399fab9e9162f2788b9vboxsync ataH2BE_U16(&pbBuf[28], 0); /* (obsolete) current write speed */
29099c2d04b11e614f1fa399fab9e9162f2788b9vboxsync ataH2BE_U16(&pbBuf[30], 0); /* copy management revision supported 0=no CSS */
29099c2d04b11e614f1fa399fab9e9162f2788b9vboxsync pbBuf[32] = 0; /* reserved */
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync pbBuf[33] = 0; /* reserved */
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync pbBuf[34] = 0; /* reserved */
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync pbBuf[35] = 1; /* rotation control CAV */
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync ataH2BE_U16(&pbBuf[36], 0); /* current write speed */
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync ataH2BE_U16(&pbBuf[38], 0); /* number of write speed performance descriptors */
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync s->iSourceSink = ATAFN_SS_NULL;
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync atapiCmdOK(s);
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync return false;
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync}
29099c2d04b11e614f1fa399fab9e9162f2788b9vboxsync
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync
29099c2d04b11e614f1fa399fab9e9162f2788b9vboxsyncstatic bool atapiRequestSenseSS(ATADevState *s)
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync{
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync uint8_t *pbBuf = s->CTX_SUFF(pbIOBuffer);
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync Assert(s->uTxDir == PDMBLOCKTXDIR_FROM_DEVICE);
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync memset(pbBuf, '\0', s->cbElementaryTransfer);
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync memcpy(pbBuf, s->abATAPISense, RT_MIN(s->cbElementaryTransfer, sizeof(s->abATAPISense)));
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync s->iSourceSink = ATAFN_SS_NULL;
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync atapiCmdOK(s);
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync return false;
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync}
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsyncstatic bool atapiMechanismStatusSS(ATADevState *s)
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync{
0c94a8282c9042b02f022302a3d987746140eab9vboxsync uint8_t *pbBuf = s->CTX_SUFF(pbIOBuffer);
0c94a8282c9042b02f022302a3d987746140eab9vboxsync
0c94a8282c9042b02f022302a3d987746140eab9vboxsync Assert(s->uTxDir == PDMBLOCKTXDIR_FROM_DEVICE);
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync Assert(s->cbElementaryTransfer <= 8);
0c94a8282c9042b02f022302a3d987746140eab9vboxsync ataH2BE_U16(pbBuf, 0);
0c94a8282c9042b02f022302a3d987746140eab9vboxsync /* no current LBA */
0c94a8282c9042b02f022302a3d987746140eab9vboxsync pbBuf[2] = 0;
0c94a8282c9042b02f022302a3d987746140eab9vboxsync pbBuf[3] = 0;
0c94a8282c9042b02f022302a3d987746140eab9vboxsync pbBuf[4] = 0;
0c94a8282c9042b02f022302a3d987746140eab9vboxsync pbBuf[5] = 1;
0c94a8282c9042b02f022302a3d987746140eab9vboxsync ataH2BE_U16(pbBuf + 6, 0);
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync s->iSourceSink = ATAFN_SS_NULL;
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync atapiCmdOK(s);
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync return false;
e250515922582e0410c9bcb6d24b0f17bef083a0vboxsync}
e250515922582e0410c9bcb6d24b0f17bef083a0vboxsync
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsyncstatic bool atapiReadTOCNormalSS(ATADevState *s)
0c69348b58bb8eabb1bea8867ee932b667bd0d34vboxsync{
uint8_t *pbBuf = s->CTX_SUFF(pbIOBuffer), *q, iStartTrack;
bool fMSF;
uint32_t cbSize;
Assert(s->uTxDir == PDMBLOCKTXDIR_FROM_DEVICE);
fMSF = (s->aATAPICmd[1] >> 1) & 1;
iStartTrack = s->aATAPICmd[6];
if (iStartTrack > 1 && iStartTrack != 0xaa)
{
atapiCmdErrorSimple(s, SCSI_SENSE_ILLEGAL_REQUEST, SCSI_ASC_INV_FIELD_IN_CMD_PACKET);
return false;
}
q = pbBuf + 2;
*q++ = 1; /* first session */
*q++ = 1; /* last session */
if (iStartTrack <= 1)
{
*q++ = 0; /* reserved */
*q++ = 0x14; /* ADR, control */
*q++ = 1; /* track number */
*q++ = 0; /* reserved */
if (fMSF)
{
*q++ = 0; /* reserved */
ataLBA2MSF(q, 0);
q += 3;
}
else
{
/* sector 0 */
ataH2BE_U32(q, 0);
q += 4;
}
}
/* lead out track */
*q++ = 0; /* reserved */
*q++ = 0x14; /* ADR, control */
*q++ = 0xaa; /* track number */
*q++ = 0; /* reserved */
if (fMSF)
{
*q++ = 0; /* reserved */
ataLBA2MSF(q, s->cTotalSectors);
q += 3;
}
else
{
ataH2BE_U32(q, s->cTotalSectors);
q += 4;
}
cbSize = q - pbBuf;
ataH2BE_U16(pbBuf, cbSize - 2);
if (cbSize < s->cbTotalTransfer)
s->cbTotalTransfer = cbSize;
s->iSourceSink = ATAFN_SS_NULL;
atapiCmdOK(s);
return false;
}
static bool atapiReadTOCMultiSS(ATADevState *s)
{
uint8_t *pbBuf = s->CTX_SUFF(pbIOBuffer);
bool fMSF;
Assert(s->uTxDir == PDMBLOCKTXDIR_FROM_DEVICE);
Assert(s->cbElementaryTransfer <= 12);
fMSF = (s->aATAPICmd[1] >> 1) & 1;
/* multi session: only a single session defined */
/** @todo double-check this stuff against what a real drive says for a CD-ROM (not a CD-R) with only a single data session. Maybe solve the problem with "cdrdao read-toc" not being able to figure out whether numbers are in BCD or hex. */
memset(pbBuf, 0, 12);
pbBuf[1] = 0x0a;
pbBuf[2] = 0x01;
pbBuf[3] = 0x01;
pbBuf[5] = 0x14; /* ADR, control */
pbBuf[6] = 1; /* first track in last complete session */
if (fMSF)
{
pbBuf[8] = 0; /* reserved */
ataLBA2MSF(&pbBuf[9], 0);
}
else
{
/* sector 0 */
ataH2BE_U32(pbBuf + 8, 0);
}
s->iSourceSink = ATAFN_SS_NULL;
atapiCmdOK(s);
return false;
}
static bool atapiReadTOCRawSS(ATADevState *s)
{
uint8_t *pbBuf = s->CTX_SUFF(pbIOBuffer), *q, iStartTrack;
bool fMSF;
uint32_t cbSize;
Assert(s->uTxDir == PDMBLOCKTXDIR_FROM_DEVICE);
fMSF = (s->aATAPICmd[1] >> 1) & 1;
iStartTrack = s->aATAPICmd[6];
q = pbBuf + 2;
*q++ = 1; /* first session */
*q++ = 1; /* last session */
*q++ = 1; /* session number */
*q++ = 0x14; /* data track */
*q++ = 0; /* track number */
*q++ = 0xa0; /* first track in program area */
*q++ = 0; /* min */
*q++ = 0; /* sec */
*q++ = 0; /* frame */
*q++ = 0;
*q++ = 1; /* first track */
*q++ = 0x00; /* disk type CD-DA or CD data */
*q++ = 0;
*q++ = 1; /* session number */
*q++ = 0x14; /* data track */
*q++ = 0; /* track number */
*q++ = 0xa1; /* last track in program area */
*q++ = 0; /* min */
*q++ = 0; /* sec */
*q++ = 0; /* frame */
*q++ = 0;
*q++ = 1; /* last track */
*q++ = 0;
*q++ = 0;
*q++ = 1; /* session number */
*q++ = 0x14; /* data track */
*q++ = 0; /* track number */
*q++ = 0xa2; /* lead-out */
*q++ = 0; /* min */
*q++ = 0; /* sec */
*q++ = 0; /* frame */
if (fMSF)
{
*q++ = 0; /* reserved */
ataLBA2MSF(q, s->cTotalSectors);
q += 3;
}
else
{
ataH2BE_U32(q, s->cTotalSectors);
q += 4;
}
*q++ = 1; /* session number */
*q++ = 0x14; /* ADR, control */
*q++ = 0; /* track number */
*q++ = 1; /* point */
*q++ = 0; /* min */
*q++ = 0; /* sec */
*q++ = 0; /* frame */
if (fMSF)
{
*q++ = 0; /* reserved */
ataLBA2MSF(q, 0);
q += 3;
}
else
{
/* sector 0 */
ataH2BE_U32(q, 0);
q += 4;
}
cbSize = q - pbBuf;
ataH2BE_U16(pbBuf, cbSize - 2);
if (cbSize < s->cbTotalTransfer)
s->cbTotalTransfer = cbSize;
s->iSourceSink = ATAFN_SS_NULL;
atapiCmdOK(s);
return false;
}
static void atapiParseCmdVirtualATAPI(ATADevState *s)
{
const uint8_t *pbPacket;
uint8_t *pbBuf;
uint32_t cbMax;
pbPacket = s->aATAPICmd;
pbBuf = s->CTX_SUFF(pbIOBuffer);
switch (pbPacket[0])
{
case SCSI_TEST_UNIT_READY:
if (s->cNotifiedMediaChange > 0)
{
if (s->cNotifiedMediaChange-- > 2)
atapiCmdErrorSimple(s, SCSI_SENSE_NOT_READY, SCSI_ASC_MEDIUM_NOT_PRESENT);
else
atapiCmdErrorSimple(s, SCSI_SENSE_UNIT_ATTENTION, SCSI_ASC_MEDIUM_MAY_HAVE_CHANGED); /* media changed */
}
else if (s->pDrvMount->pfnIsMounted(s->pDrvMount))
atapiCmdOK(s);
else
atapiCmdErrorSimple(s, SCSI_SENSE_NOT_READY, SCSI_ASC_MEDIUM_NOT_PRESENT);
break;
case SCSI_GET_EVENT_STATUS_NOTIFICATION:
cbMax = ataBE2H_U16(pbPacket + 7);
ataStartTransfer(s, RT_MIN(cbMax, 8), PDMBLOCKTXDIR_FROM_DEVICE, ATAFN_BT_ATAPI_CMD, ATAFN_SS_ATAPI_GET_EVENT_STATUS_NOTIFICATION, true);
break;
case SCSI_MODE_SENSE_10:
{
uint8_t uPageControl, uPageCode;
cbMax = ataBE2H_U16(pbPacket + 7);
uPageControl = pbPacket[2] >> 6;
uPageCode = pbPacket[2] & 0x3f;
switch (uPageControl)
{
case SCSI_PAGECONTROL_CURRENT:
switch (uPageCode)
{
case SCSI_MODEPAGE_ERROR_RECOVERY:
ataStartTransfer(s, RT_MIN(cbMax, 16), PDMBLOCKTXDIR_FROM_DEVICE, ATAFN_BT_ATAPI_CMD, ATAFN_SS_ATAPI_MODE_SENSE_ERROR_RECOVERY, true);
break;
case SCSI_MODEPAGE_CD_STATUS:
ataStartTransfer(s, RT_MIN(cbMax, 40), PDMBLOCKTXDIR_FROM_DEVICE, ATAFN_BT_ATAPI_CMD, ATAFN_SS_ATAPI_MODE_SENSE_CD_STATUS, true);
break;
default:
goto error_cmd;
}
break;
case SCSI_PAGECONTROL_CHANGEABLE:
goto error_cmd;
case SCSI_PAGECONTROL_DEFAULT:
goto error_cmd;
default:
case SCSI_PAGECONTROL_SAVED:
atapiCmdErrorSimple(s, SCSI_SENSE_ILLEGAL_REQUEST, SCSI_ASC_SAVING_PARAMETERS_NOT_SUPPORTED);
break;
}
}
break;
case SCSI_REQUEST_SENSE:
cbMax = pbPacket[4];
ataStartTransfer(s, RT_MIN(cbMax, 18), PDMBLOCKTXDIR_FROM_DEVICE, ATAFN_BT_ATAPI_CMD, ATAFN_SS_ATAPI_REQUEST_SENSE, true);
break;
case SCSI_PREVENT_ALLOW_MEDIUM_REMOVAL:
if (s->pDrvMount->pfnIsMounted(s->pDrvMount))
{
if (pbPacket[4] & 1)
s->pDrvMount->pfnLock(s->pDrvMount);
else
s->pDrvMount->pfnUnlock(s->pDrvMount);
atapiCmdOK(s);
}
else
atapiCmdErrorSimple(s, SCSI_SENSE_NOT_READY, SCSI_ASC_MEDIUM_NOT_PRESENT);
break;
case SCSI_READ_10:
case SCSI_READ_12:
{
uint32_t cSectors, iATAPILBA;
if (s->cNotifiedMediaChange > 0)
{
s->cNotifiedMediaChange-- ;
atapiCmdErrorSimple(s, SCSI_SENSE_UNIT_ATTENTION, SCSI_ASC_MEDIUM_MAY_HAVE_CHANGED); /* media changed */
break;
}
else if (!s->pDrvMount->pfnIsMounted(s->pDrvMount))
{
atapiCmdErrorSimple(s, SCSI_SENSE_NOT_READY, SCSI_ASC_MEDIUM_NOT_PRESENT);
break;
}
if (pbPacket[0] == SCSI_READ_10)
cSectors = ataBE2H_U16(pbPacket + 7);
else
cSectors = ataBE2H_U32(pbPacket + 6);
iATAPILBA = ataBE2H_U32(pbPacket + 2);
if (cSectors == 0)
{
atapiCmdOK(s);
break;
}
if ((uint64_t)iATAPILBA + cSectors > s->cTotalSectors)
{
/* Rate limited logging, one log line per second. For
* guests that insist on reading from places outside the
* valid area this often generates too many release log
* entries otherwise. */
static uint64_t uLastLogTS = 0;
if (RTTimeMilliTS() >= uLastLogTS + 1000)
{
LogRel(("PIIX3 ATA: LUN#%d: CD-ROM block number %Ld invalid (READ)\n", s->iLUN, (uint64_t)iATAPILBA + cSectors));
uLastLogTS = RTTimeMilliTS();
}
atapiCmdErrorSimple(s, SCSI_SENSE_ILLEGAL_REQUEST, SCSI_ASC_LOGICAL_BLOCK_OOR);
break;
}
atapiReadSectors(s, iATAPILBA, cSectors, 2048);
}
break;
case SCSI_READ_CD:
{
uint32_t cSectors, iATAPILBA;
if (s->cNotifiedMediaChange > 0)
{
s->cNotifiedMediaChange-- ;
atapiCmdErrorSimple(s, SCSI_SENSE_UNIT_ATTENTION, SCSI_ASC_MEDIUM_MAY_HAVE_CHANGED); /* media changed */
break;
}
else if (!s->pDrvMount->pfnIsMounted(s->pDrvMount))
{
atapiCmdErrorSimple(s, SCSI_SENSE_NOT_READY, SCSI_ASC_MEDIUM_NOT_PRESENT);
break;
}
cSectors = (pbPacket[6] << 16) | (pbPacket[7] << 8) | pbPacket[8];
iATAPILBA = ataBE2H_U32(pbPacket + 2);
if (cSectors == 0)
{
atapiCmdOK(s);
break;
}
if ((uint64_t)iATAPILBA + cSectors > s->cTotalSectors)
{
/* Rate limited logging, one log line per second. For
* guests that insist on reading from places outside the
* valid area this often generates too many release log
* entries otherwise. */
static uint64_t uLastLogTS = 0;
if (RTTimeMilliTS() >= uLastLogTS + 1000)
{
LogRel(("PIIX3 ATA: LUN#%d: CD-ROM block number %Ld invalid (READ CD)\n", s->iLUN, (uint64_t)iATAPILBA + cSectors));
uLastLogTS = RTTimeMilliTS();
}
atapiCmdErrorSimple(s, SCSI_SENSE_ILLEGAL_REQUEST, SCSI_ASC_LOGICAL_BLOCK_OOR);
break;
}
switch (pbPacket[9] & 0xf8)
{
case 0x00:
/* nothing */
atapiCmdOK(s);
break;
case 0x10:
/* normal read */
atapiReadSectors(s, iATAPILBA, cSectors, 2048);
break;
case 0xf8:
/* read all data */
atapiReadSectors(s, iATAPILBA, cSectors, 2352);
break;
default:
LogRel(("PIIX3 ATA: LUN#%d: CD-ROM sector format not supported (%#x)\n", s->iLUN, pbPacket[9] & 0xf8));
atapiCmdErrorSimple(s, SCSI_SENSE_ILLEGAL_REQUEST, SCSI_ASC_INV_FIELD_IN_CMD_PACKET);
break;
}
}
break;
case SCSI_SEEK_10:
{
uint32_t iATAPILBA;
if (s->cNotifiedMediaChange > 0)
{
s->cNotifiedMediaChange-- ;
atapiCmdErrorSimple(s, SCSI_SENSE_UNIT_ATTENTION, SCSI_ASC_MEDIUM_MAY_HAVE_CHANGED); /* media changed */
break;
}
else if (!s->pDrvMount->pfnIsMounted(s->pDrvMount))
{
atapiCmdErrorSimple(s, SCSI_SENSE_NOT_READY, SCSI_ASC_MEDIUM_NOT_PRESENT);
break;
}
iATAPILBA = ataBE2H_U32(pbPacket + 2);
if (iATAPILBA > s->cTotalSectors)
{
/* Rate limited logging, one log line per second. For
* guests that insist on seeking to places outside the
* valid area this often generates too many release log
* entries otherwise. */
static uint64_t uLastLogTS = 0;
if (RTTimeMilliTS() >= uLastLogTS + 1000)
{
LogRel(("PIIX3 ATA: LUN#%d: CD-ROM block number %Ld invalid (SEEK)\n", s->iLUN, (uint64_t)iATAPILBA));
uLastLogTS = RTTimeMilliTS();
}
atapiCmdErrorSimple(s, SCSI_SENSE_ILLEGAL_REQUEST, SCSI_ASC_LOGICAL_BLOCK_OOR);
break;
}
atapiCmdOK(s);
ataSetStatus(s, ATA_STAT_SEEK); /* Linux expects this. */
}
break;
case SCSI_START_STOP_UNIT:
{
int rc = VINF_SUCCESS;
switch (pbPacket[4] & 3)
{
case 0: /* 00 - Stop motor */
case 1: /* 01 - Start motor */
break;
case 2: /* 10 - Eject media */
/* This must be done from EMT. */
{
PATACONTROLLER pCtl = ATADEVSTATE_2_CONTROLLER(s);
PPDMDEVINS pDevIns = ATADEVSTATE_2_DEVINS(s);
PVMREQ pReq;
PDMCritSectLeave(&pCtl->lock);
rc = VMR3ReqCall(PDMDevHlpGetVM(pDevIns), VMREQDEST_ANY, &pReq, RT_INDEFINITE_WAIT,
(PFNRT)s->pDrvMount->pfnUnmount, 2, s->pDrvMount, false);
AssertReleaseRC(rc);
VMR3ReqFree(pReq);
{
STAM_PROFILE_START(&pCtl->StatLockWait, a);
PDMCritSectEnter(&pCtl->lock, VINF_SUCCESS);
STAM_PROFILE_STOP(&pCtl->StatLockWait, a);
}
}
break;
case 3: /* 11 - Load media */
/** @todo rc = s->pDrvMount->pfnLoadMedia(s->pDrvMount) */
break;
}
if (RT_SUCCESS(rc))
atapiCmdOK(s);
else
atapiCmdErrorSimple(s, SCSI_SENSE_NOT_READY, SCSI_ASC_MEDIA_LOAD_OR_EJECT_FAILED);
}
break;
case SCSI_MECHANISM_STATUS:
{
cbMax = ataBE2H_U16(pbPacket + 8);
ataStartTransfer(s, RT_MIN(cbMax, 8), PDMBLOCKTXDIR_FROM_DEVICE, ATAFN_BT_ATAPI_CMD, ATAFN_SS_ATAPI_MECHANISM_STATUS, true);
}
break;
case SCSI_READ_TOC_PMA_ATIP:
{
uint8_t format;
if (s->cNotifiedMediaChange > 0)
{
s->cNotifiedMediaChange-- ;
atapiCmdErrorSimple(s, SCSI_SENSE_UNIT_ATTENTION, SCSI_ASC_MEDIUM_MAY_HAVE_CHANGED); /* media changed */
break;
}
else if (!s->pDrvMount->pfnIsMounted(s->pDrvMount))
{
atapiCmdErrorSimple(s, SCSI_SENSE_NOT_READY, SCSI_ASC_MEDIUM_NOT_PRESENT);
break;
}
cbMax = ataBE2H_U16(pbPacket + 7);
/* SCSI MMC-3 spec says format is at offset 2 (lower 4 bits),
* but Linux kernel uses offset 9 (topmost 2 bits). Hope that
* the other field is clear... */
format = (pbPacket[2] & 0xf) | (pbPacket[9] >> 6);
switch (format)
{
case 0:
ataStartTransfer(s, cbMax, PDMBLOCKTXDIR_FROM_DEVICE, ATAFN_BT_ATAPI_CMD, ATAFN_SS_ATAPI_READ_TOC_NORMAL, true);
break;
case 1:
ataStartTransfer(s, RT_MIN(cbMax, 12), PDMBLOCKTXDIR_FROM_DEVICE, ATAFN_BT_ATAPI_CMD, ATAFN_SS_ATAPI_READ_TOC_MULTI, true);
break;
case 2:
ataStartTransfer(s, cbMax, PDMBLOCKTXDIR_FROM_DEVICE, ATAFN_BT_ATAPI_CMD, ATAFN_SS_ATAPI_READ_TOC_RAW, true);
break;
default:
error_cmd:
atapiCmdErrorSimple(s, SCSI_SENSE_ILLEGAL_REQUEST, SCSI_ASC_INV_FIELD_IN_CMD_PACKET);
break;
}
}
break;
case SCSI_READ_CAPACITY:
if (s->cNotifiedMediaChange > 0)
{
s->cNotifiedMediaChange-- ;
atapiCmdErrorSimple(s, SCSI_SENSE_UNIT_ATTENTION, SCSI_ASC_MEDIUM_MAY_HAVE_CHANGED); /* media changed */
break;
}
else if (!s->pDrvMount->pfnIsMounted(s->pDrvMount))
{
atapiCmdErrorSimple(s, SCSI_SENSE_NOT_READY, SCSI_ASC_MEDIUM_NOT_PRESENT);
break;
}
ataStartTransfer(s, 8, PDMBLOCKTXDIR_FROM_DEVICE, ATAFN_BT_ATAPI_CMD, ATAFN_SS_ATAPI_READ_CAPACITY, true);
break;
case SCSI_READ_DISC_INFORMATION:
if (s->cNotifiedMediaChange > 0)
{
s->cNotifiedMediaChange-- ;
atapiCmdErrorSimple(s, SCSI_SENSE_UNIT_ATTENTION, SCSI_ASC_MEDIUM_MAY_HAVE_CHANGED); /* media changed */
break;
}
else if (!s->pDrvMount->pfnIsMounted(s->pDrvMount))
{
atapiCmdErrorSimple(s, SCSI_SENSE_NOT_READY, SCSI_ASC_MEDIUM_NOT_PRESENT);
break;
}
cbMax = ataBE2H_U16(pbPacket + 7);
ataStartTransfer(s, RT_MIN(cbMax, 34), PDMBLOCKTXDIR_FROM_DEVICE, ATAFN_BT_ATAPI_CMD, ATAFN_SS_ATAPI_READ_DISC_INFORMATION, true);
break;
case SCSI_READ_TRACK_INFORMATION:
if (s->cNotifiedMediaChange > 0)
{
s->cNotifiedMediaChange-- ;
atapiCmdErrorSimple(s, SCSI_SENSE_UNIT_ATTENTION, SCSI_ASC_MEDIUM_MAY_HAVE_CHANGED); /* media changed */
break;
}
else if (!s->pDrvMount->pfnIsMounted(s->pDrvMount))
{
atapiCmdErrorSimple(s, SCSI_SENSE_NOT_READY, SCSI_ASC_MEDIUM_NOT_PRESENT);
break;
}
cbMax = ataBE2H_U16(pbPacket + 7);
ataStartTransfer(s, RT_MIN(cbMax, 36), PDMBLOCKTXDIR_FROM_DEVICE, ATAFN_BT_ATAPI_CMD, ATAFN_SS_ATAPI_READ_TRACK_INFORMATION, true);
break;
case SCSI_GET_CONFIGURATION:
/* No media change stuff here, it can confuse Linux guests. */
cbMax = ataBE2H_U16(pbPacket + 7);
ataStartTransfer(s, RT_MIN(cbMax, 32), PDMBLOCKTXDIR_FROM_DEVICE, ATAFN_BT_ATAPI_CMD, ATAFN_SS_ATAPI_GET_CONFIGURATION, true);
break;
case SCSI_INQUIRY:
cbMax = ataBE2H_U16(pbPacket + 3);
ataStartTransfer(s, RT_MIN(cbMax, 36), PDMBLOCKTXDIR_FROM_DEVICE, ATAFN_BT_ATAPI_CMD, ATAFN_SS_ATAPI_INQUIRY, true);
break;
default:
atapiCmdErrorSimple(s, SCSI_SENSE_ILLEGAL_REQUEST, SCSI_ASC_ILLEGAL_OPCODE);
break;
}
}
/*
* Parse ATAPI commands, passing them directly to the CD/DVD drive.
*/
static void atapiParseCmdPassthrough(ATADevState *s)
{
const uint8_t *pbPacket;
uint8_t *pbBuf;
uint32_t cSectors, iATAPILBA;
uint32_t cbTransfer = 0;
PDMBLOCKTXDIR uTxDir = PDMBLOCKTXDIR_NONE;
pbPacket = s->aATAPICmd;
pbBuf = s->CTX_SUFF(pbIOBuffer);
switch (pbPacket[0])
{
case SCSI_BLANK:
goto sendcmd;
case SCSI_CLOSE_TRACK_SESSION:
goto sendcmd;
case SCSI_ERASE_10:
iATAPILBA = ataBE2H_U32(pbPacket + 2);
cbTransfer = ataBE2H_U16(pbPacket + 7);
Log2(("ATAPI PT: lba %d\n", iATAPILBA));
uTxDir = PDMBLOCKTXDIR_TO_DEVICE;
goto sendcmd;
case SCSI_FORMAT_UNIT:
cbTransfer = s->uATARegLCyl | (s->uATARegHCyl << 8); /* use ATAPI transfer length */
uTxDir = PDMBLOCKTXDIR_TO_DEVICE;
goto sendcmd;
case SCSI_GET_CONFIGURATION:
cbTransfer = ataBE2H_U16(pbPacket + 7);
uTxDir = PDMBLOCKTXDIR_FROM_DEVICE;
goto sendcmd;
case SCSI_GET_EVENT_STATUS_NOTIFICATION:
cbTransfer = ataBE2H_U16(pbPacket + 7);
if (ASMAtomicReadU32(&s->MediaEventStatus) != ATA_EVENT_STATUS_UNCHANGED)
{
ataStartTransfer(s, RT_MIN(cbTransfer, 8), PDMBLOCKTXDIR_FROM_DEVICE, ATAFN_BT_ATAPI_CMD, ATAFN_SS_ATAPI_GET_EVENT_STATUS_NOTIFICATION, true);
break;
}
uTxDir = PDMBLOCKTXDIR_FROM_DEVICE;
goto sendcmd;
case SCSI_GET_PERFORMANCE:
cbTransfer = s->uATARegLCyl | (s->uATARegHCyl << 8); /* use ATAPI transfer length */
uTxDir = PDMBLOCKTXDIR_FROM_DEVICE;
goto sendcmd;
case SCSI_INQUIRY:
cbTransfer = ataBE2H_U16(pbPacket + 3);
uTxDir = PDMBLOCKTXDIR_FROM_DEVICE;
goto sendcmd;
case SCSI_LOAD_UNLOAD_MEDIUM:
goto sendcmd;
case SCSI_MECHANISM_STATUS:
cbTransfer = ataBE2H_U16(pbPacket + 8);
uTxDir = PDMBLOCKTXDIR_FROM_DEVICE;
goto sendcmd;
case SCSI_MODE_SELECT_10:
cbTransfer = ataBE2H_U16(pbPacket + 7);
uTxDir = PDMBLOCKTXDIR_TO_DEVICE;
goto sendcmd;
case SCSI_MODE_SENSE_10:
cbTransfer = ataBE2H_U16(pbPacket + 7);
uTxDir = PDMBLOCKTXDIR_FROM_DEVICE;
goto sendcmd;
case SCSI_PAUSE_RESUME:
goto sendcmd;
case SCSI_PLAY_AUDIO_10:
goto sendcmd;
case SCSI_PLAY_AUDIO_12:
goto sendcmd;
case SCSI_PLAY_AUDIO_MSF:
goto sendcmd;
case SCSI_PREVENT_ALLOW_MEDIUM_REMOVAL:
/** @todo do not forget to unlock when a VM is shut down */
goto sendcmd;
case SCSI_READ_10:
iATAPILBA = ataBE2H_U32(pbPacket + 2);
cSectors = ataBE2H_U16(pbPacket + 7);
Log2(("ATAPI PT: lba %d sectors %d\n", iATAPILBA, cSectors));
s->cbATAPISector = 2048; /**< @todo this size is not always correct */
cbTransfer = cSectors * s->cbATAPISector;
uTxDir = PDMBLOCKTXDIR_FROM_DEVICE;
goto sendcmd;
case SCSI_READ_12:
iATAPILBA = ataBE2H_U32(pbPacket + 2);
cSectors = ataBE2H_U32(pbPacket + 6);
Log2(("ATAPI PT: lba %d sectors %d\n", iATAPILBA, cSectors));
s->cbATAPISector = 2048; /**< @todo this size is not always correct */
cbTransfer = cSectors * s->cbATAPISector;
uTxDir = PDMBLOCKTXDIR_FROM_DEVICE;
goto sendcmd;
case SCSI_READ_BUFFER:
cbTransfer = ataBE2H_U24(pbPacket + 6);
uTxDir = PDMBLOCKTXDIR_FROM_DEVICE;
goto sendcmd;
case SCSI_READ_BUFFER_CAPACITY:
cbTransfer = ataBE2H_U16(pbPacket + 7);
uTxDir = PDMBLOCKTXDIR_FROM_DEVICE;
goto sendcmd;
case SCSI_READ_CAPACITY:
cbTransfer = 8;
uTxDir = PDMBLOCKTXDIR_FROM_DEVICE;
goto sendcmd;
case SCSI_READ_CD:
s->cbATAPISector = 2048; /**< @todo this size is not always correct */
cbTransfer = ataBE2H_U24(pbPacket + 6) / s->cbATAPISector * s->cbATAPISector;
uTxDir = PDMBLOCKTXDIR_FROM_DEVICE;
goto sendcmd;
case SCSI_READ_CD_MSF:
cSectors = ataMSF2LBA(pbPacket + 6) - ataMSF2LBA(pbPacket + 3);
if (cSectors > 32)
cSectors = 32; /* Limit transfer size to 64~74K. Safety first. In any case this can only harm software doing CDDA extraction. */
s->cbATAPISector = 2048; /**< @todo this size is not always correct */
cbTransfer = cSectors * s->cbATAPISector;
uTxDir = PDMBLOCKTXDIR_FROM_DEVICE;
goto sendcmd;
case SCSI_READ_DISC_INFORMATION:
cbTransfer = ataBE2H_U16(pbPacket + 7);
uTxDir = PDMBLOCKTXDIR_FROM_DEVICE;
goto sendcmd;
case SCSI_READ_DVD_STRUCTURE:
cbTransfer = ataBE2H_U16(pbPacket + 8);
uTxDir = PDMBLOCKTXDIR_FROM_DEVICE;
goto sendcmd;
case SCSI_READ_FORMAT_CAPACITIES:
cbTransfer = ataBE2H_U16(pbPacket + 7);
uTxDir = PDMBLOCKTXDIR_FROM_DEVICE;
goto sendcmd;
case SCSI_READ_SUBCHANNEL:
cbTransfer = ataBE2H_U16(pbPacket + 7);
uTxDir = PDMBLOCKTXDIR_FROM_DEVICE;
goto sendcmd;
case SCSI_READ_TOC_PMA_ATIP:
cbTransfer = ataBE2H_U16(pbPacket + 7);
uTxDir = PDMBLOCKTXDIR_FROM_DEVICE;
goto sendcmd;
case SCSI_READ_TRACK_INFORMATION:
cbTransfer = ataBE2H_U16(pbPacket + 7);
uTxDir = PDMBLOCKTXDIR_FROM_DEVICE;
goto sendcmd;
case SCSI_REPAIR_TRACK:
goto sendcmd;
case SCSI_REPORT_KEY:
cbTransfer = ataBE2H_U16(pbPacket + 8);
uTxDir = PDMBLOCKTXDIR_FROM_DEVICE;
goto sendcmd;
case SCSI_REQUEST_SENSE:
cbTransfer = pbPacket[4];
if ((s->abATAPISense[2] & 0x0f) != SCSI_SENSE_NONE)
{
ataStartTransfer(s, RT_MIN(cbTransfer, 18), PDMBLOCKTXDIR_FROM_DEVICE, ATAFN_BT_ATAPI_CMD, ATAFN_SS_ATAPI_REQUEST_SENSE, true);
break;
}
uTxDir = PDMBLOCKTXDIR_FROM_DEVICE;
goto sendcmd;
case SCSI_RESERVE_TRACK:
goto sendcmd;
case SCSI_SCAN:
goto sendcmd;
case SCSI_SEEK_10:
goto sendcmd;
case SCSI_SEND_CUE_SHEET:
cbTransfer = ataBE2H_U24(pbPacket + 6);
uTxDir = PDMBLOCKTXDIR_TO_DEVICE;
goto sendcmd;
case SCSI_SEND_DVD_STRUCTURE:
cbTransfer = ataBE2H_U16(pbPacket + 8);
uTxDir = PDMBLOCKTXDIR_TO_DEVICE;
goto sendcmd;
case SCSI_SEND_EVENT:
cbTransfer = ataBE2H_U16(pbPacket + 8);
uTxDir = PDMBLOCKTXDIR_TO_DEVICE;
goto sendcmd;
case SCSI_SEND_KEY:
cbTransfer = ataBE2H_U16(pbPacket + 8);
uTxDir = PDMBLOCKTXDIR_TO_DEVICE;
goto sendcmd;
case SCSI_SEND_OPC_INFORMATION:
cbTransfer = ataBE2H_U16(pbPacket + 7);
uTxDir = PDMBLOCKTXDIR_TO_DEVICE;
goto sendcmd;
case SCSI_SET_CD_SPEED:
goto sendcmd;
case SCSI_SET_READ_AHEAD:
goto sendcmd;
case SCSI_SET_STREAMING:
cbTransfer = ataBE2H_U16(pbPacket + 9);
uTxDir = PDMBLOCKTXDIR_TO_DEVICE;
goto sendcmd;
case SCSI_START_STOP_UNIT:
goto sendcmd;
case SCSI_STOP_PLAY_SCAN:
goto sendcmd;
case SCSI_SYNCHRONIZE_CACHE:
goto sendcmd;
case SCSI_TEST_UNIT_READY:
goto sendcmd;
case SCSI_VERIFY_10:
goto sendcmd;
case SCSI_WRITE_10:
iATAPILBA = ataBE2H_U32(pbPacket + 2);
cSectors = ataBE2H_U16(pbPacket + 7);
Log2(("ATAPI PT: lba %d sectors %d\n", iATAPILBA, cSectors));
#if 0
/* The sector size is determined by the async I/O thread. */
s->cbATAPISector = 0;
/* Preliminary, will be corrected once the sector size is known. */
cbTransfer = cSectors;
#else
s->cbATAPISector = 2048; /**< @todo this size is not always correct */
cbTransfer = cSectors * s->cbATAPISector;
#endif
uTxDir = PDMBLOCKTXDIR_TO_DEVICE;
goto sendcmd;
case SCSI_WRITE_12:
iATAPILBA = ataBE2H_U32(pbPacket + 2);
cSectors = ataBE2H_U32(pbPacket + 6);
Log2(("ATAPI PT: lba %d sectors %d\n", iATAPILBA, cSectors));
#if 0
/* The sector size is determined by the async I/O thread. */
s->cbATAPISector = 0;
/* Preliminary, will be corrected once the sector size is known. */
cbTransfer = cSectors;
#else
s->cbATAPISector = 2048; /**< @todo this size is not always correct */
cbTransfer = cSectors * s->cbATAPISector;
#endif
uTxDir = PDMBLOCKTXDIR_TO_DEVICE;
goto sendcmd;
case SCSI_WRITE_AND_VERIFY_10:
iATAPILBA = ataBE2H_U32(pbPacket + 2);
cSectors = ataBE2H_U16(pbPacket + 7);
Log2(("ATAPI PT: lba %d sectors %d\n", iATAPILBA, cSectors));
/* The sector size is determined by the async I/O thread. */
s->cbATAPISector = 0;
/* Preliminary, will be corrected once the sector size is known. */
cbTransfer = cSectors;
uTxDir = PDMBLOCKTXDIR_TO_DEVICE;
goto sendcmd;
case SCSI_WRITE_BUFFER:
switch (pbPacket[1] & 0x1f)
{
case 0x04: /* download microcode */
case 0x05: /* download microcode and save */
case 0x06: /* download microcode with offsets */
case 0x07: /* download microcode with offsets and save */
case 0x0e: /* download microcode with offsets and defer activation */
case 0x0f: /* activate deferred microcode */
LogRel(("PIIX3 ATA: LUN#%d: CD-ROM passthrough command attempted to update firmware, blocked\n", s->iLUN));
atapiCmdErrorSimple(s, SCSI_SENSE_ILLEGAL_REQUEST, SCSI_ASC_INV_FIELD_IN_CMD_PACKET);
break;
default:
cbTransfer = ataBE2H_U16(pbPacket + 6);
uTxDir = PDMBLOCKTXDIR_TO_DEVICE;
goto sendcmd;
}
break;
case SCSI_REPORT_LUNS: /* Not part of MMC-3, but used by Windows. */
cbTransfer = ataBE2H_U32(pbPacket + 6);
uTxDir = PDMBLOCKTXDIR_FROM_DEVICE;
goto sendcmd;
case SCSI_REZERO_UNIT:
/* Obsolete command used by cdrecord. What else would one expect?
* This command is not sent to the drive, it is handled internally,
* as the Linux kernel doesn't like it (message "scsi: unknown
* opcode 0x01" in syslog) and replies with a sense code of 0,
* which sends cdrecord to an endless loop. */
atapiCmdErrorSimple(s, SCSI_SENSE_ILLEGAL_REQUEST, SCSI_ASC_ILLEGAL_OPCODE);
break;
default:
LogRel(("PIIX3 ATA: LUN#%d: passthrough unimplemented for command %#x\n", s->iLUN, pbPacket[0]));
atapiCmdErrorSimple(s, SCSI_SENSE_ILLEGAL_REQUEST, SCSI_ASC_ILLEGAL_OPCODE);
break;
sendcmd:
/* Send a command to the drive, passing data in/out as required. */
Log2(("ATAPI PT: max size %d\n", cbTransfer));
Assert(cbTransfer <= s->cbIOBuffer);
if (cbTransfer == 0)
uTxDir = PDMBLOCKTXDIR_NONE;
ataStartTransfer(s, cbTransfer, uTxDir, ATAFN_BT_ATAPI_PASSTHROUGH_CMD, ATAFN_SS_ATAPI_PASSTHROUGH, true);
}
}
static void atapiParseCmd(ATADevState *s)
{
const uint8_t *pbPacket;
pbPacket = s->aATAPICmd;
#ifdef DEBUG
Log(("%s: LUN#%d DMA=%d CMD=%#04x \"%s\"\n", __FUNCTION__, s->iLUN, s->fDMA, pbPacket[0], SCSICmdText(pbPacket[0])));
#else /* !DEBUG */
Log(("%s: LUN#%d DMA=%d CMD=%#04x\n", __FUNCTION__, s->iLUN, s->fDMA, pbPacket[0]));
#endif /* !DEBUG */
Log2(("%s: limit=%#x packet: %.*Rhxs\n", __FUNCTION__, s->uATARegLCyl | (s->uATARegHCyl << 8), ATAPI_PACKET_SIZE, pbPacket));
if (s->fATAPIPassthrough)
atapiParseCmdPassthrough(s);
else
atapiParseCmdVirtualATAPI(s);
}
static bool ataPacketSS(ATADevState *s)
{
s->fDMA = !!(s->uATARegFeature & 1);
memcpy(s->aATAPICmd, s->CTX_SUFF(pbIOBuffer), ATAPI_PACKET_SIZE);
s->uTxDir = PDMBLOCKTXDIR_NONE;
s->cbTotalTransfer = 0;
s->cbElementaryTransfer = 0;
atapiParseCmd(s);
return false;
}
/**
* SCSI_GET_EVENT_STATUS_NOTIFICATION should return "medium removed" event
* from now on, regardless if there was a medium inserted or not.
*/
static void ataMediumRemoved(ATADevState *s)
{
ASMAtomicWriteU32(&s->MediaEventStatus, ATA_EVENT_STATUS_MEDIA_REMOVED);
}
/**
* SCSI_GET_EVENT_STATUS_NOTIFICATION should return "medium inserted". If
* there was already a medium inserted, don't forget to send the "medium
* removed" event first.
*/
static void ataMediumInserted(ATADevState *s)
{
uint32_t OldStatus, NewStatus;
do
{
OldStatus = ASMAtomicReadU32(&s->MediaEventStatus);
switch (OldStatus)
{
case ATA_EVENT_STATUS_MEDIA_CHANGED:
case ATA_EVENT_STATUS_MEDIA_REMOVED:
/* no change, we will send "medium removed" + "medium inserted" */
NewStatus = ATA_EVENT_STATUS_MEDIA_CHANGED;
break;
default:
NewStatus = ATA_EVENT_STATUS_MEDIA_NEW;
break;
}
} while (!ASMAtomicCmpXchgU32(&s->MediaEventStatus, NewStatus, OldStatus));
}
/**
* Called when a media is mounted.
*
* @param pInterface Pointer to the interface structure containing the called function pointer.
*/
static DECLCALLBACK(void) ataMountNotify(PPDMIMOUNTNOTIFY pInterface)
{
ATADevState *pIf = PDMIMOUNTNOTIFY_2_ATASTATE(pInterface);
Log(("%s: changing LUN#%d\n", __FUNCTION__, pIf->iLUN));
/* Ignore the call if we're called while being attached. */
if (!pIf->pDrvBlock)
return;
if (pIf->fATAPI)
pIf->cTotalSectors = pIf->pDrvBlock->pfnGetSize(pIf->pDrvBlock) / 2048;
else
pIf->cTotalSectors = pIf->pDrvBlock->pfnGetSize(pIf->pDrvBlock) / 512;
/* Report media changed in TEST UNIT and other (probably incorrect) places. */
if (pIf->cNotifiedMediaChange < 2)
pIf->cNotifiedMediaChange = 2;
ataMediumInserted(pIf);
}
/**
* Called when a media is unmounted
* @param pInterface Pointer to the interface structure containing the called function pointer.
*/
static DECLCALLBACK(void) ataUnmountNotify(PPDMIMOUNTNOTIFY pInterface)
{
ATADevState *pIf = PDMIMOUNTNOTIFY_2_ATASTATE(pInterface);
Log(("%s:\n", __FUNCTION__));
pIf->cTotalSectors = 0;
/*
* Whatever I do, XP will not use the GET MEDIA STATUS nor the EVENT stuff.
* However, it will respond to TEST UNIT with a 0x6 0x28 (media changed) sense code.
* So, we'll give it 4 TEST UNIT command to catch up, two which the media is not
* present and 2 in which it is changed.
*/
pIf->cNotifiedMediaChange = 4;
ataMediumRemoved(pIf);
}
static void ataPacketBT(ATADevState *s)
{
s->cbElementaryTransfer = s->cbTotalTransfer;
s->uATARegNSector = (s->uATARegNSector & ~7) | ATAPI_INT_REASON_CD;
Log2(("%s: interrupt reason %#04x\n", __FUNCTION__, s->uATARegNSector));
ataSetStatusValue(s, ATA_STAT_READY);
}
static void ataResetDevice(ATADevState *s)
{
s->cMultSectors = ATA_MAX_MULT_SECTORS;
s->cNotifiedMediaChange = 0;
ASMAtomicWriteU32(&s->MediaEventStatus, ATA_EVENT_STATUS_UNCHANGED);
ataUnsetIRQ(s);
s->uATARegSelect = 0x20;
ataSetStatusValue(s, ATA_STAT_READY);
ataSetSignature(s);
s->cbTotalTransfer = 0;
s->cbElementaryTransfer = 0;
s->iIOBufferPIODataStart = 0;
s->iIOBufferPIODataEnd = 0;
s->iBeginTransfer = ATAFN_BT_NULL;
s->iSourceSink = ATAFN_SS_NULL;
s->fATAPITransfer = false;
s->uATATransferMode = ATA_MODE_UDMA | 2; /* PIIX3 supports only up to UDMA2 */
s->uATARegFeature = 0;
}
static bool ataExecuteDeviceDiagnosticSS(ATADevState *s)
{
ataSetSignature(s);
if (s->fATAPI)
ataSetStatusValue(s, 0); /* NOTE: READY is _not_ set */
else
ataSetStatusValue(s, ATA_STAT_READY);
s->uATARegError = 0x01;
return false;
}
static void ataParseCmd(ATADevState *s, uint8_t cmd)
{
#ifdef DEBUG
Log(("%s: LUN#%d CMD=%#04x \"%s\"\n", __FUNCTION__, s->iLUN, cmd, ATACmdText(cmd)));
#else /* !DEBUG */
Log(("%s: LUN#%d CMD=%#04x\n", __FUNCTION__, s->iLUN, cmd));
#endif /* !DEBUG */
s->fLBA48 = false;
s->fDMA = false;
if (cmd == ATA_IDLE_IMMEDIATE)
{
/* Detect Linux timeout recovery, first tries IDLE IMMEDIATE (which
* would overwrite the failing command unfortunately), then RESET. */
int32_t uCmdWait = -1;
uint64_t uNow = RTTimeNanoTS();
if (s->u64CmdTS)
uCmdWait = (uNow - s->u64CmdTS) / 1000;
LogRel(("PIIX3 ATA: LUN#%d: IDLE IMMEDIATE, CmdIf=%#04x (%d usec ago)\n",
s->iLUN, s->uATARegCommand, uCmdWait));
}
s->uATARegCommand = cmd;
switch (cmd)
{
case ATA_IDENTIFY_DEVICE:
if (s->pDrvBlock && !s->fATAPI)
ataStartTransfer(s, 512, PDMBLOCKTXDIR_FROM_DEVICE, ATAFN_BT_NULL, ATAFN_SS_IDENTIFY, false);
else
{
if (s->fATAPI)
ataSetSignature(s);
ataCmdError(s, ABRT_ERR);
ataSetIRQ(s); /* Shortcut, do not use AIO thread. */
}
break;
case ATA_INITIALIZE_DEVICE_PARAMETERS:
case ATA_RECALIBRATE:
ataCmdOK(s, ATA_STAT_SEEK);
ataSetIRQ(s); /* Shortcut, do not use AIO thread. */
break;
case ATA_SET_MULTIPLE_MODE:
if ( s->uATARegNSector != 0
&& ( s->uATARegNSector > ATA_MAX_MULT_SECTORS
|| (s->uATARegNSector & (s->uATARegNSector - 1)) != 0))
{
ataCmdError(s, ABRT_ERR);
}
else
{
Log2(("%s: set multi sector count to %d\n", __FUNCTION__, s->uATARegNSector));
s->cMultSectors = s->uATARegNSector;
ataCmdOK(s, 0);
}
ataSetIRQ(s); /* Shortcut, do not use AIO thread. */
break;
case ATA_READ_VERIFY_SECTORS_EXT:
s->fLBA48 = true;
case ATA_READ_VERIFY_SECTORS:
case ATA_READ_VERIFY_SECTORS_WITHOUT_RETRIES:
/* do sector number check ? */
ataCmdOK(s, 0);
ataSetIRQ(s); /* Shortcut, do not use AIO thread. */
break;
case ATA_READ_SECTORS_EXT:
s->fLBA48 = true;
case ATA_READ_SECTORS:
case ATA_READ_SECTORS_WITHOUT_RETRIES:
if (!s->pDrvBlock)
goto abort_cmd;
s->cSectorsPerIRQ = 1;
ataStartTransfer(s, ataGetNSectors(s) * 512, PDMBLOCKTXDIR_FROM_DEVICE, ATAFN_BT_READ_WRITE_SECTORS, ATAFN_SS_READ_SECTORS, false);
break;
case ATA_WRITE_SECTORS_EXT:
s->fLBA48 = true;
case ATA_WRITE_SECTORS:
case ATA_WRITE_SECTORS_WITHOUT_RETRIES:
s->cSectorsPerIRQ = 1;
ataStartTransfer(s, ataGetNSectors(s) * 512, PDMBLOCKTXDIR_TO_DEVICE, ATAFN_BT_READ_WRITE_SECTORS, ATAFN_SS_WRITE_SECTORS, false);
break;
case ATA_READ_MULTIPLE_EXT:
s->fLBA48 = true;
case ATA_READ_MULTIPLE:
if (!s->cMultSectors)
goto abort_cmd;
s->cSectorsPerIRQ = s->cMultSectors;
ataStartTransfer(s, ataGetNSectors(s) * 512, PDMBLOCKTXDIR_FROM_DEVICE, ATAFN_BT_READ_WRITE_SECTORS, ATAFN_SS_READ_SECTORS, false);
break;
case ATA_WRITE_MULTIPLE_EXT:
s->fLBA48 = true;
case ATA_WRITE_MULTIPLE:
if (!s->cMultSectors)
goto abort_cmd;
s->cSectorsPerIRQ = s->cMultSectors;
ataStartTransfer(s, ataGetNSectors(s) * 512, PDMBLOCKTXDIR_TO_DEVICE, ATAFN_BT_READ_WRITE_SECTORS, ATAFN_SS_WRITE_SECTORS, false);
break;
case ATA_READ_DMA_EXT:
s->fLBA48 = true;
case ATA_READ_DMA:
case ATA_READ_DMA_WITHOUT_RETRIES:
if (!s->pDrvBlock)
goto abort_cmd;
s->cSectorsPerIRQ = ATA_MAX_MULT_SECTORS;
s->fDMA = true;
ataStartTransfer(s, ataGetNSectors(s) * 512, PDMBLOCKTXDIR_FROM_DEVICE, ATAFN_BT_READ_WRITE_SECTORS, ATAFN_SS_READ_SECTORS, false);
break;
case ATA_WRITE_DMA_EXT:
s->fLBA48 = true;
case ATA_WRITE_DMA:
case ATA_WRITE_DMA_WITHOUT_RETRIES:
if (!s->pDrvBlock)
goto abort_cmd;
s->cSectorsPerIRQ = ATA_MAX_MULT_SECTORS;
s->fDMA = true;
ataStartTransfer(s, ataGetNSectors(s) * 512, PDMBLOCKTXDIR_TO_DEVICE, ATAFN_BT_READ_WRITE_SECTORS, ATAFN_SS_WRITE_SECTORS, false);
break;
case ATA_READ_NATIVE_MAX_ADDRESS_EXT:
s->fLBA48 = true;
ataSetSector(s, s->cTotalSectors - 1);
ataCmdOK(s, 0);
ataSetIRQ(s); /* Shortcut, do not use AIO thread. */
break;
case ATA_SEEK: /* Used by the SCO OpenServer. Command is marked as obsolete */
ataCmdOK(s, 0);
ataSetIRQ(s); /* Shortcut, do not use AIO thread. */
break;
case ATA_READ_NATIVE_MAX_ADDRESS:
ataSetSector(s, RT_MIN(s->cTotalSectors, 1 << 28) - 1);
ataCmdOK(s, 0);
ataSetIRQ(s); /* Shortcut, do not use AIO thread. */
break;
case ATA_CHECK_POWER_MODE:
s->uATARegNSector = 0xff; /* drive active or idle */
ataCmdOK(s, 0);
ataSetIRQ(s); /* Shortcut, do not use AIO thread. */
break;
case ATA_SET_FEATURES:
Log2(("%s: feature=%#x\n", __FUNCTION__, s->uATARegFeature));
if (!s->pDrvBlock)
goto abort_cmd;
switch (s->uATARegFeature)
{
case 0x02: /* write cache enable */
Log2(("%s: write cache enable\n", __FUNCTION__));
ataCmdOK(s, ATA_STAT_SEEK);
ataSetIRQ(s); /* Shortcut, do not use AIO thread. */
break;
case 0xaa: /* read look-ahead enable */
Log2(("%s: read look-ahead enable\n", __FUNCTION__));
ataCmdOK(s, ATA_STAT_SEEK);
ataSetIRQ(s); /* Shortcut, do not use AIO thread. */
break;
case 0x55: /* read look-ahead disable */
Log2(("%s: read look-ahead disable\n", __FUNCTION__));
ataCmdOK(s, ATA_STAT_SEEK);
ataSetIRQ(s); /* Shortcut, do not use AIO thread. */
break;
case 0xcc: /* reverting to power-on defaults enable */
Log2(("%s: revert to power-on defaults enable\n", __FUNCTION__));
ataCmdOK(s, ATA_STAT_SEEK);
ataSetIRQ(s); /* Shortcut, do not use AIO thread. */
break;
case 0x66: /* reverting to power-on defaults disable */
Log2(("%s: revert to power-on defaults disable\n", __FUNCTION__));
ataCmdOK(s, ATA_STAT_SEEK);
ataSetIRQ(s); /* Shortcut, do not use AIO thread. */
break;
case 0x82: /* write cache disable */
Log2(("%s: write cache disable\n", __FUNCTION__));
/* As per the ATA/ATAPI-6 specs, a write cache disable
* command MUST flush the write buffers to disc. */
ataStartTransfer(s, 0, PDMBLOCKTXDIR_NONE, ATAFN_BT_NULL, ATAFN_SS_FLUSH, false);
break;
case 0x03: { /* set transfer mode */
Log2(("%s: transfer mode %#04x\n", __FUNCTION__, s->uATARegNSector));
switch (s->uATARegNSector & 0xf8)
{
case 0x00: /* PIO default */
case 0x08: /* PIO mode */
break;
case ATA_MODE_MDMA: /* MDMA mode */
s->uATATransferMode = (s->uATARegNSector & 0xf8) | RT_MIN(s->uATARegNSector & 0x07, ATA_MDMA_MODE_MAX);
break;
case ATA_MODE_UDMA: /* UDMA mode */
s->uATATransferMode = (s->uATARegNSector & 0xf8) | RT_MIN(s->uATARegNSector & 0x07, ATA_UDMA_MODE_MAX);
break;
default:
goto abort_cmd;
}
ataCmdOK(s, ATA_STAT_SEEK);
ataSetIRQ(s); /* Shortcut, do not use AIO thread. */
break;
}
default:
goto abort_cmd;
}
/*
* OS/2 workarond:
* The OS/2 IDE driver from MCP2 appears to rely on the feature register being
* reset here. According to the specification, this is a driver bug as the register
* contents are undefined after the call. This means we can just as well reset it.
*/
s->uATARegFeature = 0;
break;
case ATA_FLUSH_CACHE_EXT:
case ATA_FLUSH_CACHE:
if (!s->pDrvBlock || s->fATAPI)
goto abort_cmd;
ataStartTransfer(s, 0, PDMBLOCKTXDIR_NONE, ATAFN_BT_NULL, ATAFN_SS_FLUSH, false);
break;
case ATA_STANDBY_IMMEDIATE:
ataCmdOK(s, 0);
ataSetIRQ(s); /* Shortcut, do not use AIO thread. */
break;
case ATA_IDLE_IMMEDIATE:
LogRel(("PIIX3 ATA: LUN#%d: aborting current command\n", s->iLUN));
ataAbortCurrentCommand(s, false);
break;
/* ATAPI commands */
case ATA_IDENTIFY_PACKET_DEVICE:
if (s->fATAPI)
ataStartTransfer(s, 512, PDMBLOCKTXDIR_FROM_DEVICE, ATAFN_BT_NULL, ATAFN_SS_ATAPI_IDENTIFY, false);
else
{
ataCmdError(s, ABRT_ERR);
ataSetIRQ(s); /* Shortcut, do not use AIO thread. */
}
break;
case ATA_EXECUTE_DEVICE_DIAGNOSTIC:
ataStartTransfer(s, 0, PDMBLOCKTXDIR_NONE, ATAFN_BT_NULL, ATAFN_SS_EXECUTE_DEVICE_DIAGNOSTIC, false);
break;
case ATA_DEVICE_RESET:
if (!s->fATAPI)
goto abort_cmd;
LogRel(("PIIX3 ATA: LUN#%d: performing device RESET\n", s->iLUN));
ataAbortCurrentCommand(s, true);
break;
case ATA_PACKET:
if (!s->fATAPI)
goto abort_cmd;
/* overlapping commands not supported */
if (s->uATARegFeature & 0x02)
goto abort_cmd;
ataStartTransfer(s, ATAPI_PACKET_SIZE, PDMBLOCKTXDIR_TO_DEVICE, ATAFN_BT_PACKET, ATAFN_SS_PACKET, false);
break;
default:
abort_cmd:
ataCmdError(s, ABRT_ERR);
ataSetIRQ(s); /* Shortcut, do not use AIO thread. */
break;
}
}
/**
* Waits for a particular async I/O thread to complete whatever it
* is doing at the moment.
*
* @returns true on success.
* @returns false when the thread is still processing.
* @param pThis Pointer to the controller data.
* @param cMillies How long to wait (total).
*/
static bool ataWaitForAsyncIOIsIdle(PATACONTROLLER pCtl, unsigned cMillies)
{
uint64_t u64Start;
/*
* Wait for any pending async operation to finish
*/
u64Start = RTTimeMilliTS();
for (;;)
{
if (ataAsyncIOIsIdle(pCtl, false))
return true;
if (RTTimeMilliTS() - u64Start >= cMillies)
break;
/* Sleep for a bit. */
RTThreadSleep(100);
}
return false;
}
#endif /* IN_RING3 */
static int ataIOPortWriteU8(PATACONTROLLER pCtl, uint32_t addr, uint32_t val)
{
Log2(("%s: write addr=%#x val=%#04x\n", __FUNCTION__, addr, val));
addr &= 7;
switch (addr)
{
case 0:
break;
case 1: /* feature register */
/* NOTE: data is written to the two drives */
pCtl->aIfs[0].uATARegDevCtl &= ~ATA_DEVCTL_HOB;
pCtl->aIfs[1].uATARegDevCtl &= ~ATA_DEVCTL_HOB;
pCtl->aIfs[0].uATARegFeatureHOB = pCtl->aIfs[0].uATARegFeature;
pCtl->aIfs[1].uATARegFeatureHOB = pCtl->aIfs[1].uATARegFeature;
pCtl->aIfs[0].uATARegFeature = val;
pCtl->aIfs[1].uATARegFeature = val;
break;
case 2: /* sector count */
pCtl->aIfs[0].uATARegDevCtl &= ~ATA_DEVCTL_HOB;
pCtl->aIfs[1].uATARegDevCtl &= ~ATA_DEVCTL_HOB;
pCtl->aIfs[0].uATARegNSectorHOB = pCtl->aIfs[0].uATARegNSector;
pCtl->aIfs[1].uATARegNSectorHOB = pCtl->aIfs[1].uATARegNSector;
pCtl->aIfs[0].uATARegNSector = val;
pCtl->aIfs[1].uATARegNSector = val;
break;
case 3: /* sector number */
pCtl->aIfs[0].uATARegDevCtl &= ~ATA_DEVCTL_HOB;
pCtl->aIfs[1].uATARegDevCtl &= ~ATA_DEVCTL_HOB;
pCtl->aIfs[0].uATARegSectorHOB = pCtl->aIfs[0].uATARegSector;
pCtl->aIfs[1].uATARegSectorHOB = pCtl->aIfs[1].uATARegSector;
pCtl->aIfs[0].uATARegSector = val;
pCtl->aIfs[1].uATARegSector = val;
break;
case 4: /* cylinder low */
pCtl->aIfs[0].uATARegDevCtl &= ~ATA_DEVCTL_HOB;
pCtl->aIfs[1].uATARegDevCtl &= ~ATA_DEVCTL_HOB;
pCtl->aIfs[0].uATARegLCylHOB = pCtl->aIfs[0].uATARegLCyl;
pCtl->aIfs[1].uATARegLCylHOB = pCtl->aIfs[1].uATARegLCyl;
pCtl->aIfs[0].uATARegLCyl = val;
pCtl->aIfs[1].uATARegLCyl = val;
break;
case 5: /* cylinder high */
pCtl->aIfs[0].uATARegDevCtl &= ~ATA_DEVCTL_HOB;
pCtl->aIfs[1].uATARegDevCtl &= ~ATA_DEVCTL_HOB;
pCtl->aIfs[0].uATARegHCylHOB = pCtl->aIfs[0].uATARegHCyl;
pCtl->aIfs[1].uATARegHCylHOB = pCtl->aIfs[1].uATARegHCyl;
pCtl->aIfs[0].uATARegHCyl = val;
pCtl->aIfs[1].uATARegHCyl = val;
break;
case 6: /* drive/head */
pCtl->aIfs[0].uATARegSelect = (val & ~0x10) | 0xa0;
pCtl->aIfs[1].uATARegSelect = (val | 0x10) | 0xa0;
if (((val >> 4) & 1) != pCtl->iSelectedIf)
{
PPDMDEVINS pDevIns = CONTROLLER_2_DEVINS(pCtl);
/* select another drive */
pCtl->iSelectedIf = (val >> 4) & 1;
/* The IRQ line is multiplexed between the two drives, so
* update the state when switching to another drive. Only need
* to update interrupt line if it is enabled and there is a
* state change. */
if ( !(pCtl->aIfs[pCtl->iSelectedIf].uATARegDevCtl & ATA_DEVCTL_DISABLE_IRQ)
&& ( pCtl->aIfs[pCtl->iSelectedIf].fIrqPending
!= pCtl->aIfs[pCtl->iSelectedIf ^ 1].fIrqPending))
{
if (pCtl->aIfs[pCtl->iSelectedIf].fIrqPending)
{
Log2(("%s: LUN#%d asserting IRQ (drive select change)\n", __FUNCTION__, pCtl->aIfs[pCtl->iSelectedIf].iLUN));
/* The BMDMA unit unconditionally sets BM_STATUS_INT if
* the interrupt line is asserted. It monitors the line
* for a rising edge. */
pCtl->BmDma.u8Status |= BM_STATUS_INT;
if (pCtl->irq == 16)
PDMDevHlpPCISetIrqNoWait(pDevIns, 0, 1);
else
PDMDevHlpISASetIrqNoWait(pDevIns, pCtl->irq, 1);
}
else
{
Log2(("%s: LUN#%d deasserting IRQ (drive select change)\n", __FUNCTION__, pCtl->aIfs[pCtl->iSelectedIf].iLUN));
if (pCtl->irq == 16)
PDMDevHlpPCISetIrqNoWait(pDevIns, 0, 0);
else
PDMDevHlpISASetIrqNoWait(pDevIns, pCtl->irq, 0);
}
}
}
break;
default:
case 7: /* command */
/* ignore commands to non existant slave */
if (pCtl->iSelectedIf && !pCtl->aIfs[pCtl->iSelectedIf].pDrvBlock)
break;
#ifndef IN_RING3
/* Don't do anything complicated in GC */
return VINF_IOM_HC_IOPORT_WRITE;
#else /* IN_RING3 */
ataParseCmd(&pCtl->aIfs[pCtl->iSelectedIf], val);
#endif /* !IN_RING3 */
}
return VINF_SUCCESS;
}
static int ataIOPortReadU8(PATACONTROLLER pCtl, uint32_t addr, uint32_t *pu32)
{
ATADevState *s = &pCtl->aIfs[pCtl->iSelectedIf];
uint32_t val;
bool fHOB;
fHOB = !!(s->uATARegDevCtl & (1 << 7));
switch (addr & 7)
{
case 0: /* data register */
val = 0xff;
break;
case 1: /* error register */
/* The ATA specification is very terse when it comes to specifying
* the precise effects of reading back the error/feature register.
* The error register (read-only) shares the register number with
* the feature register (write-only), so it seems that it's not
* necessary to support the usual HOB readback here. */
if (!s->pDrvBlock)
val = 0;
else
val = s->uATARegError;
break;
case 2: /* sector count */
if (!s->pDrvBlock)
val = 0;
else if (fHOB)
val = s->uATARegNSectorHOB;
else
val = s->uATARegNSector;
break;
case 3: /* sector number */
if (!s->pDrvBlock)
val = 0;
else if (fHOB)
val = s->uATARegSectorHOB;
else
val = s->uATARegSector;
break;
case 4: /* cylinder low */
if (!s->pDrvBlock)
val = 0;
else if (fHOB)
val = s->uATARegLCylHOB;
else
val = s->uATARegLCyl;
break;
case 5: /* cylinder high */
if (!s->pDrvBlock)
val = 0;
else if (fHOB)
val = s->uATARegHCylHOB;
else
val = s->uATARegHCyl;
break;
case 6: /* drive/head */
/* This register must always work as long as there is at least
* one drive attached to the controller. It is common between
* both drives anyway (completely identical content). */
if (!pCtl->aIfs[0].pDrvBlock && !pCtl->aIfs[1].pDrvBlock)
val = 0;
else
val = s->uATARegSelect;
break;
default:
case 7: /* primary status */
{
/* Counter for number of busy status seen in GC in a row. */
static unsigned cBusy = 0;
if (!s->pDrvBlock)
val = 0;
else
val = s->uATARegStatus;
/* Give the async I/O thread an opportunity to make progress,
* don't let it starve by guests polling frequently. EMT has a
* lower priority than the async I/O thread, but sometimes the
* host OS doesn't care. With some guests we are only allowed to
* be busy for about 5 milliseconds in some situations. Note that
* this is no guarantee for any other VBox thread getting
* scheduled, so this just lowers the CPU load a bit when drives
* are busy. It cannot help with timing problems. */
if (val & ATA_STAT_BUSY)
{
#ifdef IN_RING3
cBusy = 0;
PDMCritSectLeave(&pCtl->lock);
RTThreadYield();
{
STAM_PROFILE_START(&pCtl->StatLockWait, a);
PDMCritSectEnter(&pCtl->lock, VINF_SUCCESS);
STAM_PROFILE_STOP(&pCtl->StatLockWait, a);
}
val = s->uATARegStatus;
#else /* !IN_RING3 */
/* Cannot yield CPU in guest context. And switching to host
* context for each and every busy status is too costly,
* especially on SMP systems where we don't gain much by
* yielding the CPU to someone else. */
if (++cBusy >= 20)
{
cBusy = 0;
return VINF_IOM_HC_IOPORT_READ;
}
#endif /* !IN_RING3 */
}
else
cBusy = 0;
ataUnsetIRQ(s);
break;
}
}
Log2(("%s: addr=%#x val=%#04x\n", __FUNCTION__, addr, val));
*pu32 = val;
return VINF_SUCCESS;
}
static uint32_t ataStatusRead(PATACONTROLLER pCtl, uint32_t addr)
{
ATADevState *s = &pCtl->aIfs[pCtl->iSelectedIf];
uint32_t val;
if ((!pCtl->aIfs[0].pDrvBlock && !pCtl->aIfs[1].pDrvBlock) ||
(pCtl->iSelectedIf == 1 && !s->pDrvBlock))
val = 0;
else
val = s->uATARegStatus;
Log2(("%s: addr=%#x val=%#04x\n", __FUNCTION__, addr, val));
return val;
}
static int ataControlWrite(PATACONTROLLER pCtl, uint32_t addr, uint32_t val)
{
#ifndef IN_RING3
if ((val ^ pCtl->aIfs[0].uATARegDevCtl) & ATA_DEVCTL_RESET)
return VINF_IOM_HC_IOPORT_WRITE; /* The RESET stuff is too complicated for GC. */
#endif /* !IN_RING3 */
Log2(("%s: addr=%#x val=%#04x\n", __FUNCTION__, addr, val));
/* RESET is common for both drives attached to a controller. */
if (!(pCtl->aIfs[0].uATARegDevCtl & ATA_DEVCTL_RESET) &&
(val & ATA_DEVCTL_RESET))
{
#ifdef IN_RING3
/* Software RESET low to high */
int32_t uCmdWait0 = -1, uCmdWait1 = -1;
uint64_t uNow = RTTimeNanoTS();
if (pCtl->aIfs[0].u64CmdTS)
uCmdWait0 = (uNow - pCtl->aIfs[0].u64CmdTS) / 1000;
if (pCtl->aIfs[1].u64CmdTS)
uCmdWait1 = (uNow - pCtl->aIfs[1].u64CmdTS) / 1000;
LogRel(("PIIX3 ATA: Ctl#%d: RESET, DevSel=%d AIOIf=%d CmdIf0=%#04x (%d usec ago) CmdIf1=%#04x (%d usec ago)\n",
ATACONTROLLER_IDX(pCtl), pCtl->iSelectedIf, pCtl->iAIOIf,
pCtl->aIfs[0].uATARegCommand, uCmdWait0,
pCtl->aIfs[1].uATARegCommand, uCmdWait1));
pCtl->fReset = true;
/* Everything must be done after the reset flag is set, otherwise
* there are unavoidable races with the currently executing request
* (which might just finish in the mean time). */
pCtl->fChainedTransfer = false;
for (uint32_t i = 0; i < RT_ELEMENTS(pCtl->aIfs); i++)
{
ataResetDevice(&pCtl->aIfs[i]);
/* The following cannot be done using ataSetStatusValue() since the
* reset flag is already set, which suppresses all status changes. */
pCtl->aIfs[i].uATARegStatus = ATA_STAT_BUSY | ATA_STAT_SEEK;
Log2(("%s: LUN#%d status %#04x\n", __FUNCTION__, pCtl->aIfs[i].iLUN, pCtl->aIfs[i].uATARegStatus));
pCtl->aIfs[i].uATARegError = 0x01;
}
ataAsyncIOClearRequests(pCtl);
Log2(("%s: Ctl#%d: message to async I/O thread, resetA\n", __FUNCTION__, ATACONTROLLER_IDX(pCtl)));
if (val & ATA_DEVCTL_HOB)
{
val &= ~ATA_DEVCTL_HOB;
Log2(("%s: ignored setting HOB\n", __FUNCTION__));
}
ataAsyncIOPutRequest(pCtl, &ataResetARequest);
#else /* !IN_RING3 */
AssertMsgFailed(("RESET handling is too complicated for GC\n"));
#endif /* IN_RING3 */
}
else if ((pCtl->aIfs[0].uATARegDevCtl & ATA_DEVCTL_RESET) &&
!(val & ATA_DEVCTL_RESET))
{
#ifdef IN_RING3
/* Software RESET high to low */
Log(("%s: deasserting RESET\n", __FUNCTION__));
Log2(("%s: Ctl#%d: message to async I/O thread, resetC\n", __FUNCTION__, ATACONTROLLER_IDX(pCtl)));
if (val & ATA_DEVCTL_HOB)
{
val &= ~ATA_DEVCTL_HOB;
Log2(("%s: ignored setting HOB\n", __FUNCTION__));
}
ataAsyncIOPutRequest(pCtl, &ataResetCRequest);
#else /* !IN_RING3 */
AssertMsgFailed(("RESET handling is too complicated for GC\n"));
#endif /* IN_RING3 */
}
/* Change of interrupt disable flag. Update interrupt line if interrupt
* is pending on the current interface. */
if ((val ^ pCtl->aIfs[0].uATARegDevCtl) & ATA_DEVCTL_DISABLE_IRQ
&& pCtl->aIfs[pCtl->iSelectedIf].fIrqPending)
{
if (!(val & ATA_DEVCTL_DISABLE_IRQ))
{
Log2(("%s: LUN#%d asserting IRQ (interrupt disable change)\n", __FUNCTION__, pCtl->aIfs[pCtl->iSelectedIf].iLUN));
/* The BMDMA unit unconditionally sets BM_STATUS_INT if the
* interrupt line is asserted. It monitors the line for a rising
* edge. */
pCtl->BmDma.u8Status |= BM_STATUS_INT;
if (pCtl->irq == 16)
PDMDevHlpPCISetIrqNoWait(CONTROLLER_2_DEVINS(pCtl), 0, 1);
else
PDMDevHlpISASetIrqNoWait(CONTROLLER_2_DEVINS(pCtl), pCtl->irq, 1);
}
else
{
Log2(("%s: LUN#%d deasserting IRQ (interrupt disable change)\n", __FUNCTION__, pCtl->aIfs[pCtl->iSelectedIf].iLUN));
if (pCtl->irq == 16)
PDMDevHlpPCISetIrqNoWait(CONTROLLER_2_DEVINS(pCtl), 0, 0);
else
PDMDevHlpISASetIrqNoWait(CONTROLLER_2_DEVINS(pCtl), pCtl->irq, 0);
}
}
if (val & ATA_DEVCTL_HOB)
Log2(("%s: set HOB\n", __FUNCTION__));
pCtl->aIfs[0].uATARegDevCtl = val;
pCtl->aIfs[1].uATARegDevCtl = val;
return VINF_SUCCESS;
}
#ifdef IN_RING3
static void ataPIOTransfer(PATACONTROLLER pCtl)
{
ATADevState *s;
s = &pCtl->aIfs[pCtl->iAIOIf];
Log3(("%s: if=%p\n", __FUNCTION__, s));
if (s->cbTotalTransfer && s->iIOBufferCur > s->iIOBufferEnd)
{
LogRel(("PIIX3 ATA: LUN#%d: %s data in the middle of a PIO transfer - VERY SLOW\n", s->iLUN, s->uTxDir == PDMBLOCKTXDIR_FROM_DEVICE ? "loading" : "storing"));
/* Any guest OS that triggers this case has a pathetic ATA driver.
* In a real system it would block the CPU via IORDY, here we do it
* very similarly by not continuing with the current instruction
* until the transfer to/from the storage medium is completed. */
if (s->iSourceSink != ATAFN_SS_NULL)
{
bool fRedo;
uint8_t status = s->uATARegStatus;
ataSetStatusValue(s, ATA_STAT_BUSY);
Log2(("%s: calling source/sink function\n", __FUNCTION__));
fRedo = g_apfnSourceSinkFuncs[s->iSourceSink](s);
pCtl->fRedo = fRedo;
if (RT_UNLIKELY(fRedo))
return;
ataSetStatusValue(s, status);
s->iIOBufferCur = 0;
s->iIOBufferEnd = s->cbElementaryTransfer;
}
}
if (s->cbTotalTransfer)
{
if (s->fATAPITransfer)
ataPIOTransferLimitATAPI(s);
if (s->uTxDir == PDMBLOCKTXDIR_TO_DEVICE && s->cbElementaryTransfer > s->cbTotalTransfer)
s->cbElementaryTransfer = s->cbTotalTransfer;
Log2(("%s: %s tx_size=%d elem_tx_size=%d index=%d end=%d\n",
__FUNCTION__, s->uTxDir == PDMBLOCKTXDIR_FROM_DEVICE ? "T2I" : "I2T",
s->cbTotalTransfer, s->cbElementaryTransfer,
s->iIOBufferCur, s->iIOBufferEnd));
ataPIOTransferStart(s, s->iIOBufferCur, s->cbElementaryTransfer);
s->cbTotalTransfer -= s->cbElementaryTransfer;
s->iIOBufferCur += s->cbElementaryTransfer;
if (s->uTxDir == PDMBLOCKTXDIR_FROM_DEVICE && s->cbElementaryTransfer > s->cbTotalTransfer)
s->cbElementaryTransfer = s->cbTotalTransfer;
}
else
ataPIOTransferStop(s);
}
DECLINLINE(void) ataPIOTransferFinish(PATACONTROLLER pCtl, ATADevState *s)
{
/* Do not interfere with RESET processing if the PIO transfer finishes
* while the RESET line is asserted. */
if (pCtl->fReset)
{
Log2(("%s: Ctl#%d: suppressed continuing PIO transfer as RESET is active\n", __FUNCTION__, ATACONTROLLER_IDX(pCtl)));
return;
}
if ( s->uTxDir == PDMBLOCKTXDIR_TO_DEVICE
|| ( s->iSourceSink != ATAFN_SS_NULL
&& s->iIOBufferCur >= s->iIOBufferEnd))
{
/* Need to continue the transfer in the async I/O thread. This is
* the case for write operations or generally for not yet finished
* transfers (some data might need to be read). */
ataUnsetStatus(s, ATA_STAT_READY | ATA_STAT_DRQ);
ataSetStatus(s, ATA_STAT_BUSY);
Log2(("%s: Ctl#%d: message to async I/O thread, continuing PIO transfer\n", __FUNCTION__, ATACONTROLLER_IDX(pCtl)));
ataAsyncIOPutRequest(pCtl, &ataPIORequest);
}
else
{
/* Either everything finished (though some data might still be pending)
* or some data is pending before the next read is due. */
/* Continue a previously started transfer. */
ataUnsetStatus(s, ATA_STAT_DRQ);
ataSetStatus(s, ATA_STAT_READY);
if (s->cbTotalTransfer)
{
/* There is more to transfer, happens usually for large ATAPI
* reads - the protocol limits the chunk size to 65534 bytes. */
ataPIOTransfer(pCtl);
ataSetIRQ(s);
}
else
{
Log2(("%s: Ctl#%d: skipping message to async I/O thread, ending PIO transfer\n", __FUNCTION__, ATACONTROLLER_IDX(pCtl)));
/* Finish PIO transfer. */
ataPIOTransfer(pCtl);
Assert(!pCtl->fRedo);
}
}
}
#endif /* IN_RING3 */
static int ataDataWrite(PATACONTROLLER pCtl, uint32_t addr, uint32_t cbSize, const uint8_t *pbBuf)
{
ATADevState *s = &pCtl->aIfs[pCtl->iSelectedIf];
uint8_t *p;
if (s->iIOBufferPIODataStart < s->iIOBufferPIODataEnd)
{
Assert(s->uTxDir == PDMBLOCKTXDIR_TO_DEVICE);
p = s->CTX_SUFF(pbIOBuffer) + s->iIOBufferPIODataStart;
#ifndef IN_RING3
/* All but the last transfer unit is simple enough for GC, but
* sending a request to the async IO thread is too complicated. */
if (s->iIOBufferPIODataStart + cbSize < s->iIOBufferPIODataEnd)
{
memcpy(p, pbBuf, cbSize);
s->iIOBufferPIODataStart += cbSize;
}
else
return VINF_IOM_HC_IOPORT_WRITE;
#else /* IN_RING3 */
memcpy(p, pbBuf, cbSize);
s->iIOBufferPIODataStart += cbSize;
if (s->iIOBufferPIODataStart >= s->iIOBufferPIODataEnd)
ataPIOTransferFinish(pCtl, s);
#endif /* !IN_RING3 */
}
else
Log2(("%s: DUMMY data\n", __FUNCTION__));
Log3(("%s: addr=%#x val=%.*Rhxs\n", __FUNCTION__, addr, cbSize, pbBuf));
return VINF_SUCCESS;
}
static int ataDataRead(PATACONTROLLER pCtl, uint32_t addr, uint32_t cbSize, uint8_t *pbBuf)
{
ATADevState *s = &pCtl->aIfs[pCtl->iSelectedIf];
uint8_t *p;
if (s->iIOBufferPIODataStart < s->iIOBufferPIODataEnd)
{
Assert(s->uTxDir == PDMBLOCKTXDIR_FROM_DEVICE);
p = s->CTX_SUFF(pbIOBuffer) + s->iIOBufferPIODataStart;
#ifndef IN_RING3
/* All but the last transfer unit is simple enough for GC, but
* sending a request to the async IO thread is too complicated. */
if (s->iIOBufferPIODataStart + cbSize < s->iIOBufferPIODataEnd)
{
memcpy(pbBuf, p, cbSize);
s->iIOBufferPIODataStart += cbSize;
}
else
return VINF_IOM_HC_IOPORT_READ;
#else /* IN_RING3 */
memcpy(pbBuf, p, cbSize);
s->iIOBufferPIODataStart += cbSize;
if (s->iIOBufferPIODataStart >= s->iIOBufferPIODataEnd)
ataPIOTransferFinish(pCtl, s);
#endif /* !IN_RING3 */
}
else
{
Log2(("%s: DUMMY data\n", __FUNCTION__));
memset(pbBuf, '\xff', cbSize);
}
Log3(("%s: addr=%#x val=%.*Rhxs\n", __FUNCTION__, addr, cbSize, pbBuf));
return VINF_SUCCESS;
}
#ifdef IN_RING3
static void ataDMATransferStop(ATADevState *s)
{
s->cbTotalTransfer = 0;
s->cbElementaryTransfer = 0;
s->iBeginTransfer = ATAFN_BT_NULL;
s->iSourceSink = ATAFN_SS_NULL;
}
/**
* Perform the entire DMA transfer in one go (unless a source/sink operation
* has to be redone or a RESET comes in between). Unlike the PIO counterpart
* this function cannot handle empty transfers.
*
* @param pCtl Controller for which to perform the transfer.
*/
static void ataDMATransfer(PATACONTROLLER pCtl)
{
PPDMDEVINS pDevIns = CONTROLLER_2_DEVINS(pCtl);
ATADevState *s = &pCtl->aIfs[pCtl->iAIOIf];
bool fRedo;
RTGCPHYS32 pDesc;
uint32_t cbTotalTransfer, cbElementaryTransfer;
uint32_t iIOBufferCur, iIOBufferEnd;
uint32_t dmalen;
PDMBLOCKTXDIR uTxDir;
bool fLastDesc = false;
Assert(sizeof(BMDMADesc) == 8);
fRedo = pCtl->fRedo;
if (RT_LIKELY(!fRedo))
Assert(s->cbTotalTransfer);
uTxDir = (PDMBLOCKTXDIR)s->uTxDir;
cbTotalTransfer = s->cbTotalTransfer;
cbElementaryTransfer = s->cbElementaryTransfer;
iIOBufferCur = s->iIOBufferCur;
iIOBufferEnd = s->iIOBufferEnd;
/* The DMA loop is designed to hold the lock only when absolutely
* necessary. This avoids long freezes should the guest access the
* ATA registers etc. for some reason. */
PDMCritSectLeave(&pCtl->lock);
Log2(("%s: %s tx_size=%d elem_tx_size=%d index=%d end=%d\n",
__FUNCTION__, uTxDir == PDMBLOCKTXDIR_FROM_DEVICE ? "T2I" : "I2T",
cbTotalTransfer, cbElementaryTransfer,
iIOBufferCur, iIOBufferEnd));
for (pDesc = pCtl->pFirstDMADesc; pDesc <= pCtl->pLastDMADesc; pDesc += sizeof(BMDMADesc))
{
BMDMADesc DMADesc;
RTGCPHYS32 pBuffer;
uint32_t cbBuffer;
if (RT_UNLIKELY(fRedo))
{
pBuffer = pCtl->pRedoDMABuffer;
cbBuffer = pCtl->cbRedoDMABuffer;
fLastDesc = pCtl->fRedoDMALastDesc;
}
else
{
PDMDevHlpPhysRead(pDevIns, pDesc, &DMADesc, sizeof(BMDMADesc));
pBuffer = RT_LE2H_U32(DMADesc.pBuffer);
cbBuffer = RT_LE2H_U32(DMADesc.cbBuffer);
fLastDesc = !!(cbBuffer & 0x80000000);
cbBuffer &= 0xfffe;
if (cbBuffer == 0)
cbBuffer = 0x10000;
if (cbBuffer > cbTotalTransfer)
cbBuffer = cbTotalTransfer;
}
while (RT_UNLIKELY(fRedo) || (cbBuffer && cbTotalTransfer))
{
if (RT_LIKELY(!fRedo))
{
dmalen = RT_MIN(cbBuffer, iIOBufferEnd - iIOBufferCur);
Log2(("%s: DMA desc %#010x: addr=%#010x size=%#010x\n", __FUNCTION__,
(int)pDesc, pBuffer, cbBuffer));
if (uTxDir == PDMBLOCKTXDIR_FROM_DEVICE)
PDMDevHlpPhysWrite(pDevIns, pBuffer, s->CTX_SUFF(pbIOBuffer) + iIOBufferCur, dmalen);
else
PDMDevHlpPhysRead(pDevIns, pBuffer, s->CTX_SUFF(pbIOBuffer) + iIOBufferCur, dmalen);
iIOBufferCur += dmalen;
cbTotalTransfer -= dmalen;
cbBuffer -= dmalen;
pBuffer += dmalen;
}
if ( iIOBufferCur == iIOBufferEnd
&& (uTxDir == PDMBLOCKTXDIR_TO_DEVICE || cbTotalTransfer))
{
if (uTxDir == PDMBLOCKTXDIR_FROM_DEVICE && cbElementaryTransfer > cbTotalTransfer)
cbElementaryTransfer = cbTotalTransfer;
{
STAM_PROFILE_START(&pCtl->StatLockWait, a);
PDMCritSectEnter(&pCtl->lock, VINF_SUCCESS);
STAM_PROFILE_STOP(&pCtl->StatLockWait, a);
}
/* The RESET handler could have cleared the DMA transfer
* state (since we didn't hold the lock until just now
* the guest can continue in parallel). If so, the state
* is already set up so the loop is exited immediately. */
if (s->iSourceSink != ATAFN_SS_NULL)
{
s->iIOBufferCur = iIOBufferCur;
s->iIOBufferEnd = iIOBufferEnd;
s->cbElementaryTransfer = cbElementaryTransfer;
s->cbTotalTransfer = cbTotalTransfer;
Log2(("%s: calling source/sink function\n", __FUNCTION__));
fRedo = g_apfnSourceSinkFuncs[s->iSourceSink](s);
if (RT_UNLIKELY(fRedo))
{
pCtl->pFirstDMADesc = pDesc;
pCtl->pRedoDMABuffer = pBuffer;
pCtl->cbRedoDMABuffer = cbBuffer;
pCtl->fRedoDMALastDesc = fLastDesc;
}
else
{
cbTotalTransfer = s->cbTotalTransfer;
cbElementaryTransfer = s->cbElementaryTransfer;
if (uTxDir == PDMBLOCKTXDIR_TO_DEVICE && cbElementaryTransfer > cbTotalTransfer)
cbElementaryTransfer = cbTotalTransfer;
iIOBufferCur = 0;
iIOBufferEnd = cbElementaryTransfer;
}
pCtl->fRedo = fRedo;
}
else
{
/* This forces the loop to exit immediately. */
pDesc = pCtl->pLastDMADesc + 1;
}
PDMCritSectLeave(&pCtl->lock);
if (RT_UNLIKELY(fRedo))
break;
}
}
if (RT_UNLIKELY(fRedo))
break;
/* end of transfer */
if (!cbTotalTransfer || fLastDesc)
break;
{
STAM_PROFILE_START(&pCtl->StatLockWait, a);
PDMCritSectEnter(&pCtl->lock, VINF_SUCCESS);
STAM_PROFILE_STOP(&pCtl->StatLockWait, a);
}
if (!(pCtl->BmDma.u8Cmd & BM_CMD_START) || pCtl->fReset)
{
LogRel(("PIIX3 ATA: Ctl#%d: ABORT DMA%s\n", ATACONTROLLER_IDX(pCtl), pCtl->fReset ? " due to RESET" : ""));
if (!pCtl->fReset)
ataDMATransferStop(s);
/* This forces the loop to exit immediately. */
pDesc = pCtl->pLastDMADesc + 1;
}
PDMCritSectLeave(&pCtl->lock);
}
{
STAM_PROFILE_START(&pCtl->StatLockWait, a);
PDMCritSectEnter(&pCtl->lock, VINF_SUCCESS);
STAM_PROFILE_STOP(&pCtl->StatLockWait, a);
}
if (RT_UNLIKELY(fRedo))
return;
if (fLastDesc)
pCtl->BmDma.u8Status &= ~BM_STATUS_DMAING;
s->cbTotalTransfer = cbTotalTransfer;
s->cbElementaryTransfer = cbElementaryTransfer;
s->iIOBufferCur = iIOBufferCur;
s->iIOBufferEnd = iIOBufferEnd;
}
/**
* Suspend I/O operations on a controller. Also suspends EMT, because it's
* waiting for I/O to make progress. The next attempt to perform an I/O
* operation will be made when EMT is resumed up again (as the resume
* callback below restarts I/O).
*
* @param pCtl Controller for which to suspend I/O.
*/
static void ataSuspendRedo(PATACONTROLLER pCtl)
{
PPDMDEVINS pDevIns = CONTROLLER_2_DEVINS(pCtl);
PVMREQ pReq;
int rc;
pCtl->fRedoIdle = true;
rc = VMR3ReqCall(PDMDevHlpGetVM(pDevIns), VMREQDEST_ANY, &pReq, RT_INDEFINITE_WAIT,
(PFNRT)PDMDevHlpVMSuspend, 1, pDevIns);
AssertReleaseRC(rc);
VMR3ReqFree(pReq);
}
/** Asynch I/O thread for an interface. Once upon a time this was readable
* code with several loops and a different semaphore for each purpose. But
* then came the "how can one save the state in the middle of a PIO transfer"
* question. The solution was to use an ASM, which is what's there now. */
static DECLCALLBACK(int) ataAsyncIOLoop(RTTHREAD ThreadSelf, void *pvUser)
{
const ATARequest *pReq;
uint64_t u64TS = 0; /* shut up gcc */
uint64_t uWait;
int rc = VINF_SUCCESS;
PATACONTROLLER pCtl = (PATACONTROLLER)pvUser;
ATADevState *s;
pReq = NULL;
pCtl->fChainedTransfer = false;
while (!pCtl->fShutdown)
{
/* Keep this thread from doing anything as long as EMT is suspended. */
while (pCtl->fRedoIdle)
{
rc = RTSemEventWait(pCtl->SuspendIOSem, RT_INDEFINITE_WAIT);
if (RT_FAILURE(rc) || pCtl->fShutdown)
break;
pCtl->fRedoIdle = false;
}
/* Wait for work. */
if (pReq == NULL)
{
LogBird(("ata: %x: going to sleep...\n", pCtl->IOPortBase1));
rc = RTSemEventWait(pCtl->AsyncIOSem, RT_INDEFINITE_WAIT);
LogBird(("ata: %x: waking up\n", pCtl->IOPortBase1));
if (RT_FAILURE(rc) || pCtl->fShutdown)
break;
pReq = ataAsyncIOGetCurrentRequest(pCtl);
}
if (pReq == NULL)
continue;
ATAAIO ReqType = pReq->ReqType;
Log2(("%s: Ctl#%d: state=%d, req=%d\n", __FUNCTION__, ATACONTROLLER_IDX(pCtl), pCtl->uAsyncIOState, ReqType));
if (pCtl->uAsyncIOState != ReqType)
{
/* The new state is not the state that was expected by the normal
* state changes. This is either a RESET/ABORT or there's something
* really strange going on. */
if ( (pCtl->uAsyncIOState == ATA_AIO_PIO || pCtl->uAsyncIOState == ATA_AIO_DMA)
&& (ReqType == ATA_AIO_PIO || ReqType == ATA_AIO_DMA))
{
/* Incorrect sequence of PIO/DMA states. Dump request queue. */
ataAsyncIODumpRequests(pCtl);
}
AssertReleaseMsg(ReqType == ATA_AIO_RESET_ASSERTED || ReqType == ATA_AIO_RESET_CLEARED || ReqType == ATA_AIO_ABORT || pCtl->uAsyncIOState == ReqType, ("I/O state inconsistent: state=%d request=%d\n", pCtl->uAsyncIOState, ReqType));
}
/* Do our work. */
{
STAM_PROFILE_START(&pCtl->StatLockWait, a);
LogBird(("ata: %x: entering critsect\n", pCtl->IOPortBase1));
PDMCritSectEnter(&pCtl->lock, VINF_SUCCESS);
LogBird(("ata: %x: entered\n", pCtl->IOPortBase1));
STAM_PROFILE_STOP(&pCtl->StatLockWait, a);
}
if (pCtl->uAsyncIOState == ATA_AIO_NEW && !pCtl->fChainedTransfer)
{
u64TS = RTTimeNanoTS();
#if defined(DEBUG) || defined(VBOX_WITH_STATISTICS)
STAM_PROFILE_ADV_START(&pCtl->StatAsyncTime, a);
#endif /* DEBUG || VBOX_WITH_STATISTICS */
}
switch (ReqType)
{
case ATA_AIO_NEW:
pCtl->iAIOIf = pReq->u.t.iIf;
s = &pCtl->aIfs[pCtl->iAIOIf];
s->cbTotalTransfer = pReq->u.t.cbTotalTransfer;
s->uTxDir = pReq->u.t.uTxDir;
s->iBeginTransfer = pReq->u.t.iBeginTransfer;
s->iSourceSink = pReq->u.t.iSourceSink;
s->iIOBufferEnd = 0;
s->u64CmdTS = u64TS;
if (s->fATAPI)
{
if (pCtl->fChainedTransfer)
{
/* Only count the actual transfers, not the PIO
* transfer of the ATAPI command bytes. */
if (s->fDMA)
STAM_REL_COUNTER_INC(&s->StatATAPIDMA);
else
STAM_REL_COUNTER_INC(&s->StatATAPIPIO);
}
}
else
{
if (s->fDMA)
STAM_REL_COUNTER_INC(&s->StatATADMA);
else
STAM_REL_COUNTER_INC(&s->StatATAPIO);
}
pCtl->fChainedTransfer = false;
if (s->iBeginTransfer != ATAFN_BT_NULL)
{
Log2(("%s: Ctl#%d: calling begin transfer function\n", __FUNCTION__, ATACONTROLLER_IDX(pCtl)));
g_apfnBeginTransFuncs[s->iBeginTransfer](s);
s->iBeginTransfer = ATAFN_BT_NULL;
if (s->uTxDir != PDMBLOCKTXDIR_FROM_DEVICE)
s->iIOBufferEnd = s->cbElementaryTransfer;
}
else
{
s->cbElementaryTransfer = s->cbTotalTransfer;
s->iIOBufferEnd = s->cbTotalTransfer;
}
s->iIOBufferCur = 0;
if (s->uTxDir != PDMBLOCKTXDIR_TO_DEVICE)
{
if (s->iSourceSink != ATAFN_SS_NULL)
{
bool fRedo;
Log2(("%s: Ctl#%d: calling source/sink function\n", __FUNCTION__, ATACONTROLLER_IDX(pCtl)));
fRedo = g_apfnSourceSinkFuncs[s->iSourceSink](s);
pCtl->fRedo = fRedo;
if (RT_UNLIKELY(fRedo))
{
/* Operation failed at the initial transfer, restart
* everything from scratch by resending the current
* request. Occurs very rarely, not worth optimizing. */
LogRel(("%s: Ctl#%d: redo entire operation\n", __FUNCTION__, ATACONTROLLER_IDX(pCtl)));
ataAsyncIOPutRequest(pCtl, pReq);
ataSuspendRedo(pCtl);
break;
}
}
else
ataCmdOK(s, 0);
s->iIOBufferEnd = s->cbElementaryTransfer;
}
/* Do not go into the transfer phase if RESET is asserted.
* The CritSect is released while waiting for the host OS
* to finish the I/O, thus RESET is possible here. Most
* important: do not change uAsyncIOState. */
if (pCtl->fReset)
break;
if (s->fDMA)
{
if (s->cbTotalTransfer)
{
ataSetStatus(s, ATA_STAT_DRQ);
pCtl->uAsyncIOState = ATA_AIO_DMA;
/* If BMDMA is already started, do the transfer now. */
if (pCtl->BmDma.u8Cmd & BM_CMD_START)
{
Log2(("%s: Ctl#%d: message to async I/O thread, continuing DMA transfer immediately\n", __FUNCTION__, ATACONTROLLER_IDX(pCtl)));
ataAsyncIOPutRequest(pCtl, &ataDMARequest);
}
}
else
{
Assert(s->uTxDir == PDMBLOCKTXDIR_NONE); /* Any transfer which has an initial transfer size of 0 must be marked as such. */
/* Finish DMA transfer. */
ataDMATransferStop(s);
ataSetIRQ(s);
pCtl->uAsyncIOState = ATA_AIO_NEW;
}
}
else
{
if (s->cbTotalTransfer)
{
ataPIOTransfer(pCtl);
Assert(!pCtl->fRedo);
if (s->fATAPITransfer || s->uTxDir != PDMBLOCKTXDIR_TO_DEVICE)
ataSetIRQ(s);
if (s->uTxDir == PDMBLOCKTXDIR_TO_DEVICE || s->iSourceSink != ATAFN_SS_NULL)
{
/* Write operations and not yet finished transfers
* must be completed in the async I/O thread. */
pCtl->uAsyncIOState = ATA_AIO_PIO;
}
else
{
/* Finished read operation can be handled inline
* in the end of PIO transfer handling code. Linux
* depends on this, as it waits only briefly for
* devices to become ready after incoming data
* transfer. Cannot find anything in the ATA spec
* that backs this assumption, but as all kernels
* are affected (though most of the time it does
* not cause any harm) this must work. */
pCtl->uAsyncIOState = ATA_AIO_NEW;
}
}
else
{
Assert(s->uTxDir == PDMBLOCKTXDIR_NONE); /* Any transfer which has an initial transfer size of 0 must be marked as such. */
/* Finish PIO transfer. */
ataPIOTransfer(pCtl);
Assert(!pCtl->fRedo);
if (!s->fATAPITransfer)
ataSetIRQ(s);
pCtl->uAsyncIOState = ATA_AIO_NEW;
}
}
break;
case ATA_AIO_DMA:
{
BMDMAState *bm = &pCtl->BmDma;
s = &pCtl->aIfs[pCtl->iAIOIf]; /* Do not remove or there's an instant crash after loading the saved state */
ATAFNSS iOriginalSourceSink = (ATAFNSS)s->iSourceSink; /* Used by the hack below, but gets reset by then. */
if (s->uTxDir == PDMBLOCKTXDIR_FROM_DEVICE)
AssertRelease(bm->u8Cmd & BM_CMD_WRITE);
else
AssertRelease(!(bm->u8Cmd & BM_CMD_WRITE));
if (RT_LIKELY(!pCtl->fRedo))
{
/* The specs say that the descriptor table must not cross a
* 4K boundary. */
pCtl->pFirstDMADesc = bm->pvAddr;
pCtl->pLastDMADesc = RT_ALIGN_32(bm->pvAddr + 1, _4K) - sizeof(BMDMADesc);
}
ataDMATransfer(pCtl);
if (RT_UNLIKELY(pCtl->fRedo))
{
LogRel(("PIIX3 ATA: Ctl#%d: redo DMA operation\n", ATACONTROLLER_IDX(pCtl)));
ataAsyncIOPutRequest(pCtl, &ataDMARequest);
ataSuspendRedo(pCtl);
break;
}
/* The infamous delay IRQ hack. */
if ( iOriginalSourceSink == ATAFN_SS_WRITE_SECTORS
&& s->cbTotalTransfer == 0
&& pCtl->DelayIRQMillies)
{
/* Delay IRQ for writing. Required to get the Win2K
* installation work reliably (otherwise it crashes,
* usually during component install). So far no better
* solution has been found. */
Log(("%s: delay IRQ hack\n", __FUNCTION__));
PDMCritSectLeave(&pCtl->lock);
RTThreadSleep(pCtl->DelayIRQMillies);
PDMCritSectEnter(&pCtl->lock, VINF_SUCCESS);
}
ataUnsetStatus(s, ATA_STAT_DRQ);
Assert(!pCtl->fChainedTransfer);
Assert(s->iSourceSink == ATAFN_SS_NULL);
if (s->fATAPITransfer)
{
s->uATARegNSector = (s->uATARegNSector & ~7) | ATAPI_INT_REASON_IO | ATAPI_INT_REASON_CD;
Log2(("%s: Ctl#%d: interrupt reason %#04x\n", __FUNCTION__, ATACONTROLLER_IDX(pCtl), s->uATARegNSector));
s->fATAPITransfer = false;
}
ataSetIRQ(s);
pCtl->uAsyncIOState = ATA_AIO_NEW;
break;
}
case ATA_AIO_PIO:
s = &pCtl->aIfs[pCtl->iAIOIf]; /* Do not remove or there's an instant crash after loading the saved state */
if (s->iSourceSink != ATAFN_SS_NULL)
{
bool fRedo;
Log2(("%s: Ctl#%d: calling source/sink function\n", __FUNCTION__, ATACONTROLLER_IDX(pCtl)));
fRedo = g_apfnSourceSinkFuncs[s->iSourceSink](s);
pCtl->fRedo = fRedo;
if (RT_UNLIKELY(fRedo))
{
LogRel(("PIIX3 ATA: Ctl#%d: redo PIO operation\n", ATACONTROLLER_IDX(pCtl)));
ataAsyncIOPutRequest(pCtl, &ataPIORequest);
ataSuspendRedo(pCtl);
break;
}
s->iIOBufferCur = 0;
s->iIOBufferEnd = s->cbElementaryTransfer;
}
else
{
/* Continue a previously started transfer. */
ataUnsetStatus(s, ATA_STAT_BUSY);
ataSetStatus(s, ATA_STAT_READY);
}
/* It is possible that the drives on this controller get RESET
* during the above call to the source/sink function. If that's
* the case, don't restart the transfer and don't finish it the
* usual way. RESET handling took care of all that already.
* Most important: do not change uAsyncIOState. */
if (pCtl->fReset)
break;
if (s->cbTotalTransfer)
{
ataPIOTransfer(pCtl);
ataSetIRQ(s);
if (s->uTxDir == PDMBLOCKTXDIR_TO_DEVICE || s->iSourceSink != ATAFN_SS_NULL)
{
/* Write operations and not yet finished transfers
* must be completed in the async I/O thread. */
pCtl->uAsyncIOState = ATA_AIO_PIO;
}
else
{
/* Finished read operation can be handled inline
* in the end of PIO transfer handling code. Linux
* depends on this, as it waits only briefly for
* devices to become ready after incoming data
* transfer. Cannot find anything in the ATA spec
* that backs this assumption, but as all kernels
* are affected (though most of the time it does
* not cause any harm) this must work. */
pCtl->uAsyncIOState = ATA_AIO_NEW;
}
}
else
{
/* Finish PIO transfer. */
ataPIOTransfer(pCtl);
if ( !pCtl->fChainedTransfer
&& !s->fATAPITransfer
&& s->uTxDir != PDMBLOCKTXDIR_FROM_DEVICE)
{
ataSetIRQ(s);
}
pCtl->uAsyncIOState = ATA_AIO_NEW;
}
break;
case ATA_AIO_RESET_ASSERTED:
pCtl->uAsyncIOState = ATA_AIO_RESET_CLEARED;
ataPIOTransferStop(&pCtl->aIfs[0]);
ataPIOTransferStop(&pCtl->aIfs[1]);
/* Do not change the DMA registers, they are not affected by the
* ATA controller reset logic. It should be sufficient to issue a
* new command, which is now possible as the state is cleared. */
break;
case ATA_AIO_RESET_CLEARED:
pCtl->uAsyncIOState = ATA_AIO_NEW;
pCtl->fReset = false;
LogRel(("PIIX3 ATA: Ctl#%d: finished processing RESET\n",
ATACONTROLLER_IDX(pCtl)));
for (uint32_t i = 0; i < RT_ELEMENTS(pCtl->aIfs); i++)
{
if (pCtl->aIfs[i].fATAPI)
ataSetStatusValue(&pCtl->aIfs[i], 0); /* NOTE: READY is _not_ set */
else
ataSetStatusValue(&pCtl->aIfs[i], ATA_STAT_READY | ATA_STAT_SEEK);
ataSetSignature(&pCtl->aIfs[i]);
}
break;
case ATA_AIO_ABORT:
/* Abort the current command only if it operates on the same interface. */
if (pCtl->iAIOIf == pReq->u.a.iIf)
{
s = &pCtl->aIfs[pCtl->iAIOIf];
pCtl->uAsyncIOState = ATA_AIO_NEW;
/* Do not change the DMA registers, they are not affected by the
* ATA controller reset logic. It should be sufficient to issue a
* new command, which is now possible as the state is cleared. */
if (pReq->u.a.fResetDrive)
{
ataResetDevice(s);
ataExecuteDeviceDiagnosticSS(s);
}
else
{
ataPIOTransferStop(s);
ataUnsetStatus(s, ATA_STAT_BUSY | ATA_STAT_DRQ | ATA_STAT_SEEK | ATA_STAT_ERR);
ataSetStatus(s, ATA_STAT_READY);
ataSetIRQ(s);
}
}
break;
default:
AssertMsgFailed(("Undefined async I/O state %d\n", pCtl->uAsyncIOState));
}
ataAsyncIORemoveCurrentRequest(pCtl, ReqType);
pReq = ataAsyncIOGetCurrentRequest(pCtl);
if (pCtl->uAsyncIOState == ATA_AIO_NEW && !pCtl->fChainedTransfer)
{
#if defined(DEBUG) || defined(VBOX_WITH_STATISTICS)
STAM_PROFILE_ADV_STOP(&pCtl->StatAsyncTime, a);
#endif /* DEBUG || VBOX_WITH_STATISTICS */
u64TS = RTTimeNanoTS() - u64TS;
uWait = u64TS / 1000;
Log(("%s: Ctl#%d: LUN#%d finished I/O transaction in %d microseconds\n", __FUNCTION__, ATACONTROLLER_IDX(pCtl), pCtl->aIfs[pCtl->iAIOIf].iLUN, (uint32_t)(uWait)));
/* Mark command as finished. */
pCtl->aIfs[pCtl->iAIOIf].u64CmdTS = 0;
/*
* Release logging of command execution times depends on the
* command type. ATAPI commands often take longer (due to CD/DVD
* spin up time etc.) so the threshold is different.
*/
if (pCtl->aIfs[pCtl->iAIOIf].uATARegCommand != ATA_PACKET)
{
if (uWait > 8 * 1000 * 1000)
{
/*
* Command took longer than 8 seconds. This is close
* enough or over the guest's command timeout, so place
* an entry in the release log to allow tracking such
* timing errors (which are often caused by the host).
*/
LogRel(("PIIX3 ATA: execution time for ATA command %#04x was %d seconds\n", pCtl->aIfs[pCtl->iAIOIf].uATARegCommand, uWait / (1000 * 1000)));
}
}
else
{
if (uWait > 20 * 1000 * 1000)
{
/*
* Command took longer than 20 seconds. This is close
* enough or over the guest's command timeout, so place
* an entry in the release log to allow tracking such
* timing errors (which are often caused by the host).
*/
LogRel(("PIIX3 ATA: execution time for ATAPI command %#04x was %d seconds\n", pCtl->aIfs[pCtl->iAIOIf].aATAPICmd[0], uWait / (1000 * 1000)));
}
}
#if defined(DEBUG) || defined(VBOX_WITH_STATISTICS)
if (uWait < pCtl->StatAsyncMinWait || !pCtl->StatAsyncMinWait)
pCtl->StatAsyncMinWait = uWait;
if (uWait > pCtl->StatAsyncMaxWait)
pCtl->StatAsyncMaxWait = uWait;
STAM_COUNTER_ADD(&pCtl->StatAsyncTimeUS, uWait);
STAM_COUNTER_INC(&pCtl->StatAsyncOps);
#endif /* DEBUG || VBOX_WITH_STATISTICS */
}
LogBird(("ata: %x: leaving critsect\n", pCtl->IOPortBase1));
PDMCritSectLeave(&pCtl->lock);
}
/* Cleanup the state. */
if (pCtl->AsyncIOSem)
{
RTSemEventDestroy(pCtl->AsyncIOSem);
pCtl->AsyncIOSem = NIL_RTSEMEVENT;
}
if (pCtl->SuspendIOSem)
{
RTSemEventDestroy(pCtl->SuspendIOSem);
pCtl->SuspendIOSem = NIL_RTSEMEVENT;
}
/* Do not destroy request mutex yet, still needed for proper shutdown. */
pCtl->fShutdown = false;
/* This must be last, as it also signals thread exit to EMT. */
pCtl->AsyncIOThread = NIL_RTTHREAD;
Log2(("%s: Ctl#%d: return %Rrc\n", __FUNCTION__, ATACONTROLLER_IDX(pCtl), rc));
return rc;
}
#endif /* IN_RING3 */
static uint32_t ataBMDMACmdReadB(PATACONTROLLER pCtl, uint32_t addr)
{
uint32_t val = pCtl->BmDma.u8Cmd;
Log2(("%s: addr=%#06x val=%#04x\n", __FUNCTION__, addr, val));
return val;
}
static void ataBMDMACmdWriteB(PATACONTROLLER pCtl, uint32_t addr, uint32_t val)
{
Log2(("%s: addr=%#06x val=%#04x\n", __FUNCTION__, addr, val));
if (!(val & BM_CMD_START))
{
pCtl->BmDma.u8Status &= ~BM_STATUS_DMAING;
pCtl->BmDma.u8Cmd = val & (BM_CMD_START | BM_CMD_WRITE);
}
else
{
#ifdef IN_RING3
/* Check whether the guest OS wants to change DMA direction in
* mid-flight. Not allowed, according to the PIIX3 specs. */
Assert(!(pCtl->BmDma.u8Status & BM_STATUS_DMAING) || !((val ^ pCtl->BmDma.u8Cmd) & 0x04));
pCtl->BmDma.u8Status |= BM_STATUS_DMAING;
pCtl->BmDma.u8Cmd = val & (BM_CMD_START | BM_CMD_WRITE);
/* Do not continue DMA transfers while the RESET line is asserted. */
if (pCtl->fReset)
{
Log2(("%s: Ctl#%d: suppressed continuing DMA transfer as RESET is active\n", __FUNCTION__, ATACONTROLLER_IDX(pCtl)));
return;
}
/* Do not start DMA transfers if there's a PIO transfer going on. */
if (!pCtl->aIfs[pCtl->iSelectedIf].fDMA)
return;
if (pCtl->aIfs[pCtl->iAIOIf].uATARegStatus & ATA_STAT_DRQ)
{
Log2(("%s: Ctl#%d: message to async I/O thread, continuing DMA transfer\n", __FUNCTION__, ATACONTROLLER_IDX(pCtl)));
ataAsyncIOPutRequest(pCtl, &ataDMARequest);
}
#else /* !IN_RING3 */
AssertMsgFailed(("DMA START handling is too complicated for GC\n"));
#endif /* IN_RING3 */
}
}
static uint32_t ataBMDMAStatusReadB(PATACONTROLLER pCtl, uint32_t addr)
{
uint32_t val = pCtl->BmDma.u8Status;
Log2(("%s: addr=%#06x val=%#04x\n", __FUNCTION__, addr, val));
return val;
}
static void ataBMDMAStatusWriteB(PATACONTROLLER pCtl, uint32_t addr, uint32_t val)
{
Log2(("%s: addr=%#06x val=%#04x\n", __FUNCTION__, addr, val));
pCtl->BmDma.u8Status = (val & (BM_STATUS_D0DMA | BM_STATUS_D1DMA))
| (pCtl->BmDma.u8Status & BM_STATUS_DMAING)
| (pCtl->BmDma.u8Status & ~val & (BM_STATUS_ERROR | BM_STATUS_INT));
}
static uint32_t ataBMDMAAddrReadL(PATACONTROLLER pCtl, uint32_t addr)
{
uint32_t val = (uint32_t)pCtl->BmDma.pvAddr;
Log2(("%s: addr=%#06x val=%#010x\n", __FUNCTION__, addr, val));
return val;
}
static void ataBMDMAAddrWriteL(PATACONTROLLER pCtl, uint32_t addr, uint32_t val)
{
Log2(("%s: addr=%#06x val=%#010x\n", __FUNCTION__, addr, val));
pCtl->BmDma.pvAddr = val & ~3;
}
static void ataBMDMAAddrWriteLowWord(PATACONTROLLER pCtl, uint32_t addr, uint32_t val)
{
Log2(("%s: addr=%#06x val=%#010x\n", __FUNCTION__, addr, val));
pCtl->BmDma.pvAddr = (pCtl->BmDma.pvAddr & 0xFFFF0000) | RT_LOWORD(val & ~3);
}
static void ataBMDMAAddrWriteHighWord(PATACONTROLLER pCtl, uint32_t addr, uint32_t val)
{
Log2(("%s: addr=%#06x val=%#010x\n", __FUNCTION__, addr, val));
pCtl->BmDma.pvAddr = (RT_LOWORD(val) << 16) | RT_LOWORD(pCtl->BmDma.pvAddr);
}
#define VAL(port, size) ( ((port) & 7) | ((size) << 3) )
/**
* Port I/O Handler for bus master DMA IN operations.
* @see FNIOMIOPORTIN for details.
*/
PDMBOTHCBDECL(int) ataBMDMAIOPortRead(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t *pu32, unsigned cb)
{
uint32_t i = (uint32_t)(uintptr_t)pvUser;
PCIATAState *pThis = PDMINS_2_DATA(pDevIns, PCIATAState *);
PATACONTROLLER pCtl = &pThis->aCts[i];
int rc;
rc = PDMCritSectEnter(&pCtl->lock, VINF_IOM_HC_IOPORT_READ);
if (rc != VINF_SUCCESS)
return rc;
switch (VAL(Port, cb))
{
case VAL(0, 1): *pu32 = ataBMDMACmdReadB(pCtl, Port); break;
case VAL(0, 2): *pu32 = ataBMDMACmdReadB(pCtl, Port); break;
case VAL(2, 1): *pu32 = ataBMDMAStatusReadB(pCtl, Port); break;
case VAL(2, 2): *pu32 = ataBMDMAStatusReadB(pCtl, Port); break;
case VAL(4, 4): *pu32 = ataBMDMAAddrReadL(pCtl, Port); break;
case VAL(0, 4):
/* The SCO OpenServer tries to read 4 bytes starting from offset 0. */
*pu32 = ataBMDMACmdReadB(pCtl, Port) | (ataBMDMAStatusReadB(pCtl, Port) << 16);
break;
default:
AssertMsgFailed(("%s: Unsupported read from port %x size=%d\n", __FUNCTION__, Port, cb));
PDMCritSectLeave(&pCtl->lock);
return VERR_IOM_IOPORT_UNUSED;
}
PDMCritSectLeave(&pCtl->lock);
return rc;
}
/**
* Port I/O Handler for bus master DMA OUT operations.
* @see FNIOMIOPORTOUT for details.
*/
PDMBOTHCBDECL(int) ataBMDMAIOPortWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb)
{
uint32_t i = (uint32_t)(uintptr_t)pvUser;
PCIATAState *pThis = PDMINS_2_DATA(pDevIns, PCIATAState *);
PATACONTROLLER pCtl = &pThis->aCts[i];
int rc;
rc = PDMCritSectEnter(&pCtl->lock, VINF_IOM_HC_IOPORT_WRITE);
if (rc != VINF_SUCCESS)
return rc;
switch (VAL(Port, cb))
{
case VAL(0, 1):
#ifndef IN_RING3
if (u32 & BM_CMD_START)
{
rc = VINF_IOM_HC_IOPORT_WRITE;
break;
}
#endif /* !IN_RING3 */
ataBMDMACmdWriteB(pCtl, Port, u32);
break;
case VAL(2, 1): ataBMDMAStatusWriteB(pCtl, Port, u32); break;
case VAL(4, 4): ataBMDMAAddrWriteL(pCtl, Port, u32); break;
case VAL(4, 2): ataBMDMAAddrWriteLowWord(pCtl, Port, u32); break;
case VAL(6, 2): ataBMDMAAddrWriteHighWord(pCtl, Port, u32); break;
default: AssertMsgFailed(("%s: Unsupported write to port %x size=%d val=%x\n", __FUNCTION__, Port, cb, u32)); break;
}
PDMCritSectLeave(&pCtl->lock);
return rc;
}
#undef VAL
#ifdef IN_RING3
/**
* Callback function for mapping an PCI I/O region.
*
* @return VBox status code.
* @param pPciDev Pointer to PCI device. Use pPciDev->pDevIns to get the device instance.
* @param iRegion The region number.
* @param GCPhysAddress Physical address of the region. If iType is PCI_ADDRESS_SPACE_IO, this is an
* I/O port, else it's a physical address.
* This address is *NOT* relative to pci_mem_base like earlier!
* @param enmType One of the PCI_ADDRESS_SPACE_* values.
*/
static DECLCALLBACK(int) ataBMDMAIORangeMap(PPCIDEVICE pPciDev, /*unsigned*/ int iRegion, RTGCPHYS GCPhysAddress, uint32_t cb, PCIADDRESSSPACE enmType)
{
PCIATAState *pThis = PCIDEV_2_PCIATASTATE(pPciDev);
int rc = VINF_SUCCESS;
Assert(enmType == PCI_ADDRESS_SPACE_IO);
Assert(iRegion == 4);
AssertMsg(RT_ALIGN(GCPhysAddress, 8) == GCPhysAddress, ("Expected 8 byte alignment. GCPhysAddress=%#x\n", GCPhysAddress));
/* Register the port range. */
for (uint32_t i = 0; i < RT_ELEMENTS(pThis->aCts); i++)
{
int rc2 = PDMDevHlpIOPortRegister(pPciDev->pDevIns, (RTIOPORT)GCPhysAddress + i * 8, 8,
(RTHCPTR)i, ataBMDMAIOPortWrite, ataBMDMAIOPortRead, NULL, NULL, "ATA Bus Master DMA");
AssertRC(rc2);
if (rc2 < rc)
rc = rc2;
if (pThis->fGCEnabled)
{
rc2 = PDMDevHlpIOPortRegisterGC(pPciDev->pDevIns, (RTIOPORT)GCPhysAddress + i * 8, 8,
(RTGCPTR)i, "ataBMDMAIOPortWrite", "ataBMDMAIOPortRead", NULL, NULL, "ATA Bus Master DMA");
AssertRC(rc2);
if (rc2 < rc)
rc = rc2;
}
if (pThis->fR0Enabled)
{
rc2 = PDMDevHlpIOPortRegisterR0(pPciDev->pDevIns, (RTIOPORT)GCPhysAddress + i * 8, 8,
(RTR0PTR)i, "ataBMDMAIOPortWrite", "ataBMDMAIOPortRead", NULL, NULL, "ATA Bus Master DMA");
AssertRC(rc2);
if (rc2 < rc)
rc = rc2;
}
}
return rc;
}
/**
* Reset notification.
*
* @returns VBox status.
* @param pDevIns The device instance data.
*/
static DECLCALLBACK(void) ataReset(PPDMDEVINS pDevIns)
{
PCIATAState *pThis = PDMINS_2_DATA(pDevIns, PCIATAState *);
for (uint32_t i = 0; i < RT_ELEMENTS(pThis->aCts); i++)
{
pThis->aCts[i].iSelectedIf = 0;
pThis->aCts[i].iAIOIf = 0;
pThis->aCts[i].BmDma.u8Cmd = 0;
/* Report that both drives present on the bus are in DMA mode. This
* pretends that there is a BIOS that has set it up. Normal reset
* default is 0x00. */
pThis->aCts[i].BmDma.u8Status = (pThis->aCts[i].aIfs[0].pDrvBase != NULL ? BM_STATUS_D0DMA : 0)
| (pThis->aCts[i].aIfs[1].pDrvBase != NULL ? BM_STATUS_D1DMA : 0);
pThis->aCts[i].BmDma.pvAddr = 0;
pThis->aCts[i].fReset = true;
pThis->aCts[i].fRedo = false;
pThis->aCts[i].fRedoIdle = false;
ataAsyncIOClearRequests(&pThis->aCts[i]);
Log2(("%s: Ctl#%d: message to async I/O thread, reset controller\n", __FUNCTION__, i));
ataAsyncIOPutRequest(&pThis->aCts[i], &ataResetARequest);
ataAsyncIOPutRequest(&pThis->aCts[i], &ataResetCRequest);
if (!ataWaitForAsyncIOIsIdle(&pThis->aCts[i], 30000))
{
VMSetRuntimeError(PDMDevHlpGetVM(pDevIns),
false, "DevATA_ASYNCBUSY",
N_("The IDE async I/O thread remained busy after a reset, usually a host filesystem performance problem\n"));
AssertMsgFailed(("Async I/O thread busy after reset\n"));
}
for (uint32_t j = 0; j < RT_ELEMENTS(pThis->aCts[i].aIfs); j++)
ataResetDevice(&pThis->aCts[i].aIfs[j]);
}
}
/* -=-=-=-=-=- PCIATAState::IBase -=-=-=-=-=- */
/**
* Queries an interface to the driver.
*
* @returns Pointer to interface.
* @returns NULL if the interface was not supported by the device.
* @param pInterface Pointer to ATADevState::IBase.
* @param enmInterface The requested interface identification.
*/
static DECLCALLBACK(void *) ataStatus_QueryInterface(PPDMIBASE pInterface, PDMINTERFACE enmInterface)
{
PCIATAState *pThis = PDMIBASE_2_PCIATASTATE(pInterface);
switch (enmInterface)
{
case PDMINTERFACE_BASE:
return &pThis->IBase;
case PDMINTERFACE_LED_PORTS:
return &pThis->ILeds;
default:
return NULL;
}
}
/* -=-=-=-=-=- PCIATAState::ILeds -=-=-=-=-=- */
/**
* Gets the pointer to the status LED of a unit.
*
* @returns VBox status code.
* @param pInterface Pointer to the interface structure containing the called function pointer.
* @param iLUN The unit which status LED we desire.
* @param ppLed Where to store the LED pointer.
*/
static DECLCALLBACK(int) ataStatus_QueryStatusLed(PPDMILEDPORTS pInterface, unsigned iLUN, PPDMLED *ppLed)
{
PCIATAState *pThis = PDMILEDPORTS_2_PCIATASTATE(pInterface);
if (iLUN < 4)
{
switch (iLUN)
{
case 0: *ppLed = &pThis->aCts[0].aIfs[0].Led; break;
case 1: *ppLed = &pThis->aCts[0].aIfs[1].Led; break;
case 2: *ppLed = &pThis->aCts[1].aIfs[0].Led; break;
case 3: *ppLed = &pThis->aCts[1].aIfs[1].Led; break;
}
Assert((*ppLed)->u32Magic == PDMLED_MAGIC);
return VINF_SUCCESS;
}
return VERR_PDM_LUN_NOT_FOUND;
}
/* -=-=-=-=-=- ATADevState::IBase -=-=-=-=-=- */
/**
* Queries an interface to the driver.
*
* @returns Pointer to interface.
* @returns NULL if the interface was not supported by the device.
* @param pInterface Pointer to ATADevState::IBase.
* @param enmInterface The requested interface identification.
*/
static DECLCALLBACK(void *) ataQueryInterface(PPDMIBASE pInterface, PDMINTERFACE enmInterface)
{
ATADevState *pIf = PDMIBASE_2_ATASTATE(pInterface);
switch (enmInterface)
{
case PDMINTERFACE_BASE:
return &pIf->IBase;
case PDMINTERFACE_BLOCK_PORT:
return &pIf->IPort;
case PDMINTERFACE_MOUNT_NOTIFY:
return &pIf->IMountNotify;
default:
return NULL;
}
}
#endif /* IN_RING3 */
/* -=-=-=-=-=- Wrappers -=-=-=-=-=- */
/**
* Port I/O Handler for primary port range OUT operations.
* @see FNIOMIOPORTOUT for details.
*/
PDMBOTHCBDECL(int) ataIOPortWrite1(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb)
{
uint32_t i = (uint32_t)(uintptr_t)pvUser;
PCIATAState *pThis = PDMINS_2_DATA(pDevIns, PCIATAState *);
PATACONTROLLER pCtl = &pThis->aCts[i];
int rc = VINF_SUCCESS;
Assert(i < 2);
rc = PDMCritSectEnter(&pCtl->lock, VINF_IOM_HC_IOPORT_WRITE);
if (rc != VINF_SUCCESS)
return rc;
if (cb == 1)
rc = ataIOPortWriteU8(pCtl, Port, u32);
else if (Port == pCtl->IOPortBase1)
{
Assert(cb == 2 || cb == 4);
rc = ataDataWrite(pCtl, Port, cb, (const uint8_t *)&u32);
}
else
AssertMsgFailed(("ataIOPortWrite1: unsupported write to port %x val=%x size=%d\n", Port, u32, cb));
LogBird(("ata: leaving critsect\n"));
PDMCritSectLeave(&pCtl->lock);
LogBird(("ata: left critsect\n"));
return rc;
}
/**
* Port I/O Handler for primary port range IN operations.
* @see FNIOMIOPORTIN for details.
*/
PDMBOTHCBDECL(int) ataIOPortRead1(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t *pu32, unsigned cb)
{
uint32_t i = (uint32_t)(uintptr_t)pvUser;
PCIATAState *pThis = PDMINS_2_DATA(pDevIns, PCIATAState *);
PATACONTROLLER pCtl = &pThis->aCts[i];
int rc = VINF_SUCCESS;
Assert(i < 2);
rc = PDMCritSectEnter(&pCtl->lock, VINF_IOM_HC_IOPORT_READ);
if (rc != VINF_SUCCESS)
return rc;
if (cb == 1)
{
rc = ataIOPortReadU8(pCtl, Port, pu32);
}
else if (Port == pCtl->IOPortBase1)
{
Assert(cb == 2 || cb == 4);
rc = ataDataRead(pCtl, Port, cb, (uint8_t *)pu32);
if (cb == 2)
*pu32 &= 0xffff;
}
else
{
AssertMsgFailed(("ataIOPortRead1: unsupported read from port %x size=%d\n", Port, cb));
rc = VERR_IOM_IOPORT_UNUSED;
}
PDMCritSectLeave(&pCtl->lock);
return rc;
}
#ifndef IN_RING0
/**
* Port I/O Handler for primary port range IN string operations.
* @see FNIOMIOPORTINSTRING for details.
*/
PDMBOTHCBDECL(int) ataIOPortReadStr1(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, RTGCPTR *pGCPtrDst, PRTGCUINTREG pcTransfer, unsigned cb)
{
uint32_t i = (uint32_t)(uintptr_t)pvUser;
PCIATAState *pThis = PDMINS_2_DATA(pDevIns, PCIATAState *);
PATACONTROLLER pCtl = &pThis->aCts[i];
int rc = VINF_SUCCESS;
Assert(i < 2);
rc = PDMCritSectEnter(&pCtl->lock, VINF_IOM_HC_IOPORT_READ);
if (rc != VINF_SUCCESS)
return rc;
if (Port == pCtl->IOPortBase1)
{
uint32_t cTransAvailable, cTransfer = *pcTransfer, cbTransfer;
RTGCPTR GCDst = *pGCPtrDst;
ATADevState *s = &pCtl->aIfs[pCtl->iSelectedIf];
Assert(cb == 2 || cb == 4);
cTransAvailable = (s->iIOBufferPIODataEnd - s->iIOBufferPIODataStart) / cb;
#ifndef IN_RING3
/* The last transfer unit cannot be handled in GC, as it involves thread communication. */
cTransAvailable--;
#endif /* !IN_RING3 */
/* Do not handle the dummy transfer stuff here, leave it to the single-word transfers.
* They are not performance-critical and generally shouldn't occur at all. */
if (cTransAvailable > cTransfer)
cTransAvailable = cTransfer;
cbTransfer = cTransAvailable * cb;
#ifdef IN_RC
for (uint32_t i = 0; i < cbTransfer; i += cb)
MMGCRamWriteNoTrapHandler((char *)GCDst + i, s->CTX_SUFF(pbIOBuffer) + s->iIOBufferPIODataStart + i, cb);
#else /* !IN_RC */
rc = PGMPhysSimpleDirtyWriteGCPtr(PDMDevHlpGetVM(pDevIns), GCDst, s->CTX_SUFF(pbIOBuffer) + s->iIOBufferPIODataStart, cbTransfer);
Assert(rc == VINF_SUCCESS);
#endif /* IN_RC */
if (cbTransfer)
Log3(("%s: addr=%#x val=%.*Rhxs\n", __FUNCTION__, Port, cbTransfer, s->CTX_SUFF(pbIOBuffer) + s->iIOBufferPIODataStart));
s->iIOBufferPIODataStart += cbTransfer;
*pGCPtrDst = (RTGCPTR)((RTGCUINTPTR)GCDst + cbTransfer);
*pcTransfer = cTransfer - cTransAvailable;
#ifdef IN_RING3
if (s->iIOBufferPIODataStart >= s->iIOBufferPIODataEnd)
ataPIOTransferFinish(pCtl, s);
#endif /* IN_RING3 */
}
PDMCritSectLeave(&pCtl->lock);
return rc;
}
/**
* Port I/O Handler for primary port range OUT string operations.
* @see FNIOMIOPORTOUTSTRING for details.
*/
PDMBOTHCBDECL(int) ataIOPortWriteStr1(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, RTGCPTR *pGCPtrSrc, PRTGCUINTREG pcTransfer, unsigned cb)
{
uint32_t i = (uint32_t)(uintptr_t)pvUser;
PCIATAState *pThis = PDMINS_2_DATA(pDevIns, PCIATAState *);
PATACONTROLLER pCtl = &pThis->aCts[i];
int rc;
Assert(i < 2);
rc = PDMCritSectEnter(&pCtl->lock, VINF_IOM_HC_IOPORT_WRITE);
if (rc != VINF_SUCCESS)
return rc;
if (Port == pCtl->IOPortBase1)
{
uint32_t cTransAvailable, cTransfer = *pcTransfer, cbTransfer;
RTGCPTR GCSrc = *pGCPtrSrc;
ATADevState *s = &pCtl->aIfs[pCtl->iSelectedIf];
Assert(cb == 2 || cb == 4);
cTransAvailable = (s->iIOBufferPIODataEnd - s->iIOBufferPIODataStart) / cb;
#ifndef IN_RING3
/* The last transfer unit cannot be handled in GC, as it involves thread communication. */
cTransAvailable--;
#endif /* !IN_RING3 */
/* Do not handle the dummy transfer stuff here, leave it to the single-word transfers.
* They are not performance-critical and generally shouldn't occur at all. */
if (cTransAvailable > cTransfer)
cTransAvailable = cTransfer;
cbTransfer = cTransAvailable * cb;
#ifdef IN_RC
for (uint32_t i = 0; i < cbTransfer; i += cb)
MMGCRamReadNoTrapHandler(s->CTX_SUFF(pbIOBuffer) + s->iIOBufferPIODataStart + i, (char *)GCSrc + i, cb);
#else /* !IN_RC */
rc = PGMPhysSimpleReadGCPtr(PDMDevHlpGetVM(pDevIns), s->CTX_SUFF(pbIOBuffer) + s->iIOBufferPIODataStart, GCSrc, cbTransfer);
Assert(rc == VINF_SUCCESS);
#endif /* IN_RC */
if (cbTransfer)
Log3(("%s: addr=%#x val=%.*Rhxs\n", __FUNCTION__, Port, cbTransfer, s->CTX_SUFF(pbIOBuffer) + s->iIOBufferPIODataStart));
s->iIOBufferPIODataStart += cbTransfer;
*pGCPtrSrc = (RTGCPTR)((RTGCUINTPTR)GCSrc + cbTransfer);
*pcTransfer = cTransfer - cTransAvailable;
#ifdef IN_RING3
if (s->iIOBufferPIODataStart >= s->iIOBufferPIODataEnd)
ataPIOTransferFinish(pCtl, s);
#endif /* IN_RING3 */
}
PDMCritSectLeave(&pCtl->lock);
return rc;
}
#endif /* !IN_RING0 */
/**
* Port I/O Handler for secondary port range OUT operations.
* @see FNIOMIOPORTOUT for details.
*/
PDMBOTHCBDECL(int) ataIOPortWrite2(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb)
{
uint32_t i = (uint32_t)(uintptr_t)pvUser;
PCIATAState *pThis = PDMINS_2_DATA(pDevIns, PCIATAState *);
PATACONTROLLER pCtl = &pThis->aCts[i];
int rc;
Assert(i < 2);
if (cb != 1)
return VINF_SUCCESS;
rc = PDMCritSectEnter(&pCtl->lock, VINF_IOM_HC_IOPORT_WRITE);
if (rc != VINF_SUCCESS)
return rc;
rc = ataControlWrite(pCtl, Port, u32);
PDMCritSectLeave(&pCtl->lock);
return rc;
}
/**
* Port I/O Handler for secondary port range IN operations.
* @see FNIOMIOPORTIN for details.
*/
PDMBOTHCBDECL(int) ataIOPortRead2(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t *pu32, unsigned cb)
{
uint32_t i = (uint32_t)(uintptr_t)pvUser;
PCIATAState *pThis = PDMINS_2_DATA(pDevIns, PCIATAState *);
PATACONTROLLER pCtl = &pThis->aCts[i];
int rc;
Assert(i < 2);
if (cb != 1)
return VERR_IOM_IOPORT_UNUSED;
rc = PDMCritSectEnter(&pCtl->lock, VINF_IOM_HC_IOPORT_READ);
if (rc != VINF_SUCCESS)
return rc;
*pu32 = ataStatusRead(pCtl, Port);
PDMCritSectLeave(&pCtl->lock);
return VINF_SUCCESS;
}
#ifdef IN_RING3
/**
* Waits for all async I/O threads to complete whatever they
* are doing at the moment.
*
* @returns true on success.
* @returns false when one or more threads is still processing.
* @param pThis Pointer to the instance data.
* @param cMillies How long to wait (total).
*/
static bool ataWaitForAllAsyncIOIsIdle(PPDMDEVINS pDevIns, unsigned cMillies)
{
PCIATAState *pThis = PDMINS_2_DATA(pDevIns, PCIATAState *);
bool fVMLocked;
uint64_t u64Start;
PATACONTROLLER pCtl;
bool fAllIdle = false;
/* The only way to deal cleanly with the VM lock is to check whether
* it is owned now (it always is owned by EMT, which is the current
* thread). Since this function is called several times during VM
* shutdown, and the VM lock is only held for the first call (which
* can be either from ataPowerOff or ataSuspend), there is no other
* reasonable solution. */
fVMLocked = VMMR3LockIsOwner(PDMDevHlpGetVM(pDevIns));
if (fVMLocked)
pDevIns->pDevHlpR3->pfnUnlockVM(pDevIns);
/*
* Wait for any pending async operation to finish
*/
u64Start = RTTimeMilliTS();
for (;;)
{
/* Check all async I/O threads. */
fAllIdle = true;
for (uint32_t i = 0; i < RT_ELEMENTS(pThis->aCts); i++)
{
pCtl = &pThis->aCts[i];
/*
* Only check if the thread is idling if the request mutex is set up.
* It is possible that the creation of the first controller failed and that
* the request mutex is not initialized on the second one yet
* But it would be called without the following check.
*/
if (pCtl->AsyncIORequestMutex != NIL_RTSEMEVENT)
{
fAllIdle &= ataAsyncIOIsIdle(pCtl, false);
if (!fAllIdle)
break;
}
}
if ( fAllIdle
|| RTTimeMilliTS() - u64Start >= cMillies)
break;
/* Sleep for a bit. */
RTThreadSleep(100);
}
if (fVMLocked)
pDevIns->pDevHlpR3->pfnLockVM(pDevIns);
if (!fAllIdle)
LogRel(("PIIX3 ATA: Ctl#%d is still executing, DevSel=%d AIOIf=%d CmdIf0=%#04x CmdIf1=%#04x\n",
ATACONTROLLER_IDX(pCtl), pCtl->iSelectedIf, pCtl->iAIOIf,
pCtl->aIfs[0].uATARegCommand, pCtl->aIfs[1].uATARegCommand));
return fAllIdle;
}
DECLINLINE(void) ataRelocBuffer(PPDMDEVINS pDevIns, ATADevState *s)
{
if (s->pbIOBufferR3)
s->pbIOBufferRC = MMHyperR3ToRC(PDMDevHlpGetVM(pDevIns), s->pbIOBufferR3);
}
/**
* @copydoc FNPDMDEVRELOCATE
*/
static DECLCALLBACK(void) ataRelocate(PPDMDEVINS pDevIns, RTGCINTPTR offDelta)
{
PCIATAState *pThis = PDMINS_2_DATA(pDevIns, PCIATAState *);
for (uint32_t i = 0; i < RT_ELEMENTS(pThis->aCts); i++)
{
pThis->aCts[i].pDevInsRC += offDelta;
pThis->aCts[i].aIfs[0].pDevInsRC += offDelta;
pThis->aCts[i].aIfs[0].pControllerRC += offDelta;
ataRelocBuffer(pDevIns, &pThis->aCts[i].aIfs[0]);
pThis->aCts[i].aIfs[1].pDevInsRC += offDelta;
pThis->aCts[i].aIfs[1].pControllerRC += offDelta;
ataRelocBuffer(pDevIns, &pThis->aCts[i].aIfs[1]);
}
}
/**
* Destroy a driver instance.
*
* Most VM resources are freed by the VM. This callback is provided so that any non-VM
* resources can be freed correctly.
*
* @param pDevIns The device instance data.
*/
static DECLCALLBACK(int) ataDestruct(PPDMDEVINS pDevIns)
{
PCIATAState *pThis = PDMINS_2_DATA(pDevIns, PCIATAState *);
int rc;
Log(("%s:\n", __FUNCTION__));
/*
* Terminate all async helper threads
*/
for (uint32_t i = 0; i < RT_ELEMENTS(pThis->aCts); i++)
{
if (pThis->aCts[i].AsyncIOThread != NIL_RTTHREAD)
{
ASMAtomicXchgU32(&pThis->aCts[i].fShutdown, true);
rc = RTSemEventSignal(pThis->aCts[i].AsyncIOSem);
AssertRC(rc);
}
}
/*
* Wait for them to complete whatever they are doing and then
* for them to terminate.
*/
if (ataWaitForAllAsyncIOIsIdle(pDevIns, 20000))
{
for (unsigned i = 0; i < RT_ELEMENTS(pThis->aCts); i++)
{
rc = RTThreadWait(pThis->aCts[i].AsyncIOThread, 30000 /* 30 s*/, NULL);
AssertMsgRC(rc || rc == VERR_INVALID_HANDLE, ("rc=%Rrc i=%d\n", rc, i));
}
}
else
AssertMsgFailed(("Async I/O is still busy!\n"));
/*
* Now the request mutexes are no longer needed. Free resources.
*/
for (uint32_t i = 0; i < RT_ELEMENTS(pThis->aCts); i++)
{
if (pThis->aCts[i].AsyncIORequestMutex != NIL_RTSEMEVENT)
{
RTSemMutexDestroy(pThis->aCts[i].AsyncIORequestMutex);
pThis->aCts[i].AsyncIORequestMutex = NIL_RTSEMEVENT;
}
}
return VINF_SUCCESS;
}
/**
* Detach notification.
*
* The DVD drive has been unplugged.
*
* @param pDevIns The device instance.
* @param iLUN The logical unit which is being detached.
*/
static DECLCALLBACK(void) ataDetach(PPDMDEVINS pDevIns, unsigned iLUN)
{
PCIATAState *pThis = PDMINS_2_DATA(pDevIns, PCIATAState *);
PATACONTROLLER pCtl;
ATADevState *pIf;
unsigned iController;
unsigned iInterface;
/*
* Locate the controller and stuff.
*/
iController = iLUN / RT_ELEMENTS(pThis->aCts[0].aIfs);
AssertReleaseMsg(iController < RT_ELEMENTS(pThis->aCts), ("iController=%d iLUN=%d\n", iController, iLUN));
pCtl = &pThis->aCts[iController];
iInterface = iLUN % RT_ELEMENTS(pThis->aCts[0].aIfs);
pIf = &pCtl->aIfs[iInterface];
/*
* Zero some important members.
*/
pIf->pDrvBase = NULL;
pIf->pDrvBlock = NULL;
pIf->pDrvBlockBios = NULL;
pIf->pDrvMount = NULL;
/*
* In case there was a medium inserted.
*/
ataMediumRemoved(pIf);
}
/**
* Configure a LUN.
*
* @returns VBox status code.
* @param pDevIns The device instance.
* @param pIf The ATA unit state.
*/
static int ataConfigLun(PPDMDEVINS pDevIns, ATADevState *pIf)
{
int rc;
PDMBLOCKTYPE enmType;
/*
* Query Block, Bios and Mount interfaces.
*/
pIf->pDrvBlock = (PDMIBLOCK *)pIf->pDrvBase->pfnQueryInterface(pIf->pDrvBase, PDMINTERFACE_BLOCK);
if (!pIf->pDrvBlock)
{
AssertMsgFailed(("Configuration error: LUN#%d hasn't a block interface!\n", pIf->iLUN));
return VERR_PDM_MISSING_INTERFACE;
}
/** @todo implement the BIOS invisible code path. */
pIf->pDrvBlockBios = (PDMIBLOCKBIOS *)pIf->pDrvBase->pfnQueryInterface(pIf->pDrvBase, PDMINTERFACE_BLOCK_BIOS);
if (!pIf->pDrvBlockBios)
{
AssertMsgFailed(("Configuration error: LUN#%d hasn't a block BIOS interface!\n", pIf->iLUN));
return VERR_PDM_MISSING_INTERFACE;
}
pIf->pDrvMount = (PDMIMOUNT *)pIf->pDrvBase->pfnQueryInterface(pIf->pDrvBase, PDMINTERFACE_MOUNT);
/*
* Validate type.
*/
enmType = pIf->pDrvBlock->pfnGetType(pIf->pDrvBlock);
if ( enmType != PDMBLOCKTYPE_CDROM
&& enmType != PDMBLOCKTYPE_DVD
&& enmType != PDMBLOCKTYPE_HARD_DISK)
{
AssertMsgFailed(("Configuration error: LUN#%d isn't a disk or cd/dvd-rom. enmType=%d\n", pIf->iLUN, enmType));
return VERR_PDM_UNSUPPORTED_BLOCK_TYPE;
}
if ( ( enmType == PDMBLOCKTYPE_DVD
|| enmType == PDMBLOCKTYPE_CDROM)
&& !pIf->pDrvMount)
{
AssertMsgFailed(("Internal error: cdrom without a mountable interface, WTF???!\n"));
return VERR_INTERNAL_ERROR;
}
pIf->fATAPI = enmType == PDMBLOCKTYPE_DVD || enmType == PDMBLOCKTYPE_CDROM;
pIf->fATAPIPassthrough = pIf->fATAPI ? (pIf->pDrvBlock->pfnSendCmd != NULL) : false;
/*
* Allocate I/O buffer.
*/
PVM pVM = PDMDevHlpGetVM(pDevIns);
if (pIf->cbIOBuffer)
{
/* Buffer is (probably) already allocated. Validate the fields,
* because memory corruption can also overwrite pIf->cbIOBuffer. */
if (pIf->fATAPI)
AssertRelease(pIf->cbIOBuffer == _128K);
else
AssertRelease(pIf->cbIOBuffer == ATA_MAX_MULT_SECTORS * 512);
Assert(pIf->pbIOBufferR3);
Assert(pIf->pbIOBufferR0 == MMHyperR3ToR0(pVM, pIf->pbIOBufferR3));
Assert(pIf->pbIOBufferRC == MMHyperR3ToRC(pVM, pIf->pbIOBufferR3));
}
else
{
if (pIf->fATAPI)
pIf->cbIOBuffer = _128K;
else
pIf->cbIOBuffer = ATA_MAX_MULT_SECTORS * 512;
Assert(!pIf->pbIOBufferR3);
rc = MMR3HyperAllocOnceNoRel(pVM, pIf->cbIOBuffer, 0, MM_TAG_PDM_DEVICE_USER, (void **)&pIf->pbIOBufferR3);
if (RT_FAILURE(rc))
return VERR_NO_MEMORY;
pIf->pbIOBufferR0 = MMHyperR3ToR0(pVM, pIf->pbIOBufferR3);
pIf->pbIOBufferRC = MMHyperR3ToRC(pVM, pIf->pbIOBufferR3);
}
/*
* Init geometry (only for non-CD/DVD media).
*/
if (pIf->fATAPI)
{
pIf->cTotalSectors = pIf->pDrvBlock->pfnGetSize(pIf->pDrvBlock) / 2048;
pIf->PCHSGeometry.cCylinders = 0; /* dummy */
pIf->PCHSGeometry.cHeads = 0; /* dummy */
pIf->PCHSGeometry.cSectors = 0; /* dummy */
LogRel(("PIIX3 ATA: LUN#%d: CD/DVD, total number of sectors %Ld, passthrough %s\n", pIf->iLUN, pIf->cTotalSectors, (pIf->fATAPIPassthrough ? "enabled" : "disabled")));
}
else
{
pIf->cTotalSectors = pIf->pDrvBlock->pfnGetSize(pIf->pDrvBlock) / 512;
rc = pIf->pDrvBlockBios->pfnGetPCHSGeometry(pIf->pDrvBlockBios,
&pIf->PCHSGeometry);
if (rc == VERR_PDM_MEDIA_NOT_MOUNTED)
{
pIf->PCHSGeometry.cCylinders = 0;
pIf->PCHSGeometry.cHeads = 16; /*??*/
pIf->PCHSGeometry.cSectors = 63; /*??*/
}
else if (rc == VERR_PDM_GEOMETRY_NOT_SET)
{
pIf->PCHSGeometry.cCylinders = 0; /* autodetect marker */
rc = VINF_SUCCESS;
}
AssertRC(rc);
if ( pIf->PCHSGeometry.cCylinders == 0
|| pIf->PCHSGeometry.cHeads == 0
|| pIf->PCHSGeometry.cSectors == 0
)
{
uint64_t cCylinders = pIf->cTotalSectors / (16 * 63);
pIf->PCHSGeometry.cCylinders = RT_MAX(RT_MIN(cCylinders, 16383), 1);
pIf->PCHSGeometry.cHeads = 16;
pIf->PCHSGeometry.cSectors = 63;
/* Set the disk geometry information. */
rc = pIf->pDrvBlockBios->pfnSetPCHSGeometry(pIf->pDrvBlockBios,
&pIf->PCHSGeometry);
}
LogRel(("PIIX3 ATA: LUN#%d: disk, PCHS=%u/%u/%u, total number of sectors %Ld\n", pIf->iLUN, pIf->PCHSGeometry.cCylinders, pIf->PCHSGeometry.cHeads, pIf->PCHSGeometry.cSectors, pIf->cTotalSectors));
}
return VINF_SUCCESS;
}
/**
* Attach command.
*
* This is called when we change block driver for the DVD drive.
*
* @returns VBox status code.
* @param pDevIns The device instance.
* @param iLUN The logical unit which is being detached.
*/
static DECLCALLBACK(int) ataAttach(PPDMDEVINS pDevIns, unsigned iLUN)
{
PCIATAState *pThis = PDMINS_2_DATA(pDevIns, PCIATAState *);
PATACONTROLLER pCtl;
ATADevState *pIf;
int rc;
unsigned iController;
unsigned iInterface;
/*
* Locate the controller and stuff.
*/
iController = iLUN / RT_ELEMENTS(pThis->aCts[0].aIfs);
AssertReleaseMsg(iController < RT_ELEMENTS(pThis->aCts), ("iController=%d iLUN=%d\n", iController, iLUN));
pCtl = &pThis->aCts[iController];
iInterface = iLUN % RT_ELEMENTS(pThis->aCts[0].aIfs);
pIf = &pCtl->aIfs[iInterface];
/* the usual paranoia */
AssertRelease(!pIf->pDrvBase);
AssertRelease(!pIf->pDrvBlock);
Assert(ATADEVSTATE_2_CONTROLLER(pIf) == pCtl);
Assert(pIf->iLUN == iLUN);
/*
* Try attach the block device and get the interfaces,
* required as well as optional.
*/
rc = PDMDevHlpDriverAttach(pDevIns, pIf->iLUN, &pIf->IBase, &pIf->pDrvBase, NULL);
if (RT_SUCCESS(rc))
{
rc = ataConfigLun(pDevIns, pIf);
/*
* In case there is a medium inserted.
*/
ataMediumInserted(pIf);
}
else
AssertMsgFailed(("Failed to attach LUN#%d. rc=%Rrc\n", pIf->iLUN, rc));
if (RT_FAILURE(rc))
{
pIf->pDrvBase = NULL;
pIf->pDrvBlock = NULL;
}
return rc;
}
/**
* Suspend notification.
*
* @returns VBox status.
* @param pDevIns The device instance data.
*/
static DECLCALLBACK(void) ataSuspend(PPDMDEVINS pDevIns)
{
Log(("%s:\n", __FUNCTION__));
if (!ataWaitForAllAsyncIOIsIdle(pDevIns, 20000))
AssertMsgFailed(("Async I/O didn't stop in 20 seconds!\n"));
return;
}
/**
* Resume notification.
*
* @returns VBox status.
* @param pDevIns The device instance data.
*/
static DECLCALLBACK(void) ataResume(PPDMDEVINS pDevIns)
{
PCIATAState *pThis = PDMINS_2_DATA(pDevIns, PCIATAState *);
int rc;
Log(("%s:\n", __FUNCTION__));
for (uint32_t i = 0; i < RT_ELEMENTS(pThis->aCts); i++)
{
if (pThis->aCts[i].fRedo && pThis->aCts[i].fRedoIdle)
{
rc = RTSemEventSignal(pThis->aCts[i].SuspendIOSem);
AssertRC(rc);
}
}
return;
}
/**
* Power Off notification.
*
* @returns VBox status.
* @param pDevIns The device instance data.
*/
static DECLCALLBACK(void) ataPowerOff(PPDMDEVINS pDevIns)
{
Log(("%s:\n", __FUNCTION__));
if (!ataWaitForAllAsyncIOIsIdle(pDevIns, 20000))
AssertMsgFailed(("Async I/O didn't stop in 20 seconds!\n"));
return;
}
/**
* Prepare state save and load operation.
*
* @returns VBox status code.
* @param pDevIns Device instance of the device which registered the data unit.
* @param pSSM SSM operation handle.
*/
static DECLCALLBACK(int) ataSaveLoadPrep(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
{
PCIATAState *pThis = PDMINS_2_DATA(pDevIns, PCIATAState *);
/* sanity - the suspend notification will wait on the async stuff. */
for (uint32_t i = 0; i < RT_ELEMENTS(pThis->aCts); i++)
{
Assert(ataAsyncIOIsIdle(&pThis->aCts[i], false));
if (!ataAsyncIOIsIdle(&pThis->aCts[i], false))
return VERR_SSM_IDE_ASYNC_TIMEOUT;
}
return VINF_SUCCESS;
}
/**
* Saves a state of the ATA device.
*
* @returns VBox status code.
* @param pDevIns The device instance.
* @param pSSMHandle The handle to save the state to.
*/
static DECLCALLBACK(int) ataSaveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSMHandle)
{
PCIATAState *pThis = PDMINS_2_DATA(pDevIns, PCIATAState *);
for (uint32_t i = 0; i < RT_ELEMENTS(pThis->aCts); i++)
{
SSMR3PutU8(pSSMHandle, pThis->aCts[i].iSelectedIf);
SSMR3PutU8(pSSMHandle, pThis->aCts[i].iAIOIf);
SSMR3PutU8(pSSMHandle, pThis->aCts[i].uAsyncIOState);
SSMR3PutBool(pSSMHandle, pThis->aCts[i].fChainedTransfer);
SSMR3PutBool(pSSMHandle, pThis->aCts[i].fReset);
SSMR3PutBool(pSSMHandle, pThis->aCts[i].fRedo);
SSMR3PutBool(pSSMHandle, pThis->aCts[i].fRedoIdle);
SSMR3PutBool(pSSMHandle, pThis->aCts[i].fRedoDMALastDesc);
SSMR3PutMem(pSSMHandle, &pThis->aCts[i].BmDma, sizeof(pThis->aCts[i].BmDma));
SSMR3PutGCPhys32(pSSMHandle, pThis->aCts[i].pFirstDMADesc);
SSMR3PutGCPhys32(pSSMHandle, pThis->aCts[i].pLastDMADesc);
SSMR3PutGCPhys32(pSSMHandle, pThis->aCts[i].pRedoDMABuffer);
SSMR3PutU32(pSSMHandle, pThis->aCts[i].cbRedoDMABuffer);
for (uint32_t j = 0; j < RT_ELEMENTS(pThis->aCts[i].aIfs); j++)
{
SSMR3PutBool(pSSMHandle, pThis->aCts[i].aIfs[j].fLBA48);
SSMR3PutBool(pSSMHandle, pThis->aCts[i].aIfs[j].fATAPI);
SSMR3PutBool(pSSMHandle, pThis->aCts[i].aIfs[j].fIrqPending);
SSMR3PutU8(pSSMHandle, pThis->aCts[i].aIfs[j].cMultSectors);
SSMR3PutU32(pSSMHandle, pThis->aCts[i].aIfs[j].PCHSGeometry.cCylinders);
SSMR3PutU32(pSSMHandle, pThis->aCts[i].aIfs[j].PCHSGeometry.cHeads);
SSMR3PutU32(pSSMHandle, pThis->aCts[i].aIfs[j].PCHSGeometry.cSectors);
SSMR3PutU32(pSSMHandle, pThis->aCts[i].aIfs[j].cSectorsPerIRQ);
SSMR3PutU64(pSSMHandle, pThis->aCts[i].aIfs[j].cTotalSectors);
SSMR3PutU8(pSSMHandle, pThis->aCts[i].aIfs[j].uATARegFeature);
SSMR3PutU8(pSSMHandle, pThis->aCts[i].aIfs[j].uATARegFeatureHOB);
SSMR3PutU8(pSSMHandle, pThis->aCts[i].aIfs[j].uATARegError);
SSMR3PutU8(pSSMHandle, pThis->aCts[i].aIfs[j].uATARegNSector);
SSMR3PutU8(pSSMHandle, pThis->aCts[i].aIfs[j].uATARegNSectorHOB);
SSMR3PutU8(pSSMHandle, pThis->aCts[i].aIfs[j].uATARegSector);
SSMR3PutU8(pSSMHandle, pThis->aCts[i].aIfs[j].uATARegSectorHOB);
SSMR3PutU8(pSSMHandle, pThis->aCts[i].aIfs[j].uATARegLCyl);
SSMR3PutU8(pSSMHandle, pThis->aCts[i].aIfs[j].uATARegLCylHOB);
SSMR3PutU8(pSSMHandle, pThis->aCts[i].aIfs[j].uATARegHCyl);
SSMR3PutU8(pSSMHandle, pThis->aCts[i].aIfs[j].uATARegHCylHOB);
SSMR3PutU8(pSSMHandle, pThis->aCts[i].aIfs[j].uATARegSelect);
SSMR3PutU8(pSSMHandle, pThis->aCts[i].aIfs[j].uATARegStatus);
SSMR3PutU8(pSSMHandle, pThis->aCts[i].aIfs[j].uATARegCommand);
SSMR3PutU8(pSSMHandle, pThis->aCts[i].aIfs[j].uATARegDevCtl);
SSMR3PutU8(pSSMHandle, pThis->aCts[i].aIfs[j].uATATransferMode);
SSMR3PutU8(pSSMHandle, pThis->aCts[i].aIfs[j].uTxDir);
SSMR3PutU8(pSSMHandle, pThis->aCts[i].aIfs[j].iBeginTransfer);
SSMR3PutU8(pSSMHandle, pThis->aCts[i].aIfs[j].iSourceSink);
SSMR3PutBool(pSSMHandle, pThis->aCts[i].aIfs[j].fDMA);
SSMR3PutBool(pSSMHandle, pThis->aCts[i].aIfs[j].fATAPITransfer);
SSMR3PutU32(pSSMHandle, pThis->aCts[i].aIfs[j].cbTotalTransfer);
SSMR3PutU32(pSSMHandle, pThis->aCts[i].aIfs[j].cbElementaryTransfer);
SSMR3PutU32(pSSMHandle, pThis->aCts[i].aIfs[j].iIOBufferCur);
SSMR3PutU32(pSSMHandle, pThis->aCts[i].aIfs[j].iIOBufferEnd);
SSMR3PutU32(pSSMHandle, pThis->aCts[i].aIfs[j].iIOBufferPIODataStart);
SSMR3PutU32(pSSMHandle, pThis->aCts[i].aIfs[j].iIOBufferPIODataEnd);
SSMR3PutU32(pSSMHandle, pThis->aCts[i].aIfs[j].iATAPILBA);
SSMR3PutU32(pSSMHandle, pThis->aCts[i].aIfs[j].cbATAPISector);
SSMR3PutMem(pSSMHandle, &pThis->aCts[i].aIfs[j].aATAPICmd, sizeof(pThis->aCts[i].aIfs[j].aATAPICmd));
SSMR3PutMem(pSSMHandle, &pThis->aCts[i].aIfs[j].abATAPISense, sizeof(pThis->aCts[i].aIfs[j].abATAPISense));
SSMR3PutU8(pSSMHandle, pThis->aCts[i].aIfs[j].cNotifiedMediaChange);
SSMR3PutU32(pSSMHandle, pThis->aCts[i].aIfs[j].MediaEventStatus);
SSMR3PutMem(pSSMHandle, &pThis->aCts[i].aIfs[j].Led, sizeof(pThis->aCts[i].aIfs[j].Led));
SSMR3PutU32(pSSMHandle, pThis->aCts[i].aIfs[j].cbIOBuffer);
if (pThis->aCts[i].aIfs[j].cbIOBuffer)
SSMR3PutMem(pSSMHandle, pThis->aCts[i].aIfs[j].CTX_SUFF(pbIOBuffer), pThis->aCts[i].aIfs[j].cbIOBuffer);
else
Assert(pThis->aCts[i].aIfs[j].CTX_SUFF(pbIOBuffer) == NULL);
}
}
SSMR3PutBool(pSSMHandle, pThis->fPIIX4);
return SSMR3PutU32(pSSMHandle, ~0); /* sanity/terminator */
}
/**
* Loads a saved ATA device state.
*
* @returns VBox status code.
* @param pDevIns The device instance.
* @param pSSMHandle The handle to the saved state.
* @param u32Version The data unit version number.
*/
static DECLCALLBACK(int) ataLoadExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSMHandle, uint32_t u32Version)
{
PCIATAState *pThis = PDMINS_2_DATA(pDevIns, PCIATAState *);
int rc;
uint32_t u32;
if ( u32Version != ATA_SAVED_STATE_VERSION
&& u32Version != ATA_SAVED_STATE_VERSION_WITHOUT_FULL_SENSE
&& u32Version != ATA_SAVED_STATE_VERSION_WITHOUT_EVENT_STATUS)
{
AssertMsgFailed(("u32Version=%d\n", u32Version));
return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
}
/*
* Restore valid parts of the PCIATAState structure
*/
for (uint32_t i = 0; i < RT_ELEMENTS(pThis->aCts); i++)
{
/* integrity check */
if (!ataAsyncIOIsIdle(&pThis->aCts[i], false))
{
AssertMsgFailed(("Async I/O for controller %d is active\n", i));
rc = VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
return rc;
}
SSMR3GetU8(pSSMHandle, &pThis->aCts[i].iSelectedIf);
SSMR3GetU8(pSSMHandle, &pThis->aCts[i].iAIOIf);
SSMR3GetU8(pSSMHandle, &pThis->aCts[i].uAsyncIOState);
SSMR3GetBool(pSSMHandle, &pThis->aCts[i].fChainedTransfer);
SSMR3GetBool(pSSMHandle, (bool *)&pThis->aCts[i].fReset);
SSMR3GetBool(pSSMHandle, (bool *)&pThis->aCts[i].fRedo);
SSMR3GetBool(pSSMHandle, (bool *)&pThis->aCts[i].fRedoIdle);
SSMR3GetBool(pSSMHandle, (bool *)&pThis->aCts[i].fRedoDMALastDesc);
SSMR3GetMem(pSSMHandle, &pThis->aCts[i].BmDma, sizeof(pThis->aCts[i].BmDma));
SSMR3GetGCPhys32(pSSMHandle, &pThis->aCts[i].pFirstDMADesc);
SSMR3GetGCPhys32(pSSMHandle, &pThis->aCts[i].pLastDMADesc);
SSMR3GetGCPhys32(pSSMHandle, &pThis->aCts[i].pRedoDMABuffer);
SSMR3GetU32(pSSMHandle, &pThis->aCts[i].cbRedoDMABuffer);
for (uint32_t j = 0; j < RT_ELEMENTS(pThis->aCts[i].aIfs); j++)
{
SSMR3GetBool(pSSMHandle, &pThis->aCts[i].aIfs[j].fLBA48);
SSMR3GetBool(pSSMHandle, &pThis->aCts[i].aIfs[j].fATAPI);
SSMR3GetBool(pSSMHandle, &pThis->aCts[i].aIfs[j].fIrqPending);
SSMR3GetU8(pSSMHandle, &pThis->aCts[i].aIfs[j].cMultSectors);
SSMR3GetU32(pSSMHandle, &pThis->aCts[i].aIfs[j].PCHSGeometry.cCylinders);
SSMR3GetU32(pSSMHandle, &pThis->aCts[i].aIfs[j].PCHSGeometry.cHeads);
SSMR3GetU32(pSSMHandle, &pThis->aCts[i].aIfs[j].PCHSGeometry.cSectors);
SSMR3GetU32(pSSMHandle, &pThis->aCts[i].aIfs[j].cSectorsPerIRQ);
SSMR3GetU64(pSSMHandle, &pThis->aCts[i].aIfs[j].cTotalSectors);
SSMR3GetU8(pSSMHandle, &pThis->aCts[i].aIfs[j].uATARegFeature);
SSMR3GetU8(pSSMHandle, &pThis->aCts[i].aIfs[j].uATARegFeatureHOB);
SSMR3GetU8(pSSMHandle, &pThis->aCts[i].aIfs[j].uATARegError);
SSMR3GetU8(pSSMHandle, &pThis->aCts[i].aIfs[j].uATARegNSector);
SSMR3GetU8(pSSMHandle, &pThis->aCts[i].aIfs[j].uATARegNSectorHOB);
SSMR3GetU8(pSSMHandle, &pThis->aCts[i].aIfs[j].uATARegSector);
SSMR3GetU8(pSSMHandle, &pThis->aCts[i].aIfs[j].uATARegSectorHOB);
SSMR3GetU8(pSSMHandle, &pThis->aCts[i].aIfs[j].uATARegLCyl);
SSMR3GetU8(pSSMHandle, &pThis->aCts[i].aIfs[j].uATARegLCylHOB);
SSMR3GetU8(pSSMHandle, &pThis->aCts[i].aIfs[j].uATARegHCyl);
SSMR3GetU8(pSSMHandle, &pThis->aCts[i].aIfs[j].uATARegHCylHOB);
SSMR3GetU8(pSSMHandle, &pThis->aCts[i].aIfs[j].uATARegSelect);
SSMR3GetU8(pSSMHandle, &pThis->aCts[i].aIfs[j].uATARegStatus);
SSMR3GetU8(pSSMHandle, &pThis->aCts[i].aIfs[j].uATARegCommand);
SSMR3GetU8(pSSMHandle, &pThis->aCts[i].aIfs[j].uATARegDevCtl);
SSMR3GetU8(pSSMHandle, &pThis->aCts[i].aIfs[j].uATATransferMode);
SSMR3GetU8(pSSMHandle, &pThis->aCts[i].aIfs[j].uTxDir);
SSMR3GetU8(pSSMHandle, &pThis->aCts[i].aIfs[j].iBeginTransfer);
SSMR3GetU8(pSSMHandle, &pThis->aCts[i].aIfs[j].iSourceSink);
SSMR3GetBool(pSSMHandle, &pThis->aCts[i].aIfs[j].fDMA);
SSMR3GetBool(pSSMHandle, &pThis->aCts[i].aIfs[j].fATAPITransfer);
SSMR3GetU32(pSSMHandle, &pThis->aCts[i].aIfs[j].cbTotalTransfer);
SSMR3GetU32(pSSMHandle, &pThis->aCts[i].aIfs[j].cbElementaryTransfer);
SSMR3GetU32(pSSMHandle, &pThis->aCts[i].aIfs[j].iIOBufferCur);
SSMR3GetU32(pSSMHandle, &pThis->aCts[i].aIfs[j].iIOBufferEnd);
SSMR3GetU32(pSSMHandle, &pThis->aCts[i].aIfs[j].iIOBufferPIODataStart);
SSMR3GetU32(pSSMHandle, &pThis->aCts[i].aIfs[j].iIOBufferPIODataEnd);
SSMR3GetU32(pSSMHandle, &pThis->aCts[i].aIfs[j].iATAPILBA);
SSMR3GetU32(pSSMHandle, &pThis->aCts[i].aIfs[j].cbATAPISector);
SSMR3GetMem(pSSMHandle, &pThis->aCts[i].aIfs[j].aATAPICmd, sizeof(pThis->aCts[i].aIfs[j].aATAPICmd));
if (u32Version > ATA_SAVED_STATE_VERSION_WITHOUT_FULL_SENSE)
{
SSMR3GetMem(pSSMHandle, pThis->aCts[i].aIfs[j].abATAPISense, sizeof(pThis->aCts[i].aIfs[j].abATAPISense));
}
else
{
uint8_t uATAPISenseKey, uATAPIASC;
memset(pThis->aCts[i].aIfs[j].abATAPISense, '\0', sizeof(pThis->aCts[i].aIfs[j].abATAPISense));
pThis->aCts[i].aIfs[j].abATAPISense[0] = 0x70 | (1 << 7);
pThis->aCts[i].aIfs[j].abATAPISense[7] = 10;
SSMR3GetU8(pSSMHandle, &uATAPISenseKey);
SSMR3GetU8(pSSMHandle, &uATAPIASC);
pThis->aCts[i].aIfs[j].abATAPISense[2] = uATAPISenseKey & 0x0f;
pThis->aCts[i].aIfs[j].abATAPISense[12] = uATAPIASC;
}
/** @todo triple-check this hack after passthrough is working */
SSMR3GetU8(pSSMHandle, &pThis->aCts[i].aIfs[j].cNotifiedMediaChange);
if (u32Version > ATA_SAVED_STATE_VERSION_WITHOUT_EVENT_STATUS)
SSMR3GetU32(pSSMHandle, (uint32_t*)&pThis->aCts[i].aIfs[j].MediaEventStatus);
else
pThis->aCts[i].aIfs[j].MediaEventStatus = ATA_EVENT_STATUS_UNCHANGED;
SSMR3GetMem(pSSMHandle, &pThis->aCts[i].aIfs[j].Led, sizeof(pThis->aCts[i].aIfs[j].Led));
SSMR3GetU32(pSSMHandle, &pThis->aCts[i].aIfs[j].cbIOBuffer);
if (pThis->aCts[i].aIfs[j].cbIOBuffer)
{
if (pThis->aCts[i].aIfs[j].CTX_SUFF(pbIOBuffer))
SSMR3GetMem(pSSMHandle, pThis->aCts[i].aIfs[j].CTX_SUFF(pbIOBuffer), pThis->aCts[i].aIfs[j].cbIOBuffer);
else
{
LogRel(("ATA: No buffer for %d/%d\n", i, j));
if (SSMR3HandleGetAfter(pSSMHandle) != SSMAFTER_DEBUG_IT)
return VERR_SSM_LOAD_CONFIG_MISMATCH;
/* skip the buffer if we're loading for the debugger / animator. */
uint8_t u8Ignored;
size_t cbLeft = pThis->aCts[i].aIfs[j].cbIOBuffer;
while (cbLeft-- > 0)
SSMR3GetU8(pSSMHandle, &u8Ignored);
}
}
else
Assert(pThis->aCts[i].aIfs[j].CTX_SUFF(pbIOBuffer) == NULL);
}
}
SSMR3GetBool(pSSMHandle, &pThis->fPIIX4);
rc = SSMR3GetU32(pSSMHandle, &u32);
if (RT_FAILURE(rc))
return rc;
if (u32 != ~0U)
{
AssertMsgFailed(("u32=%#x expected ~0\n", u32));
rc = VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
return rc;
}
return VINF_SUCCESS;
}
/**
* Construct a device instance for a VM.
*
* @returns VBox status.
* @param pDevIns The device instance data.
* If the registration structure is needed, pDevIns->pDevReg points to it.
* @param iInstance Instance number. Use this to figure out which registers and such to use.
* The device number is also found in pDevIns->iInstance, but since it's
* likely to be freqently used PDM passes it as parameter.
* @param pCfgHandle Configuration node handle for the device. Use this to obtain the configuration
* of the device instance. It's also found in pDevIns->pCfgHandle, but like
* iInstance it's expected to be used a bit in this function.
*/
static DECLCALLBACK(int) ataConstruct(PPDMDEVINS pDevIns, int iInstance, PCFGMNODE pCfgHandle)
{
PCIATAState *pThis = PDMINS_2_DATA(pDevIns, PCIATAState *);
PPDMIBASE pBase;
int rc;
bool fGCEnabled;
bool fR0Enabled;
uint32_t DelayIRQMillies;
Assert(iInstance == 0);
/*
* Initialize NIL handle values (for the destructor).
*/
for (uint32_t i = 0; i < RT_ELEMENTS(pThis->aCts); i++)
{
pThis->aCts[i].AsyncIOSem = NIL_RTSEMEVENT;
pThis->aCts[i].SuspendIOSem = NIL_RTSEMEVENT;
pThis->aCts[i].AsyncIORequestMutex = NIL_RTSEMEVENT;
}
/*
* Validate and read configuration.
*/
if (!CFGMR3AreValuesValid(pCfgHandle, "GCEnabled\0IRQDelay\0R0Enabled\0PIIX4\0"))
return PDMDEV_SET_ERROR(pDevIns, VERR_PDM_DEVINS_UNKNOWN_CFG_VALUES,
N_("PIIX3 configuration error: unknown option specified"));
rc = CFGMR3QueryBoolDef(pCfgHandle, "GCEnabled", &fGCEnabled, true);
if (RT_FAILURE(rc))
return PDMDEV_SET_ERROR(pDevIns, rc,
N_("PIIX3 configuration error: failed to read GCEnabled as boolean"));
Log(("%s: fGCEnabled=%d\n", __FUNCTION__, fGCEnabled));
rc = CFGMR3QueryBoolDef(pCfgHandle, "R0Enabled", &fR0Enabled, true);
if (RT_FAILURE(rc))
return PDMDEV_SET_ERROR(pDevIns, rc,
N_("PIIX3 configuration error: failed to read R0Enabled as boolean"));
Log(("%s: fR0Enabled=%d\n", __FUNCTION__, fR0Enabled));
rc = CFGMR3QueryU32Def(pCfgHandle, "IRQDelay", &DelayIRQMillies, 0);
if (RT_FAILURE(rc))
return PDMDEV_SET_ERROR(pDevIns, rc,
N_("PIIX3 configuration error: failed to read IRQDelay as integer"));
Log(("%s: DelayIRQMillies=%d\n", __FUNCTION__, DelayIRQMillies));
Assert(DelayIRQMillies < 50);
rc = CFGMR3QueryBoolDef(pCfgHandle, "PIIX4", &pThis->fPIIX4, false);
if (RT_FAILURE(rc))
return PDMDEV_SET_ERROR(pDevIns, rc,
N_("PIIX3 configuration error: failed to read PIIX4 as boolean"));
Log(("%s: fPIIX4=%d\n", __FUNCTION__, pThis->fPIIX4));
/*
* Initialize data (most of it anyway).
*/
/* Status LUN. */
pThis->IBase.pfnQueryInterface = ataStatus_QueryInterface;
pThis->ILeds.pfnQueryStatusLed = ataStatus_QueryStatusLed;
/* PCI configuration space. */
PCIDevSetVendorId(&pThis->dev, 0x8086); /* Intel */
if (pThis->fPIIX4)
{
PCIDevSetDeviceId(&pThis->dev, 0x7111); /* PIIX4 IDE */
PCIDevSetRevisionId(&pThis->dev, 0x01); /* PIIX4E */
pThis->dev.config[0x48] = 0x00; /* UDMACTL */
pThis->dev.config[0x4A] = 0x00; /* UDMATIM */
pThis->dev.config[0x4B] = 0x00;
}
else
PCIDevSetDeviceId(&pThis->dev, 0x7010); /* PIIX3 IDE */
PCIDevSetCommand( &pThis->dev, PCI_COMMAND_IOACCESS | PCI_COMMAND_MEMACCESS | PCI_COMMAND_BUSMASTER);
PCIDevSetClassProg( &pThis->dev, 0x8a); /* programming interface = PCI_IDE bus master is supported */
PCIDevSetClassSub( &pThis->dev, 0x01); /* class_sub = PCI_IDE */
PCIDevSetClassBase( &pThis->dev, 0x01); /* class_base = PCI_mass_storage */
PCIDevSetHeaderType(&pThis->dev, 0x00);
pThis->pDevIns = pDevIns;
pThis->fGCEnabled = fGCEnabled;
pThis->fR0Enabled = fR0Enabled;
for (uint32_t i = 0; i < RT_ELEMENTS(pThis->aCts); i++)
{
pThis->aCts[i].pDevInsR3 = pDevIns;
pThis->aCts[i].pDevInsR0 = PDMDEVINS_2_R0PTR(pDevIns);
pThis->aCts[i].pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
pThis->aCts[i].DelayIRQMillies = (uint32_t)DelayIRQMillies;
for (uint32_t j = 0; j < RT_ELEMENTS(pThis->aCts[i].aIfs); j++)
{
ATADevState *pIf = &pThis->aCts[i].aIfs[j];
pIf->iLUN = i * RT_ELEMENTS(pThis->aCts) + j;
pIf->pDevInsR3 = pDevIns;
pIf->pDevInsR0 = PDMDEVINS_2_R0PTR(pDevIns);
pIf->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
pIf->pControllerR3 = &pThis->aCts[i];
pIf->pControllerR0 = MMHyperR3ToR0(PDMDevHlpGetVM(pDevIns), &pThis->aCts[i]);
pIf->pControllerRC = MMHyperR3ToRC(PDMDevHlpGetVM(pDevIns), &pThis->aCts[i]);
pIf->IBase.pfnQueryInterface = ataQueryInterface;
pIf->IMountNotify.pfnMountNotify = ataMountNotify;
pIf->IMountNotify.pfnUnmountNotify = ataUnmountNotify;
pIf->Led.u32Magic = PDMLED_MAGIC;
/*
* Init vendor product data.
*/
static const char *s_apszDescs[2][2] =
{
{ "PrimaryMaster", "PrimarySlave" },
{ "SecondaryMaster", "SecondarySlave" }
};
char aSerial[20];
RTUUID Uuid;
if (pIf->pDrvBlock)
rc = pIf->pDrvBlock->pfnGetUuid(pIf->pDrvBlock, &Uuid);
else
RTUuidClear(&Uuid);
if (RT_FAILURE(rc) || RTUuidIsNull(&Uuid))
{
/* Generate a predictable serial for drives which don't have a UUID. */
RTStrPrintf(aSerial, sizeof(aSerial), "VB%x-%04x%04x",
pIf->iLUN + pDevIns->iInstance * 32,
pThis->aCts[i].IOPortBase1, pThis->aCts[i].IOPortBase2);
}
else
RTStrPrintf(aSerial, sizeof(aSerial), "VB%08x-%08x", Uuid.au32[0], Uuid.au32[3]);
strncpy((char *)pIf->abSerialNumber, aSerial, 20);
strncpy((char *)pIf->abFirmwareRevision, "1.0", 8);
strncpy((char *)pIf->abModelNumber, "VBOX HARDDISK", 40);
/* Check if the user provided some values to overwrite. */
PCFGMNODE pCfgNode = CFGMR3GetChild(pCfgHandle, s_apszDescs[i][j]);
if (pCfgNode)
{
char *pszCFGMValue;
rc = CFGMR3QueryStringAlloc(pCfgNode, "SerialNumber", &pszCFGMValue);
if (RT_SUCCESS(rc))
{
/* Check length of the serial number. It shouldn't be longer than 20 bytes. */
if (strlen(pszCFGMValue) > 20)
return PDMDEV_SET_ERROR(pDevIns, VERR_INVALID_PARAMETER,
N_("PIIX3 configuration error: \"SerialNumber\" is longer than 20 bytes"));
/* Copy the data over. */
strncpy((char *)pIf->abSerialNumber, pszCFGMValue, 20);
MMR3HeapFree(pszCFGMValue);
}
else if (rc != VERR_CFGM_VALUE_NOT_FOUND)
return PDMDEV_SET_ERROR(pDevIns, rc,
N_("PIIX3 configuration error: failed to read \"SerialNumber\" as string"));
rc = CFGMR3QueryStringAlloc(pCfgNode, "FirmwareRevision", &pszCFGMValue);
if (RT_SUCCESS(rc))
{
/* Check length of the firmware revision. It shouldn't be longer than 8 bytes. */
if (strlen(pszCFGMValue) > 8)
return PDMDEV_SET_ERROR(pDevIns, VERR_INVALID_PARAMETER,
N_("PIIX3 configuration error: \"FirmwareRevision\" is longer than 8 bytes"));
/* Copy the data over. */
strncpy((char *)pIf->abFirmwareRevision, pszCFGMValue, 8);
MMR3HeapFree(pszCFGMValue);
}
else if (rc != VERR_CFGM_VALUE_NOT_FOUND)
return PDMDEV_SET_ERROR(pDevIns, rc,
N_("PIIX3 configuration error: failed to read \"FirmwareRevision\" as string"));
rc = CFGMR3QueryStringAlloc(pCfgNode, "ModelNumber", &pszCFGMValue);
if (RT_SUCCESS(rc))
{
/* Check length of the model number. It shouldn't be longer than 40 bytes. */
if (strlen(pszCFGMValue) > 40)
return PDMDEV_SET_ERROR(pDevIns, VERR_INVALID_PARAMETER,
N_("PIIX3 configuration error: \"ModelNumber\" is longer than 40 bytes"));
/* Copy the data over. */
strncpy((char *)pIf->abModelNumber, pszCFGMValue, 40);
MMR3HeapFree(pszCFGMValue);
}
else if (rc != VERR_CFGM_VALUE_NOT_FOUND)
return PDMDEV_SET_ERROR(pDevIns, rc,
N_("PIIX3 configuration error: failed to read \"ModelNumber\" as string"));
}
}
}
Assert(RT_ELEMENTS(pThis->aCts) == 2);
pThis->aCts[0].irq = 14;
pThis->aCts[0].IOPortBase1 = 0x1f0;
pThis->aCts[0].IOPortBase2 = 0x3f6;
pThis->aCts[1].irq = 15;
pThis->aCts[1].IOPortBase1 = 0x170;
pThis->aCts[1].IOPortBase2 = 0x376;
/*
* Register the PCI device.
* N.B. There's a hack in the PIIX3 PCI bridge device to assign this
* device the slot next to itself.
*/
rc = PDMDevHlpPCIRegister(pDevIns, &pThis->dev);
if (RT_FAILURE(rc))
return PDMDEV_SET_ERROR(pDevIns, rc,
N_("PIIX3 cannot register PCI device"));
AssertMsg(pThis->dev.devfn == 9 || iInstance != 0, ("pThis->dev.devfn=%d\n", pThis->dev.devfn));
rc = PDMDevHlpPCIIORegionRegister(pDevIns, 4, 0x10, PCI_ADDRESS_SPACE_IO, ataBMDMAIORangeMap);
if (RT_FAILURE(rc))
return PDMDEV_SET_ERROR(pDevIns, rc,
N_("PIIX3 cannot register PCI I/O region for BMDMA"));
/*
* Register the I/O ports.
* The ports are all hardcoded and enforced by the PIIX3 host bridge controller.
*/
for (uint32_t i = 0; i < RT_ELEMENTS(pThis->aCts); i++)
{
rc = PDMDevHlpIOPortRegister(pDevIns, pThis->aCts[i].IOPortBase1, 8, (RTHCPTR)i,
ataIOPortWrite1, ataIOPortRead1, ataIOPortWriteStr1, ataIOPortReadStr1, "ATA I/O Base 1");
if (RT_FAILURE(rc))
return PDMDEV_SET_ERROR(pDevIns, rc, N_("PIIX3 cannot register I/O handlers"));
if (fGCEnabled)
{
rc = PDMDevHlpIOPortRegisterGC(pDevIns, pThis->aCts[i].IOPortBase1, 8, (RTGCPTR)i,
"ataIOPortWrite1", "ataIOPortRead1", "ataIOPortWriteStr1", "ataIOPortReadStr1", "ATA I/O Base 1");
if (RT_FAILURE(rc))
return PDMDEV_SET_ERROR(pDevIns, rc, N_("PIIX3 cannot register I/O handlers (GC)"));
}
if (fR0Enabled)
{
#if 1
rc = PDMDevHlpIOPortRegisterR0(pDevIns, pThis->aCts[i].IOPortBase1, 8, (RTR0PTR)i,
"ataIOPortWrite1", "ataIOPortRead1", NULL, NULL, "ATA I/O Base 1");
#else
rc = PDMDevHlpIOPortRegisterR0(pDevIns, pThis->aCts[i].IOPortBase1, 8, (RTR0PTR)i,
"ataIOPortWrite1", "ataIOPortRead1", "ataIOPortWriteStr1", "ataIOPortReadStr1", "ATA I/O Base 1");
#endif
if (RT_FAILURE(rc))
return PDMDEV_SET_ERROR(pDevIns, rc, "PIIX3 cannot register I/O handlers (R0).");
}
rc = PDMDevHlpIOPortRegister(pDevIns, pThis->aCts[i].IOPortBase2, 1, (RTHCPTR)i,
ataIOPortWrite2, ataIOPortRead2, NULL, NULL, "ATA I/O Base 2");
if (RT_FAILURE(rc))
return PDMDEV_SET_ERROR(pDevIns, rc, N_("PIIX3 cannot register base2 I/O handlers"));
if (fGCEnabled)
{
rc = PDMDevHlpIOPortRegisterGC(pDevIns, pThis->aCts[i].IOPortBase2, 1, (RTGCPTR)i,
"ataIOPortWrite2", "ataIOPortRead2", NULL, NULL, "ATA I/O Base 2");
if (RT_FAILURE(rc))
return PDMDEV_SET_ERROR(pDevIns, rc, N_("PIIX3 cannot register base2 I/O handlers (GC)"));
}
if (fR0Enabled)
{
rc = PDMDevHlpIOPortRegisterR0(pDevIns, pThis->aCts[i].IOPortBase2, 1, (RTR0PTR)i,
"ataIOPortWrite2", "ataIOPortRead2", NULL, NULL, "ATA I/O Base 2");
if (RT_FAILURE(rc))
return PDMDEV_SET_ERROR(pDevIns, rc, N_("PIIX3 cannot register base2 I/O handlers (R0)"));
}
for (uint32_t j = 0; j < RT_ELEMENTS(pThis->aCts[i].aIfs); j++)
{
ATADevState *pIf = &pThis->aCts[i].aIfs[j];
PDMDevHlpSTAMRegisterF(pDevIns, &pIf->StatATADMA, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, "Number of ATA DMA transfers.", "/Devices/ATA%d/Unit%d/DMA", i, j);
PDMDevHlpSTAMRegisterF(pDevIns, &pIf->StatATAPIO, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, "Number of ATA PIO transfers.", "/Devices/ATA%d/Unit%d/PIO", i, j);
PDMDevHlpSTAMRegisterF(pDevIns, &pIf->StatATAPIDMA, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, "Number of ATAPI DMA transfers.", "/Devices/ATA%d/Unit%d/AtapiDMA", i, j);
PDMDevHlpSTAMRegisterF(pDevIns, &pIf->StatATAPIPIO, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, "Number of ATAPI PIO transfers.", "/Devices/ATA%d/Unit%d/AtapiPIO", i, j);
#ifdef VBOX_WITH_STATISTICS /** @todo release too. */
PDMDevHlpSTAMRegisterF(pDevIns, &pIf->StatReads, STAMTYPE_PROFILE_ADV, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_CALL, "Profiling of the read operations.", "/Devices/ATA%d/Unit%d/Reads", i, j);
#endif
PDMDevHlpSTAMRegisterF(pDevIns, &pIf->StatBytesRead, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_BYTES, "Amount of data read.", "/Devices/ATA%d/Unit%d/ReadBytes", i, j);
#ifdef VBOX_INSTRUMENT_DMA_WRITES
PDMDevHlpSTAMRegisterF(pDevIns, &pIf->StatInstrVDWrites,STAMTYPE_PROFILE_ADV, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_CALL, "Profiling of the VD DMA write operations.","/Devices/ATA%d/Unit%d/InstrVDWrites", i, j);
#endif
#ifdef VBOX_WITH_STATISTICS
PDMDevHlpSTAMRegisterF(pDevIns, &pIf->StatWrites, STAMTYPE_PROFILE_ADV, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_CALL, "Profiling of the write operations.","/Devices/ATA%d/Unit%d/Writes", i, j);
#endif
PDMDevHlpSTAMRegisterF(pDevIns, &pIf->StatBytesWritten, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_BYTES, "Amount of data written.", "/Devices/ATA%d/Unit%d/WrittenBytes", i, j);
#ifdef VBOX_WITH_STATISTICS
PDMDevHlpSTAMRegisterF(pDevIns, &pIf->StatFlushes, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_CALL, "Profiling of the flush operations.","/Devices/ATA%d/Unit%d/Flushes", i, j);
#endif
}
#ifdef VBOX_WITH_STATISTICS /** @todo release too. */
PDMDevHlpSTAMRegisterF(pDevIns, &pThis->aCts[i].StatAsyncOps, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, "The number of async operations.", "/Devices/ATA%d/Async/Operations", i);
/** @todo STAMUNIT_MICROSECS */
PDMDevHlpSTAMRegisterF(pDevIns, &pThis->aCts[i].StatAsyncMinWait, STAMTYPE_U64_RESET, STAMVISIBILITY_ALWAYS, STAMUNIT_NONE, "Minimum wait in microseconds.", "/Devices/ATA%d/Async/MinWait", i);
PDMDevHlpSTAMRegisterF(pDevIns, &pThis->aCts[i].StatAsyncMaxWait, STAMTYPE_U64_RESET, STAMVISIBILITY_ALWAYS, STAMUNIT_NONE, "Maximum wait in microseconds.", "/Devices/ATA%d/Async/MaxWait", i);
PDMDevHlpSTAMRegisterF(pDevIns, &pThis->aCts[i].StatAsyncTimeUS, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_NONE, "Total time spent in microseconds.","/Devices/ATA%d/Async/TotalTimeUS", i);
PDMDevHlpSTAMRegisterF(pDevIns, &pThis->aCts[i].StatAsyncTime, STAMTYPE_PROFILE_ADV, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_CALL, "Profiling of async operations.", "/Devices/ATA%d/Async/Time", i);
PDMDevHlpSTAMRegisterF(pDevIns, &pThis->aCts[i].StatLockWait, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_CALL, "Profiling of locks.", "/Devices/ATA%d/Async/LockWait", i);
#endif /* VBOX_WITH_STATISTICS */
/* Initialize per-controller critical section */
char szName[24];
RTStrPrintf(szName, sizeof(szName), "ATA%d", i);
rc = PDMDevHlpCritSectInit(pDevIns, &pThis->aCts[i].lock, szName);
if (RT_FAILURE(rc))
return PDMDEV_SET_ERROR(pDevIns, rc, N_("PIIX3 cannot initialize critical section"));
}
/*
* Attach status driver (optional).
*/
rc = PDMDevHlpDriverAttach(pDevIns, PDM_STATUS_LUN, &pThis->IBase, &pBase, "Status Port");
if (RT_SUCCESS(rc))
pThis->pLedsConnector = (PDMILEDCONNECTORS *)pBase->pfnQueryInterface(pBase, PDMINTERFACE_LED_CONNECTORS);
else if (rc != VERR_PDM_NO_ATTACHED_DRIVER)
{
AssertMsgFailed(("Failed to attach to status driver. rc=%Rrc\n", rc));
return PDMDEV_SET_ERROR(pDevIns, rc, N_("PIIX3 cannot attach to status driver"));
}
/*
* Attach the units.
*/
uint32_t cbTotalBuffer = 0;
for (uint32_t i = 0; i < RT_ELEMENTS(pThis->aCts); i++)
{
PATACONTROLLER pCtl = &pThis->aCts[i];
/*
* Start the worker thread.
*/
pCtl->uAsyncIOState = ATA_AIO_NEW;
rc = RTSemEventCreate(&pCtl->AsyncIOSem);
AssertRC(rc);
rc = RTSemEventCreate(&pCtl->SuspendIOSem);
AssertRC(rc);
rc = RTSemMutexCreate(&pCtl->AsyncIORequestMutex);
AssertRC(rc);
ataAsyncIOClearRequests(pCtl);
rc = RTThreadCreate(&pCtl->AsyncIOThread, ataAsyncIOLoop, (void *)pCtl, 128*1024, RTTHREADTYPE_IO, RTTHREADFLAGS_WAITABLE, "ATA");
AssertRC(rc);
Assert(pCtl->AsyncIOThread != NIL_RTTHREAD && pCtl->AsyncIOSem != NIL_RTSEMEVENT && pCtl->SuspendIOSem != NIL_RTSEMEVENT && pCtl->AsyncIORequestMutex != NIL_RTSEMMUTEX);
Log(("%s: controller %d AIO thread id %#x; sem %p susp_sem %p mutex %p\n", __FUNCTION__, i, pCtl->AsyncIOThread, pCtl->AsyncIOSem, pCtl->SuspendIOSem, pCtl->AsyncIORequestMutex));
for (uint32_t j = 0; j < RT_ELEMENTS(pCtl->aIfs); j++)
{
static const char *s_apszDescs[RT_ELEMENTS(pThis->aCts)][RT_ELEMENTS(pCtl->aIfs)] =
{
{ "Primary Master", "Primary Slave" },
{ "Secondary Master", "Secondary Slave" }
};
/*
* Try attach the block device and get the interfaces,
* required as well as optional.
*/
ATADevState *pIf = &pCtl->aIfs[j];
rc = PDMDevHlpDriverAttach(pDevIns, pIf->iLUN, &pIf->IBase, &pIf->pDrvBase, s_apszDescs[i][j]);
if (RT_SUCCESS(rc))
rc = ataConfigLun(pDevIns, pIf);
else if (rc == VERR_PDM_NO_ATTACHED_DRIVER)
{
pIf->pDrvBase = NULL;
pIf->pDrvBlock = NULL;
pIf->cbIOBuffer = 0;
pIf->pbIOBufferR3 = NULL;
pIf->pbIOBufferR0 = NIL_RTR0PTR;
pIf->pbIOBufferRC = NIL_RTGCPTR;
LogRel(("PIIX3 ATA: LUN#%d: no unit\n", pIf->iLUN));
}
else
{
switch (rc)
{
case VERR_ACCESS_DENIED:
/* Error already catched by DrvHostBase */
return rc;
default:
return PDMDevHlpVMSetError(pDevIns, rc, RT_SRC_POS,
N_("PIIX3 cannot attach drive to the %s"),
s_apszDescs[i][j]);
}
}
cbTotalBuffer += pIf->cbIOBuffer;
}
}
rc = PDMDevHlpSSMRegister(pDevIns, pDevIns->pDevReg->szDeviceName, iInstance,
ATA_SAVED_STATE_VERSION, sizeof(*pThis) + cbTotalBuffer,
ataSaveLoadPrep, ataSaveExec, NULL,
ataSaveLoadPrep, ataLoadExec, NULL);
if (RT_FAILURE(rc))
return PDMDEV_SET_ERROR(pDevIns, rc, N_("PIIX3 cannot register save state handlers"));
/*
* Initialize the device state.
*/
ataReset(pDevIns);
return VINF_SUCCESS;
}
/**
* The device registration structure.
*/
const PDMDEVREG g_DevicePIIX3IDE =
{
/* u32Version */
PDM_DEVREG_VERSION,
/* szDeviceName */
"piix3ide",
/* szRCMod */
"VBoxDDGC.gc",
/* szR0Mod */
"VBoxDDR0.r0",
/* pszDescription */
"Intel PIIX3 ATA controller.\n"
" LUN #0 is primary master.\n"
" LUN #1 is primary slave.\n"
" LUN #2 is secondary master.\n"
" LUN #3 is secondary slave.\n"
" LUN #999 is the LED/Status connector.",
/* fFlags */
PDM_DEVREG_FLAGS_DEFAULT_BITS | PDM_DEVREG_FLAGS_RC | PDM_DEVREG_FLAGS_R0,
/* fClass */
PDM_DEVREG_CLASS_STORAGE,
/* cMaxInstances */
1,
/* cbInstance */
sizeof(PCIATAState),
/* pfnConstruct */
ataConstruct,
/* pfnDestruct */
ataDestruct,
/* pfnRelocate */
ataRelocate,
/* pfnIOCtl */
NULL,
/* pfnPowerOn */
NULL,
/* pfnReset */
ataReset,
/* pfnSuspend */
ataSuspend,
/* pfnResume */
ataResume,
/* pfnAttach */
ataAttach,
/* pfnDetach */
ataDetach,
/* pfnQueryInterface. */
NULL,
/* pfnInitComplete */
NULL,
/* pfnPowerOff */
ataPowerOff,
/* pfnSoftReset */
NULL,
/* u32VersionEnd */
PDM_DEVREG_VERSION
};
#endif /* IN_RING3 */
#endif /* !VBOX_DEVICE_STRUCT_TESTCASE */