DevAHCI.cpp revision f20f7cf8c2a0f141965d11345d910cc8e65c1fb3
c58c758d3642ac45d3f12356c406c631fcd8f538vboxsync * DevAHCI - AHCI controller device (disk and cdrom).
c58c758d3642ac45d3f12356c406c631fcd8f538vboxsync * Implements the AHCI standard 1.1
c58c758d3642ac45d3f12356c406c631fcd8f538vboxsync * Copyright (C) 2006-2013 Oracle Corporation
c58c758d3642ac45d3f12356c406c631fcd8f538vboxsync * This file is part of VirtualBox Open Source Edition (OSE), as
c58c758d3642ac45d3f12356c406c631fcd8f538vboxsync * available from http://www.virtualbox.org. This file is free software;
c58c758d3642ac45d3f12356c406c631fcd8f538vboxsync * you can redistribute it and/or modify it under the terms of the GNU
c58c758d3642ac45d3f12356c406c631fcd8f538vboxsync * General Public License (GPL) as published by the Free Software
c58c758d3642ac45d3f12356c406c631fcd8f538vboxsync * Foundation, in version 2 as it comes in the "COPYING" file of the
c58c758d3642ac45d3f12356c406c631fcd8f538vboxsync * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
c58c758d3642ac45d3f12356c406c631fcd8f538vboxsync * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
c58c758d3642ac45d3f12356c406c631fcd8f538vboxsync/** @page pg_dev_ahci AHCI - Advanced Host Controller Interface Emulation.
c58c758d3642ac45d3f12356c406c631fcd8f538vboxsync * This component implements an AHCI serial ATA controller. The device is split
c58c758d3642ac45d3f12356c406c631fcd8f538vboxsync * into two parts. The first part implements the register interface for the
c58c758d3642ac45d3f12356c406c631fcd8f538vboxsync * guest and the second one does the data transfer.
c58c758d3642ac45d3f12356c406c631fcd8f538vboxsync * The guest can access the controller in two ways. The first one is the native
c58c758d3642ac45d3f12356c406c631fcd8f538vboxsync * way implementing the registers described in the AHCI specification and is
c58c758d3642ac45d3f12356c406c631fcd8f538vboxsync * the preferred one. The second implements the I/O ports used for booting from
c58c758d3642ac45d3f12356c406c631fcd8f538vboxsync * the hard disk and for guests which don't have an AHCI SATA driver.
5a5b5956f8b592c807c94785d58c25e717d430c4vboxsync * The data is transferred in an asynchronous way using one thread per implemented
c58c758d3642ac45d3f12356c406c631fcd8f538vboxsync * port or using the new async completion interface which is still under
c58c758d3642ac45d3f12356c406c631fcd8f538vboxsync * development. [not quite up to date]
c58c758d3642ac45d3f12356c406c631fcd8f538vboxsync/*******************************************************************************
5a5b5956f8b592c807c94785d58c25e717d430c4vboxsync* Header Files *
e4bf6817370e1a71833a02285515694afcda7599vboxsync*******************************************************************************/
1025ef7261a6961d07d390e85a095d806ccb88d9vboxsync && defined(IN_RING3) \
71e045383a3316b27563b2f44b0e0e1231968bdcvboxsync# define VBOXDD_AHCI_REQ_SUBMIT(a,b,c,d) do { } while (0)
71e045383a3316b27563b2f44b0e0e1231968bdcvboxsync# define VBOXDD_AHCI_REQ_SUBMIT_TIMESTAMP(a,b) do { } while (0)
71e045383a3316b27563b2f44b0e0e1231968bdcvboxsync# define VBOXDD_AHCI_REQ_COMPLETED(a,b,c,d,e) do { } while (0)
c553cea6bfe2ce63ff5517ca4ec288502a890e99vboxsync# define VBOXDD_AHCI_REQ_COMPLETED_TIMESTAMP(a,b) do { } while (0)
c553cea6bfe2ce63ff5517ca4ec288502a890e99vboxsync/** Maximum number of ports available.
71e045383a3316b27563b2f44b0e0e1231968bdcvboxsync * Spec defines 32 but we have one allocated for command completion coalescing
71e045383a3316b27563b2f44b0e0e1231968bdcvboxsync * and another for a reserved future feature.
c553cea6bfe2ce63ff5517ca4ec288502a890e99vboxsync/** Maximum number of command slots available. */
c553cea6bfe2ce63ff5517ca4ec288502a890e99vboxsync/** The current saved state version. */
c553cea6bfe2ce63ff5517ca4ec288502a890e99vboxsync/** The saved state version before changing the port reset logic in an incompatible way. */
c553cea6bfe2ce63ff5517ca4ec288502a890e99vboxsync#define AHCI_SAVED_STATE_VERSION_PRE_PORT_RESET_CHANGES 7
c553cea6bfe2ce63ff5517ca4ec288502a890e99vboxsync/** Saved state version before the per port hotplug port was added. */
c553cea6bfe2ce63ff5517ca4ec288502a890e99vboxsync/** Saved state version before legacy ATA emulation was dropped. */
c553cea6bfe2ce63ff5517ca4ec288502a890e99vboxsync/** Saved state version before ATAPI support was added. */
c553cea6bfe2ce63ff5517ca4ec288502a890e99vboxsync/** The saved state version use in VirtualBox 3.0 and earlier.
c553cea6bfe2ce63ff5517ca4ec288502a890e99vboxsync * This was before the config was added and ahciIOTasks was dropped. */
c553cea6bfe2ce63ff5517ca4ec288502a890e99vboxsync/* for Older ATA state Read handling */
c553cea6bfe2ce63ff5517ca4ec288502a890e99vboxsync#define ATA_CTL_SAVED_STATE_VERSION_WITHOUT_FULL_SENSE 1
c553cea6bfe2ce63ff5517ca4ec288502a890e99vboxsync#define ATA_CTL_SAVED_STATE_VERSION_WITHOUT_EVENT_STATUS 2
c553cea6bfe2ce63ff5517ca4ec288502a890e99vboxsync/** The maximum number of release log entries per device. */
c553cea6bfe2ce63ff5517ca4ec288502a890e99vboxsync * Maximum number of sectors to transfer in a READ/WRITE MULTIPLE request.
c553cea6bfe2ce63ff5517ca4ec288502a890e99vboxsync * Set to 1 to disable multi-sector read support. According to the ATA
c553cea6bfe2ce63ff5517ca4ec288502a890e99vboxsync * specification this must be a power of 2 and it must fit in an 8 bit
c553cea6bfe2ce63ff5517ca4ec288502a890e99vboxsync * value. Thus the only valid values are 1, 2, 4, 8, 16, 32, 64 and 128.
c553cea6bfe2ce63ff5517ca4ec288502a890e99vboxsync * Fastest PIO mode supported by the drive.
c553cea6bfe2ce63ff5517ca4ec288502a890e99vboxsync * Fastest MDMA mode supported by the drive.
c553cea6bfe2ce63ff5517ca4ec288502a890e99vboxsync * Fastest UDMA mode supported by the drive.
c553cea6bfe2ce63ff5517ca4ec288502a890e99vboxsync * Length of the configurable VPD data (without termination)
c553cea6bfe2ce63ff5517ca4ec288502a890e99vboxsync/* MediaEventStatus */
c553cea6bfe2ce63ff5517ca4ec288502a890e99vboxsync#define ATA_EVENT_STATUS_UNCHANGED 0 /**< medium event status not changed */
c553cea6bfe2ce63ff5517ca4ec288502a890e99vboxsync#define ATA_EVENT_STATUS_MEDIA_NEW 1 /**< new medium inserted */
c553cea6bfe2ce63ff5517ca4ec288502a890e99vboxsync#define ATA_EVENT_STATUS_MEDIA_REMOVED 2 /**< medium removed */
c553cea6bfe2ce63ff5517ca4ec288502a890e99vboxsync#define ATA_EVENT_STATUS_MEDIA_CHANGED 3 /**< medium was removed + new medium was inserted */
c553cea6bfe2ce63ff5517ca4ec288502a890e99vboxsync#define ATA_EVENT_STATUS_MEDIA_EJECT_REQUESTED 4 /**< medium eject requested (eject button pressed) */
1025ef7261a6961d07d390e85a095d806ccb88d9vboxsync/* Media track type */
1025ef7261a6961d07d390e85a095d806ccb88d9vboxsync#define ATA_MEDIA_TYPE_UNKNOWN 0 /**< unknown CD type */
1025ef7261a6961d07d390e85a095d806ccb88d9vboxsync/** ATAPI sense info size. */
1025ef7261a6961d07d390e85a095d806ccb88d9vboxsync * Command Header.
1025ef7261a6961d07d390e85a095d806ccb88d9vboxsynctypedef struct
1025ef7261a6961d07d390e85a095d806ccb88d9vboxsync /** Description Information. */
1025ef7261a6961d07d390e85a095d806ccb88d9vboxsync /** Command status. */
1025ef7261a6961d07d390e85a095d806ccb88d9vboxsync /** Command Table Base Address. */
1025ef7261a6961d07d390e85a095d806ccb88d9vboxsync /** Command Table Base Address - upper 32-bits. */
1025ef7261a6961d07d390e85a095d806ccb88d9vboxsync /** Reserved */
1025ef7261a6961d07d390e85a095d806ccb88d9vboxsync/* Defines for the command header. */
1025ef7261a6961d07d390e85a095d806ccb88d9vboxsync#define AHCI_CMDHDR_PRDTL_ENTRIES(x) ((x & AHCI_CMDHDR_PRDTL_MASK) >> 16)
1025ef7261a6961d07d390e85a095d806ccb88d9vboxsync/* Defines for the command FIS. */
1025ef7261a6961d07d390e85a095d806ccb88d9vboxsync/* Defines that are used in the first double word. */
1025ef7261a6961d07d390e85a095d806ccb88d9vboxsync# define AHCI_CMDFIS_TYPE_H2D 0x27 /* Register - Host to Device FIS. */
1025ef7261a6961d07d390e85a095d806ccb88d9vboxsync# define AHCI_CMDFIS_TYPE_H2D_SIZE 20 /* Five double words. */
1025ef7261a6961d07d390e85a095d806ccb88d9vboxsync# define AHCI_CMDFIS_TYPE_D2H 0x34 /* Register - Device to Host FIS. */
1025ef7261a6961d07d390e85a095d806ccb88d9vboxsync# define AHCI_CMDFIS_TYPE_D2H_SIZE 20 /* Five double words. */
1025ef7261a6961d07d390e85a095d806ccb88d9vboxsync# define AHCI_CMDFIS_TYPE_SETDEVBITS 0xa1 /* Set Device Bits - Device to Host FIS. */
1025ef7261a6961d07d390e85a095d806ccb88d9vboxsync# define AHCI_CMDFIS_TYPE_SETDEVBITS_SIZE 8 /* Two double words. */
1025ef7261a6961d07d390e85a095d806ccb88d9vboxsync# define AHCI_CMDFIS_TYPE_DMAACTD2H 0x39 /* DMA Activate - Device to Host FIS. */
1025ef7261a6961d07d390e85a095d806ccb88d9vboxsync# define AHCI_CMDFIS_TYPE_DMAACTD2H_SIZE 4 /* One double word. */
1025ef7261a6961d07d390e85a095d806ccb88d9vboxsync# define AHCI_CMDFIS_TYPE_DMASETUP 0x41 /* DMA Setup - Bidirectional FIS. */
1025ef7261a6961d07d390e85a095d806ccb88d9vboxsync# define AHCI_CMDFIS_TYPE_DMASETUP_SIZE 28 /* Seven double words. */
1025ef7261a6961d07d390e85a095d806ccb88d9vboxsync# define AHCI_CMDFIS_TYPE_PIOSETUP 0x5f /* PIO Setup - Device to Host FIS. */
1025ef7261a6961d07d390e85a095d806ccb88d9vboxsync# define AHCI_CMDFIS_TYPE_PIOSETUP_SIZE 20 /* Five double words. */
1025ef7261a6961d07d390e85a095d806ccb88d9vboxsync# define AHCI_CMDFIS_TYPE_DATA 0x46 /* Data - Bidirectional FIS. */
1025ef7261a6961d07d390e85a095d806ccb88d9vboxsync#define AHCI_CMDFIS_BITS 1 /* Interrupt and Update bit. */
1025ef7261a6961d07d390e85a095d806ccb88d9vboxsync#define AHCI_CMDFIS_C RT_BIT(7) /* Host to device. */
1025ef7261a6961d07d390e85a095d806ccb88d9vboxsync#define AHCI_CMDFIS_I RT_BIT(6) /* Device to Host. */
1025ef7261a6961d07d390e85a095d806ccb88d9vboxsync# define AHCI_CMDFIS_CTL_SRST RT_BIT(2) /* Reset device. */
1025ef7261a6961d07d390e85a095d806ccb88d9vboxsync# define AHCI_CMDFIS_CTL_NIEN RT_BIT(1) /* Assert or clear interrupt. */
1025ef7261a6961d07d390e85a095d806ccb88d9vboxsync/* For D2H FIS */
1025ef7261a6961d07d390e85a095d806ccb88d9vboxsync/** Pointer to a task state. */
1025ef7261a6961d07d390e85a095d806ccb88d9vboxsync * Data processing callback
1025ef7261a6961d07d390e85a095d806ccb88d9vboxsync * @returns VBox status.
1025ef7261a6961d07d390e85a095d806ccb88d9vboxsync * @param pAhciReq The task state.
1025ef7261a6961d07d390e85a095d806ccb88d9vboxsync * @param ppvProc Where to store the pointer to the buffer holding the processed data on success.
1025ef7261a6961d07d390e85a095d806ccb88d9vboxsync * Must be freed with RTMemFree().
1025ef7261a6961d07d390e85a095d806ccb88d9vboxsync * @param pcbProc Where to store the size of the buffer on success.
1025ef7261a6961d07d390e85a095d806ccb88d9vboxsynctypedef DECLCALLBACK(int) FNAHCIPOSTPROCESS(PAHCIREQ pAhciReq, void **ppvProc, size_t *pcbProc);
1025ef7261a6961d07d390e85a095d806ccb88d9vboxsync/** Pointer to a FNAHCIPOSTPROCESS() function. */
1025ef7261a6961d07d390e85a095d806ccb88d9vboxsync * Transfer type.
1025ef7261a6961d07d390e85a095d806ccb88d9vboxsync /** Invalid */
1025ef7261a6961d07d390e85a095d806ccb88d9vboxsync /** None */
1025ef7261a6961d07d390e85a095d806ccb88d9vboxsync /** Read */
1025ef7261a6961d07d390e85a095d806ccb88d9vboxsync /** Write */
1025ef7261a6961d07d390e85a095d806ccb88d9vboxsync /** Flush */
1025ef7261a6961d07d390e85a095d806ccb88d9vboxsync /** Trim */
1025ef7261a6961d07d390e85a095d806ccb88d9vboxsync * Task state.
1025ef7261a6961d07d390e85a095d806ccb88d9vboxsync /** Invalid. */
1025ef7261a6961d07d390e85a095d806ccb88d9vboxsync /** Task is not active. */
e4bf6817370e1a71833a02285515694afcda7599vboxsync /** Task is active */
e4bf6817370e1a71833a02285515694afcda7599vboxsync /** Task was canceled but the request didn't completed yet. */
e4bf6817370e1a71833a02285515694afcda7599vboxsync /** 32bit hack. */
e4bf6817370e1a71833a02285515694afcda7599vboxsync/** Task encountered a buffer overflow. */
1025ef7261a6961d07d390e85a095d806ccb88d9vboxsync/** Request is a PIO data command, if this flag is not set it either is
113a43aca041000560f93f9a8ee23dfcf01a9e7cvboxsync * a command which does not transfer data or a DMA command based on the transfer size. */
113a43aca041000560f93f9a8ee23dfcf01a9e7cvboxsync/** The request has the SACT register set. */
113a43aca041000560f93f9a8ee23dfcf01a9e7cvboxsync/** FLag whether the request is queued. */
113a43aca041000560f93f9a8ee23dfcf01a9e7cvboxsync * A task state.
113a43aca041000560f93f9a8ee23dfcf01a9e7cvboxsynctypedef struct AHCIREQ
113a43aca041000560f93f9a8ee23dfcf01a9e7cvboxsync /** Task state. */
113a43aca041000560f93f9a8ee23dfcf01a9e7cvboxsync /** Start timestamp of the request. */
113a43aca041000560f93f9a8ee23dfcf01a9e7cvboxsync /** Tag of the task. */
113a43aca041000560f93f9a8ee23dfcf01a9e7cvboxsync /** The command header for this task. */
113a43aca041000560f93f9a8ee23dfcf01a9e7cvboxsync /** The command Fis for this task. */
113a43aca041000560f93f9a8ee23dfcf01a9e7cvboxsync /** The ATAPI command data. */
113a43aca041000560f93f9a8ee23dfcf01a9e7cvboxsync /** Size of one sector for the ATAPI transfer. */
113a43aca041000560f93f9a8ee23dfcf01a9e7cvboxsync /** Physical address of the command header. - GC */
113a43aca041000560f93f9a8ee23dfcf01a9e7cvboxsync /** Physical address if the PRDT */
113a43aca041000560f93f9a8ee23dfcf01a9e7cvboxsync /** Number of entries in the PRDTL. */
113a43aca041000560f93f9a8ee23dfcf01a9e7cvboxsync /** Data direction. */
113a43aca041000560f93f9a8ee23dfcf01a9e7cvboxsync /** Start offset. */
113a43aca041000560f93f9a8ee23dfcf01a9e7cvboxsync /** Number of bytes to transfer. */
113a43aca041000560f93f9a8ee23dfcf01a9e7cvboxsync /** ATA error register */
113a43aca041000560f93f9a8ee23dfcf01a9e7cvboxsync /** ATA status register */
113a43aca041000560f93f9a8ee23dfcf01a9e7cvboxsync /** Flags for this task. */
113a43aca041000560f93f9a8ee23dfcf01a9e7cvboxsync /** Additional memory allocation for this task. */
113a43aca041000560f93f9a8ee23dfcf01a9e7cvboxsync /** Siize of the allocation. */
113a43aca041000560f93f9a8ee23dfcf01a9e7cvboxsync /** Number of times we had too much memory allocated for the request. */
113a43aca041000560f93f9a8ee23dfcf01a9e7cvboxsync /** Data dependent on the transfer direction. */
113a43aca041000560f93f9a8ee23dfcf01a9e7cvboxsync /** Data for an I/O request. */
113a43aca041000560f93f9a8ee23dfcf01a9e7cvboxsync /** Data segment. */
113a43aca041000560f93f9a8ee23dfcf01a9e7cvboxsync /** Post processing callback.
113a43aca041000560f93f9a8ee23dfcf01a9e7cvboxsync * If this is set we will use a buffer for the data
113a43aca041000560f93f9a8ee23dfcf01a9e7cvboxsync * and the callback returns a buffer with the final data. */
c58c758d3642ac45d3f12356c406c631fcd8f538vboxsync /** Data for a trim request. */
e4bf6817370e1a71833a02285515694afcda7599vboxsync /** Pointer to the array of ranges to trim. */
e4bf6817370e1a71833a02285515694afcda7599vboxsync /** Number of entries in the array. */
5b0a093ca572a855886faa6747ad46df859dd041vboxsync * Notifier queue item.
5b0a093ca572a855886faa6747ad46df859dd041vboxsync /** The core part owned by the queue manager. */
5b0a093ca572a855886faa6747ad46df859dd041vboxsync /** The port to process. */
5b0a093ca572a855886faa6747ad46df859dd041vboxsync} DEVPORTNOTIFIERQUEUEITEM, *PDEVPORTNOTIFIERQUEUEITEM;
5b0a093ca572a855886faa6747ad46df859dd041vboxsync * @implements PDMIBASE
5b0a093ca572a855886faa6747ad46df859dd041vboxsync * @implements PDMIBLOCKPORT
5b0a093ca572a855886faa6747ad46df859dd041vboxsync * @implements PDMIBLOCKASYNCPORT
5b0a093ca572a855886faa6747ad46df859dd041vboxsync * @implements PDMIMOUNTNOTIFY
5b0a093ca572a855886faa6747ad46df859dd041vboxsynctypedef struct AHCIPort
5b0a093ca572a855886faa6747ad46df859dd041vboxsync /** Pointer to the device instance - HC ptr */
ad66a27959d7085aa31760f63ce082943be60e89vboxsync /** Pointer to the device instance - R0 ptr */
ad66a27959d7085aa31760f63ce082943be60e89vboxsync /** Pointer to the device instance - RC ptr. */
ad66a27959d7085aa31760f63ce082943be60e89vboxsync /** Pointer to the parent AHCI structure - R3 ptr. */
ad66a27959d7085aa31760f63ce082943be60e89vboxsync /** Pointer to the parent AHCI structure - R0 ptr. */
c553cea6bfe2ce63ff5517ca4ec288502a890e99vboxsync /** Pointer to the parent AHCI structure - RC ptr. */
ad66a27959d7085aa31760f63ce082943be60e89vboxsync /** Command List Base Address. */
ad66a27959d7085aa31760f63ce082943be60e89vboxsync /** Command List Base Address upper bits. */
4b8c66482cbc69a01ac399b8588b8bc80b310523vboxsync /** FIS Base Address. */
4b8c66482cbc69a01ac399b8588b8bc80b310523vboxsync /** FIS Base Address upper bits. */
4b8c66482cbc69a01ac399b8588b8bc80b310523vboxsync /** Interrupt Status. */
4b8c66482cbc69a01ac399b8588b8bc80b310523vboxsync /** Interrupt Enable. */
4b8c66482cbc69a01ac399b8588b8bc80b310523vboxsync /** Command. */
4b8c66482cbc69a01ac399b8588b8bc80b310523vboxsync /** Task File Data. */
4b8c66482cbc69a01ac399b8588b8bc80b310523vboxsync /** Signature */
4b8c66482cbc69a01ac399b8588b8bc80b310523vboxsync /** Serial ATA Status. */
4bf996d915405be92dc4394b2db1395e00e14d58vboxsync /** Serial ATA Control. */
c58c758d3642ac45d3f12356c406c631fcd8f538vboxsync /** Serial ATA Error. */
c58c758d3642ac45d3f12356c406c631fcd8f538vboxsync /** Serial ATA Active. */
5b0a093ca572a855886faa6747ad46df859dd041vboxsync /** Command Issue. */
ad66a27959d7085aa31760f63ce082943be60e89vboxsync /** Current number of active tasks. */
5b0a093ca572a855886faa6747ad46df859dd041vboxsync /** Command List Base Address */
5b0a093ca572a855886faa6747ad46df859dd041vboxsync /** FIS Base Address */
5b0a093ca572a855886faa6747ad46df859dd041vboxsync /** Device is powered on. */
5b0a093ca572a855886faa6747ad46df859dd041vboxsync /** Device has spun up. */
5b0a093ca572a855886faa6747ad46df859dd041vboxsync /** First D2H FIS was send. */
3bb3e26b3306b9f62b18c17380bdf2ca3a98ca49vboxsync /** Mark the drive as having a non-rotational medium (i.e. as a SSD). */
5b0a093ca572a855886faa6747ad46df859dd041vboxsync /** Attached device is a CD/DVD drive. */
ad66a27959d7085aa31760f63ce082943be60e89vboxsync /** Passthrough SCSI commands. */
ad66a27959d7085aa31760f63ce082943be60e89vboxsync /** Flag whether this port is in a reset state. */
ad66a27959d7085aa31760f63ce082943be60e89vboxsync volatile bool fPortReset;
ad66a27959d7085aa31760f63ce082943be60e89vboxsync /** If we use the new async interface. */
ad66a27959d7085aa31760f63ce082943be60e89vboxsync /** Flag if we are in a device reset. */
ad66a27959d7085aa31760f63ce082943be60e89vboxsync /** Flag whether this port is hot plug capable. */
e4bf6817370e1a71833a02285515694afcda7599vboxsync /** Flag whether the port is in redo task mode. */
e4bf6817370e1a71833a02285515694afcda7599vboxsync volatile bool fRedo;
e961f5bfe1727c6816d3dad3805ebe21b6ba1c64vboxsync /** Flag whether the worker thread is sleeping. */
4b8c66482cbc69a01ac399b8588b8bc80b310523vboxsync /** Number of total sectors. */
4b8c66482cbc69a01ac399b8588b8bc80b310523vboxsync /** Size of one sector. */
4b8c66482cbc69a01ac399b8588b8bc80b310523vboxsync /** Currently configured number of sectors in a multi-sector transfer. */
4b8c66482cbc69a01ac399b8588b8bc80b310523vboxsync /** Currently active transfer mode (MDMA/UDMA) and speed. */
4b8c66482cbc69a01ac399b8588b8bc80b310523vboxsync /** ATAPI sense data. */
4b8c66482cbc69a01ac399b8588b8bc80b310523vboxsync /** HACK: Countdown till we report a newly unmounted drive as mounted. */
4b8c66482cbc69a01ac399b8588b8bc80b310523vboxsync /** Exponent of logical sectors in a physical sector, number of logical sectors is 2^exp. */
c58c758d3642ac45d3f12356c406c631fcd8f538vboxsync /** The same for GET_EVENT_STATUS for mechanism */
c58c758d3642ac45d3f12356c406c631fcd8f538vboxsync /** Media type if known. */
4bf996d915405be92dc4394b2db1395e00e14d58vboxsync /** The LUN. */
b26e5b503baa3dffc58048982eaf17ad1b53f207vboxsync /** Bitmap for finished tasks (R3 -> Guest). */
b26e5b503baa3dffc58048982eaf17ad1b53f207vboxsync /** Bitmap for finished queued tasks (R3 -> Guest). */
b26e5b503baa3dffc58048982eaf17ad1b53f207vboxsync /** Bitmap for new queued tasks (Guest -> R3). */
71e045383a3316b27563b2f44b0e0e1231968bdcvboxsync /** Bitmap of tasks which must be redone because of a non fatal error. */
b26e5b503baa3dffc58048982eaf17ad1b53f207vboxsync /** Current command slot processed.
71e045383a3316b27563b2f44b0e0e1231968bdcvboxsync * Accessed by the guest by reading the CMD register.
b26e5b503baa3dffc58048982eaf17ad1b53f207vboxsync * Holds the command slot of the command processed at the moment. */
71e045383a3316b27563b2f44b0e0e1231968bdcvboxsync /** Device specific settings (R3 only stuff). */
4bf996d915405be92dc4394b2db1395e00e14d58vboxsync /** Pointer to the attached driver's base interface. */
4bf996d915405be92dc4394b2db1395e00e14d58vboxsync /** Pointer to the attached driver's block interface. */
ad66a27959d7085aa31760f63ce082943be60e89vboxsync /** Pointer to the attached driver's async block interface. */
71e045383a3316b27563b2f44b0e0e1231968bdcvboxsync /** Pointer to the attached driver's block bios interface. */
4bf996d915405be92dc4394b2db1395e00e14d58vboxsync /** Pointer to the attached driver's mount interface. */
4bf996d915405be92dc4394b2db1395e00e14d58vboxsync /** The base interface. */
4bf996d915405be92dc4394b2db1395e00e14d58vboxsync /** The block port interface. */
4bf996d915405be92dc4394b2db1395e00e14d58vboxsync /** The optional block async port interface. */
4bf996d915405be92dc4394b2db1395e00e14d58vboxsync /** The mount notify interface. */
4bf996d915405be92dc4394b2db1395e00e14d58vboxsync /** Physical geometry of this image. */
4bf996d915405be92dc4394b2db1395e00e14d58vboxsync /** The status LED state for this drive. */
4bf996d915405be92dc4394b2db1395e00e14d58vboxsync /** Async IO Thread. */
4b8c66482cbc69a01ac399b8588b8bc80b310523vboxsync * Array of cached tasks. The tag number is the index value.
4bf996d915405be92dc4394b2db1395e00e14d58vboxsync * Only used with the async interface.
4bf996d915405be92dc4394b2db1395e00e14d58vboxsync R3PTRTYPE(PAHCIREQ) aCachedTasks[AHCI_NR_COMMAND_SLOTS];
4bf996d915405be92dc4394b2db1395e00e14d58vboxsync /** First task throwing an error. */
4bf996d915405be92dc4394b2db1395e00e14d58vboxsync /** The current tracklist of the loaded medium if passthrough is used. */
4bf996d915405be92dc4394b2db1395e00e14d58vboxsync /** The event semaphore the processing thread waits on. */
4bf996d915405be92dc4394b2db1395e00e14d58vboxsync /** Release statistics: number of DMA commands. */
4bf996d915405be92dc4394b2db1395e00e14d58vboxsync /** Release statistics: number of bytes written. */
4bf996d915405be92dc4394b2db1395e00e14d58vboxsync /** Release statistics: number of bytes read. */
4bf996d915405be92dc4394b2db1395e00e14d58vboxsync /** Release statistics: Number of I/O requests processed per second. */
4bf996d915405be92dc4394b2db1395e00e14d58vboxsync /** Statistics: Time to complete one request. */
4bf996d915405be92dc4394b2db1395e00e14d58vboxsync /** Statistics: Amount of time to read/write data. */
4bf996d915405be92dc4394b2db1395e00e14d58vboxsync#endif /* VBOX_WITH_STATISTICS */
4bf996d915405be92dc4394b2db1395e00e14d58vboxsync /** The serial numnber to use for IDENTIFY DEVICE commands. */
4bf996d915405be92dc4394b2db1395e00e14d58vboxsync char szSerialNumber[AHCI_SERIAL_NUMBER_LENGTH+1]; /** < one extra byte for termination */
4bf996d915405be92dc4394b2db1395e00e14d58vboxsync /** The firmware revision to use for IDENTIFY DEVICE commands. */
4bf996d915405be92dc4394b2db1395e00e14d58vboxsync char szFirmwareRevision[AHCI_FIRMWARE_REVISION_LENGTH+1]; /** < one extra byte for termination */
4bf996d915405be92dc4394b2db1395e00e14d58vboxsync /** The model number to use for IDENTIFY DEVICE commands. */
4bf996d915405be92dc4394b2db1395e00e14d58vboxsync char szModelNumber[AHCI_MODEL_NUMBER_LENGTH+1]; /** < one extra byte for termination */
4bf996d915405be92dc4394b2db1395e00e14d58vboxsync /** The vendor identification string for SCSI INQUIRY commands. */
4bf996d915405be92dc4394b2db1395e00e14d58vboxsync char szInquiryVendorId[AHCI_ATAPI_INQUIRY_VENDOR_ID_LENGTH+1];
4bf996d915405be92dc4394b2db1395e00e14d58vboxsync /** The product identification string for SCSI INQUIRY commands. */
4bf996d915405be92dc4394b2db1395e00e14d58vboxsync char szInquiryProductId[AHCI_ATAPI_INQUIRY_PRODUCT_ID_LENGTH+1];
e4bf6817370e1a71833a02285515694afcda7599vboxsync /** The revision string for SCSI INQUIRY commands. */
e4bf6817370e1a71833a02285515694afcda7599vboxsync char szInquiryRevision[AHCI_ATAPI_INQUIRY_REVISION_LENGTH+1];
e4bf6817370e1a71833a02285515694afcda7599vboxsync /** Error counter */
e4bf6817370e1a71833a02285515694afcda7599vboxsync/** Pointer to the state of an AHCI port. */
e4bf6817370e1a71833a02285515694afcda7599vboxsync * Main AHCI device state.
e4bf6817370e1a71833a02285515694afcda7599vboxsync * @implements PDMILEDPORTS
e4bf6817370e1a71833a02285515694afcda7599vboxsynctypedef struct AHCI
e4bf6817370e1a71833a02285515694afcda7599vboxsync /** The PCI device structure. */
e4bf6817370e1a71833a02285515694afcda7599vboxsync /** Pointer to the device instance - R3 ptr */
e4bf6817370e1a71833a02285515694afcda7599vboxsync /** Pointer to the device instance - R0 ptr */
e4bf6817370e1a71833a02285515694afcda7599vboxsync /** Pointer to the device instance - RC ptr. */
e4bf6817370e1a71833a02285515694afcda7599vboxsync /** Status LUN: The base interface. */
e4bf6817370e1a71833a02285515694afcda7599vboxsync /** Status LUN: Leds interface. */
e4bf6817370e1a71833a02285515694afcda7599vboxsync /** Status LUN: Partner of ILeds. */
e4bf6817370e1a71833a02285515694afcda7599vboxsync /** Status LUN: Media Notifys. */
725fba5c64717677ac66072bae37e5b3686f3e6dvboxsync /** Base address of the MMIO region. */
e4bf6817370e1a71833a02285515694afcda7599vboxsync /** Base address of the I/O port region for Idx/Data. */
e4bf6817370e1a71833a02285515694afcda7599vboxsync /** Global Host Control register of the HBA */
e4bf6817370e1a71833a02285515694afcda7599vboxsync /** HBA Capabilities - Readonly */
e4bf6817370e1a71833a02285515694afcda7599vboxsync /** HBA Control */
725fba5c64717677ac66072bae37e5b3686f3e6dvboxsync /** Interrupt Status */
e4bf6817370e1a71833a02285515694afcda7599vboxsync /** Ports Implemented - Readonly */
e4bf6817370e1a71833a02285515694afcda7599vboxsync /** AHCI Version - Readonly */
e4bf6817370e1a71833a02285515694afcda7599vboxsync /** Command completion coalescing control */
725fba5c64717677ac66072bae37e5b3686f3e6dvboxsync /** Command completion coalescing ports */
e4bf6817370e1a71833a02285515694afcda7599vboxsync /** Index register for BIOS access. */
e4bf6817370e1a71833a02285515694afcda7599vboxsync /** Countdown timer for command completion coalescing - R3 ptr */
e4bf6817370e1a71833a02285515694afcda7599vboxsync /** Countdown timer for command completion coalescing - R0 ptr */
e4bf6817370e1a71833a02285515694afcda7599vboxsync /** Countdown timer for command completion coalescing - RC ptr */
e4bf6817370e1a71833a02285515694afcda7599vboxsync /** Queue to send tasks to R3. - HC ptr */
e4bf6817370e1a71833a02285515694afcda7599vboxsync /** Queue to send tasks to R3. - HC ptr */
e4bf6817370e1a71833a02285515694afcda7599vboxsync /** Queue to send tasks to R3. - RC ptr */
e4bf6817370e1a71833a02285515694afcda7599vboxsync /** Which port number is used to mark an CCC interrupt */
e4bf6817370e1a71833a02285515694afcda7599vboxsync /** Timeout value */
e4bf6817370e1a71833a02285515694afcda7599vboxsync /** Number of completions used to assert an interrupt */
e4bf6817370e1a71833a02285515694afcda7599vboxsync /** Current number of completed commands */
725fba5c64717677ac66072bae37e5b3686f3e6dvboxsync /** Register structure per port */
e4bf6817370e1a71833a02285515694afcda7599vboxsync /** The critical section. */
e4bf6817370e1a71833a02285515694afcda7599vboxsync /** Bitmask of ports which asserted an interrupt. */
e4bf6817370e1a71833a02285515694afcda7599vboxsync /** Number of I/O threads currently active - used for async controller reset handling. */
e4bf6817370e1a71833a02285515694afcda7599vboxsync /** Device is in a reset state. */
e4bf6817370e1a71833a02285515694afcda7599vboxsync /** Supports 64bit addressing */
e4bf6817370e1a71833a02285515694afcda7599vboxsync /** GC enabled. */
e4bf6817370e1a71833a02285515694afcda7599vboxsync /** R0 enabled. */
e4bf6817370e1a71833a02285515694afcda7599vboxsync /** If the new async interface is used if available. */
e4bf6817370e1a71833a02285515694afcda7599vboxsync /** Indicates that PDMDevHlpAsyncNotificationCompleted should be called when
e4bf6817370e1a71833a02285515694afcda7599vboxsync * a port is entering the idle state. */
e4bf6817370e1a71833a02285515694afcda7599vboxsync bool volatile fSignalIdle;
e4bf6817370e1a71833a02285515694afcda7599vboxsync /** Flag whether the controller has BIOS access enabled. */
e4bf6817370e1a71833a02285515694afcda7599vboxsync /** Flag whether the legacy port reset method should be used to make it work with saved states. */
e4bf6817370e1a71833a02285515694afcda7599vboxsync /** Number of usable ports on this controller. */
e4bf6817370e1a71833a02285515694afcda7599vboxsync /** Number of usable command slots for each port. */
113a43aca041000560f93f9a8ee23dfcf01a9e7cvboxsync /** Flag whether we have written the first 4bytes in an 8byte MMIO write successfully. */
113a43aca041000560f93f9a8ee23dfcf01a9e7cvboxsync /** The support driver session handle. */
113a43aca041000560f93f9a8ee23dfcf01a9e7cvboxsync/** Pointer to the state of an AHCI device. */
113a43aca041000560f93f9a8ee23dfcf01a9e7cvboxsync * Scatter gather list entry.
e4bf6817370e1a71833a02285515694afcda7599vboxsynctypedef struct
e4bf6817370e1a71833a02285515694afcda7599vboxsync /** Data Base Address. */
725fba5c64717677ac66072bae37e5b3686f3e6dvboxsync /** Data Base Address - Upper 32-bits. */
e4bf6817370e1a71833a02285515694afcda7599vboxsync /** Reserved */
e4bf6817370e1a71833a02285515694afcda7599vboxsync /** Description information. */
e4bf6817370e1a71833a02285515694afcda7599vboxsync/** Defines for a scatter gather list entry. */
725fba5c64717677ac66072bae37e5b3686f3e6dvboxsync/* Defines for the global host control registers for the HBA. */
e4bf6817370e1a71833a02285515694afcda7599vboxsync/* Defines for the HBA Capabilities - Readonly */
e4bf6817370e1a71833a02285515694afcda7599vboxsync#define AHCI_HBA_CAP_ISS (RT_BIT(23) | RT_BIT(22) | RT_BIT(21) | RT_BIT(20))
e4bf6817370e1a71833a02285515694afcda7599vboxsync# define AHCI_HBA_CAP_ISS_SHIFT(x) (((x) << 20) & AHCI_HBA_CAP_ISS)
e4bf6817370e1a71833a02285515694afcda7599vboxsync#define AHCI_HBA_CAP_NCS (RT_BIT(12) | RT_BIT(11) | RT_BIT(10) | RT_BIT(9) | RT_BIT(8))
e4bf6817370e1a71833a02285515694afcda7599vboxsync#define AHCI_HBA_CAP_NCS_SET(x) (((x-1) << 8) & AHCI_HBA_CAP_NCS) /* 0's based */
e4bf6817370e1a71833a02285515694afcda7599vboxsync#define AHCI_HBA_CAP_NP (RT_BIT(4) | RT_BIT(3) | RT_BIT(2) | RT_BIT(1) | RT_BIT(0))
e4bf6817370e1a71833a02285515694afcda7599vboxsync#define AHCI_HBA_CAP_NP_SET(x) ((x-1) & AHCI_HBA_CAP_NP) /* 0's based */
e4bf6817370e1a71833a02285515694afcda7599vboxsync/* Defines for the HBA Control register - Read/Write */
e4bf6817370e1a71833a02285515694afcda7599vboxsync#define AHCI_HBA_CTRL_RW_MASK (RT_BIT(0) | RT_BIT(1)) /* Mask for the used bits */
e4bf6817370e1a71833a02285515694afcda7599vboxsync/* Defines for the HBA Version register - Readonly (We support AHCI 1.0) */
e4bf6817370e1a71833a02285515694afcda7599vboxsync/* Defines for the command completion coalescing control register */
e4bf6817370e1a71833a02285515694afcda7599vboxsync#define AHCI_HBA_CCC_CTL_TV_GET(x) ((x & AHCI_HBA_CCC_CTL_TV) >> 16)
e4bf6817370e1a71833a02285515694afcda7599vboxsync#define AHCI_HBA_CCC_CTL_CC_GET(x) ((x & AHCI_HBA_CCC_CTL_CC) >> 8)
e4bf6817370e1a71833a02285515694afcda7599vboxsync#define AHCI_HBA_CCC_CTL_INT_GET(x) ((x & AHCI_HBA_CCC_CTL_INT) >> 3)
e4bf6817370e1a71833a02285515694afcda7599vboxsync/* Defines for the port registers. */
e4bf6817370e1a71833a02285515694afcda7599vboxsync#define AHCI_PORT_CLB_RESERVED 0xfffffc00 /* For masking out the reserved bits. */
725fba5c64717677ac66072bae37e5b3686f3e6dvboxsync#define AHCI_PORT_FB_RESERVED 0xffffff00 /* For masking out the reserved bits. */
725fba5c64717677ac66072bae37e5b3686f3e6dvboxsync#define AHCI_PORT_IS_READONLY 0xfd8000af /* Readonly mask including reserved bits. */
113a43aca041000560f93f9a8ee23dfcf01a9e7cvboxsync#define AHCI_PORT_IE_DIE RT_BIT(7) /* Not supported for now, readonly. */
725fba5c64717677ac66072bae37e5b3686f3e6dvboxsync#define AHCI_PORT_IE_READONLY (0xfdc000ff) /* Readonly mask including reserved bits. */
725fba5c64717677ac66072bae37e5b3686f3e6dvboxsync#define AHCI_PORT_CMD_ICC (RT_BIT(28) | RT_BIT(29) | RT_BIT(30) | RT_BIT(31))
725fba5c64717677ac66072bae37e5b3686f3e6dvboxsync#define AHCI_PORT_CMD_ASP RT_BIT(27) /* Not supported - Readonly */
113a43aca041000560f93f9a8ee23dfcf01a9e7cvboxsync#define AHCI_PORT_CMD_ALPE RT_BIT(26) /* Not supported - Readonly */
e4bf6817370e1a71833a02285515694afcda7599vboxsync#define AHCI_PORT_CMD_PMA RT_BIT(17) /* Not supported - Readonly */
4b8c66482cbc69a01ac399b8588b8bc80b310523vboxsync#define AHCI_PORT_CMD_CCS (RT_BIT(8) | RT_BIT(9) | RT_BIT(10) | RT_BIT(11) | RT_BIT(12))
4b8c66482cbc69a01ac399b8588b8bc80b310523vboxsync#define AHCI_PORT_CMD_CCS_SHIFT(x) (x << 8) /* Readonly */
4b8c66482cbc69a01ac399b8588b8bc80b310523vboxsync#define AHCI_PORT_CMD_READONLY (0xff02001f & ~(AHCI_PORT_CMD_ASP | AHCI_PORT_CMD_ALPE | AHCI_PORT_CMD_PMA))
4b8c66482cbc69a01ac399b8588b8bc80b310523vboxsync#define AHCI_PORT_SCTL_IPM (RT_BIT(11) | RT_BIT(10) | RT_BIT(9) | RT_BIT(8))
4b8c66482cbc69a01ac399b8588b8bc80b310523vboxsync#define AHCI_PORT_SCTL_IPM_GET(x) ((x & AHCI_PORT_SCTL_IPM) >> 8)
4b8c66482cbc69a01ac399b8588b8bc80b310523vboxsync#define AHCI_PORT_SCTL_SPD (RT_BIT(7) | RT_BIT(6) | RT_BIT(5) | RT_BIT(4))
4b8c66482cbc69a01ac399b8588b8bc80b310523vboxsync#define AHCI_PORT_SCTL_SPD_GET(x) ((x & AHCI_PORT_SCTL_SPD) >> 4)
4b8c66482cbc69a01ac399b8588b8bc80b310523vboxsync#define AHCI_PORT_SCTL_DET (RT_BIT(3) | RT_BIT(2) | RT_BIT(1) | RT_BIT(0))
4b8c66482cbc69a01ac399b8588b8bc80b310523vboxsync#define AHCI_PORT_SCTL_DET_GET(x) (x & AHCI_PORT_SCTL_DET)
4b8c66482cbc69a01ac399b8588b8bc80b310523vboxsync#define AHCI_PORT_SSTS_IPM (RT_BIT(11) | RT_BIT(10) | RT_BIT(9) | RT_BIT(8))
4b8c66482cbc69a01ac399b8588b8bc80b310523vboxsync#define AHCI_PORT_SSTS_IPM_GET(x) ((x & AHCI_PORT_SCTL_IPM) >> 8)
4b8c66482cbc69a01ac399b8588b8bc80b310523vboxsync#define AHCI_PORT_SSTS_SPD (RT_BIT(7) | RT_BIT(6) | RT_BIT(5) | RT_BIT(4))
4b8c66482cbc69a01ac399b8588b8bc80b310523vboxsync#define AHCI_PORT_SSTS_SPD_GET(x) ((x & AHCI_PORT_SCTL_SPD) >> 4)
4b8c66482cbc69a01ac399b8588b8bc80b310523vboxsync#define AHCI_PORT_SSTS_DET (RT_BIT(3) | RT_BIT(2) | RT_BIT(1) | RT_BIT(0))
4b8c66482cbc69a01ac399b8588b8bc80b310523vboxsync#define AHCI_PORT_SSTS_DET_GET(x) (x & AHCI_PORT_SCTL_DET)
725fba5c64717677ac66072bae37e5b3686f3e6dvboxsync/* Signatures for attached storage devices. */
725fba5c64717677ac66072bae37e5b3686f3e6dvboxsync * The AHCI spec defines an area of memory where the HBA posts received FIS's from the device.
725fba5c64717677ac66072bae37e5b3686f3e6dvboxsync * regFB points to the base of this area.
725fba5c64717677ac66072bae37e5b3686f3e6dvboxsync * Every FIS type has an offset where it is posted in this area.
725fba5c64717677ac66072bae37e5b3686f3e6dvboxsync#define AHCI_RECFIS_DSFIS_OFFSET 0x00 /* DMA Setup FIS */
725fba5c64717677ac66072bae37e5b3686f3e6dvboxsync#define AHCI_RECFIS_PSFIS_OFFSET 0x20 /* PIO Setup FIS */
725fba5c64717677ac66072bae37e5b3686f3e6dvboxsync#define AHCI_RECFIS_RFIS_OFFSET 0x40 /* D2H Register FIS */
725fba5c64717677ac66072bae37e5b3686f3e6dvboxsync#define AHCI_RECFIS_SDBFIS_OFFSET 0x58 /* Set Device Bits FIS */
725fba5c64717677ac66072bae37e5b3686f3e6dvboxsync#define AHCI_RECFIS_UFIS_OFFSET 0x60 /* Unknown FIS type */
725fba5c64717677ac66072bae37e5b3686f3e6dvboxsync/** Mask to get the LBA value from a LBA range. */
725fba5c64717677ac66072bae37e5b3686f3e6dvboxsync#define AHCI_RANGE_LBA_MASK UINT64_C(0xffffffffffff)
725fba5c64717677ac66072bae37e5b3686f3e6dvboxsync/** Mas to get the length value from a LBA range. */
725fba5c64717677ac66072bae37e5b3686f3e6dvboxsync#define AHCI_RANGE_LENGTH_MASK UINT64_C(0xffff000000000000)
725fba5c64717677ac66072bae37e5b3686f3e6dvboxsync/** Returns the length of the range in sectors. */
725fba5c64717677ac66072bae37e5b3686f3e6dvboxsync#define AHCI_RANGE_LENGTH_GET(val) (((val) & AHCI_RANGE_LENGTH_MASK) >> 48)
725fba5c64717677ac66072bae37e5b3686f3e6dvboxsync * AHCI register operator.
725fba5c64717677ac66072bae37e5b3686f3e6dvboxsynctypedef struct ahci_opreg
725fba5c64717677ac66072bae37e5b3686f3e6dvboxsync const char *pszName;
725fba5c64717677ac66072bae37e5b3686f3e6dvboxsync int (*pfnRead )(PAHCI ahci, uint32_t iReg, uint32_t *pu32Value);
725fba5c64717677ac66072bae37e5b3686f3e6dvboxsync int (*pfnWrite)(PAHCI ahci, uint32_t iReg, uint32_t u32Value);
725fba5c64717677ac66072bae37e5b3686f3e6dvboxsync * AHCI port register operator.
725fba5c64717677ac66072bae37e5b3686f3e6dvboxsync const char *pszName;
725fba5c64717677ac66072bae37e5b3686f3e6dvboxsync int (*pfnRead )(PAHCI ahci, PAHCIPort pAhciPort, uint32_t iReg, uint32_t *pu32Value);
725fba5c64717677ac66072bae37e5b3686f3e6dvboxsync int (*pfnWrite)(PAHCI ahci, PAHCIPort pAhciPort, uint32_t iReg, uint32_t u32Value);
725fba5c64717677ac66072bae37e5b3686f3e6dvboxsyncstatic int ahciPostFisIntoMemory(PAHCIPort pAhciPort, unsigned uFisType, uint8_t *cmdFis);
725fba5c64717677ac66072bae37e5b3686f3e6dvboxsyncstatic void ahciPostFirstD2HFisIntoMemory(PAHCIPort pAhciPort);
725fba5c64717677ac66072bae37e5b3686f3e6dvboxsyncstatic size_t ahciCopyToPrdtl(PPDMDEVINS pDevIns, PAHCIREQ pAhciReq,
725fba5c64717677ac66072bae37e5b3686f3e6dvboxsyncstatic size_t ahciCopyFromPrdtl(PPDMDEVINS pDevIns, PAHCIREQ pAhciReq,
725fba5c64717677ac66072bae37e5b3686f3e6dvboxsyncstatic bool ahciCancelActiveTasks(PAHCIPort pAhciPort);
725fba5c64717677ac66072bae37e5b3686f3e6dvboxsync#define PCIDEV_2_PAHCI(pPciDev) ( (PAHCI)(pPciDev) )
725fba5c64717677ac66072bae37e5b3686f3e6dvboxsync#define PDMIMOUNT_2_PAHCIPORT(pInterface) ( (PAHCIPort)((uintptr_t)(pInterface) - RT_OFFSETOF(AHCIPort, IMount)) )
725fba5c64717677ac66072bae37e5b3686f3e6dvboxsync#define PDMIMOUNTNOTIFY_2_PAHCIPORT(pInterface) ( (PAHCIPort)((uintptr_t)(pInterface) - RT_OFFSETOF(AHCIPort, IMountNotify)) )
725fba5c64717677ac66072bae37e5b3686f3e6dvboxsync#define PDMIBASE_2_PAHCIPORT(pInterface) ( (PAHCIPort)((uintptr_t)(pInterface) - RT_OFFSETOF(AHCIPort, IBase)) )
725fba5c64717677ac66072bae37e5b3686f3e6dvboxsync#define PDMIBLOCKPORT_2_PAHCIPORT(pInterface) ( (PAHCIPort)((uintptr_t)(pInterface) - RT_OFFSETOF(AHCIPort, IPort)) )
725fba5c64717677ac66072bae37e5b3686f3e6dvboxsync#define PDMIBASE_2_PAHCI(pInterface) ( (PAHCI)((uintptr_t)(pInterface) - RT_OFFSETOF(AHCI, IBase)) )
725fba5c64717677ac66072bae37e5b3686f3e6dvboxsync#define PDMILEDPORTS_2_PAHCI(pInterface) ( (PAHCI)((uintptr_t)(pInterface) - RT_OFFSETOF(AHCI, ILeds)) )
725fba5c64717677ac66072bae37e5b3686f3e6dvboxsync#define AHCI_RTGCPHYS_FROM_U32(Hi, Lo) ( (RTGCPHYS)RT_MAKE_U64(Lo, Hi) )
725fba5c64717677ac66072bae37e5b3686f3e6dvboxsync# define ahciLog(a) \
725fba5c64717677ac66072bae37e5b3686f3e6dvboxsync Log(("R3 P%u: %M", pAhciPort->iLUN, _LogRelRemoveParentheseis a))
725fba5c64717677ac66072bae37e5b3686f3e6dvboxsync# define ahciLog(a) \
725fba5c64717677ac66072bae37e5b3686f3e6dvboxsync do { Log(("R3 P%u: ", pAhciPort->iLUN)); Log(a); } while(0)
725fba5c64717677ac66072bae37e5b3686f3e6dvboxsync# define ahciLog(a) \
725fba5c64717677ac66072bae37e5b3686f3e6dvboxsync Log(("R0 P%u: %M", pAhciPort->iLUN, _LogRelRemoveParentheseis a))
725fba5c64717677ac66072bae37e5b3686f3e6dvboxsync# define ahciLog(a) \
725fba5c64717677ac66072bae37e5b3686f3e6dvboxsync do { Log(("R0 P%u: ", pAhciPort->iLUN)); Log(a); } while(0)
113a43aca041000560f93f9a8ee23dfcf01a9e7cvboxsync# define ahciLog(a) \
113a43aca041000560f93f9a8ee23dfcf01a9e7cvboxsync Log(("GC P%u: %M", pAhciPort->iLUN, _LogRelRemoveParentheseis a))
113a43aca041000560f93f9a8ee23dfcf01a9e7cvboxsync# define ahciLog(a) \
113a43aca041000560f93f9a8ee23dfcf01a9e7cvboxsync do { Log(("GC P%u: ", pAhciPort->iLUN)); Log(a); } while(0)
113a43aca041000560f93f9a8ee23dfcf01a9e7cvboxsync * Update PCI IRQ levels
113a43aca041000560f93f9a8ee23dfcf01a9e7cvboxsync PDMDevHlpPCISetIrq(pAhci->CTX_SUFF(pDevIns), 0, 0);
113a43aca041000560f93f9a8ee23dfcf01a9e7cvboxsync * Updates the IRQ level and sets port bit in the global interrupt status register of the HBA.
113a43aca041000560f93f9a8ee23dfcf01a9e7cvboxsyncstatic int ahciHbaSetInterrupt(PAHCI pAhci, uint8_t iPort, int rcBusy)
113a43aca041000560f93f9a8ee23dfcf01a9e7cvboxsync Log(("P%u: %s: Setting interrupt\n", iPort, __FUNCTION__));
113a43aca041000560f93f9a8ee23dfcf01a9e7cvboxsync if ((pAhci->regHbaCccCtl & AHCI_HBA_CCC_CTL_EN) && (pAhci->regHbaCccPorts & (1 << iPort)))
113a43aca041000560f93f9a8ee23dfcf01a9e7cvboxsync /* Reset command completion coalescing state. */
113a43aca041000560f93f9a8ee23dfcf01a9e7cvboxsync TMTimerSetMillies(pAhci->CTX_SUFF(pHbaCccTimer), pAhci->uCccTimeout);
113a43aca041000560f93f9a8ee23dfcf01a9e7cvboxsync pAhci->u32PortsInterrupted |= (1 << pAhci->uCccPortNr);
113a43aca041000560f93f9a8ee23dfcf01a9e7cvboxsync if (!(pAhci->u32PortsInterrupted & ~(1 << pAhci->uCccPortNr)))
113a43aca041000560f93f9a8ee23dfcf01a9e7cvboxsync Log(("P%u: %s: Fire interrupt\n", iPort, __FUNCTION__));
113a43aca041000560f93f9a8ee23dfcf01a9e7cvboxsync PDMDevHlpPCISetIrq(pAhci->CTX_SUFF(pDevIns), 0, 1);
113a43aca041000560f93f9a8ee23dfcf01a9e7cvboxsync /* If only the bit of the actual port is set assert an interrupt
113a43aca041000560f93f9a8ee23dfcf01a9e7cvboxsync * because the interrupt status register was already read by the guest
113a43aca041000560f93f9a8ee23dfcf01a9e7cvboxsync * and we need to send a new notification.
113a43aca041000560f93f9a8ee23dfcf01a9e7cvboxsync * Otherwise an interrupt is still pending.
113a43aca041000560f93f9a8ee23dfcf01a9e7cvboxsync ASMAtomicOrU32((volatile uint32_t *)&pAhci->u32PortsInterrupted, (1 << iPort));
113a43aca041000560f93f9a8ee23dfcf01a9e7cvboxsync Log(("P%u: %s: Fire interrupt\n", iPort, __FUNCTION__));
113a43aca041000560f93f9a8ee23dfcf01a9e7cvboxsync PDMDevHlpPCISetIrq(pAhci->CTX_SUFF(pDevIns), 0, 1);
113a43aca041000560f93f9a8ee23dfcf01a9e7cvboxsync * Assert irq when an CCC timeout occurs
113a43aca041000560f93f9a8ee23dfcf01a9e7cvboxsyncDECLCALLBACK(void) ahciCccTimer(PPDMDEVINS pDevIns, PTMTIMER pTimer, void *pvUser)
113a43aca041000560f93f9a8ee23dfcf01a9e7cvboxsync int rc = ahciHbaSetInterrupt(pAhci, pAhci->uCccPortNr, VERR_IGNORED);
113a43aca041000560f93f9a8ee23dfcf01a9e7cvboxsync * Finishes the port reset of the given port.
113a43aca041000560f93f9a8ee23dfcf01a9e7cvboxsync * @returns nothing.
113a43aca041000560f93f9a8ee23dfcf01a9e7cvboxsync * @param pAhciPort The port to finish the reset on.
113a43aca041000560f93f9a8ee23dfcf01a9e7cvboxsyncstatic void ahciPortResetFinish(PAHCIPort pAhciPort)
113a43aca041000560f93f9a8ee23dfcf01a9e7cvboxsync /* Cancel all tasks first. */
113a43aca041000560f93f9a8ee23dfcf01a9e7cvboxsync bool fAllTasksCanceled = ahciCancelActiveTasks(pAhciPort);
113a43aca041000560f93f9a8ee23dfcf01a9e7cvboxsync /* Signature for SATA device. */
113a43aca041000560f93f9a8ee23dfcf01a9e7cvboxsync pAhciPort->regSSTS = (0x01 << 8) | /* Interface is active. */
113a43aca041000560f93f9a8ee23dfcf01a9e7cvboxsync (0x03 << 0); /* Device detected and communication established. */
113a43aca041000560f93f9a8ee23dfcf01a9e7cvboxsync * Use the maximum allowed speed.
113a43aca041000560f93f9a8ee23dfcf01a9e7cvboxsync * (Not that it changes anything really)
113a43aca041000560f93f9a8ee23dfcf01a9e7cvboxsync switch (AHCI_PORT_SCTL_SPD_GET(pAhciPort->regSCTL))
113a43aca041000560f93f9a8ee23dfcf01a9e7cvboxsync pAhciPort->regSSTS |= (0x01 << 4); /* Generation 1 (1.5GBps) speed. */
113a43aca041000560f93f9a8ee23dfcf01a9e7cvboxsync pAhciPort->regSSTS |= (0x02 << 4); /* Generation 2 (3.0GBps) speed. */
113a43aca041000560f93f9a8ee23dfcf01a9e7cvboxsync /* We received a COMINIT from the device. Tell the guest. */
113a43aca041000560f93f9a8ee23dfcf01a9e7cvboxsync ASMAtomicOrU32(&pAhciPort->regIS, AHCI_PORT_IS_PCS);
113a43aca041000560f93f9a8ee23dfcf01a9e7cvboxsync if ((pAhciPort->regCMD & AHCI_PORT_CMD_FRE) && (!pAhciPort->fFirstD2HFisSend))
113a43aca041000560f93f9a8ee23dfcf01a9e7cvboxsync ASMAtomicOrU32(&pAhciPort->regIS, AHCI_PORT_IS_DHRS);
113a43aca041000560f93f9a8ee23dfcf01a9e7cvboxsync int rc = ahciHbaSetInterrupt(pAhciPort->CTX_SUFF(pAhci), pAhciPort->iLUN, VERR_IGNORED);
113a43aca041000560f93f9a8ee23dfcf01a9e7cvboxsync * Kicks the I/O thread from RC or R0.
113a43aca041000560f93f9a8ee23dfcf01a9e7cvboxsync * @returns nothing.
113a43aca041000560f93f9a8ee23dfcf01a9e7cvboxsync * @param pAhci The AHCI controller instance.
113a43aca041000560f93f9a8ee23dfcf01a9e7cvboxsync * @param pAhciPort The port to kick.
113a43aca041000560f93f9a8ee23dfcf01a9e7cvboxsyncstatic void ahciIoThreadKick(PAHCI pAhci, PAHCIPort pAhciPort)
113a43aca041000560f93f9a8ee23dfcf01a9e7cvboxsync PDEVPORTNOTIFIERQUEUEITEM pItem = (PDEVPORTNOTIFIERQUEUEITEM)PDMQueueAlloc(pAhci->CTX_SUFF(pNotifierQueue));
113a43aca041000560f93f9a8ee23dfcf01a9e7cvboxsync AssertMsg(VALID_PTR(pItem), ("Allocating item for queue failed\n"));
113a43aca041000560f93f9a8ee23dfcf01a9e7cvboxsync PDMQueueInsert(pAhci->CTX_SUFF(pNotifierQueue), (PPDMQUEUEITEMCORE)pItem);
113a43aca041000560f93f9a8ee23dfcf01a9e7cvboxsync int rc = SUPSemEventSignal(pAhci->pSupDrvSession, pAhciPort->hEvtProcess);
113a43aca041000560f93f9a8ee23dfcf01a9e7cvboxsyncstatic int PortCmdIssue_w(PAHCI ahci, PAHCIPort pAhciPort, uint32_t iReg, uint32_t u32Value)
113a43aca041000560f93f9a8ee23dfcf01a9e7cvboxsync ahciLog(("%s: write u32Value=%#010x\n", __FUNCTION__, u32Value));
113a43aca041000560f93f9a8ee23dfcf01a9e7cvboxsync /* Update the CI register first. */
113a43aca041000560f93f9a8ee23dfcf01a9e7cvboxsync uCIValue = ASMAtomicXchgU32(&pAhciPort->u32TasksFinished, 0);
4b8c66482cbc69a01ac399b8588b8bc80b310523vboxsync * Clear all tasks which are already marked as busy. The guest
4b8c66482cbc69a01ac399b8588b8bc80b310523vboxsync * shouldn't write already busy tasks actually.
4b8c66482cbc69a01ac399b8588b8bc80b310523vboxsync /* Send a notification to R3 if u32TasksNew was 0 before our write. */
4b8c66482cbc69a01ac399b8588b8bc80b310523vboxsync if (ASMAtomicReadBool(&pAhciPort->fWrkThreadSleeping))
4bf996d915405be92dc4394b2db1395e00e14d58vboxsyncstatic int PortCmdIssue_r(PAHCI ahci, PAHCIPort pAhciPort, uint32_t iReg, uint32_t *pu32Value)
113a43aca041000560f93f9a8ee23dfcf01a9e7cvboxsync uCIValue = ASMAtomicXchgU32(&pAhciPort->u32TasksFinished, 0);
113a43aca041000560f93f9a8ee23dfcf01a9e7cvboxsync ahciLog(("%s: read regCI=%#010x uCIValue=%#010x\n", __FUNCTION__, pAhciPort->regCI, uCIValue));
4bf996d915405be92dc4394b2db1395e00e14d58vboxsyncstatic int PortSActive_w(PAHCI ahci, PAHCIPort pAhciPort, uint32_t iReg, uint32_t u32Value)
4bf996d915405be92dc4394b2db1395e00e14d58vboxsync ahciLog(("%s: write u32Value=%#010x\n", __FUNCTION__, u32Value));
4bf996d915405be92dc4394b2db1395e00e14d58vboxsyncstatic int PortSActive_r(PAHCI ahci, PAHCIPort pAhciPort, uint32_t iReg, uint32_t *pu32Value)
4b8c66482cbc69a01ac399b8588b8bc80b310523vboxsync uint32_t u32TasksFinished = ASMAtomicXchgU32(&pAhciPort->u32QueuedTasksFinished, 0);
4b8c66482cbc69a01ac399b8588b8bc80b310523vboxsync ahciLog(("%s: read regSACT=%#010x regCI=%#010x u32TasksFinished=%#010x\n",
4b8c66482cbc69a01ac399b8588b8bc80b310523vboxsync __FUNCTION__, pAhciPort->regSACT, pAhciPort->regCI, u32TasksFinished));
4b8c66482cbc69a01ac399b8588b8bc80b310523vboxsyncstatic int PortSError_w(PAHCI ahci, PAHCIPort pAhciPort, uint32_t iReg, uint32_t u32Value)
4b8c66482cbc69a01ac399b8588b8bc80b310523vboxsync ahciLog(("%s: write u32Value=%#010x\n", __FUNCTION__, u32Value));
4b8c66482cbc69a01ac399b8588b8bc80b310523vboxsync ASMAtomicAndU32(&pAhciPort->regIS, ~AHCI_PORT_IS_PCS);
4b8c66482cbc69a01ac399b8588b8bc80b310523vboxsync pAhciPort->regTFD &= ~(ATA_STAT_DRQ | ATA_STAT_BUSY);
4b8c66482cbc69a01ac399b8588b8bc80b310523vboxsync ASMAtomicAndU32(&pAhciPort->regIS, ~AHCI_PORT_IS_PRCS);
4b8c66482cbc69a01ac399b8588b8bc80b310523vboxsyncstatic int PortSError_r(PAHCI ahci, PAHCIPort pAhciPort, uint32_t iReg, uint32_t *pu32Value)
4b8c66482cbc69a01ac399b8588b8bc80b310523vboxsync ahciLog(("%s: read regSERR=%#010x\n", __FUNCTION__, pAhciPort->regSERR));
4b8c66482cbc69a01ac399b8588b8bc80b310523vboxsyncstatic int PortSControl_w(PAHCI ahci, PAHCIPort pAhciPort, uint32_t iReg, uint32_t u32Value)
4b8c66482cbc69a01ac399b8588b8bc80b310523vboxsync ahciLog(("%s: write u32Value=%#010x\n", __FUNCTION__, u32Value));
4b8c66482cbc69a01ac399b8588b8bc80b310523vboxsync ahciLog(("%s: IPM=%d SPD=%d DET=%d\n", __FUNCTION__,
4b8c66482cbc69a01ac399b8588b8bc80b310523vboxsync AHCI_PORT_SCTL_IPM_GET(u32Value), AHCI_PORT_SCTL_SPD_GET(u32Value), AHCI_PORT_SCTL_DET_GET(u32Value)));
4b8c66482cbc69a01ac399b8588b8bc80b310523vboxsync if ((u32Value & AHCI_PORT_SCTL_DET) == AHCI_PORT_SCTL_DET_INIT)
4b8c66482cbc69a01ac399b8588b8bc80b310523vboxsync if (!ASMAtomicXchgBool(&pAhciPort->fPortReset, true))
4b8c66482cbc69a01ac399b8588b8bc80b310523vboxsync LogRel(("AHCI#%u: Port %d reset\n", ahci->CTX_SUFF(pDevIns)->iInstance,
4b8c66482cbc69a01ac399b8588b8bc80b310523vboxsync else if ( (u32Value & AHCI_PORT_SCTL_DET) == AHCI_PORT_SCTL_DET_NINIT
4b8c66482cbc69a01ac399b8588b8bc80b310523vboxsync && (pAhciPort->regSCTL & AHCI_PORT_SCTL_DET) == AHCI_PORT_SCTL_DET_INIT
4b8c66482cbc69a01ac399b8588b8bc80b310523vboxsync /* Do the port reset here, so the guest sees the new status immediately. */
4b8c66482cbc69a01ac399b8588b8bc80b310523vboxsync pAhciPort->regSCTL = u32Value; /* Update after finishing the reset, so the I/O thread doesn't get a chance to do the reset. */
4b8c66482cbc69a01ac399b8588b8bc80b310523vboxsync pAhciPort->regSSTS = 0x1; /* Indicate device presence detected but communication not established. */
4b8c66482cbc69a01ac399b8588b8bc80b310523vboxsync pAhciPort->regSCTL = u32Value; /* Update before kicking the I/O thread. */
4b8c66482cbc69a01ac399b8588b8bc80b310523vboxsync /* Kick the thread to finish the reset. */
4b8c66482cbc69a01ac399b8588b8bc80b310523vboxsyncstatic int PortSControl_r(PAHCI ahci, PAHCIPort pAhciPort, uint32_t iReg, uint32_t *pu32Value)
4b8c66482cbc69a01ac399b8588b8bc80b310523vboxsync ahciLog(("%s: read regSCTL=%#010x\n", __FUNCTION__, pAhciPort->regSCTL));
4b8c66482cbc69a01ac399b8588b8bc80b310523vboxsync ahciLog(("%s: IPM=%d SPD=%d DET=%d\n", __FUNCTION__,
4b8c66482cbc69a01ac399b8588b8bc80b310523vboxsync AHCI_PORT_SCTL_IPM_GET(pAhciPort->regSCTL), AHCI_PORT_SCTL_SPD_GET(pAhciPort->regSCTL),
4b8c66482cbc69a01ac399b8588b8bc80b310523vboxsyncstatic int PortSStatus_r(PAHCI ahci, PAHCIPort pAhciPort, uint32_t iReg, uint32_t *pu32Value)
4b8c66482cbc69a01ac399b8588b8bc80b310523vboxsync ahciLog(("%s: read regSSTS=%#010x\n", __FUNCTION__, pAhciPort->regSSTS));
4b8c66482cbc69a01ac399b8588b8bc80b310523vboxsync ahciLog(("%s: IPM=%d SPD=%d DET=%d\n", __FUNCTION__,
4b8c66482cbc69a01ac399b8588b8bc80b310523vboxsync AHCI_PORT_SSTS_IPM_GET(pAhciPort->regSSTS), AHCI_PORT_SSTS_SPD_GET(pAhciPort->regSSTS),
4b8c66482cbc69a01ac399b8588b8bc80b310523vboxsyncstatic int PortSignature_r(PAHCI ahci, PAHCIPort pAhciPort, uint32_t iReg, uint32_t *pu32Value)
4b8c66482cbc69a01ac399b8588b8bc80b310523vboxsync ahciLog(("%s: read regSIG=%#010x\n", __FUNCTION__, pAhciPort->regSIG));
4b8c66482cbc69a01ac399b8588b8bc80b310523vboxsyncstatic int PortTaskFileData_r(PAHCI ahci, PAHCIPort pAhciPort, uint32_t iReg, uint32_t *pu32Value)
4b8c66482cbc69a01ac399b8588b8bc80b310523vboxsync ahciLog(("%s: read regTFD=%#010x\n", __FUNCTION__, pAhciPort->regTFD));
4b8c66482cbc69a01ac399b8588b8bc80b310523vboxsync ahciLog(("%s: ERR=%x BSY=%d DRQ=%d ERR=%d\n", __FUNCTION__,
4b8c66482cbc69a01ac399b8588b8bc80b310523vboxsync (pAhciPort->regTFD >> 8), (pAhciPort->regTFD & AHCI_PORT_TFD_BSY) >> 7,
4b8c66482cbc69a01ac399b8588b8bc80b310523vboxsync (pAhciPort->regTFD & AHCI_PORT_TFD_DRQ) >> 3, (pAhciPort->regTFD & AHCI_PORT_TFD_ERR)));
4b8c66482cbc69a01ac399b8588b8bc80b310523vboxsync * Read from the port command register.
4b8c66482cbc69a01ac399b8588b8bc80b310523vboxsyncstatic int PortCmd_r(PAHCI ahci, PAHCIPort pAhciPort, uint32_t iReg, uint32_t *pu32Value)
4b8c66482cbc69a01ac399b8588b8bc80b310523vboxsync ahciLog(("%s: read regCMD=%#010x\n", __FUNCTION__, pAhciPort->regCMD | AHCI_PORT_CMD_CCS_SHIFT(pAhciPort->u32CurrentCommandSlot)));
4b8c66482cbc69a01ac399b8588b8bc80b310523vboxsync ahciLog(("%s: ICC=%d ASP=%d ALPE=%d DLAE=%d ATAPI=%d CPD=%d ISP=%d HPCP=%d PMA=%d CPS=%d CR=%d FR=%d ISS=%d CCS=%d FRE=%d CLO=%d POD=%d SUD=%d ST=%d\n",
4b8c66482cbc69a01ac399b8588b8bc80b310523vboxsync __FUNCTION__, (pAhciPort->regCMD & AHCI_PORT_CMD_ICC) >> 28, (pAhciPort->regCMD & AHCI_PORT_CMD_ASP) >> 27,
4b8c66482cbc69a01ac399b8588b8bc80b310523vboxsync (pAhciPort->regCMD & AHCI_PORT_CMD_ALPE) >> 26, (pAhciPort->regCMD & AHCI_PORT_CMD_DLAE) >> 25,
4b8c66482cbc69a01ac399b8588b8bc80b310523vboxsync (pAhciPort->regCMD & AHCI_PORT_CMD_ATAPI) >> 24, (pAhciPort->regCMD & AHCI_PORT_CMD_CPD) >> 20,
4b8c66482cbc69a01ac399b8588b8bc80b310523vboxsync (pAhciPort->regCMD & AHCI_PORT_CMD_ISP) >> 19, (pAhciPort->regCMD & AHCI_PORT_CMD_HPCP) >> 18,
4b8c66482cbc69a01ac399b8588b8bc80b310523vboxsync (pAhciPort->regCMD & AHCI_PORT_CMD_PMA) >> 17, (pAhciPort->regCMD & AHCI_PORT_CMD_CPS) >> 16,
4b8c66482cbc69a01ac399b8588b8bc80b310523vboxsync (pAhciPort->regCMD & AHCI_PORT_CMD_CR) >> 15, (pAhciPort->regCMD & AHCI_PORT_CMD_FR) >> 14,
4b8c66482cbc69a01ac399b8588b8bc80b310523vboxsync (pAhciPort->regCMD & AHCI_PORT_CMD_ISS) >> 13, pAhciPort->u32CurrentCommandSlot,
4b8c66482cbc69a01ac399b8588b8bc80b310523vboxsync (pAhciPort->regCMD & AHCI_PORT_CMD_FRE) >> 4, (pAhciPort->regCMD & AHCI_PORT_CMD_CLO) >> 3,
4b8c66482cbc69a01ac399b8588b8bc80b310523vboxsync (pAhciPort->regCMD & AHCI_PORT_CMD_POD) >> 2, (pAhciPort->regCMD & AHCI_PORT_CMD_SUD) >> 1,
4b8c66482cbc69a01ac399b8588b8bc80b310523vboxsync *pu32Value = pAhciPort->regCMD | AHCI_PORT_CMD_CCS_SHIFT(pAhciPort->u32CurrentCommandSlot);
4bf996d915405be92dc4394b2db1395e00e14d58vboxsync * Write to the port command register.
4bf996d915405be92dc4394b2db1395e00e14d58vboxsync * This is the register where all the data transfer is started
5b0a093ca572a855886faa6747ad46df859dd041vboxsyncstatic int PortCmd_w(PAHCI ahci, PAHCIPort pAhciPort, uint32_t iReg, uint32_t u32Value)
5b0a093ca572a855886faa6747ad46df859dd041vboxsync ahciLog(("%s: write u32Value=%#010x\n", __FUNCTION__, u32Value));
5b0a093ca572a855886faa6747ad46df859dd041vboxsync ahciLog(("%s: ICC=%d ASP=%d ALPE=%d DLAE=%d ATAPI=%d CPD=%d ISP=%d HPCP=%d PMA=%d CPS=%d CR=%d FR=%d ISS=%d CCS=%d FRE=%d CLO=%d POD=%d SUD=%d ST=%d\n",
5b0a093ca572a855886faa6747ad46df859dd041vboxsync __FUNCTION__, (u32Value & AHCI_PORT_CMD_ICC) >> 28, (u32Value & AHCI_PORT_CMD_ASP) >> 27,
5b0a093ca572a855886faa6747ad46df859dd041vboxsync (u32Value & AHCI_PORT_CMD_ALPE) >> 26, (u32Value & AHCI_PORT_CMD_DLAE) >> 25,
5b0a093ca572a855886faa6747ad46df859dd041vboxsync (u32Value & AHCI_PORT_CMD_ATAPI) >> 24, (u32Value & AHCI_PORT_CMD_CPD) >> 20,
5b0a093ca572a855886faa6747ad46df859dd041vboxsync (u32Value & AHCI_PORT_CMD_ISP) >> 19, (u32Value & AHCI_PORT_CMD_HPCP) >> 18,
5b0a093ca572a855886faa6747ad46df859dd041vboxsync (u32Value & AHCI_PORT_CMD_PMA) >> 17, (u32Value & AHCI_PORT_CMD_CPS) >> 16,
5b0a093ca572a855886faa6747ad46df859dd041vboxsync (u32Value & AHCI_PORT_CMD_CR) >> 15, (u32Value & AHCI_PORT_CMD_FR) >> 14,
5b0a093ca572a855886faa6747ad46df859dd041vboxsync (u32Value & AHCI_PORT_CMD_ISS) >> 13, (u32Value & AHCI_PORT_CMD_CCS) >> 8,
5b0a093ca572a855886faa6747ad46df859dd041vboxsync (u32Value & AHCI_PORT_CMD_FRE) >> 4, (u32Value & AHCI_PORT_CMD_CLO) >> 3,
5b0a093ca572a855886faa6747ad46df859dd041vboxsync (u32Value & AHCI_PORT_CMD_POD) >> 2, (u32Value & AHCI_PORT_CMD_SUD) >> 1,
5b0a093ca572a855886faa6747ad46df859dd041vboxsync /* The PxCMD.CCS bits are R/O and maintained separately. */
5b0a093ca572a855886faa6747ad46df859dd041vboxsync ahciLog(("%s: Command list override requested\n", __FUNCTION__));
5b0a093ca572a855886faa6747ad46df859dd041vboxsync u32Value &= ~(AHCI_PORT_TFD_BSY | AHCI_PORT_TFD_DRQ);
5b0a093ca572a855886faa6747ad46df859dd041vboxsync /* Clear the CLO bit. */
5b0a093ca572a855886faa6747ad46df859dd041vboxsync * Set engine state to running if there is a device attached and
5b0a093ca572a855886faa6747ad46df859dd041vboxsync * IS.PCS is clear.
5b0a093ca572a855886faa6747ad46df859dd041vboxsync /* If there is something in CI, kick the I/O thread. */
5b0a093ca572a855886faa6747ad46df859dd041vboxsync && ASMAtomicReadBool(&pAhciPort->fWrkThreadSleeping))
5b0a093ca572a855886faa6747ad46df859dd041vboxsync ASMAtomicOrU32(&pAhciPort->u32TasksNew, pAhciPort->regCI);
5b0a093ca572a855886faa6747ad46df859dd041vboxsync PDEVPORTNOTIFIERQUEUEITEM pItem = (PDEVPORTNOTIFIERQUEUEITEM)PDMQueueAlloc(ahci->CTX_SUFF(pNotifierQueue));
5b0a093ca572a855886faa6747ad46df859dd041vboxsync AssertMsg(VALID_PTR(pItem), ("Allocating item for queue failed\n"));
5b0a093ca572a855886faa6747ad46df859dd041vboxsync PDMQueueInsert(ahci->CTX_SUFF(pNotifierQueue), (PPDMQUEUEITEMCORE)pItem);
5b0a093ca572a855886faa6747ad46df859dd041vboxsync int rc = SUPSemEventSignal(ahci->pSupDrvSession, pAhciPort->hEvtProcess);
71e045383a3316b27563b2f44b0e0e1231968bdcvboxsync /* Clear command issue register. */
71e045383a3316b27563b2f44b0e0e1231968bdcvboxsync /* Clear current command slot. */
4e47bb772df0d04d1ded3e06354de547d52e2d06vboxsync if ((u32Value & AHCI_PORT_CMD_POD) && (pAhciPort->regCMD & AHCI_PORT_CMD_CPS) && !pAhciPort->fPoweredOn)
71e045383a3316b27563b2f44b0e0e1231968bdcvboxsync ahciLog(("%s: Power on the device\n", __FUNCTION__));
b26e5b503baa3dffc58048982eaf17ad1b53f207vboxsync * Set states in the Port Signature and SStatus registers.
71e045383a3316b27563b2f44b0e0e1231968bdcvboxsync pAhciPort->regSSTS = (0x01 << 8) | /* Interface is active. */
71e045383a3316b27563b2f44b0e0e1231968bdcvboxsync (0x03 << 0); /* Device detected and communication established. */
4b8c66482cbc69a01ac399b8588b8bc80b310523vboxsync ASMAtomicOrU32(&pAhciPort->regIS, AHCI_PORT_IS_DHRS);
4b8c66482cbc69a01ac399b8588b8bc80b310523vboxsync int rc = ahciHbaSetInterrupt(pAhciPort->CTX_SUFF(pAhci), pAhciPort->iLUN, VERR_IGNORED);
b26e5b503baa3dffc58048982eaf17ad1b53f207vboxsync if ((u32Value & AHCI_PORT_CMD_SUD) && pAhciPort->fPoweredOn && !pAhciPort->fSpunUp)
4bf996d915405be92dc4394b2db1395e00e14d58vboxsync ahciLog(("%s: Spin up the device\n", __FUNCTION__));
4bf996d915405be92dc4394b2db1395e00e14d58vboxsync ahciLog(("%s: FIS receive enabled\n", __FUNCTION__));
4bf996d915405be92dc4394b2db1395e00e14d58vboxsync /* Send the first D2H FIS only if it wasn't already send. */
71e045383a3316b27563b2f44b0e0e1231968bdcvboxsync ahciLog(("%s: FIS receive disabled\n", __FUNCTION__));
4bf996d915405be92dc4394b2db1395e00e14d58vboxsync * Read from the port interrupt enable register.
4bf996d915405be92dc4394b2db1395e00e14d58vboxsyncstatic int PortIntrEnable_r(PAHCI ahci, PAHCIPort pAhciPort, uint32_t iReg, uint32_t *pu32Value)
4bf996d915405be92dc4394b2db1395e00e14d58vboxsync ahciLog(("%s: read regIE=%#010x\n", __FUNCTION__, pAhciPort->regIE));
4bf996d915405be92dc4394b2db1395e00e14d58vboxsync ahciLog(("%s: CPDE=%d TFEE=%d HBFE=%d HBDE=%d IFE=%d INFE=%d OFE=%d IPME=%d PRCE=%d DIE=%d PCE=%d DPE=%d UFE=%d SDBE=%d DSE=%d PSE=%d DHRE=%d\n",
71e045383a3316b27563b2f44b0e0e1231968bdcvboxsync __FUNCTION__, (pAhciPort->regIE & AHCI_PORT_IE_CPDE) >> 31, (pAhciPort->regIE & AHCI_PORT_IE_TFEE) >> 30,
b26e5b503baa3dffc58048982eaf17ad1b53f207vboxsync (pAhciPort->regIE & AHCI_PORT_IE_HBFE) >> 29, (pAhciPort->regIE & AHCI_PORT_IE_HBDE) >> 28,
71e045383a3316b27563b2f44b0e0e1231968bdcvboxsync (pAhciPort->regIE & AHCI_PORT_IE_IFE) >> 27, (pAhciPort->regIE & AHCI_PORT_IE_INFE) >> 26,
b26e5b503baa3dffc58048982eaf17ad1b53f207vboxsync (pAhciPort->regIE & AHCI_PORT_IE_OFE) >> 24, (pAhciPort->regIE & AHCI_PORT_IE_IPME) >> 23,
71e045383a3316b27563b2f44b0e0e1231968bdcvboxsync (pAhciPort->regIE & AHCI_PORT_IE_PRCE) >> 22, (pAhciPort->regIE & AHCI_PORT_IE_DIE) >> 7,
71e045383a3316b27563b2f44b0e0e1231968bdcvboxsync (pAhciPort->regIE & AHCI_PORT_IE_PCE) >> 6, (pAhciPort->regIE & AHCI_PORT_IE_DPE) >> 5,
71e045383a3316b27563b2f44b0e0e1231968bdcvboxsync (pAhciPort->regIE & AHCI_PORT_IE_UFE) >> 4, (pAhciPort->regIE & AHCI_PORT_IE_SDBE) >> 3,
71e045383a3316b27563b2f44b0e0e1231968bdcvboxsync (pAhciPort->regIE & AHCI_PORT_IE_DSE) >> 2, (pAhciPort->regIE & AHCI_PORT_IE_PSE) >> 1,
71e045383a3316b27563b2f44b0e0e1231968bdcvboxsync * Write to the port interrupt enable register.
b26e5b503baa3dffc58048982eaf17ad1b53f207vboxsyncstatic int PortIntrEnable_w(PAHCI ahci, PAHCIPort pAhciPort, uint32_t iReg, uint32_t u32Value)
b26e5b503baa3dffc58048982eaf17ad1b53f207vboxsync ahciLog(("%s: write u32Value=%#010x\n", __FUNCTION__, u32Value));
b26e5b503baa3dffc58048982eaf17ad1b53f207vboxsync ahciLog(("%s: CPDE=%d TFEE=%d HBFE=%d HBDE=%d IFE=%d INFE=%d OFE=%d IPME=%d PRCE=%d DIE=%d PCE=%d DPE=%d UFE=%d SDBE=%d DSE=%d PSE=%d DHRE=%d\n",
4bf996d915405be92dc4394b2db1395e00e14d58vboxsync __FUNCTION__, (u32Value & AHCI_PORT_IE_CPDE) >> 31, (u32Value & AHCI_PORT_IE_TFEE) >> 30,
4bf996d915405be92dc4394b2db1395e00e14d58vboxsync (u32Value & AHCI_PORT_IE_HBFE) >> 29, (u32Value & AHCI_PORT_IE_HBDE) >> 28,
4bf996d915405be92dc4394b2db1395e00e14d58vboxsync (u32Value & AHCI_PORT_IE_IFE) >> 27, (u32Value & AHCI_PORT_IE_INFE) >> 26,
4bf996d915405be92dc4394b2db1395e00e14d58vboxsync (u32Value & AHCI_PORT_IE_OFE) >> 24, (u32Value & AHCI_PORT_IE_IPME) >> 23,
4bf996d915405be92dc4394b2db1395e00e14d58vboxsync (u32Value & AHCI_PORT_IE_PRCE) >> 22, (u32Value & AHCI_PORT_IE_DIE) >> 7,
4bf996d915405be92dc4394b2db1395e00e14d58vboxsync (u32Value & AHCI_PORT_IE_PCE) >> 6, (u32Value & AHCI_PORT_IE_DPE) >> 5,
4bf996d915405be92dc4394b2db1395e00e14d58vboxsync (u32Value & AHCI_PORT_IE_UFE) >> 4, (u32Value & AHCI_PORT_IE_SDBE) >> 3,
4bf996d915405be92dc4394b2db1395e00e14d58vboxsync (u32Value & AHCI_PORT_IE_DSE) >> 2, (u32Value & AHCI_PORT_IE_PSE) >> 1,
71e045383a3316b27563b2f44b0e0e1231968bdcvboxsync /* Check if some a interrupt status bit changed*/
71e045383a3316b27563b2f44b0e0e1231968bdcvboxsync uint32_t u32IntrStatus = ASMAtomicReadU32(&pAhciPort->regIS);
b26e5b503baa3dffc58048982eaf17ad1b53f207vboxsync rc = ahciHbaSetInterrupt(ahci, pAhciPort->iLUN, VINF_IOM_R3_MMIO_WRITE);
b26e5b503baa3dffc58048982eaf17ad1b53f207vboxsync * Read from the port interrupt status register.
b26e5b503baa3dffc58048982eaf17ad1b53f207vboxsyncstatic int PortIntrSts_r(PAHCI ahci, PAHCIPort pAhciPort, uint32_t iReg, uint32_t *pu32Value)
4bf996d915405be92dc4394b2db1395e00e14d58vboxsync ahciLog(("%s: read regIS=%#010x\n", __FUNCTION__, pAhciPort->regIS));
4bf996d915405be92dc4394b2db1395e00e14d58vboxsync ahciLog(("%s: CPDS=%d TFES=%d HBFS=%d HBDS=%d IFS=%d INFS=%d OFS=%d IPMS=%d PRCS=%d DIS=%d PCS=%d DPS=%d UFS=%d SDBS=%d DSS=%d PSS=%d DHRS=%d\n",
4bf996d915405be92dc4394b2db1395e00e14d58vboxsync __FUNCTION__, (pAhciPort->regIS & AHCI_PORT_IS_CPDS) >> 31, (pAhciPort->regIS & AHCI_PORT_IS_TFES) >> 30,
4bf996d915405be92dc4394b2db1395e00e14d58vboxsync (pAhciPort->regIS & AHCI_PORT_IS_HBFS) >> 29, (pAhciPort->regIS & AHCI_PORT_IS_HBDS) >> 28,
4bf996d915405be92dc4394b2db1395e00e14d58vboxsync (pAhciPort->regIS & AHCI_PORT_IS_IFS) >> 27, (pAhciPort->regIS & AHCI_PORT_IS_INFS) >> 26,
4bf996d915405be92dc4394b2db1395e00e14d58vboxsync (pAhciPort->regIS & AHCI_PORT_IS_OFS) >> 24, (pAhciPort->regIS & AHCI_PORT_IS_IPMS) >> 23,
4bf996d915405be92dc4394b2db1395e00e14d58vboxsync (pAhciPort->regIS & AHCI_PORT_IS_PRCS) >> 22, (pAhciPort->regIS & AHCI_PORT_IS_DIS) >> 7,
4bf996d915405be92dc4394b2db1395e00e14d58vboxsync (pAhciPort->regIS & AHCI_PORT_IS_PCS) >> 6, (pAhciPort->regIS & AHCI_PORT_IS_DPS) >> 5,
71e045383a3316b27563b2f44b0e0e1231968bdcvboxsync (pAhciPort->regIS & AHCI_PORT_IS_UFS) >> 4, (pAhciPort->regIS & AHCI_PORT_IS_SDBS) >> 3,
b26e5b503baa3dffc58048982eaf17ad1b53f207vboxsync (pAhciPort->regIS & AHCI_PORT_IS_DSS) >> 2, (pAhciPort->regIS & AHCI_PORT_IS_PSS) >> 1,
71e045383a3316b27563b2f44b0e0e1231968bdcvboxsync * Write to the port interrupt status register.
b26e5b503baa3dffc58048982eaf17ad1b53f207vboxsyncstatic int PortIntrSts_w(PAHCI ahci, PAHCIPort pAhciPort, uint32_t iReg, uint32_t u32Value)
71e045383a3316b27563b2f44b0e0e1231968bdcvboxsync ahciLog(("%s: write u32Value=%#010x\n", __FUNCTION__, u32Value));
71e045383a3316b27563b2f44b0e0e1231968bdcvboxsync ASMAtomicAndU32(&pAhciPort->regIS, ~(u32Value & AHCI_PORT_IS_READONLY));
b26e5b503baa3dffc58048982eaf17ad1b53f207vboxsync * Read from the port FIS base address upper 32bit register.
b26e5b503baa3dffc58048982eaf17ad1b53f207vboxsyncstatic int PortFisAddrUp_r(PAHCI ahci, PAHCIPort pAhciPort, uint32_t iReg, uint32_t *pu32Value)
4bf996d915405be92dc4394b2db1395e00e14d58vboxsync ahciLog(("%s: read regFBU=%#010x\n", __FUNCTION__, pAhciPort->regFBU));
71e045383a3316b27563b2f44b0e0e1231968bdcvboxsync * Write to the port FIS base address upper 32bit register.
b26e5b503baa3dffc58048982eaf17ad1b53f207vboxsyncstatic int PortFisAddrUp_w(PAHCI ahci, PAHCIPort pAhciPort, uint32_t iReg, uint32_t u32Value)
71e045383a3316b27563b2f44b0e0e1231968bdcvboxsync ahciLog(("%s: write u32Value=%#010x\n", __FUNCTION__, u32Value));
71e045383a3316b27563b2f44b0e0e1231968bdcvboxsync pAhciPort->GCPhysAddrFb = AHCI_RTGCPHYS_FROM_U32(pAhciPort->regFBU, pAhciPort->regFB);
71e045383a3316b27563b2f44b0e0e1231968bdcvboxsync * Read from the port FIS base address register.
71e045383a3316b27563b2f44b0e0e1231968bdcvboxsyncstatic int PortFisAddr_r(PAHCI ahci, PAHCIPort pAhciPort, uint32_t iReg, uint32_t *pu32Value)
71e045383a3316b27563b2f44b0e0e1231968bdcvboxsync ahciLog(("%s: read regFB=%#010x\n", __FUNCTION__, pAhciPort->regFB));
71e045383a3316b27563b2f44b0e0e1231968bdcvboxsync * Write to the port FIS base address register.
71e045383a3316b27563b2f44b0e0e1231968bdcvboxsyncstatic int PortFisAddr_w(PAHCI ahci, PAHCIPort pAhciPort, uint32_t iReg, uint32_t u32Value)
71e045383a3316b27563b2f44b0e0e1231968bdcvboxsync ahciLog(("%s: write u32Value=%#010x\n", __FUNCTION__, u32Value));
71e045383a3316b27563b2f44b0e0e1231968bdcvboxsync pAhciPort->regFB = (u32Value & AHCI_PORT_FB_RESERVED);
71e045383a3316b27563b2f44b0e0e1231968bdcvboxsync pAhciPort->GCPhysAddrFb = AHCI_RTGCPHYS_FROM_U32(pAhciPort->regFBU, pAhciPort->regFB);
71e045383a3316b27563b2f44b0e0e1231968bdcvboxsync * Write to the port command list base address upper 32bit register.
71e045383a3316b27563b2f44b0e0e1231968bdcvboxsyncstatic int PortCmdLstAddrUp_w(PAHCI ahci, PAHCIPort pAhciPort, uint32_t iReg, uint32_t u32Value)
71e045383a3316b27563b2f44b0e0e1231968bdcvboxsync ahciLog(("%s: write u32Value=%#010x\n", __FUNCTION__, u32Value));
71e045383a3316b27563b2f44b0e0e1231968bdcvboxsync pAhciPort->GCPhysAddrClb = AHCI_RTGCPHYS_FROM_U32(pAhciPort->regCLBU, pAhciPort->regCLB);
71e045383a3316b27563b2f44b0e0e1231968bdcvboxsync * Read from the port command list base address upper 32bit register.
71e045383a3316b27563b2f44b0e0e1231968bdcvboxsyncstatic int PortCmdLstAddrUp_r(PAHCI ahci, PAHCIPort pAhciPort, uint32_t iReg, uint32_t *pu32Value)
b26e5b503baa3dffc58048982eaf17ad1b53f207vboxsync ahciLog(("%s: read regCLBU=%#010x\n", __FUNCTION__, pAhciPort->regCLBU));
4bf996d915405be92dc4394b2db1395e00e14d58vboxsync * Read from the port command list base address register.
71e045383a3316b27563b2f44b0e0e1231968bdcvboxsyncstatic int PortCmdLstAddr_r(PAHCI ahci, PAHCIPort pAhciPort, uint32_t iReg, uint32_t *pu32Value)
71e045383a3316b27563b2f44b0e0e1231968bdcvboxsync ahciLog(("%s: read regCLB=%#010x\n", __FUNCTION__, pAhciPort->regCLB));
71e045383a3316b27563b2f44b0e0e1231968bdcvboxsync * Write to the port command list base address register.
71e045383a3316b27563b2f44b0e0e1231968bdcvboxsyncstatic int PortCmdLstAddr_w(PAHCI ahci, PAHCIPort pAhciPort, uint32_t iReg, uint32_t u32Value)
71e045383a3316b27563b2f44b0e0e1231968bdcvboxsync ahciLog(("%s: write u32Value=%#010x\n", __FUNCTION__, u32Value));
71e045383a3316b27563b2f44b0e0e1231968bdcvboxsync pAhciPort->regCLB = (u32Value & AHCI_PORT_CLB_RESERVED);
71e045383a3316b27563b2f44b0e0e1231968bdcvboxsync pAhciPort->GCPhysAddrClb = AHCI_RTGCPHYS_FROM_U32(pAhciPort->regCLBU, pAhciPort->regCLB);
71e045383a3316b27563b2f44b0e0e1231968bdcvboxsync * Read from the global Version register.
71e045383a3316b27563b2f44b0e0e1231968bdcvboxsyncstatic int HbaVersion_r(PAHCI ahci, uint32_t iReg, uint32_t *pu32Value)
71e045383a3316b27563b2f44b0e0e1231968bdcvboxsync Log(("%s: read regHbaVs=%#010x\n", __FUNCTION__, ahci->regHbaVs));
71e045383a3316b27563b2f44b0e0e1231968bdcvboxsync * Read from the global Ports implemented register.
71e045383a3316b27563b2f44b0e0e1231968bdcvboxsyncstatic int HbaPortsImplemented_r(PAHCI ahci, uint32_t iReg, uint32_t *pu32Value)
71e045383a3316b27563b2f44b0e0e1231968bdcvboxsync Log(("%s: read regHbaPi=%#010x\n", __FUNCTION__, ahci->regHbaPi));
71e045383a3316b27563b2f44b0e0e1231968bdcvboxsync * Write to the global interrupt status register.
71e045383a3316b27563b2f44b0e0e1231968bdcvboxsyncstatic int HbaInterruptStatus_w(PAHCI ahci, uint32_t iReg, uint32_t u32Value)
71e045383a3316b27563b2f44b0e0e1231968bdcvboxsync Log(("%s: write u32Value=%#010x\n", __FUNCTION__, u32Value));
71e045383a3316b27563b2f44b0e0e1231968bdcvboxsync rc = PDMCritSectEnter(&ahci->lock, VINF_IOM_R3_MMIO_WRITE);
5a5b5956f8b592c807c94785d58c25e717d430c4vboxsync * Clear the interrupt only if no port has signalled
71e045383a3316b27563b2f44b0e0e1231968bdcvboxsync * an interrupt and the guest has cleared all set interrupt
71e045383a3316b27563b2f44b0e0e1231968bdcvboxsync * notification bits.
b26e5b503baa3dffc58048982eaf17ad1b53f207vboxsync bool fClear = true;
71e045383a3316b27563b2f44b0e0e1231968bdcvboxsync fClear = !ahci->u32PortsInterrupted && !ahci->regHbaIs;
71e045383a3316b27563b2f44b0e0e1231968bdcvboxsync unsigned i = 0;
71e045383a3316b27563b2f44b0e0e1231968bdcvboxsync /* Check if the cleared ports have a interrupt status bit set. */
71e045383a3316b27563b2f44b0e0e1231968bdcvboxsync while ((u32Value > 0) && (i < AHCI_MAX_NR_PORTS_IMPL))
71e045383a3316b27563b2f44b0e0e1231968bdcvboxsync Log(("%s: Interrupt status of port %u set -> Set interrupt again\n", __FUNCTION__, i));
71e045383a3316b27563b2f44b0e0e1231968bdcvboxsync ASMAtomicOrU32(&ahci->u32PortsInterrupted, 1 << i);
71e045383a3316b27563b2f44b0e0e1231968bdcvboxsync Log(("%s: Not clearing interrupt: u32PortsInterrupted=%#010x\n", __FUNCTION__, ahci->u32PortsInterrupted));
71e045383a3316b27563b2f44b0e0e1231968bdcvboxsync * We need to set the interrupt again because the I/O APIC does not set it again even if the
71e045383a3316b27563b2f44b0e0e1231968bdcvboxsync * line is still high.
71e045383a3316b27563b2f44b0e0e1231968bdcvboxsync * We need to clear it first because the PCI bus only calls the interrupt controller if the state changes.
b26e5b503baa3dffc58048982eaf17ad1b53f207vboxsync * Read from the global interrupt status register.
1025ef7261a6961d07d390e85a095d806ccb88d9vboxsyncstatic int HbaInterruptStatus_r(PAHCI ahci, uint32_t iReg, uint32_t *pu32Value)
71e045383a3316b27563b2f44b0e0e1231968bdcvboxsync rc = PDMCritSectEnter(&ahci->lock, VINF_IOM_R3_MMIO_READ);
71e045383a3316b27563b2f44b0e0e1231968bdcvboxsync u32PortsInterrupted = ASMAtomicXchgU32(&ahci->u32PortsInterrupted, 0);
71e045383a3316b27563b2f44b0e0e1231968bdcvboxsync Log(("%s: read regHbaIs=%#010x u32PortsInterrupted=%#010x\n", __FUNCTION__, ahci->regHbaIs, u32PortsInterrupted));
71e045383a3316b27563b2f44b0e0e1231968bdcvboxsync unsigned i;
1025ef7261a6961d07d390e85a095d806ccb88d9vboxsync * Write to the global control register.
1025ef7261a6961d07d390e85a095d806ccb88d9vboxsyncstatic int HbaControl_w(PAHCI ahci, uint32_t iReg, uint32_t u32Value)
1025ef7261a6961d07d390e85a095d806ccb88d9vboxsync "%s: AE=%d IE=%d HR=%d\n",
1025ef7261a6961d07d390e85a095d806ccb88d9vboxsync __FUNCTION__, (u32Value & AHCI_HBA_CTRL_AE) >> 31, (u32Value & AHCI_HBA_CTRL_IE) >> 1,
71e045383a3316b27563b2f44b0e0e1231968bdcvboxsync * Increase the active thread counter because we might set the host controller
71e045383a3316b27563b2f44b0e0e1231968bdcvboxsync * reset bit.
71e045383a3316b27563b2f44b0e0e1231968bdcvboxsync ASMAtomicWriteU32(&ahci->regHbaCtrl, (u32Value & AHCI_HBA_CTRL_RW_MASK) | AHCI_HBA_CTRL_AE);
71e045383a3316b27563b2f44b0e0e1231968bdcvboxsync * Do the HBA reset if requested and there is no other active thread at the moment,
71e045383a3316b27563b2f44b0e0e1231968bdcvboxsync * the work is deferred to the last active thread otherwise.
71e045383a3316b27563b2f44b0e0e1231968bdcvboxsync uint32_t cThreadsActive = ASMAtomicDecU32(&ahci->cThreadsActive);
71e045383a3316b27563b2f44b0e0e1231968bdcvboxsync * Read the global control register.
71e045383a3316b27563b2f44b0e0e1231968bdcvboxsyncstatic int HbaControl_r(PAHCI ahci, uint32_t iReg, uint32_t *pu32Value)
71e045383a3316b27563b2f44b0e0e1231968bdcvboxsync "%s: AE=%d IE=%d HR=%d\n",
1025ef7261a6961d07d390e85a095d806ccb88d9vboxsync __FUNCTION__, (ahci->regHbaCtrl & AHCI_HBA_CTRL_AE) >> 31, (ahci->regHbaCtrl & AHCI_HBA_CTRL_IE) >> 1,
1025ef7261a6961d07d390e85a095d806ccb88d9vboxsync * Read the global capabilities register.
1025ef7261a6961d07d390e85a095d806ccb88d9vboxsyncstatic int HbaCapabilities_r(PAHCI ahci, uint32_t iReg, uint32_t *pu32Value)
1025ef7261a6961d07d390e85a095d806ccb88d9vboxsync "%s: S64A=%d SNCQ=%d SIS=%d SSS=%d SALP=%d SAL=%d SCLO=%d ISS=%d SNZO=%d SAM=%d SPM=%d PMD=%d SSC=%d PSC=%d NCS=%d NP=%d\n",
1025ef7261a6961d07d390e85a095d806ccb88d9vboxsync __FUNCTION__, (ahci->regHbaCap & AHCI_HBA_CAP_S64A) >> 31, (ahci->regHbaCap & AHCI_HBA_CAP_SNCQ) >> 30,
1025ef7261a6961d07d390e85a095d806ccb88d9vboxsync (ahci->regHbaCap & AHCI_HBA_CAP_SIS) >> 28, (ahci->regHbaCap & AHCI_HBA_CAP_SSS) >> 27,
1025ef7261a6961d07d390e85a095d806ccb88d9vboxsync (ahci->regHbaCap & AHCI_HBA_CAP_SALP) >> 26, (ahci->regHbaCap & AHCI_HBA_CAP_SAL) >> 25,
1025ef7261a6961d07d390e85a095d806ccb88d9vboxsync (ahci->regHbaCap & AHCI_HBA_CAP_SCLO) >> 24, (ahci->regHbaCap & AHCI_HBA_CAP_ISS) >> 20,
1025ef7261a6961d07d390e85a095d806ccb88d9vboxsync (ahci->regHbaCap & AHCI_HBA_CAP_SNZO) >> 19, (ahci->regHbaCap & AHCI_HBA_CAP_SAM) >> 18,
1025ef7261a6961d07d390e85a095d806ccb88d9vboxsync (ahci->regHbaCap & AHCI_HBA_CAP_SPM) >> 17, (ahci->regHbaCap & AHCI_HBA_CAP_PMD) >> 15,
1025ef7261a6961d07d390e85a095d806ccb88d9vboxsync (ahci->regHbaCap & AHCI_HBA_CAP_SSC) >> 14, (ahci->regHbaCap & AHCI_HBA_CAP_PSC) >> 13,
1025ef7261a6961d07d390e85a095d806ccb88d9vboxsync (ahci->regHbaCap & AHCI_HBA_CAP_NCS) >> 8, (ahci->regHbaCap & AHCI_HBA_CAP_NP)));
113a43aca041000560f93f9a8ee23dfcf01a9e7cvboxsync * Write to the global command completion coalescing control register.
113a43aca041000560f93f9a8ee23dfcf01a9e7cvboxsyncstatic int HbaCccCtl_w(PAHCI ahci, uint32_t iReg, uint32_t u32Value)
113a43aca041000560f93f9a8ee23dfcf01a9e7cvboxsync "%s: TV=%d CC=%d INT=%d EN=%d\n",
113a43aca041000560f93f9a8ee23dfcf01a9e7cvboxsync __FUNCTION__, AHCI_HBA_CCC_CTL_TV_GET(u32Value), AHCI_HBA_CCC_CTL_CC_GET(u32Value),
113a43aca041000560f93f9a8ee23dfcf01a9e7cvboxsync AHCI_HBA_CCC_CTL_INT_GET(u32Value), (u32Value & AHCI_HBA_CCC_CTL_EN)));
113a43aca041000560f93f9a8ee23dfcf01a9e7cvboxsync ahci->uCccTimeout = AHCI_HBA_CCC_CTL_TV_GET(u32Value);
113a43aca041000560f93f9a8ee23dfcf01a9e7cvboxsync ahci->uCccPortNr = AHCI_HBA_CCC_CTL_INT_GET(u32Value);
113a43aca041000560f93f9a8ee23dfcf01a9e7cvboxsync /* Arm the timer */
113a43aca041000560f93f9a8ee23dfcf01a9e7cvboxsync TMTimerSetMillies(ahci->CTX_SUFF(pHbaCccTimer), ahci->uCccTimeout);
4bf996d915405be92dc4394b2db1395e00e14d58vboxsync * Read the global command completion coalescing control register.
4bf996d915405be92dc4394b2db1395e00e14d58vboxsyncstatic int HbaCccCtl_r(PAHCI ahci, uint32_t iReg, uint32_t *pu32Value)
71e045383a3316b27563b2f44b0e0e1231968bdcvboxsync "%s: TV=%d CC=%d INT=%d EN=%d\n",
71e045383a3316b27563b2f44b0e0e1231968bdcvboxsync __FUNCTION__, AHCI_HBA_CCC_CTL_TV_GET(ahci->regHbaCccCtl), AHCI_HBA_CCC_CTL_CC_GET(ahci->regHbaCccCtl),
71e045383a3316b27563b2f44b0e0e1231968bdcvboxsync AHCI_HBA_CCC_CTL_INT_GET(ahci->regHbaCccCtl), (ahci->regHbaCccCtl & AHCI_HBA_CCC_CTL_EN)));
4bf996d915405be92dc4394b2db1395e00e14d58vboxsync * Write to the global command completion coalescing ports register.
4bf996d915405be92dc4394b2db1395e00e14d58vboxsyncstatic int HbaCccPorts_w(PAHCI ahci, uint32_t iReg, uint32_t u32Value)
71e045383a3316b27563b2f44b0e0e1231968bdcvboxsync Log(("%s: write u32Value=%#010x\n", __FUNCTION__, u32Value));
4bf996d915405be92dc4394b2db1395e00e14d58vboxsync * Read the global command completion coalescing ports register.
4bf996d915405be92dc4394b2db1395e00e14d58vboxsyncstatic int HbaCccPorts_r(PAHCI ahci, uint32_t iReg, uint32_t *pu32Value)
4bf996d915405be92dc4394b2db1395e00e14d58vboxsync Log(("%s: read regHbaCccPorts=%#010x\n", __FUNCTION__, ahci->regHbaCccPorts));
71e045383a3316b27563b2f44b0e0e1231968bdcvboxsync unsigned i;
71e045383a3316b27563b2f44b0e0e1231968bdcvboxsync * Invalid write to global register
71e045383a3316b27563b2f44b0e0e1231968bdcvboxsyncstatic int HbaInvalid_w(PAHCI ahci, uint32_t iReg, uint32_t u32Value)
71e045383a3316b27563b2f44b0e0e1231968bdcvboxsync Log(("%s: Write denied!!! iReg=%u u32Value=%#010x\n", __FUNCTION__, iReg, u32Value));
4bf996d915405be92dc4394b2db1395e00e14d58vboxsync * Invalid Port write.
4bf996d915405be92dc4394b2db1395e00e14d58vboxsyncstatic int PortInvalid_w(PAHCI ahci, PAHCIPort pAhciPort, uint32_t iReg, uint32_t u32Value)
4bf996d915405be92dc4394b2db1395e00e14d58vboxsync ahciLog(("%s: Write denied!!! iReg=%u u32Value=%#010x\n", __FUNCTION__, iReg, u32Value));
4bf996d915405be92dc4394b2db1395e00e14d58vboxsync * Invalid Port read.
4bf996d915405be92dc4394b2db1395e00e14d58vboxsyncstatic int PortInvalid_r(PAHCI ahci, PAHCIPort pAhciPort, uint32_t iReg, uint32_t *pu32Value)
4bf996d915405be92dc4394b2db1395e00e14d58vboxsync ahciLog(("%s: Read denied!!! iReg=%u\n", __FUNCTION__, iReg));
4bf996d915405be92dc4394b2db1395e00e14d58vboxsync * Register descriptor table for global HBA registers
71e045383a3316b27563b2f44b0e0e1231968bdcvboxsync {"HbaCapabilites", HbaCapabilities_r, HbaInvalid_w}, /* Readonly */
71e045383a3316b27563b2f44b0e0e1231968bdcvboxsync {"HbaInterruptStatus", HbaInterruptStatus_r, HbaInterruptStatus_w},
71e045383a3316b27563b2f44b0e0e1231968bdcvboxsync {"HbaPortsImplemented", HbaPortsImplemented_r, HbaInvalid_w}, /* Readonly */
71e045383a3316b27563b2f44b0e0e1231968bdcvboxsync {"HbaVersion", HbaVersion_r, HbaInvalid_w}, /* ReadOnly */
71e045383a3316b27563b2f44b0e0e1231968bdcvboxsync * Register descriptor table for port registers
71e045383a3316b27563b2f44b0e0e1231968bdcvboxsync {"PortCmdLstAddr", PortCmdLstAddr_r, PortCmdLstAddr_w},
71e045383a3316b27563b2f44b0e0e1231968bdcvboxsync {"PortCmdLstAddrUp", PortCmdLstAddrUp_r, PortCmdLstAddrUp_w},
71e045383a3316b27563b2f44b0e0e1231968bdcvboxsync {"PortFisAddrUp", PortFisAddrUp_r, PortFisAddrUp_w},
71e045383a3316b27563b2f44b0e0e1231968bdcvboxsync {"PortIntrEnable", PortIntrEnable_r, PortIntrEnable_w},
71e045383a3316b27563b2f44b0e0e1231968bdcvboxsync {"PortReserved1", PortInvalid_r, PortInvalid_w}, /* Not used. */
71e045383a3316b27563b2f44b0e0e1231968bdcvboxsync {"PortTaskFileData", PortTaskFileData_r, PortInvalid_w}, /* Readonly */
71e045383a3316b27563b2f44b0e0e1231968bdcvboxsync {"PortSignature", PortSignature_r, PortInvalid_w}, /* Readonly */
71e045383a3316b27563b2f44b0e0e1231968bdcvboxsync {"PortSStatus", PortSStatus_r, PortInvalid_w}, /* Readonly */
71e045383a3316b27563b2f44b0e0e1231968bdcvboxsync {"PortReserved2", PortInvalid_r, PortInvalid_w}, /* Not used. */
ad66a27959d7085aa31760f63ce082943be60e89vboxsync * Reset initiated by system software for one port.
ad66a27959d7085aa31760f63ce082943be60e89vboxsync * @param pAhciPort The port to reset.
1025ef7261a6961d07d390e85a095d806ccb88d9vboxsync /* Cancel all tasks first. */
ad66a27959d7085aa31760f63ce082943be60e89vboxsync fAllTasksCanceled = ahciCancelActiveTasks(pAhciPort);
ad66a27959d7085aa31760f63ce082943be60e89vboxsync pAhciPort->regCMD = AHCI_PORT_CMD_CPD | /* Cold presence detection */
ad66a27959d7085aa31760f63ce082943be60e89vboxsync /* Hotplugging supported?. */
5a5b5956f8b592c807c94785d58c25e717d430c4vboxsync pAhciPort->regTFD = (1 << 8) | ATA_STAT_SEEK | ATA_STAT_WRERR;
5a5b5956f8b592c807c94785d58c25e717d430c4vboxsync ASMAtomicWriteU32(&pAhciPort->MediaEventStatus, ATA_EVENT_STATUS_UNCHANGED);
5a5b5956f8b592c807c94785d58c25e717d430c4vboxsync ASMAtomicWriteU32(&pAhciPort->MediaTrackType, ATA_MEDIA_TYPE_UNKNOWN);
5a5b5956f8b592c807c94785d58c25e717d430c4vboxsync pAhciPort->regCMD |= AHCI_PORT_CMD_CPS; /* Indicate that there is a device on that port */
5a5b5956f8b592c807c94785d58c25e717d430c4vboxsync * Set states in the Port Signature and SStatus registers.
5a5b5956f8b592c807c94785d58c25e717d430c4vboxsync pAhciPort->regSSTS = (0x01 << 8) | /* Interface is active. */
5a5b5956f8b592c807c94785d58c25e717d430c4vboxsync (0x03 << 0); /* Device detected and communication established. */
5a5b5956f8b592c807c94785d58c25e717d430c4vboxsync * Hardware reset used for machine power on and reset.
5a5b5956f8b592c807c94785d58c25e717d430c4vboxsync * @param pAhciport The port to reset.
5a5b5956f8b592c807c94785d58c25e717d430c4vboxsync /* Reset the address registers. */
4bf996d915405be92dc4394b2db1395e00e14d58vboxsync /* Reset calculated addresses. */
71e045383a3316b27563b2f44b0e0e1231968bdcvboxsync * Create implemented ports bitmap.
4bf996d915405be92dc4394b2db1395e00e14d58vboxsync * @returns 32bit bitmask with a bit set for every implemented port.
4bf996d915405be92dc4394b2db1395e00e14d58vboxsync * @param cPorts Number of ports.
4bf996d915405be92dc4394b2db1395e00e14d58vboxsyncstatic uint32_t ahciGetPortsImplemented(unsigned cPorts)
71e045383a3316b27563b2f44b0e0e1231968bdcvboxsync for (unsigned i = 0; i < cPorts; i++)
71e045383a3316b27563b2f44b0e0e1231968bdcvboxsync * Reset the entire HBA.
4bf996d915405be92dc4394b2db1395e00e14d58vboxsync * @param pThis The HBA state.
c553cea6bfe2ce63ff5517ca4ec288502a890e99vboxsync unsigned i;
71e045383a3316b27563b2f44b0e0e1231968bdcvboxsync LogRel(("AHCI#%u: Reset the HBA\n", pThis->CTX_SUFF(pDevIns)->iInstance));
c553cea6bfe2ce63ff5517ca4ec288502a890e99vboxsync /* Stop the CCC timer. */
4bf996d915405be92dc4394b2db1395e00e14d58vboxsync AssertMsgFailed(("%s: Failed to stop timer!\n", __FUNCTION__));
4bf996d915405be92dc4394b2db1395e00e14d58vboxsync /* Reset every port */
b26e5b503baa3dffc58048982eaf17ad1b53f207vboxsync /* Init Global registers */
ad66a27959d7085aa31760f63ce082943be60e89vboxsync pThis->regHbaCap = AHCI_HBA_CAP_ISS_SHIFT(AHCI_HBA_CAP_ISS_GEN2) |
4bf996d915405be92dc4394b2db1395e00e14d58vboxsync AHCI_HBA_CAP_S64A | /* 64bit addressing supported */
4bf996d915405be92dc4394b2db1395e00e14d58vboxsync AHCI_HBA_CAP_SNCQ | /* Support native command queuing */
4bf996d915405be92dc4394b2db1395e00e14d58vboxsync AHCI_HBA_CAP_CCCS | /* Support command completion coalescing */
4bf996d915405be92dc4394b2db1395e00e14d58vboxsync AHCI_HBA_CAP_NCS_SET(pThis->cCmdSlotsAvail) | /* Number of command slots we support */
71e045383a3316b27563b2f44b0e0e1231968bdcvboxsync AHCI_HBA_CAP_NP_SET(pThis->cPortsImpl); /* Number of supported ports */
4bf996d915405be92dc4394b2db1395e00e14d58vboxsync pThis->regHbaPi = ahciGetPortsImplemented(pThis->cPortsImpl);
4bf996d915405be92dc4394b2db1395e00e14d58vboxsync pThis->regHbaVs = AHCI_HBA_VS_MJR | AHCI_HBA_VS_MNR;
ad66a27959d7085aa31760f63ce082943be60e89vboxsync /* Clear pending interrupts. */
ad66a27959d7085aa31760f63ce082943be60e89vboxsync pThis->f8ByteMMIO4BytesWrittenSuccessfully = false;
ad66a27959d7085aa31760f63ce082943be60e89vboxsync /* Clear the HBA Reset bit */
1025ef7261a6961d07d390e85a095d806ccb88d9vboxsync * Reads from a AHCI controller register.
1025ef7261a6961d07d390e85a095d806ccb88d9vboxsync * @returns VBox status code.
ad66a27959d7085aa31760f63ce082943be60e89vboxsync * @param pAhci The AHCI instance.
ad66a27959d7085aa31760f63ce082943be60e89vboxsync * @param uReg The register to write.
ad66a27959d7085aa31760f63ce082943be60e89vboxsync * @param pv Where to store the result.
ad66a27959d7085aa31760f63ce082943be60e89vboxsync * @param cb Number of bytes read.
ad66a27959d7085aa31760f63ce082943be60e89vboxsyncstatic int ahciRegisterRead(PAHCI pAhci, uint32_t uReg, void *pv, unsigned cb)
ad66a27959d7085aa31760f63ce082943be60e89vboxsync * If the access offset is smaller than AHCI_HBA_GLOBAL_SIZE the guest accesses the global registers.
ad66a27959d7085aa31760f63ce082943be60e89vboxsync * Otherwise it accesses the registers of a port.
113a43aca041000560f93f9a8ee23dfcf01a9e7cvboxsync Log3(("%s: Trying to read from global register %u\n", __FUNCTION__, iReg));
113a43aca041000560f93f9a8ee23dfcf01a9e7cvboxsync Log3(("%s: Trying to read global register %u/%u!!!\n", __FUNCTION__, iReg, RT_ELEMENTS(g_aOpRegs)));
113a43aca041000560f93f9a8ee23dfcf01a9e7cvboxsync /* Calculate accessed port. */
113a43aca041000560f93f9a8ee23dfcf01a9e7cvboxsync Log3(("%s: Trying to read from port %u and register %u\n", __FUNCTION__, iPort, iReg));
113a43aca041000560f93f9a8ee23dfcf01a9e7cvboxsync const AHCIPORTOPREG *pPortReg = &g_aPortOpRegs[iReg];
b26e5b503baa3dffc58048982eaf17ad1b53f207vboxsync rc = pPortReg->pfnRead(pAhci, &pAhci->ahciPort[iPort], iReg, (uint32_t *)pv);
c553cea6bfe2ce63ff5517ca4ec288502a890e99vboxsync Log3(("%s: Trying to read port %u register %u/%u!!!\n", __FUNCTION__, iPort, iReg, RT_ELEMENTS(g_aPortOpRegs)));
b26e5b503baa3dffc58048982eaf17ad1b53f207vboxsync * Windows Vista tries to read one byte from some registers instead of four.
b26e5b503baa3dffc58048982eaf17ad1b53f207vboxsync * Correct the value according to the read size.
4bf996d915405be92dc4394b2db1395e00e14d58vboxsync Log3(("%s: iRegOffset=%u\n", __FUNCTION__, iRegOffset));
4bf996d915405be92dc4394b2db1395e00e14d58vboxsync /* Clear old value */
c58c758d3642ac45d3f12356c406c631fcd8f538vboxsync AssertMsgFailed(("%s: unsupported access width cb=%d iPort=%x iRegOffset=%x iReg=%x!!!\n",
c58c758d3642ac45d3f12356c406c631fcd8f538vboxsync * Writes a value to one of the AHCI controller registers.
4bf996d915405be92dc4394b2db1395e00e14d58vboxsync * @returns VBox status code.
4bf996d915405be92dc4394b2db1395e00e14d58vboxsync * @param pAhci The AHCI instance.
4bf996d915405be92dc4394b2db1395e00e14d58vboxsync * @param offReg The offset of the register to write to.
4bf996d915405be92dc4394b2db1395e00e14d58vboxsync * @param u32Value The value to write.
4bf996d915405be92dc4394b2db1395e00e14d58vboxsyncstatic int ahciRegisterWrite(PAHCI pAhci, uint32_t offReg, uint32_t u32Value)
4bf996d915405be92dc4394b2db1395e00e14d58vboxsync * If the access offset is smaller than 100h the guest accesses the global registers.
4bf996d915405be92dc4394b2db1395e00e14d58vboxsync * Otherwise it accesses the registers of a port.
4bf996d915405be92dc4394b2db1395e00e14d58vboxsync Log3(("%s: Trying to write global register %u/%u!!!\n", __FUNCTION__, iReg, RT_ELEMENTS(g_aOpRegs)));
c58c758d3642ac45d3f12356c406c631fcd8f538vboxsync /* Calculate accessed port. */
4bf996d915405be92dc4394b2db1395e00e14d58vboxsync Log3(("%s: Trying to write to port %u and register %u\n", __FUNCTION__, iPort, iReg));
4bf996d915405be92dc4394b2db1395e00e14d58vboxsync const AHCIPORTOPREG *pPortReg = &g_aPortOpRegs[iReg];
1025ef7261a6961d07d390e85a095d806ccb88d9vboxsync rc = pPortReg->pfnWrite(pAhci, &pAhci->ahciPort[iPort], iReg, u32Value);
4b8c66482cbc69a01ac399b8588b8bc80b310523vboxsync Log3(("%s: Trying to write port %u register %u/%u!!!\n", __FUNCTION__, iPort, iReg, RT_ELEMENTS(g_aPortOpRegs)));
4b8c66482cbc69a01ac399b8588b8bc80b310523vboxsync * Memory mapped I/O Handler for read operations.
4b8c66482cbc69a01ac399b8588b8bc80b310523vboxsync * @returns VBox status code.
4b8c66482cbc69a01ac399b8588b8bc80b310523vboxsync * @param pDevIns The device instance.
4b8c66482cbc69a01ac399b8588b8bc80b310523vboxsync * @param pvUser User argument.
4b8c66482cbc69a01ac399b8588b8bc80b310523vboxsync * @param GCPhysAddr Physical address (in GC) where the read starts.
4b8c66482cbc69a01ac399b8588b8bc80b310523vboxsync * @param pv Where to store the result.
c58c758d3642ac45d3f12356c406c631fcd8f538vboxsync * @param cb Number of bytes read.
4b8c66482cbc69a01ac399b8588b8bc80b310523vboxsyncPDMBOTHCBDECL(int) ahciMMIORead(PPDMDEVINS pDevIns, void *pvUser, RTGCPHYS GCPhysAddr, void *pv, unsigned cb)
4bf996d915405be92dc4394b2db1395e00e14d58vboxsync Log2(("#%d ahciMMIORead: pvUser=%p:{%.*Rhxs} cb=%d GCPhysAddr=%RGp\n",
4bf996d915405be92dc4394b2db1395e00e14d58vboxsync int rc = ahciRegisterRead(pAhci, GCPhysAddr - pAhci->MMIOBase, pv, cb);
4bf996d915405be92dc4394b2db1395e00e14d58vboxsync Log2(("#%d ahciMMIORead: return pvUser=%p:{%.*Rhxs} cb=%d GCPhysAddr=%RGp rc=%Rrc\n",
4bf996d915405be92dc4394b2db1395e00e14d58vboxsync pDevIns->iInstance, pv, cb, pv, cb, GCPhysAddr, rc));
71e045383a3316b27563b2f44b0e0e1231968bdcvboxsync * Memory mapped I/O Handler for write operations.
71e045383a3316b27563b2f44b0e0e1231968bdcvboxsync * @returns VBox status code.
71e045383a3316b27563b2f44b0e0e1231968bdcvboxsync * @param pDevIns The device instance.
71e045383a3316b27563b2f44b0e0e1231968bdcvboxsync * @param pvUser User argument.
71e045383a3316b27563b2f44b0e0e1231968bdcvboxsync * @param GCPhysAddr Physical address (in GC) where the read starts.
71e045383a3316b27563b2f44b0e0e1231968bdcvboxsync * @param pv Where to fetch the result.
71e045383a3316b27563b2f44b0e0e1231968bdcvboxsync * @param cb Number of bytes to write.
5a5b5956f8b592c807c94785d58c25e717d430c4vboxsyncPDMBOTHCBDECL(int) ahciMMIOWrite(PPDMDEVINS pDevIns, void *pvUser, RTGCPHYS GCPhysAddr, void const *pv, unsigned cb)
71e045383a3316b27563b2f44b0e0e1231968bdcvboxsync /* Break up 64 bits writes into two dword writes. */
4b8c66482cbc69a01ac399b8588b8bc80b310523vboxsync /** @todo Eliminate this code once the IOM/EM starts taking care of these
71e045383a3316b27563b2f44b0e0e1231968bdcvboxsync * situations. */
71e045383a3316b27563b2f44b0e0e1231968bdcvboxsync * Only write the first 4 bytes if they weren't already.
71e045383a3316b27563b2f44b0e0e1231968bdcvboxsync * It is possible that the last write to the register caused a world
71e045383a3316b27563b2f44b0e0e1231968bdcvboxsync * switch and we entered this function again.
71e045383a3316b27563b2f44b0e0e1231968bdcvboxsync * Writing the first 4 bytes again could cause indeterminate behavior
71e045383a3316b27563b2f44b0e0e1231968bdcvboxsync * which can cause errors in the guest.
5a5b5956f8b592c807c94785d58c25e717d430c4vboxsync rc = ahciMMIOWrite(pDevIns, pvUser, GCPhysAddr, pv, 4);
1025ef7261a6961d07d390e85a095d806ccb88d9vboxsync rc = ahciMMIOWrite(pDevIns, pvUser, GCPhysAddr + 4, (uint8_t *)pv + 4, 4);
1025ef7261a6961d07d390e85a095d806ccb88d9vboxsync * Reset flag again so that the first 4 bytes are written again on the next
1025ef7261a6961d07d390e85a095d806ccb88d9vboxsync * 8byte MMIO access.
71e045383a3316b27563b2f44b0e0e1231968bdcvboxsync pAhci->f8ByteMMIO4BytesWrittenSuccessfully = false;
5a5b5956f8b592c807c94785d58c25e717d430c4vboxsync /* Do the access. */
5a5b5956f8b592c807c94785d58c25e717d430c4vboxsync Log2(("#%d ahciMMIOWrite: pvUser=%p:{%.*Rhxs} cb=%d GCPhysAddr=%RGp\n", pDevIns->iInstance, pv, cb, pv, cb, GCPhysAddr));
5a5b5956f8b592c807c94785d58c25e717d430c4vboxsync return ahciRegisterWrite(pAhci, GCPhysAddr - pAhci->MMIOBase, *(uint32_t const *)pv);
cecb0b0ed75fde05db9e1958b7c813c572cf81fevboxsyncPDMBOTHCBDECL(int) ahciLegacyFakeWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb)
5a5b5956f8b592c807c94785d58c25e717d430c4vboxsyncPDMBOTHCBDECL(int) ahciLegacyFakeRead(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t *pu32, unsigned cb)
71e045383a3316b27563b2f44b0e0e1231968bdcvboxsync * I/O port handler for writes to the index/data register pair.
71e045383a3316b27563b2f44b0e0e1231968bdcvboxsync * @returns VBox status code.
71e045383a3316b27563b2f44b0e0e1231968bdcvboxsync * @param pDevIns The device instance.
71e045383a3316b27563b2f44b0e0e1231968bdcvboxsync * @param pvUser User argument.
71e045383a3316b27563b2f44b0e0e1231968bdcvboxsync * @param Port Port address where the write starts.
71e045383a3316b27563b2f44b0e0e1231968bdcvboxsync * @param pv Where to fetch the result.
1025ef7261a6961d07d390e85a095d806ccb88d9vboxsync * @param cb Number of bytes to write.
71e045383a3316b27563b2f44b0e0e1231968bdcvboxsyncPDMBOTHCBDECL(int) ahciIdxDataWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb)
5a5b5956f8b592c807c94785d58c25e717d430c4vboxsync unsigned iReg = (Port - pAhci->IOPortBase - 8) / 4;
5a5b5956f8b592c807c94785d58c25e717d430c4vboxsync /* Write the index register. */
5a5b5956f8b592c807c94785d58c25e717d430c4vboxsync /** @todo range check? */
71e045383a3316b27563b2f44b0e0e1231968bdcvboxsync /* else: ignore */
1025ef7261a6961d07d390e85a095d806ccb88d9vboxsync Log2(("#%d ahciIdxDataWrite: pu32=%p:{%.*Rhxs} cb=%d Port=%#x rc=%Rrc\n",
71e045383a3316b27563b2f44b0e0e1231968bdcvboxsync pDevIns->iInstance, &u32, cb, &u32, cb, Port, rc));
71e045383a3316b27563b2f44b0e0e1231968bdcvboxsync * I/O port handler for reads from the index/data register pair.
71e045383a3316b27563b2f44b0e0e1231968bdcvboxsync * @returns VBox status code.
1025ef7261a6961d07d390e85a095d806ccb88d9vboxsync * @param pDevIns The device instance.
71e045383a3316b27563b2f44b0e0e1231968bdcvboxsync * @param pvUser User argument.
71e045383a3316b27563b2f44b0e0e1231968bdcvboxsync * @param Port Port address where the read starts.
71e045383a3316b27563b2f44b0e0e1231968bdcvboxsync * @param pv Where to fetch the result.
5a5b5956f8b592c807c94785d58c25e717d430c4vboxsync * @param cb Number of bytes to write.
5a5b5956f8b592c807c94785d58c25e717d430c4vboxsyncPDMBOTHCBDECL(int) ahciIdxDataRead(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t *pu32, unsigned cb)
1025ef7261a6961d07d390e85a095d806ccb88d9vboxsync unsigned iReg = (Port - pAhci->IOPortBase - 8) / 4;
71e045383a3316b27563b2f44b0e0e1231968bdcvboxsync /* Read the index register. */
71e045383a3316b27563b2f44b0e0e1231968bdcvboxsync /** @todo range check? */
71e045383a3316b27563b2f44b0e0e1231968bdcvboxsync rc = ahciRegisterRead(pAhci, pAhci->regIdx, pu32, cb);
71e045383a3316b27563b2f44b0e0e1231968bdcvboxsync Log2(("#%d ahciIdxDataRead: pu32=%p:{%.*Rhxs} cb=%d Port=%#x rc=%Rrc\n",
71e045383a3316b27563b2f44b0e0e1231968bdcvboxsync pDevIns->iInstance, pu32, cb, pu32, cb, Port, rc));
71e045383a3316b27563b2f44b0e0e1231968bdcvboxsyncstatic DECLCALLBACK(int) ahciR3MMIOMap(PPCIDEVICE pPciDev, /*unsigned*/ int iRegion, RTGCPHYS GCPhysAddress, uint32_t cb, PCIADDRESSSPACE enmType)
71e045383a3316b27563b2f44b0e0e1231968bdcvboxsync Log2(("%s: registering MMIO area at GCPhysAddr=%RGp cb=%u\n", __FUNCTION__, GCPhysAddress, cb));
71e045383a3316b27563b2f44b0e0e1231968bdcvboxsync /* We use the assigned size here, because we currently only support page aligned MMIO ranges. */
71e045383a3316b27563b2f44b0e0e1231968bdcvboxsync /** @todo change this to IOMMMIO_FLAGS_WRITE_ONLY_DWORD once EM/IOM starts
71e045383a3316b27563b2f44b0e0e1231968bdcvboxsync * handling 2nd DWORD failures on split accesses correctly. */
71e045383a3316b27563b2f44b0e0e1231968bdcvboxsync rc = PDMDevHlpMMIORegister(pDevIns, GCPhysAddress, cb, NULL /*pvUser*/,
4bf996d915405be92dc4394b2db1395e00e14d58vboxsync IOMMMIO_FLAGS_READ_DWORD | IOMMMIO_FLAGS_WRITE_ONLY_DWORD_QWORD,
5a5b5956f8b592c807c94785d58c25e717d430c4vboxsync rc = PDMDevHlpMMIORegisterR0(pDevIns, GCPhysAddress, cb, NIL_RTR0PTR /*pvUser*/, "ahciMMIOWrite", "ahciMMIORead");
71e045383a3316b27563b2f44b0e0e1231968bdcvboxsync rc = PDMDevHlpMMIORegisterRC(pDevIns, GCPhysAddress, cb, NIL_RTRCPTR /*pvUser*/, "ahciMMIOWrite", "ahciMMIORead");
5a5b5956f8b592c807c94785d58c25e717d430c4vboxsync * Map the legacy I/O port ranges to make Solaris work with the controller.
5a5b5956f8b592c807c94785d58c25e717d430c4vboxsyncstatic DECLCALLBACK(int) ahciR3LegacyFakeIORangeMap(PPCIDEVICE pPciDev, /*unsigned*/ int iRegion, RTGCPHYS GCPhysAddress, uint32_t cb, PCIADDRESSSPACE enmType)
1025ef7261a6961d07d390e85a095d806ccb88d9vboxsync Log2(("%s: registering fake I/O area at GCPhysAddr=%RGp cb=%u\n", __FUNCTION__, GCPhysAddress, cb));
1025ef7261a6961d07d390e85a095d806ccb88d9vboxsync /* We use the assigned size here, because we currently only support page aligned MMIO ranges. */
1025ef7261a6961d07d390e85a095d806ccb88d9vboxsync rc = PDMDevHlpIOPortRegister(pDevIns, (RTIOPORT)GCPhysAddress, cb, NULL,
1025ef7261a6961d07d390e85a095d806ccb88d9vboxsync ahciLegacyFakeWrite, ahciLegacyFakeRead, NULL, NULL, "AHCI Fake");
4b8c66482cbc69a01ac399b8588b8bc80b310523vboxsync rc = PDMDevHlpIOPortRegisterR0(pDevIns, (RTIOPORT)GCPhysAddress, cb, 0,
4b8c66482cbc69a01ac399b8588b8bc80b310523vboxsync "ahciLegacyFakeWrite", "ahciLegacyFakeRead", NULL, NULL, "AHCI Fake");
71e045383a3316b27563b2f44b0e0e1231968bdcvboxsync rc = PDMDevHlpIOPortRegisterRC(pDevIns, (RTIOPORT)GCPhysAddress, cb, 0,
5a5b5956f8b592c807c94785d58c25e717d430c4vboxsync "ahciLegacyFakeWrite", "ahciLegacyFakeRead", NULL, NULL, "AHCI Fake");
5a5b5956f8b592c807c94785d58c25e717d430c4vboxsync * Map the BMDMA I/O port range (used for the Index/Data pair register access)
5a5b5956f8b592c807c94785d58c25e717d430c4vboxsyncstatic DECLCALLBACK(int) ahciR3IdxDataIORangeMap(PPCIDEVICE pPciDev, /*unsigned*/ int iRegion, RTGCPHYS GCPhysAddress, uint32_t cb, PCIADDRESSSPACE enmType)
71e045383a3316b27563b2f44b0e0e1231968bdcvboxsync Log2(("%s: registering fake I/O area at GCPhysAddr=%RGp cb=%u\n", __FUNCTION__, GCPhysAddress, cb));
71e045383a3316b27563b2f44b0e0e1231968bdcvboxsync /* We use the assigned size here, because we currently only support page aligned MMIO ranges. */
71e045383a3316b27563b2f44b0e0e1231968bdcvboxsync rc = PDMDevHlpIOPortRegister(pDevIns, (RTIOPORT)GCPhysAddress, cb, NULL,
71e045383a3316b27563b2f44b0e0e1231968bdcvboxsync ahciIdxDataWrite, ahciIdxDataRead, NULL, NULL, "AHCI IDX/DATA");
5a5b5956f8b592c807c94785d58c25e717d430c4vboxsync rc = PDMDevHlpIOPortRegisterR0(pDevIns, (RTIOPORT)GCPhysAddress, cb, 0,
5a5b5956f8b592c807c94785d58c25e717d430c4vboxsync "ahciIdxDataWrite", "ahciIdxDataRead", NULL, NULL, "AHCI IDX/DATA");
71e045383a3316b27563b2f44b0e0e1231968bdcvboxsync rc = PDMDevHlpIOPortRegisterRC(pDevIns, (RTIOPORT)GCPhysAddress, cb, 0,
71e045383a3316b27563b2f44b0e0e1231968bdcvboxsync "ahciIdxDataWrite", "ahciIdxDataRead", NULL, NULL, "AHCI IDX/DATA");
5a5b5956f8b592c807c94785d58c25e717d430c4vboxsync/* -=-=-=-=-=- PAHCI::ILeds -=-=-=-=-=- */
71e045383a3316b27563b2f44b0e0e1231968bdcvboxsync * Gets the pointer to the status LED of a unit.
71e045383a3316b27563b2f44b0e0e1231968bdcvboxsync * @returns VBox status code.
71e045383a3316b27563b2f44b0e0e1231968bdcvboxsync * @param pInterface Pointer to the interface structure containing the called function pointer.
71e045383a3316b27563b2f44b0e0e1231968bdcvboxsync * @param iLUN The unit which status LED we desire.
71e045383a3316b27563b2f44b0e0e1231968bdcvboxsync * @param ppLed Where to store the LED pointer.
71e045383a3316b27563b2f44b0e0e1231968bdcvboxsyncstatic DECLCALLBACK(int) ahciR3Status_QueryStatusLed(PPDMILEDPORTS pInterface, unsigned iLUN, PPDMLED *ppLed)
5a5b5956f8b592c807c94785d58c25e717d430c4vboxsync * @interface_method_impl{PDMIBASE,pfnQueryInterface}
71e045383a3316b27563b2f44b0e0e1231968bdcvboxsyncstatic DECLCALLBACK(void *) ahciR3Status_QueryInterface(PPDMIBASE pInterface, const char *pszIID)
71e045383a3316b27563b2f44b0e0e1231968bdcvboxsync PDMIBASE_RETURN_INTERFACE(pszIID, PDMIBASE, &pThis->IBase);
71e045383a3316b27563b2f44b0e0e1231968bdcvboxsync PDMIBASE_RETURN_INTERFACE(pszIID, PDMILEDPORTS, &pThis->ILeds);
71e045383a3316b27563b2f44b0e0e1231968bdcvboxsync * @interface_method_impl{PDMIBASE,pfnQueryInterface}
4bf996d915405be92dc4394b2db1395e00e14d58vboxsyncstatic DECLCALLBACK(void *) ahciR3PortQueryInterface(PPDMIBASE pInterface, const char *pszIID)
4bf996d915405be92dc4394b2db1395e00e14d58vboxsync PAHCIPort pAhciPort = PDMIBASE_2_PAHCIPORT(pInterface);
4bf996d915405be92dc4394b2db1395e00e14d58vboxsync PDMIBASE_RETURN_INTERFACE(pszIID, PDMIBASE, &pAhciPort->IBase);
4bf996d915405be92dc4394b2db1395e00e14d58vboxsync PDMIBASE_RETURN_INTERFACE(pszIID, PDMIBLOCKPORT, &pAhciPort->IPort);
4bf996d915405be92dc4394b2db1395e00e14d58vboxsync PDMIBASE_RETURN_INTERFACE(pszIID, PDMIBLOCKASYNCPORT, &pAhciPort->IPortAsync);
4bf996d915405be92dc4394b2db1395e00e14d58vboxsync PDMIBASE_RETURN_INTERFACE(pszIID, PDMIMOUNTNOTIFY, &pAhciPort->IMountNotify);
71e045383a3316b27563b2f44b0e0e1231968bdcvboxsync * @interface_method_impl{PDMIBLOCKPORT,pfnQueryDeviceLocation}
71e045383a3316b27563b2f44b0e0e1231968bdcvboxsyncstatic DECLCALLBACK(int) ahciR3PortQueryDeviceLocation(PPDMIBLOCKPORT pInterface, const char **ppcszController,
71e045383a3316b27563b2f44b0e0e1231968bdcvboxsync PAHCIPort pAhciPort = PDMIBLOCKPORT_2_PAHCIPORT(pInterface);
5a5b5956f8b592c807c94785d58c25e717d430c4vboxsync AssertPtrReturn(ppcszController, VERR_INVALID_POINTER);
5a5b5956f8b592c807c94785d58c25e717d430c4vboxsync * Dump info about the FIS
5a5b5956f8b592c807c94785d58c25e717d430c4vboxsync * @returns nothing
5a5b5956f8b592c807c94785d58c25e717d430c4vboxsync * @param pAhciPort The port the command FIS was read from.
5a5b5956f8b592c807c94785d58c25e717d430c4vboxsync * @param cmdFis The FIS to print info from.
5a5b5956f8b592c807c94785d58c25e717d430c4vboxsyncstatic void ahciDumpFisInfo(PAHCIPort pAhciPort, uint8_t *cmdFis)
5a5b5956f8b592c807c94785d58c25e717d430c4vboxsync ahciLog(("%s: *** Begin FIS info dump. ***\n", __FUNCTION__));
5a5b5956f8b592c807c94785d58c25e717d430c4vboxsync /* Print FIS type. */
5a5b5956f8b592c807c94785d58c25e717d430c4vboxsync ahciLog(("%s: Command Fis type: H2D\n", __FUNCTION__));
5a5b5956f8b592c807c94785d58c25e717d430c4vboxsync ahciLog(("%s: Command Fis size: %d bytes\n", __FUNCTION__, AHCI_CMDFIS_TYPE_H2D_SIZE));
5a5b5956f8b592c807c94785d58c25e717d430c4vboxsync ahciLog(("%s: Command register update\n", __FUNCTION__));
5a5b5956f8b592c807c94785d58c25e717d430c4vboxsync ahciLog(("%s: Control register update\n", __FUNCTION__));
5a5b5956f8b592c807c94785d58c25e717d430c4vboxsync ahciLog(("%s: CMD=%#04x \"%s\"\n", __FUNCTION__, cmdFis[AHCI_CMDFIS_CMD], ATACmdText(cmdFis[AHCI_CMDFIS_CMD])));
5a5b5956f8b592c807c94785d58c25e717d430c4vboxsync ahciLog(("%s: FEAT=%#04x\n", __FUNCTION__, cmdFis[AHCI_CMDFIS_FET]));
71e045383a3316b27563b2f44b0e0e1231968bdcvboxsync ahciLog(("%s: SECTN=%#04x\n", __FUNCTION__, cmdFis[AHCI_CMDFIS_SECTN]));
71e045383a3316b27563b2f44b0e0e1231968bdcvboxsync ahciLog(("%s: CYLL=%#04x\n", __FUNCTION__, cmdFis[AHCI_CMDFIS_CYLL]));
5a5b5956f8b592c807c94785d58c25e717d430c4vboxsync ahciLog(("%s: CYLH=%#04x\n", __FUNCTION__, cmdFis[AHCI_CMDFIS_CYLH]));
5a5b5956f8b592c807c94785d58c25e717d430c4vboxsync ahciLog(("%s: HEAD=%#04x\n", __FUNCTION__, cmdFis[AHCI_CMDFIS_HEAD]));
71e045383a3316b27563b2f44b0e0e1231968bdcvboxsync ahciLog(("%s: SECTNEXP=%#04x\n", __FUNCTION__, cmdFis[AHCI_CMDFIS_SECTNEXP]));
71e045383a3316b27563b2f44b0e0e1231968bdcvboxsync ahciLog(("%s: CYLLEXP=%#04x\n", __FUNCTION__, cmdFis[AHCI_CMDFIS_CYLLEXP]));
71e045383a3316b27563b2f44b0e0e1231968bdcvboxsync ahciLog(("%s: CYLHEXP=%#04x\n", __FUNCTION__, cmdFis[AHCI_CMDFIS_CYLHEXP]));
71e045383a3316b27563b2f44b0e0e1231968bdcvboxsync ahciLog(("%s: FETEXP=%#04x\n", __FUNCTION__, cmdFis[AHCI_CMDFIS_FETEXP]));
71e045383a3316b27563b2f44b0e0e1231968bdcvboxsync ahciLog(("%s: SECTC=%#04x\n", __FUNCTION__, cmdFis[AHCI_CMDFIS_SECTC]));
5a5b5956f8b592c807c94785d58c25e717d430c4vboxsync ahciLog(("%s: SECTCEXP=%#04x\n", __FUNCTION__, cmdFis[AHCI_CMDFIS_SECTCEXP]));
5a5b5956f8b592c807c94785d58c25e717d430c4vboxsync ahciLog(("%s: CTL=%#04x\n", __FUNCTION__, cmdFis[AHCI_CMDFIS_CTL]));
71e045383a3316b27563b2f44b0e0e1231968bdcvboxsync if (cmdFis[AHCI_CMDFIS_CTL] & AHCI_CMDFIS_CTL_SRST)
71e045383a3316b27563b2f44b0e0e1231968bdcvboxsync ahciLog(("%s: Command Fis type D2H\n", __FUNCTION__));
71e045383a3316b27563b2f44b0e0e1231968bdcvboxsync ahciLog(("%s: Command Fis size: %d\n", __FUNCTION__, AHCI_CMDFIS_TYPE_D2H_SIZE));
71e045383a3316b27563b2f44b0e0e1231968bdcvboxsync ahciLog(("%s: Command Fis type Set Device Bits\n", __FUNCTION__));
71e045383a3316b27563b2f44b0e0e1231968bdcvboxsync ahciLog(("%s: Command Fis size: %d\n", __FUNCTION__, AHCI_CMDFIS_TYPE_SETDEVBITS_SIZE));
d3dea25ec07f6546715fe3af943ea863294b392evboxsync ahciLog(("%s: Command Fis type DMA Activate H2D\n", __FUNCTION__));
d3dea25ec07f6546715fe3af943ea863294b392evboxsync ahciLog(("%s: Command Fis size: %d\n", __FUNCTION__, AHCI_CMDFIS_TYPE_DMAACTD2H_SIZE));
d3dea25ec07f6546715fe3af943ea863294b392evboxsync ahciLog(("%s: Command Fis type DMA Setup\n", __FUNCTION__));
4bf996d915405be92dc4394b2db1395e00e14d58vboxsync ahciLog(("%s: Command Fis size: %d\n", __FUNCTION__, AHCI_CMDFIS_TYPE_DMASETUP_SIZE));
71e045383a3316b27563b2f44b0e0e1231968bdcvboxsync ahciLog(("%s: Command Fis type PIO Setup\n", __FUNCTION__));
71e045383a3316b27563b2f44b0e0e1231968bdcvboxsync ahciLog(("%s: Command Fis size: %d\n", __FUNCTION__, AHCI_CMDFIS_TYPE_PIOSETUP_SIZE));
71e045383a3316b27563b2f44b0e0e1231968bdcvboxsync ahciLog(("%s: Command Fis type Data\n", __FUNCTION__));
5b0a093ca572a855886faa6747ad46df859dd041vboxsync ahciLog(("%s: ERROR Unknown command FIS type\n", __FUNCTION__));
ad66a27959d7085aa31760f63ce082943be60e89vboxsync ahciLog(("%s: *** End FIS info dump. ***\n", __FUNCTION__));
ad66a27959d7085aa31760f63ce082943be60e89vboxsync * Dump info about the command header
ad66a27959d7085aa31760f63ce082943be60e89vboxsync * @returns nothing
ad66a27959d7085aa31760f63ce082943be60e89vboxsync * @param pAhciPort Pointer to the port the command header was read from.
ad66a27959d7085aa31760f63ce082943be60e89vboxsync * @param pCmdHdr The command header to print info from.
ad66a27959d7085aa31760f63ce082943be60e89vboxsyncstatic void ahciDumpCmdHdrInfo(PAHCIPort pAhciPort, CmdHdr *pCmdHdr)
ad66a27959d7085aa31760f63ce082943be60e89vboxsync ahciLog(("%s: *** Begin command header info dump. ***\n", __FUNCTION__));
d3dea25ec07f6546715fe3af943ea863294b392evboxsync ahciLog(("%s: Number of Scatter/Gatther List entries: %u\n", __FUNCTION__, AHCI_CMDHDR_PRDTL_ENTRIES(pCmdHdr->u32DescInf)));
d3dea25ec07f6546715fe3af943ea863294b392evboxsync ahciLog(("%s: Clear busy upon R_OK\n", __FUNCTION__));
ad66a27959d7085aa31760f63ce082943be60e89vboxsync ahciLog(("%s: Command prefetchable\n", __FUNCTION__));
ad66a27959d7085aa31760f63ce082943be60e89vboxsync ahciLog(("%s: Command FIS length %u DW\n", __FUNCTION__, (pCmdHdr->u32DescInf & AHCI_CMDHDR_CFL_MASK)));
ad66a27959d7085aa31760f63ce082943be60e89vboxsync ahciLog(("%s: *** End command header info dump. ***\n", __FUNCTION__));
ad66a27959d7085aa31760f63ce082943be60e89vboxsync#endif /* LOG_ENABLED */
ad66a27959d7085aa31760f63ce082943be60e89vboxsync * Post the first D2H FIS from the device into guest memory.
ad66a27959d7085aa31760f63ce082943be60e89vboxsync * @returns nothing
c553cea6bfe2ce63ff5517ca4ec288502a890e99vboxsync * @param pAhciPort Pointer to the port which "receives" the FIS.
ad66a27959d7085aa31760f63ce082943be60e89vboxsyncstatic void ahciPostFirstD2HFisIntoMemory(PAHCIPort pAhciPort)
ad66a27959d7085aa31760f63ce082943be60e89vboxsync ahciLog(("%s: Sending First D2H FIS from FIFO\n", __FUNCTION__));
ad66a27959d7085aa31760f63ce082943be60e89vboxsync /* Set the signature based on the device type. */
ad66a27959d7085aa31760f63ce082943be60e89vboxsync pAhciPort->regTFD = (1 << 8) | ATA_STAT_SEEK | ATA_STAT_WRERR;
1025ef7261a6961d07d390e85a095d806ccb88d9vboxsync ahciPostFisIntoMemory(pAhciPort, AHCI_CMDFIS_TYPE_D2H, d2hFis);
ad66a27959d7085aa31760f63ce082943be60e89vboxsync * Post the FIS in the memory area allocated by the guest and set interrupt if necessary.
ad66a27959d7085aa31760f63ce082943be60e89vboxsync * @returns VBox status code
ad66a27959d7085aa31760f63ce082943be60e89vboxsync * @param pAhciPort The port which "receives" the FIS.
5b0a093ca572a855886faa6747ad46df859dd041vboxsync * @param uFisType The type of the FIS.
ad66a27959d7085aa31760f63ce082943be60e89vboxsync * @param pCmdFis Pointer to the FIS which is to be posted into memory.
ad66a27959d7085aa31760f63ce082943be60e89vboxsyncstatic int ahciPostFisIntoMemory(PAHCIPort pAhciPort, unsigned uFisType, uint8_t *pCmdFis)
ad66a27959d7085aa31760f63ce082943be60e89vboxsync RTGCPHYS GCPhysAddrRecFis = pAhciPort->GCPhysAddrFb;
ad66a27959d7085aa31760f63ce082943be60e89vboxsync unsigned cbFis = 0;
ad66a27959d7085aa31760f63ce082943be60e89vboxsync ahciLog(("%s: pAhciPort=%p uFisType=%u pCmdFis=%p\n", __FUNCTION__, pAhciPort, uFisType, pCmdFis));
ad66a27959d7085aa31760f63ce082943be60e89vboxsync AssertMsg(GCPhysAddrRecFis, ("%s: GCPhysAddrRecFis is 0\n", __FUNCTION__));
ad66a27959d7085aa31760f63ce082943be60e89vboxsync /* Determine the offset and size of the FIS based on uFisType. */
ad66a27959d7085aa31760f63ce082943be60e89vboxsync * We should post the unknown FIS into memory too but this never happens because
ad66a27959d7085aa31760f63ce082943be60e89vboxsync * we know which FIS types we generate. ;)
ad66a27959d7085aa31760f63ce082943be60e89vboxsync AssertMsgFailed(("%s: Unknown FIS type!\n", __FUNCTION__));
ad66a27959d7085aa31760f63ce082943be60e89vboxsync /* Post the FIS into memory. */
ad66a27959d7085aa31760f63ce082943be60e89vboxsync ahciLog(("%s: PDMDevHlpPCIPhysWrite GCPhysAddrRecFis=%RGp cbFis=%u\n", __FUNCTION__, GCPhysAddrRecFis, cbFis));
ad66a27959d7085aa31760f63ce082943be60e89vboxsync PDMDevHlpPCIPhysWrite(pAhciPort->CTX_SUFF(pDevIns), GCPhysAddrRecFis, pCmdFis, cbFis);
ad66a27959d7085aa31760f63ce082943be60e89vboxsyncDECLINLINE(void) ataH2BE_U16(uint8_t *pbBuf, uint16_t val)
ad66a27959d7085aa31760f63ce082943be60e89vboxsyncDECLINLINE(void) ataH2BE_U24(uint8_t *pbBuf, uint32_t val)
c553cea6bfe2ce63ff5517ca4ec288502a890e99vboxsyncDECLINLINE(void) ataH2BE_U32(uint8_t *pbBuf, uint32_t val)
ad66a27959d7085aa31760f63ce082943be60e89vboxsyncDECLINLINE(uint16_t) ataBE2H_U16(const uint8_t *pbBuf)
ad66a27959d7085aa31760f63ce082943be60e89vboxsyncDECLINLINE(uint32_t) ataBE2H_U24(const uint8_t *pbBuf)
ad66a27959d7085aa31760f63ce082943be60e89vboxsync return (pbBuf[0] << 16) | (pbBuf[1] << 8) | pbBuf[2];
ad66a27959d7085aa31760f63ce082943be60e89vboxsyncDECLINLINE(uint32_t) ataBE2H_U32(const uint8_t *pbBuf)
ad66a27959d7085aa31760f63ce082943be60e89vboxsync return (pbBuf[0] << 24) | (pbBuf[1] << 16) | (pbBuf[2] << 8) | pbBuf[3];
ad66a27959d7085aa31760f63ce082943be60e89vboxsyncDECLINLINE(void) ataLBA2MSF(uint8_t *pbBuf, uint32_t iATAPILBA)
ad66a27959d7085aa31760f63ce082943be60e89vboxsyncDECLINLINE(uint32_t) ataMSF2LBA(const uint8_t *pbBuf)
e4bf6817370e1a71833a02285515694afcda7599vboxsyncstatic void atapiCmdOK(PAHCIPort pAhciPort, PAHCIREQ pAhciReq)
e4bf6817370e1a71833a02285515694afcda7599vboxsync pAhciReq->uATARegStatus = ATA_STAT_READY | ATA_STAT_SEEK;
e4bf6817370e1a71833a02285515694afcda7599vboxsync pAhciReq->cmdFis[AHCI_CMDFIS_SECTN] = (pAhciReq->cmdFis[AHCI_CMDFIS_SECTN] & ~7)
e4bf6817370e1a71833a02285515694afcda7599vboxsync | ((pAhciReq->enmTxDir != AHCITXDIR_WRITE) ? ATAPI_INT_REASON_IO : 0)
c553cea6bfe2ce63ff5517ca4ec288502a890e99vboxsync | (!pAhciReq->cbTransfer ? ATAPI_INT_REASON_CD : 0);
c553cea6bfe2ce63ff5517ca4ec288502a890e99vboxsync memset(pAhciPort->abATAPISense, '\0', sizeof(pAhciPort->abATAPISense));
e4bf6817370e1a71833a02285515694afcda7599vboxsyncstatic void atapiCmdError(PAHCIPort pAhciPort, PAHCIREQ pAhciReq, const uint8_t *pabATAPISense, size_t cbATAPISense)
e4bf6817370e1a71833a02285515694afcda7599vboxsync Log(("%s: sense=%#x (%s) asc=%#x ascq=%#x (%s)\n", __FUNCTION__, pabATAPISense[2] & 0x0f, SCSISenseText(pabATAPISense[2] & 0x0f),
e4bf6817370e1a71833a02285515694afcda7599vboxsync pabATAPISense[12], pabATAPISense[13], SCSISenseExtText(pabATAPISense[12], pabATAPISense[13])));
e4bf6817370e1a71833a02285515694afcda7599vboxsync pAhciReq->uATARegStatus = ATA_STAT_READY | ATA_STAT_ERR;
e4bf6817370e1a71833a02285515694afcda7599vboxsync pAhciReq->cmdFis[AHCI_CMDFIS_SECTN] = (pAhciReq->cmdFis[AHCI_CMDFIS_SECTN] & ~7) |
e4bf6817370e1a71833a02285515694afcda7599vboxsync memset(pAhciPort->abATAPISense, '\0', sizeof(pAhciPort->abATAPISense));
e4bf6817370e1a71833a02285515694afcda7599vboxsync memcpy(pAhciPort->abATAPISense, pabATAPISense, RT_MIN(cbATAPISense, sizeof(pAhciPort->abATAPISense)));
e4bf6817370e1a71833a02285515694afcda7599vboxsync/** @todo deprecated function - doesn't provide enough info. Replace by direct
c553cea6bfe2ce63ff5517ca4ec288502a890e99vboxsync * calls to atapiCmdError() with full data. */
c553cea6bfe2ce63ff5517ca4ec288502a890e99vboxsyncstatic void atapiCmdErrorSimple(PAHCIPort pAhciPort, PAHCIREQ pAhciReq, uint8_t uATAPISenseKey, uint8_t uATAPIASC)
c553cea6bfe2ce63ff5517ca4ec288502a890e99vboxsync atapiCmdError(pAhciPort, pAhciReq, abATAPISense, sizeof(abATAPISense));
e4bf6817370e1a71833a02285515694afcda7599vboxsyncstatic void ataSCSIPadStr(uint8_t *pbDst, const char *pbSrc, uint32_t cbSize)
e4bf6817370e1a71833a02285515694afcda7599vboxsyncstatic void ataPadString(uint8_t *pbDst, const char *pbSrc, uint32_t cbSize)
e4bf6817370e1a71833a02285515694afcda7599vboxsyncstatic uint32_t ataChecksum(void* ptr, size_t count)
725fba5c64717677ac66072bae37e5b3686f3e6dvboxsync for (i = 0; i < count; i++)
725fba5c64717677ac66072bae37e5b3686f3e6dvboxsyncstatic int ahciIdentifySS(PAHCIPort pAhciPort, void *pvBuf)
113a43aca041000560f93f9a8ee23dfcf01a9e7cvboxsync p[1] = RT_H2LE_U16(RT_MIN(pAhciPort->PCHSGeometry.cCylinders, 16383));
725fba5c64717677ac66072bae37e5b3686f3e6dvboxsync p[3] = RT_H2LE_U16(pAhciPort->PCHSGeometry.cHeads);
725fba5c64717677ac66072bae37e5b3686f3e6dvboxsync /* Block size; obsolete, but required for the BIOS. */
725fba5c64717677ac66072bae37e5b3686f3e6dvboxsync p[6] = RT_H2LE_U16(pAhciPort->PCHSGeometry.cSectors);
725fba5c64717677ac66072bae37e5b3686f3e6dvboxsync ataPadString((uint8_t *)(p + 10), pAhciPort->szSerialNumber, AHCI_SERIAL_NUMBER_LENGTH); /* serial number */
725fba5c64717677ac66072bae37e5b3686f3e6dvboxsync p[20] = RT_H2LE_U16(3); /* XXX: retired, cache type */
725fba5c64717677ac66072bae37e5b3686f3e6dvboxsync p[21] = RT_H2LE_U16(512); /* XXX: retired, cache size in sectors */
725fba5c64717677ac66072bae37e5b3686f3e6dvboxsync ataPadString((uint8_t *)(p + 23), pAhciPort->szFirmwareRevision, AHCI_FIRMWARE_REVISION_LENGTH); /* firmware version */
725fba5c64717677ac66072bae37e5b3686f3e6dvboxsync ataPadString((uint8_t *)(p + 27), pAhciPort->szModelNumber, AHCI_MODEL_NUMBER_LENGTH); /* model */
725fba5c64717677ac66072bae37e5b3686f3e6dvboxsync p[47] = RT_H2LE_U16(0x8000 | ATA_MAX_MULT_SECTORS);
e4bf6817370e1a71833a02285515694afcda7599vboxsync p[48] = RT_H2LE_U16(1); /* dword I/O, used by the BIOS */
e4bf6817370e1a71833a02285515694afcda7599vboxsync p[49] = RT_H2LE_U16(1 << 11 | 1 << 9 | 1 << 8); /* DMA and LBA supported */
c553cea6bfe2ce63ff5517ca4ec288502a890e99vboxsync p[50] = RT_H2LE_U16(1 << 14); /* No drive specific standby timer minimum */
e4bf6817370e1a71833a02285515694afcda7599vboxsync p[53] = RT_H2LE_U16(1 | 1 << 1 | 1 << 2); /* words 54-58,64-70,88 valid */
e4bf6817370e1a71833a02285515694afcda7599vboxsync p[54] = RT_H2LE_U16(RT_MIN(pAhciPort->PCHSGeometry.cCylinders, 16383));
e4bf6817370e1a71833a02285515694afcda7599vboxsync p[55] = RT_H2LE_U16(pAhciPort->PCHSGeometry.cHeads);
e4bf6817370e1a71833a02285515694afcda7599vboxsync p[56] = RT_H2LE_U16(pAhciPort->PCHSGeometry.cSectors);
e4bf6817370e1a71833a02285515694afcda7599vboxsync p[57] = RT_H2LE_U16(RT_MIN(pAhciPort->PCHSGeometry.cCylinders, 16383) * pAhciPort->PCHSGeometry.cHeads * pAhciPort->PCHSGeometry.cSectors);
e4bf6817370e1a71833a02285515694afcda7599vboxsync p[58] = RT_H2LE_U16(RT_MIN(pAhciPort->PCHSGeometry.cCylinders, 16383) * pAhciPort->PCHSGeometry.cHeads * pAhciPort->PCHSGeometry.cSectors >> 16);
e4bf6817370e1a71833a02285515694afcda7599vboxsync p[59] = RT_H2LE_U16(0x100 | pAhciPort->cMultSectors);
113a43aca041000560f93f9a8ee23dfcf01a9e7cvboxsync p[61] = RT_H2LE_U16(pAhciPort->cTotalSectors >> 16);
e4bf6817370e1a71833a02285515694afcda7599vboxsync /* Report maximum number of sectors possible with LBA28 */
e4bf6817370e1a71833a02285515694afcda7599vboxsync p[63] = RT_H2LE_U16(ATA_TRANSFER_ID(ATA_MODE_MDMA, ATA_MDMA_MODE_MAX, pAhciPort->uATATransferMode)); /* MDMA modes supported / mode enabled */
e4bf6817370e1a71833a02285515694afcda7599vboxsync p[64] = RT_H2LE_U16(ATA_PIO_MODE_MAX > 2 ? (1 << (ATA_PIO_MODE_MAX - 2)) - 1 : 0); /* PIO modes beyond PIO2 supported */
e4bf6817370e1a71833a02285515694afcda7599vboxsync p[65] = RT_H2LE_U16(120); /* minimum DMA multiword tx cycle time */
e4bf6817370e1a71833a02285515694afcda7599vboxsync p[66] = RT_H2LE_U16(120); /* recommended DMA multiword tx cycle time */
e4bf6817370e1a71833a02285515694afcda7599vboxsync p[67] = RT_H2LE_U16(120); /* minimum PIO cycle time without flow control */
113a43aca041000560f93f9a8ee23dfcf01a9e7cvboxsync p[68] = RT_H2LE_U16(120); /* minimum PIO cycle time with IORDY flow control */
e4bf6817370e1a71833a02285515694afcda7599vboxsync p[80] = RT_H2LE_U16(0x1f0); /* support everything up to ATA/ATAPI-8 ACS */
c553cea6bfe2ce63ff5517ca4ec288502a890e99vboxsync p[81] = RT_H2LE_U16(0x28); /* conforms to ATA/ATAPI-8 ACS */
e4bf6817370e1a71833a02285515694afcda7599vboxsync p[80] = RT_H2LE_U16(0x7e); /* support everything up to ATA/ATAPI-6 */
e4bf6817370e1a71833a02285515694afcda7599vboxsync p[81] = RT_H2LE_U16(0x22); /* conforms to ATA/ATAPI-6 */
c553cea6bfe2ce63ff5517ca4ec288502a890e99vboxsync p[82] = RT_H2LE_U16(1 << 3 | 1 << 5 | 1 << 6); /* supports power management, write cache and look-ahead */
e4bf6817370e1a71833a02285515694afcda7599vboxsync p[83] = RT_H2LE_U16(1 << 14 | 1 << 10 | 1 << 12 | 1 << 13); /* supports LBA48, FLUSH CACHE and FLUSH CACHE EXT */
e4bf6817370e1a71833a02285515694afcda7599vboxsync p[85] = RT_H2LE_U16(1 << 3 | 1 << 5 | 1 << 6); /* enabled power management, write cache and look-ahead */
e4bf6817370e1a71833a02285515694afcda7599vboxsync p[86] = RT_H2LE_U16(1 << 10 | 1 << 12 | 1 << 13); /* enabled LBA48, FLUSH CACHE and FLUSH CACHE EXT */
e4bf6817370e1a71833a02285515694afcda7599vboxsync p[88] = RT_H2LE_U16(ATA_TRANSFER_ID(ATA_MODE_UDMA, ATA_UDMA_MODE_MAX, pAhciPort->uATATransferMode)); /* UDMA modes supported / mode enabled */
c553cea6bfe2ce63ff5517ca4ec288502a890e99vboxsync p[101] = RT_H2LE_U16(pAhciPort->cTotalSectors >> 16);
e4bf6817370e1a71833a02285515694afcda7599vboxsync p[102] = RT_H2LE_U16(pAhciPort->cTotalSectors >> 32);
e4bf6817370e1a71833a02285515694afcda7599vboxsync p[103] = RT_H2LE_U16(pAhciPort->cTotalSectors >> 48);
e4bf6817370e1a71833a02285515694afcda7599vboxsync /* valid information, more than one logical sector per physical sector, 2^cLogSectorsPerPhysicalExp logical sectors per physical sector */
e4bf6817370e1a71833a02285515694afcda7599vboxsync p[106] = RT_H2LE_U16(RT_BIT(14) | RT_BIT(13) | pAhciPort->cLogSectorsPerPhysicalExp);
725fba5c64717677ac66072bae37e5b3686f3e6dvboxsync uint32_t cSectorSizeInWords = pAhciPort->cbSector / sizeof(uint16_t);
725fba5c64717677ac66072bae37e5b3686f3e6dvboxsync /* Enable reporting of logical sector size. */
725fba5c64717677ac66072bae37e5b3686f3e6dvboxsync p[217] = RT_H2LE_U16(1); /* Non-rotational medium */
e4bf6817370e1a71833a02285515694afcda7599vboxsync && pAhciPort->pDrvBlockAsync->pfnStartDiscard)) /** @todo: Set bit 14 in word 69 too? (Deterministic read after TRIM). */
725fba5c64717677ac66072bae37e5b3686f3e6dvboxsync p[169] = RT_H2LE_U16(1); /* DATA SET MANAGEMENT command supported. */
725fba5c64717677ac66072bae37e5b3686f3e6dvboxsync /* The following are SATA specific */
c553cea6bfe2ce63ff5517ca4ec288502a890e99vboxsync p[75] = RT_H2LE_U16(pAhciPort->CTX_SUFF(pAhci)->cCmdSlotsAvail-1); /* Number of commands we support, 0's based */
113a43aca041000560f93f9a8ee23dfcf01a9e7cvboxsync p[76] = RT_H2LE_U16((1 << 8) | (1 << 2)); /* Native command queuing and Serial ATA Gen2 (3.0 Gbps) speed supported */
c553cea6bfe2ce63ff5517ca4ec288502a890e99vboxsync p[255] = RT_H2LE_U16(0xa5 | (uCsum << 8)); /* Integrity word */
c553cea6bfe2ce63ff5517ca4ec288502a890e99vboxsynctypedef int (*PAtapiFunc)(PAHCIREQ, PAHCIPort, size_t, size_t *);
3bb3e26b3306b9f62b18c17380bdf2ca3a98ca49vboxsyncstatic int atapiGetConfigurationSS(PAHCIREQ, PAHCIPort, size_t, size_t *);
4e47bb772df0d04d1ded3e06354de547d52e2d06vboxsyncstatic int atapiGetEventStatusNotificationSS(PAHCIREQ, PAHCIPort, size_t, size_t *);
e4bf6817370e1a71833a02285515694afcda7599vboxsyncstatic int atapiIdentifySS(PAHCIREQ, PAHCIPort, size_t, size_t *);
e4bf6817370e1a71833a02285515694afcda7599vboxsyncstatic int atapiInquirySS(PAHCIREQ, PAHCIPort, size_t, size_t *);
e4bf6817370e1a71833a02285515694afcda7599vboxsyncstatic int atapiMechanismStatusSS(PAHCIREQ, PAHCIPort, size_t, size_t *);
e4bf6817370e1a71833a02285515694afcda7599vboxsyncstatic int atapiModeSenseErrorRecoverySS(PAHCIREQ, PAHCIPort, size_t, size_t *);
e4bf6817370e1a71833a02285515694afcda7599vboxsyncstatic int atapiModeSenseCDStatusSS(PAHCIREQ, PAHCIPort, size_t, size_t *);
e4bf6817370e1a71833a02285515694afcda7599vboxsyncstatic int atapiReadCapacitySS(PAHCIREQ, PAHCIPort, size_t, size_t *);
e4bf6817370e1a71833a02285515694afcda7599vboxsyncstatic int atapiReadDiscInformationSS(PAHCIREQ, PAHCIPort, size_t, size_t *);
e4bf6817370e1a71833a02285515694afcda7599vboxsyncstatic int atapiReadTOCNormalSS(PAHCIREQ, PAHCIPort, size_t, size_t *);
e4bf6817370e1a71833a02285515694afcda7599vboxsyncstatic int atapiReadTOCMultiSS(PAHCIREQ, PAHCIPort, size_t, size_t *);
e4bf6817370e1a71833a02285515694afcda7599vboxsyncstatic int atapiReadTOCRawSS(PAHCIREQ, PAHCIPort, size_t, size_t *);
e4bf6817370e1a71833a02285515694afcda7599vboxsyncstatic int atapiReadTrackInformationSS(PAHCIREQ, PAHCIPort, size_t, size_t *);
e4bf6817370e1a71833a02285515694afcda7599vboxsyncstatic int atapiRequestSenseSS(PAHCIREQ, PAHCIPort, size_t, size_t *);
e4bf6817370e1a71833a02285515694afcda7599vboxsyncstatic int atapiPassthroughSS(PAHCIREQ, PAHCIPort, size_t, size_t *);
e4bf6817370e1a71833a02285515694afcda7599vboxsyncstatic int atapiReadDVDStructureSS(PAHCIREQ, PAHCIPort, size_t, size_t *);
e4bf6817370e1a71833a02285515694afcda7599vboxsync * Source/sink function indexes for g_apfnAtapiFuncs.
c553cea6bfe2ce63ff5517ca4ec288502a890e99vboxsync * Array of source/sink functions, the index is ATAFNSS.
c553cea6bfe2ce63ff5517ca4ec288502a890e99vboxsync * Make sure ATAFNSS and this array match!
c553cea6bfe2ce63ff5517ca4ec288502a890e99vboxsyncstatic const PAtapiFunc g_apfnAtapiFuncs[ATAFN_SS_MAX] =
e4bf6817370e1a71833a02285515694afcda7599vboxsyncstatic int atapiIdentifySS(PAHCIREQ pAhciReq, PAHCIPort pAhciPort, size_t cbData, size_t *pcbData)
e4bf6817370e1a71833a02285515694afcda7599vboxsync /* Removable CDROM, 50us response, 12 byte packets */
e4bf6817370e1a71833a02285515694afcda7599vboxsync p[0] = RT_H2LE_U16(2 << 14 | 5 << 8 | 1 << 7 | 2 << 5 | 0 << 0);
e4bf6817370e1a71833a02285515694afcda7599vboxsync ataPadString((uint8_t *)(p + 10), pAhciPort->szSerialNumber, AHCI_SERIAL_NUMBER_LENGTH); /* serial number */
e4bf6817370e1a71833a02285515694afcda7599vboxsync p[20] = RT_H2LE_U16(3); /* XXX: retired, cache type */
e4bf6817370e1a71833a02285515694afcda7599vboxsync p[21] = RT_H2LE_U16(512); /* XXX: retired, cache size in sectors */
e4bf6817370e1a71833a02285515694afcda7599vboxsync ataPadString((uint8_t *)(p + 23), pAhciPort->szFirmwareRevision, AHCI_FIRMWARE_REVISION_LENGTH); /* firmware version */
e4bf6817370e1a71833a02285515694afcda7599vboxsync ataPadString((uint8_t *)(p + 27), pAhciPort->szModelNumber, AHCI_MODEL_NUMBER_LENGTH); /* model */
e4bf6817370e1a71833a02285515694afcda7599vboxsync p[49] = RT_H2LE_U16(1 << 11 | 1 << 9 | 1 << 8); /* DMA and LBA supported */
e4bf6817370e1a71833a02285515694afcda7599vboxsync p[50] = RT_H2LE_U16(1 << 14); /* No drive specific standby timer minimum */
e4bf6817370e1a71833a02285515694afcda7599vboxsync p[53] = RT_H2LE_U16(1 << 1 | 1 << 2); /* words 64-70,88 are valid */
725fba5c64717677ac66072bae37e5b3686f3e6dvboxsync p[63] = RT_H2LE_U16(ATA_TRANSFER_ID(ATA_MODE_MDMA, ATA_MDMA_MODE_MAX, pAhciPort->uATATransferMode)); /* MDMA modes supported / mode enabled */
725fba5c64717677ac66072bae37e5b3686f3e6dvboxsync p[64] = RT_H2LE_U16(ATA_PIO_MODE_MAX > 2 ? (1 << (ATA_PIO_MODE_MAX - 2)) - 1 : 0); /* PIO modes beyond PIO2 supported */
e4bf6817370e1a71833a02285515694afcda7599vboxsync p[65] = RT_H2LE_U16(120); /* minimum DMA multiword tx cycle time */
725fba5c64717677ac66072bae37e5b3686f3e6dvboxsync p[66] = RT_H2LE_U16(120); /* recommended DMA multiword tx cycle time */
e4bf6817370e1a71833a02285515694afcda7599vboxsync p[67] = RT_H2LE_U16(120); /* minimum PIO cycle time without flow control */
e4bf6817370e1a71833a02285515694afcda7599vboxsync p[68] = RT_H2LE_U16(120); /* minimum PIO cycle time with IORDY flow control */
e4bf6817370e1a71833a02285515694afcda7599vboxsync p[73] = RT_H2LE_U16(0x003e); /* ATAPI CDROM major */
e4bf6817370e1a71833a02285515694afcda7599vboxsync p[80] = RT_H2LE_U16(0x7e); /* support everything up to ATA/ATAPI-6 */
725fba5c64717677ac66072bae37e5b3686f3e6dvboxsync p[81] = RT_H2LE_U16(0x22); /* conforms to ATA/ATAPI-6 */
725fba5c64717677ac66072bae37e5b3686f3e6dvboxsync p[82] = RT_H2LE_U16(1 << 4 | 1 << 9); /* supports packet command set and DEVICE RESET */
e4bf6817370e1a71833a02285515694afcda7599vboxsync p[85] = RT_H2LE_U16(1 << 4 | 1 << 9); /* enabled packet command set and DEVICE RESET */
e4bf6817370e1a71833a02285515694afcda7599vboxsync p[88] = RT_H2LE_U16(ATA_TRANSFER_ID(ATA_MODE_UDMA, ATA_UDMA_MODE_MAX, pAhciPort->uATATransferMode)); /* UDMA modes supported / mode enabled */
e4bf6817370e1a71833a02285515694afcda7599vboxsync p[93] = RT_H2LE_U16((1 | 1 << 1) << ((pAhciPort->iLUN & 1) == 0 ? 0 : 8) | 1 << 13 | 1 << 14);
e4bf6817370e1a71833a02285515694afcda7599vboxsync /* The following are SATA specific */
e4bf6817370e1a71833a02285515694afcda7599vboxsync p[75] = RT_H2LE_U16(31); /* We support 32 commands */
e4bf6817370e1a71833a02285515694afcda7599vboxsync p[76] = RT_H2LE_U16((1 << 8) | (1 << 2)); /* Native command queuing and Serial ATA Gen2 (3.0 Gbps) speed supported */
113a43aca041000560f93f9a8ee23dfcf01a9e7cvboxsync /* Copy the buffer in to the scatter gather list. */
e4bf6817370e1a71833a02285515694afcda7599vboxsync *pcbData = ahciCopyToPrdtl(pAhciPort->pDevInsR3, pAhciReq, (void *)&p[0],
c553cea6bfe2ce63ff5517ca4ec288502a890e99vboxsyncstatic int atapiReadCapacitySS(PAHCIREQ pAhciReq, PAHCIPort pAhciPort, size_t cbData, size_t *pcbData)
725fba5c64717677ac66072bae37e5b3686f3e6dvboxsync /* Copy the buffer in to the scatter gather list. */
725fba5c64717677ac66072bae37e5b3686f3e6dvboxsync *pcbData = ahciCopyToPrdtl(pAhciPort->pDevInsR3, pAhciReq, (void *)&aBuf[0],
e4bf6817370e1a71833a02285515694afcda7599vboxsyncstatic int atapiReadDiscInformationSS(PAHCIREQ pAhciReq, PAHCIPort pAhciPort, size_t cbData, size_t *pcbData)
e4bf6817370e1a71833a02285515694afcda7599vboxsync aBuf[2] = (0 << 4) | (3 << 2) | (2 << 0); /* not erasable, complete session, complete disc */
e4bf6817370e1a71833a02285515694afcda7599vboxsync aBuf[5] = 1; /* first track number in last session (LSB) */
113a43aca041000560f93f9a8ee23dfcf01a9e7cvboxsync aBuf[6] = 1; /* last track number in last session (LSB) */
113a43aca041000560f93f9a8ee23dfcf01a9e7cvboxsync aBuf[7] = (0 << 7) | (0 << 6) | (1 << 5) | (0 << 2) | (0 << 0); /* disc id not valid, disc bar code not valid, unrestricted use, not dirty, not RW medium */
113a43aca041000560f93f9a8ee23dfcf01a9e7cvboxsync ataH2BE_U32(aBuf + 16, 0x00ffffff); /* last session lead-in start time is not available */
113a43aca041000560f93f9a8ee23dfcf01a9e7cvboxsync ataH2BE_U32(aBuf + 20, 0x00ffffff); /* last possible start time for lead-out is not available */
c553cea6bfe2ce63ff5517ca4ec288502a890e99vboxsync /* Copy the buffer in to the scatter gather list. */
e4bf6817370e1a71833a02285515694afcda7599vboxsync *pcbData = ahciCopyToPrdtl(pAhciPort->pDevInsR3, pAhciReq, (void *)&aBuf[0],
e4bf6817370e1a71833a02285515694afcda7599vboxsyncstatic int atapiReadTrackInformationSS(PAHCIREQ pAhciReq, PAHCIPort pAhciPort, size_t cbData, size_t *pcbData)
1025ef7261a6961d07d390e85a095d806ccb88d9vboxsync /* Accept address/number type of 1 only, and only track 1 exists. */
e4bf6817370e1a71833a02285515694afcda7599vboxsync if ((pAhciReq->aATAPICmd[1] & 0x03) != 1 || ataBE2H_U32(&pAhciReq->aATAPICmd[2]) != 1)
1025ef7261a6961d07d390e85a095d806ccb88d9vboxsync atapiCmdErrorSimple(pAhciPort, pAhciReq, SCSI_SENSE_ILLEGAL_REQUEST, SCSI_ASC_INV_FIELD_IN_CMD_PACKET);
e4bf6817370e1a71833a02285515694afcda7599vboxsync aBuf[5] = (0 << 5) | (0 << 4) | (4 << 0); /* not damaged, primary copy, data track */
e4bf6817370e1a71833a02285515694afcda7599vboxsync aBuf[6] = (0 << 7) | (0 << 6) | (0 << 5) | (0 << 6) | (1 << 0); /* not reserved track, not blank, not packet writing, not fixed packet, data mode 1 */
113a43aca041000560f93f9a8ee23dfcf01a9e7cvboxsync aBuf[7] = (0 << 1) | (0 << 0); /* last recorded address not valid, next recordable address not valid */
e4bf6817370e1a71833a02285515694afcda7599vboxsync ataH2BE_U32(aBuf + 8, 0); /* track start address is 0 */
e4bf6817370e1a71833a02285515694afcda7599vboxsync ataH2BE_U32(aBuf + 24, pAhciPort->cTotalSectors); /* track size */
1025ef7261a6961d07d390e85a095d806ccb88d9vboxsync /* Copy the buffer in to the scatter gather list. */
113a43aca041000560f93f9a8ee23dfcf01a9e7cvboxsync *pcbData = ahciCopyToPrdtl(pAhciPort->pDevInsR3, pAhciReq, (void *)&aBuf[0],
e4bf6817370e1a71833a02285515694afcda7599vboxsyncstatic size_t atapiGetConfigurationFillFeatureListProfiles(PAHCIPort pAhciPort, uint8_t *pbBuf, size_t cbBuf)
e4bf6817370e1a71833a02285515694afcda7599vboxsync ataH2BE_U16(pbBuf, 0x0); /* feature 0: list of profiles supported */
1025ef7261a6961d07d390e85a095d806ccb88d9vboxsync pbBuf[2] = (0 << 2) | (1 << 1) | (1 || 0); /* version 0, persistent, current */
e4bf6817370e1a71833a02285515694afcda7599vboxsync /* The MMC-3 spec says that DVD-ROM read capability should be reported
e4bf6817370e1a71833a02285515694afcda7599vboxsync * before CD-ROM read capability. */
e4bf6817370e1a71833a02285515694afcda7599vboxsync ataH2BE_U16(pbBuf + 4, 0x10); /* profile: read-only DVD */
e4bf6817370e1a71833a02285515694afcda7599vboxsync ataH2BE_U16(pbBuf + 8, 0x08); /* profile: read only CD */
e4bf6817370e1a71833a02285515694afcda7599vboxsyncstatic size_t atapiGetConfigurationFillFeatureCore(PAHCIPort pAhciPort, uint8_t *pbBuf, size_t cbBuf)
3bb3e26b3306b9f62b18c17380bdf2ca3a98ca49vboxsync ataH2BE_U16(pbBuf, 0x1); /* feature 0001h: Core Feature */
3bb3e26b3306b9f62b18c17380bdf2ca3a98ca49vboxsync pbBuf[2] = (0x2 << 2) | RT_BIT(1) | RT_BIT(0); /* Version | Persistent | Current */
3bb3e26b3306b9f62b18c17380bdf2ca3a98ca49vboxsync ataH2BE_U16(pbBuf + 4, 0x00000002); /* Physical interface ATAPI. */
e4bf6817370e1a71833a02285515694afcda7599vboxsync /* Rest is reserved. */
3bb3e26b3306b9f62b18c17380bdf2ca3a98ca49vboxsyncstatic size_t atapiGetConfigurationFillFeatureMorphing(PAHCIPort pAhciPort, uint8_t *pbBuf, size_t cbBuf)
e4bf6817370e1a71833a02285515694afcda7599vboxsync ataH2BE_U16(pbBuf, 0x2); /* feature 0002h: Morphing Feature */
e4bf6817370e1a71833a02285515694afcda7599vboxsync pbBuf[2] = (0x1 << 2) | RT_BIT(1) | RT_BIT(0); /* Version | Persistent | Current */
3bb3e26b3306b9f62b18c17380bdf2ca3a98ca49vboxsync /* Rest is reserved. */
e4bf6817370e1a71833a02285515694afcda7599vboxsyncstatic size_t atapiGetConfigurationFillFeatureRemovableMedium(PAHCIPort pAhciPort, uint8_t *pbBuf, size_t cbBuf)
e4bf6817370e1a71833a02285515694afcda7599vboxsync ataH2BE_U16(pbBuf, 0x3); /* feature 0003h: Removable Medium Feature */
3bb3e26b3306b9f62b18c17380bdf2ca3a98ca49vboxsync pbBuf[2] = (0x2 << 2) | RT_BIT(1) | RT_BIT(0); /* Version | Persistent | Current */
e4bf6817370e1a71833a02285515694afcda7599vboxsync /* Tray type loading | Load | Eject | !Pvnt Jmpr | !DBML | Lock */
e4bf6817370e1a71833a02285515694afcda7599vboxsync pbBuf[4] = (0x2 << 5) | RT_BIT(4) | RT_BIT(3) | (0x0 << 2) | (0x0 << 1) | RT_BIT(0);
e4bf6817370e1a71833a02285515694afcda7599vboxsync /* Rest is reserved. */
e4bf6817370e1a71833a02285515694afcda7599vboxsyncstatic size_t atapiGetConfigurationFillFeatureRandomReadable(PAHCIPort pAhciPort, uint8_t *pbBuf, size_t cbBuf)
113a43aca041000560f93f9a8ee23dfcf01a9e7cvboxsync ataH2BE_U16(pbBuf, 0x10); /* feature 0010h: Random Readable Feature */
113a43aca041000560f93f9a8ee23dfcf01a9e7cvboxsync pbBuf[2] = (0x0 << 2) | RT_BIT(1) | RT_BIT(0); /* Version | Persistent | Current */
113a43aca041000560f93f9a8ee23dfcf01a9e7cvboxsync ataH2BE_U32(pbBuf + 4, 2048); /* Logical block size. */
113a43aca041000560f93f9a8ee23dfcf01a9e7cvboxsync ataH2BE_U16(pbBuf + 8, 0x10); /* Blocking (0x10 for DVD, CD is not defined). */
113a43aca041000560f93f9a8ee23dfcf01a9e7cvboxsync /* Rest is reserved. */
113a43aca041000560f93f9a8ee23dfcf01a9e7cvboxsyncstatic size_t atapiGetConfigurationFillFeatureCDRead(PAHCIPort pAhciPort, uint8_t *pbBuf, size_t cbBuf)
113a43aca041000560f93f9a8ee23dfcf01a9e7cvboxsync ataH2BE_U16(pbBuf, 0x1e); /* feature 001Eh: CD Read Feature */
113a43aca041000560f93f9a8ee23dfcf01a9e7cvboxsync pbBuf[2] = (0x2 << 2) | RT_BIT(1) | RT_BIT(0); /* Version | Persistent | Current */
113a43aca041000560f93f9a8ee23dfcf01a9e7cvboxsync pbBuf[4] = (0x0 << 7) | (0x0 << 1) | 0x0; /* !DAP | !C2-Flags | !CD-Text. */
113a43aca041000560f93f9a8ee23dfcf01a9e7cvboxsync /* Rest is reserved. */
113a43aca041000560f93f9a8ee23dfcf01a9e7cvboxsyncstatic size_t atapiGetConfigurationFillFeaturePowerManagement(PAHCIPort pAhciPort, uint8_t *pbBuf, size_t cbBuf)
113a43aca041000560f93f9a8ee23dfcf01a9e7cvboxsync ataH2BE_U16(pbBuf, 0x100); /* feature 0100h: Power Management Feature */
113a43aca041000560f93f9a8ee23dfcf01a9e7cvboxsync pbBuf[2] = (0x0 << 2) | RT_BIT(1) | RT_BIT(0); /* Version | Persistent | Current */
113a43aca041000560f93f9a8ee23dfcf01a9e7cvboxsyncstatic size_t atapiGetConfigurationFillFeatureTimeout(PAHCIPort pAhciPort, uint8_t *pbBuf, size_t cbBuf)
113a43aca041000560f93f9a8ee23dfcf01a9e7cvboxsync ataH2BE_U16(pbBuf, 0x105); /* feature 0105h: Timeout Feature */
113a43aca041000560f93f9a8ee23dfcf01a9e7cvboxsync pbBuf[2] = (0x0 << 2) | RT_BIT(1) | RT_BIT(0); /* Version | Persistent | Current */
113a43aca041000560f93f9a8ee23dfcf01a9e7cvboxsyncstatic int atapiGetConfigurationSS(PAHCIREQ pAhciReq, PAHCIPort pAhciPort, size_t cbData, size_t *pcbData)
113a43aca041000560f93f9a8ee23dfcf01a9e7cvboxsync /* Accept valid request types only, and only starting feature 0. */
113a43aca041000560f93f9a8ee23dfcf01a9e7cvboxsync if ((pAhciReq->aATAPICmd[1] & 0x03) == 3 || ataBE2H_U16(&pAhciReq->aATAPICmd[2]) != 0)
113a43aca041000560f93f9a8ee23dfcf01a9e7cvboxsync atapiCmdErrorSimple(pAhciPort, pAhciReq, SCSI_SENSE_ILLEGAL_REQUEST, SCSI_ASC_INV_FIELD_IN_CMD_PACKET);
113a43aca041000560f93f9a8ee23dfcf01a9e7cvboxsync /** @todo implement switching between CD-ROM and DVD-ROM profile (the only
113a43aca041000560f93f9a8ee23dfcf01a9e7cvboxsync * way to differentiate them right now is based on the image size). */
113a43aca041000560f93f9a8ee23dfcf01a9e7cvboxsync ataH2BE_U16(pbBuf + 6, 0x08); /* current profile: read-only CD */
113a43aca041000560f93f9a8ee23dfcf01a9e7cvboxsync ataH2BE_U16(pbBuf + 6, 0x00); /* current profile: none -> no media */
113a43aca041000560f93f9a8ee23dfcf01a9e7cvboxsync cbCopied = atapiGetConfigurationFillFeatureListProfiles(pAhciPort, pbBuf, cbBuf);
113a43aca041000560f93f9a8ee23dfcf01a9e7cvboxsync cbCopied = atapiGetConfigurationFillFeatureCore(pAhciPort, pbBuf, cbBuf);
113a43aca041000560f93f9a8ee23dfcf01a9e7cvboxsync cbCopied = atapiGetConfigurationFillFeatureMorphing(pAhciPort, pbBuf, cbBuf);
113a43aca041000560f93f9a8ee23dfcf01a9e7cvboxsync cbCopied = atapiGetConfigurationFillFeatureRemovableMedium(pAhciPort, pbBuf, cbBuf);
113a43aca041000560f93f9a8ee23dfcf01a9e7cvboxsync cbCopied = atapiGetConfigurationFillFeatureRandomReadable(pAhciPort, pbBuf, cbBuf);
113a43aca041000560f93f9a8ee23dfcf01a9e7cvboxsync cbCopied = atapiGetConfigurationFillFeatureCDRead(pAhciPort, pbBuf, cbBuf);
113a43aca041000560f93f9a8ee23dfcf01a9e7cvboxsync cbCopied = atapiGetConfigurationFillFeaturePowerManagement(pAhciPort, pbBuf, cbBuf);
113a43aca041000560f93f9a8ee23dfcf01a9e7cvboxsync cbCopied = atapiGetConfigurationFillFeatureTimeout(pAhciPort, pbBuf, cbBuf);
113a43aca041000560f93f9a8ee23dfcf01a9e7cvboxsync /* Set data length now. */
113a43aca041000560f93f9a8ee23dfcf01a9e7cvboxsync /* Copy the buffer in to the scatter gather list. */
113a43aca041000560f93f9a8ee23dfcf01a9e7cvboxsync *pcbData = ahciCopyToPrdtl(pAhciPort->pDevInsR3, pAhciReq, (void *)&aBuf[0],
113a43aca041000560f93f9a8ee23dfcf01a9e7cvboxsyncstatic int atapiGetEventStatusNotificationSS(PAHCIREQ pAhciReq, PAHCIPort pAhciPort, size_t cbData, size_t *pcbData)
113a43aca041000560f93f9a8ee23dfcf01a9e7cvboxsync /* no asynchronous operation supported */
113a43aca041000560f93f9a8ee23dfcf01a9e7cvboxsync atapiCmdErrorSimple(pAhciPort, pAhciReq, SCSI_SENSE_ILLEGAL_REQUEST, SCSI_ASC_INV_FIELD_IN_CMD_PACKET);
113a43aca041000560f93f9a8ee23dfcf01a9e7cvboxsync OldStatus = ASMAtomicReadU32(&pAhciPort->MediaEventStatus);
113a43aca041000560f93f9a8ee23dfcf01a9e7cvboxsync /* mount */
113a43aca041000560f93f9a8ee23dfcf01a9e7cvboxsync abBuf[3] = 0x5e; /* supported = busy|media|external|power|operational */
113a43aca041000560f93f9a8ee23dfcf01a9e7cvboxsync abBuf[5] = 0x02; /* medium present / door closed */
113a43aca041000560f93f9a8ee23dfcf01a9e7cvboxsync /* umount */
113a43aca041000560f93f9a8ee23dfcf01a9e7cvboxsync abBuf[3] = 0x5e; /* supported = busy|media|external|power|operational */
113a43aca041000560f93f9a8ee23dfcf01a9e7cvboxsync case ATA_EVENT_STATUS_MEDIA_EJECT_REQUESTED: /* currently unused */
113a43aca041000560f93f9a8ee23dfcf01a9e7cvboxsync abBuf[3] = 0x5e; /* supported = busy|media|external|power|operational */
113a43aca041000560f93f9a8ee23dfcf01a9e7cvboxsync abBuf[4] = 0x01; /* eject requested (eject button pressed) */
113a43aca041000560f93f9a8ee23dfcf01a9e7cvboxsync abBuf[5] = 0x02; /* medium present / door closed */
113a43aca041000560f93f9a8ee23dfcf01a9e7cvboxsync abBuf[2] = 0x01; /* operational change request / notification */
113a43aca041000560f93f9a8ee23dfcf01a9e7cvboxsync abBuf[3] = 0x5e; /* supported = busy|media|external|power|operational */
113a43aca041000560f93f9a8ee23dfcf01a9e7cvboxsync } while (!ASMAtomicCmpXchgU32(&pAhciPort->MediaEventStatus, NewStatus, OldStatus));
113a43aca041000560f93f9a8ee23dfcf01a9e7cvboxsync *pcbData = ahciCopyToPrdtl(pAhciPort->pDevInsR3, pAhciReq, (void *)&abBuf[0],
113a43aca041000560f93f9a8ee23dfcf01a9e7cvboxsyncstatic int atapiInquirySS(PAHCIREQ pAhciReq, PAHCIPort pAhciPort, size_t cbData, size_t *pcbData)
113a43aca041000560f93f9a8ee23dfcf01a9e7cvboxsync ataSCSIPadStr(aBuf + 8, pAhciPort->szInquiryVendorId, 8);
113a43aca041000560f93f9a8ee23dfcf01a9e7cvboxsync ataSCSIPadStr(aBuf + 16, pAhciPort->szInquiryProductId, 16);
113a43aca041000560f93f9a8ee23dfcf01a9e7cvboxsync ataSCSIPadStr(aBuf + 32, pAhciPort->szInquiryRevision, 4);
113a43aca041000560f93f9a8ee23dfcf01a9e7cvboxsync /* Copy the buffer in to the scatter gather list. */
113a43aca041000560f93f9a8ee23dfcf01a9e7cvboxsync *pcbData = ahciCopyToPrdtl(pAhciPort->pDevInsR3, pAhciReq, (void *)&aBuf[0],
113a43aca041000560f93f9a8ee23dfcf01a9e7cvboxsyncstatic int atapiModeSenseErrorRecoverySS(PAHCIREQ pAhciReq, PAHCIPort pAhciPort, size_t cbData, size_t *pcbData)
4b8c66482cbc69a01ac399b8588b8bc80b310523vboxsync /* Copy the buffer in to the scatter gather list. */
4b8c66482cbc69a01ac399b8588b8bc80b310523vboxsync *pcbData = ahciCopyToPrdtl(pAhciPort->pDevInsR3, pAhciReq, (void *)&aBuf[0],
e4bf6817370e1a71833a02285515694afcda7599vboxsyncstatic int atapiModeSenseCDStatusSS(PAHCIREQ pAhciReq, PAHCIPort pAhciPort, size_t cbData, size_t *pcbData)
725fba5c64717677ac66072bae37e5b3686f3e6dvboxsync /* The following claims we support audio play. This is obviously false,
725fba5c64717677ac66072bae37e5b3686f3e6dvboxsync * but the Linux generic CDROM support makes many features depend on this
725fba5c64717677ac66072bae37e5b3686f3e6dvboxsync * capability. If it's not set, this causes many things to be disabled. */
725fba5c64717677ac66072bae37e5b3686f3e6dvboxsync aBuf[12] = 0x71; /* multisession support, mode 2 form 1/2 support, audio play */
725fba5c64717677ac66072bae37e5b3686f3e6dvboxsync aBuf[13] = 0x00; /* no subchannel reads supported */
725fba5c64717677ac66072bae37e5b3686f3e6dvboxsync aBuf[14] = (1 << 0) | (1 << 3) | (1 << 5); /* lock supported, eject supported, tray type loading mechanism */
725fba5c64717677ac66072bae37e5b3686f3e6dvboxsync if (pAhciPort->pDrvMount->pfnIsLocked(pAhciPort->pDrvMount))
725fba5c64717677ac66072bae37e5b3686f3e6dvboxsync aBuf[15] = 0; /* no subchannel reads supported, no separate audio volume control, no changer etc. */
725fba5c64717677ac66072bae37e5b3686f3e6dvboxsync ataH2BE_U16(&aBuf[16], 5632); /* (obsolete) claim 32x speed support */
725fba5c64717677ac66072bae37e5b3686f3e6dvboxsync ataH2BE_U16(&aBuf[18], 2); /* number of audio volume levels */
725fba5c64717677ac66072bae37e5b3686f3e6dvboxsync ataH2BE_U16(&aBuf[20], 128); /* buffer size supported in Kbyte - We don't have a buffer because we write directly into guest memory.
725fba5c64717677ac66072bae37e5b3686f3e6dvboxsync Just write the value DevATA is using. */
725fba5c64717677ac66072bae37e5b3686f3e6dvboxsync ataH2BE_U16(&aBuf[22], 5632); /* (obsolete) current read speed 32x */
725fba5c64717677ac66072bae37e5b3686f3e6dvboxsync aBuf[25] = 0; /* reserved for digital audio (see idx 15) */
725fba5c64717677ac66072bae37e5b3686f3e6dvboxsync ataH2BE_U16(&aBuf[26], 0); /* (obsolete) maximum write speed */
725fba5c64717677ac66072bae37e5b3686f3e6dvboxsync ataH2BE_U16(&aBuf[28], 0); /* (obsolete) current write speed */
725fba5c64717677ac66072bae37e5b3686f3e6dvboxsync ataH2BE_U16(&aBuf[30], 0); /* copy management revision supported 0=no CSS */
4b8c66482cbc69a01ac399b8588b8bc80b310523vboxsync ataH2BE_U16(&aBuf[36], 0); /* current write speed */
4b8c66482cbc69a01ac399b8588b8bc80b310523vboxsync ataH2BE_U16(&aBuf[38], 0); /* number of write speed performance descriptors */
4b8c66482cbc69a01ac399b8588b8bc80b310523vboxsync /* Copy the buffer in to the scatter gather list. */
4b8c66482cbc69a01ac399b8588b8bc80b310523vboxsync *pcbData = ahciCopyToPrdtl(pAhciPort->pDevInsR3, pAhciReq, (void *)&aBuf[0],
3bb3e26b3306b9f62b18c17380bdf2ca3a98ca49vboxsyncstatic int atapiRequestSenseSS(PAHCIREQ pAhciReq, PAHCIPort pAhciPort, size_t cbData, size_t *pcbData)
4b8c66482cbc69a01ac399b8588b8bc80b310523vboxsync /* Copy the buffer in to the scatter gather list. */
4b8c66482cbc69a01ac399b8588b8bc80b310523vboxsync *pcbData = ahciCopyToPrdtl(pAhciPort->pDevInsR3, pAhciReq,
725fba5c64717677ac66072bae37e5b3686f3e6dvboxsync pAhciPort->abATAPISense, RT_MIN(cbData, sizeof(pAhciPort->abATAPISense)));
725fba5c64717677ac66072bae37e5b3686f3e6dvboxsyncstatic int atapiMechanismStatusSS(PAHCIREQ pAhciReq, PAHCIPort pAhciPort, size_t cbData, size_t *pcbData)
4b8c66482cbc69a01ac399b8588b8bc80b310523vboxsync /* no current LBA */
4b8c66482cbc69a01ac399b8588b8bc80b310523vboxsync /* Copy the buffer in to the scatter gather list. */
4b8c66482cbc69a01ac399b8588b8bc80b310523vboxsync *pcbData = ahciCopyToPrdtl(pAhciPort->pDevInsR3, pAhciReq, (void *)&aBuf[0],
3bb3e26b3306b9f62b18c17380bdf2ca3a98ca49vboxsyncstatic int atapiReadTOCNormalSS(PAHCIREQ pAhciReq, PAHCIPort pAhciPort, size_t cbData, size_t *pcbData)
725fba5c64717677ac66072bae37e5b3686f3e6dvboxsync atapiCmdErrorSimple(pAhciPort, pAhciReq, SCSI_SENSE_ILLEGAL_REQUEST, SCSI_ASC_INV_FIELD_IN_CMD_PACKET);
725fba5c64717677ac66072bae37e5b3686f3e6dvboxsync *q++ = 0; /* reserved */
1025ef7261a6961d07d390e85a095d806ccb88d9vboxsync *q++ = 0; /* reserved */
1025ef7261a6961d07d390e85a095d806ccb88d9vboxsync *q++ = 0; /* reserved */
1025ef7261a6961d07d390e85a095d806ccb88d9vboxsync /* sector 0 */
725fba5c64717677ac66072bae37e5b3686f3e6dvboxsync /* lead out track */
725fba5c64717677ac66072bae37e5b3686f3e6dvboxsync *q++ = 0; /* reserved */
725fba5c64717677ac66072bae37e5b3686f3e6dvboxsync *q++ = 0; /* reserved */
725fba5c64717677ac66072bae37e5b3686f3e6dvboxsync *q++ = 0; /* reserved */
725fba5c64717677ac66072bae37e5b3686f3e6dvboxsync /* Copy the buffer in to the scatter gather list. */
725fba5c64717677ac66072bae37e5b3686f3e6dvboxsync *pcbData = ahciCopyToPrdtl(pAhciPort->pDevInsR3, pAhciReq, (void *)&aBuf[0],
e4bf6817370e1a71833a02285515694afcda7599vboxsyncstatic int atapiReadTOCMultiSS(PAHCIREQ pAhciReq, PAHCIPort pAhciPort, size_t cbData, size_t *pcbData)
e4bf6817370e1a71833a02285515694afcda7599vboxsync /* multi session: only a single session defined */
725fba5c64717677ac66072bae37e5b3686f3e6dvboxsync/** @todo double-check this stuff against what a real drive says for a CD-ROM (not a CD-R) with only a single data session. Maybe solve the problem with "cdrdao read-toc" not being able to figure out whether numbers are in BCD or hex. */
e4bf6817370e1a71833a02285515694afcda7599vboxsync aBuf[6] = 1; /* first track in last complete session */
e4bf6817370e1a71833a02285515694afcda7599vboxsync /* sector 0 */
725fba5c64717677ac66072bae37e5b3686f3e6dvboxsync /* Copy the buffer in to the scatter gather list. */
e4bf6817370e1a71833a02285515694afcda7599vboxsync *pcbData = ahciCopyToPrdtl(pAhciPort->pDevInsR3, pAhciReq, (void *)&aBuf[0],
1025ef7261a6961d07d390e85a095d806ccb88d9vboxsyncstatic int atapiReadTOCRawSS(PAHCIREQ pAhciReq, PAHCIPort pAhciPort, size_t cbData, size_t *pcbData)
1025ef7261a6961d07d390e85a095d806ccb88d9vboxsync uint8_t aBuf[50]; /* Counted a maximum of 45 bytes but better be on the safe side. */
1025ef7261a6961d07d390e85a095d806ccb88d9vboxsync *q++ = 0; /* track number */
1025ef7261a6961d07d390e85a095d806ccb88d9vboxsync *q++ = 0; /* min */
1025ef7261a6961d07d390e85a095d806ccb88d9vboxsync *q++ = 0; /* sec */
1025ef7261a6961d07d390e85a095d806ccb88d9vboxsync *q++ = 0; /* frame */
1025ef7261a6961d07d390e85a095d806ccb88d9vboxsync *q++ = 0; /* track number */
1025ef7261a6961d07d390e85a095d806ccb88d9vboxsync *q++ = 0; /* min */
1025ef7261a6961d07d390e85a095d806ccb88d9vboxsync *q++ = 0; /* sec */
1025ef7261a6961d07d390e85a095d806ccb88d9vboxsync *q++ = 0; /* frame */
1025ef7261a6961d07d390e85a095d806ccb88d9vboxsync *q++ = 0; /* track number */
1025ef7261a6961d07d390e85a095d806ccb88d9vboxsync *q++ = 0; /* min */
1025ef7261a6961d07d390e85a095d806ccb88d9vboxsync *q++ = 0; /* sec */
1025ef7261a6961d07d390e85a095d806ccb88d9vboxsync *q++ = 0; /* frame */
1025ef7261a6961d07d390e85a095d806ccb88d9vboxsync *q++ = 0; /* reserved */
1025ef7261a6961d07d390e85a095d806ccb88d9vboxsync *q++ = 0; /* track number */
1025ef7261a6961d07d390e85a095d806ccb88d9vboxsync *q++ = 0; /* min */
1025ef7261a6961d07d390e85a095d806ccb88d9vboxsync *q++ = 0; /* sec */
1025ef7261a6961d07d390e85a095d806ccb88d9vboxsync *q++ = 0; /* frame */
1025ef7261a6961d07d390e85a095d806ccb88d9vboxsync *q++ = 0; /* reserved */
1025ef7261a6961d07d390e85a095d806ccb88d9vboxsync /* sector 0 */
1025ef7261a6961d07d390e85a095d806ccb88d9vboxsync /* Copy the buffer in to the scatter gather list. */
1025ef7261a6961d07d390e85a095d806ccb88d9vboxsync *pcbData = ahciCopyToPrdtl(pAhciPort->pDevInsR3, pAhciReq, (void *)&aBuf[0],
1025ef7261a6961d07d390e85a095d806ccb88d9vboxsync * Sets the given media track type.
70aa086e9e9d2f85d2e997d0e69169018a001e54vboxsyncstatic uint32_t ahciMediumTypeSet(PAHCIPort pAhciPort, uint32_t MediaTrackType)
1025ef7261a6961d07d390e85a095d806ccb88d9vboxsync return ASMAtomicXchgU32(&pAhciPort->MediaTrackType, MediaTrackType);
c553cea6bfe2ce63ff5517ca4ec288502a890e99vboxsyncstatic int atapiPassthroughSS(PAHCIREQ pAhciReq, PAHCIPort pAhciPort, size_t cbData, size_t *pcbData)
725fba5c64717677ac66072bae37e5b3686f3e6dvboxsync ahciCopyFromPrdtl(pAhciPort->pDevInsR3, pAhciReq, pvBuf, cbTransfer);
725fba5c64717677ac66072bae37e5b3686f3e6dvboxsync /* Simple heuristics: if there is at least one sector of data
725fba5c64717677ac66072bae37e5b3686f3e6dvboxsync * to transfer, it's worth updating the LEDs. */
ed521f15dde29451cbdb1df104f666204e04ba65vboxsync pAhciPort->Led.Asserted.s.fReading = pAhciPort->Led.Actual.s.fReading = 1;
725fba5c64717677ac66072bae37e5b3686f3e6dvboxsync pAhciPort->Led.Asserted.s.fWriting = pAhciPort->Led.Actual.s.fWriting = 1;
1025ef7261a6961d07d390e85a095d806ccb88d9vboxsync /* Linux accepts commands with up to 100KB of data, but expects
1025ef7261a6961d07d390e85a095d806ccb88d9vboxsync * us to handle commands with up to 128KB of data. The usual
725fba5c64717677ac66072bae37e5b3686f3e6dvboxsync * imbalance of powers. */
725fba5c64717677ac66072bae37e5b3686f3e6dvboxsync uint32_t iATAPILBA, cSectors, cReqSectors, cbCurrTX;
015d66d7947b8b6a38619a0c205842f86c832fe3vboxsync cSectors = ataMSF2LBA(pAhciReq->aATAPICmd + 6) - iATAPILBA;
015d66d7947b8b6a38619a0c205842f86c832fe3vboxsync AssertMsgFailed(("Don't know how to split command %#04x\n", pAhciReq->aATAPICmd[0]));
725fba5c64717677ac66072bae37e5b3686f3e6dvboxsync LogRel(("AHCI: LUN#%d: CD-ROM passthrough split error\n", pAhciPort->iLUN));
c553cea6bfe2ce63ff5517ca4ec288502a890e99vboxsync atapiCmdErrorSimple(pAhciPort, pAhciReq, SCSI_SENSE_ILLEGAL_REQUEST, SCSI_ASC_ILLEGAL_OPCODE);
725fba5c64717677ac66072bae37e5b3686f3e6dvboxsync memcpy(aATAPICmd, pAhciReq->aATAPICmd, ATAPI_PACKET_SIZE);
725fba5c64717677ac66072bae37e5b3686f3e6dvboxsync for (uint32_t i = cSectors; i > 0; i -= cReqSectors)
725fba5c64717677ac66072bae37e5b3686f3e6dvboxsync if (i * pAhciReq->cbATAPISector > SCSI_MAX_BUFFER_SIZE)
725fba5c64717677ac66072bae37e5b3686f3e6dvboxsync cReqSectors = SCSI_MAX_BUFFER_SIZE / pAhciReq->cbATAPISector;
ad66a27959d7085aa31760f63ce082943be60e89vboxsync ataLBA2MSF(aATAPICmd + 6, iATAPILBA + cReqSectors);
ad66a27959d7085aa31760f63ce082943be60e89vboxsync rc = pAhciPort->pDrvBlock->pfnSendCmd(pAhciPort->pDrvBlock,
725fba5c64717677ac66072bae37e5b3686f3e6dvboxsync AssertMsgFailed(("Invalid transfer direction %d\n", pAhciReq->enmTxDir));
e4bf6817370e1a71833a02285515694afcda7599vboxsync rc = pAhciPort->pDrvBlock->pfnSendCmd(pAhciPort->pDrvBlock,
e4bf6817370e1a71833a02285515694afcda7599vboxsync /* Update the LEDs and the read/write statistics. */
725fba5c64717677ac66072bae37e5b3686f3e6dvboxsync STAM_REL_COUNTER_ADD(&pAhciPort->StatBytesRead, cbTransfer);
113a43aca041000560f93f9a8ee23dfcf01a9e7cvboxsync STAM_REL_COUNTER_ADD(&pAhciPort->StatBytesWritten, cbTransfer);
725fba5c64717677ac66072bae37e5b3686f3e6dvboxsync /* Do post processing for certain commands. */
113a43aca041000560f93f9a8ee23dfcf01a9e7cvboxsync rc = ATAPIPassthroughTrackListCreateEmpty(&pAhciPort->pTrackList);
113a43aca041000560f93f9a8ee23dfcf01a9e7cvboxsync rc = ATAPIPassthroughTrackListUpdate(pAhciPort->pTrackList, pAhciReq->aATAPICmd, pvBuf);
c553cea6bfe2ce63ff5517ca4ec288502a890e99vboxsync LogRel(("AHCI: Error (%Rrc) while updating the tracklist during %s, burning the disc might fail\n",
725fba5c64717677ac66072bae37e5b3686f3e6dvboxsync rc, pAhciReq->aATAPICmd[0] == SCSI_SEND_CUE_SHEET ? "SEND CUE SHEET" : "READ TOC/PMA/ATIP"));
725fba5c64717677ac66072bae37e5b3686f3e6dvboxsync ATAPIPassthroughTrackListClear(pAhciPort->pTrackList);
725fba5c64717677ac66072bae37e5b3686f3e6dvboxsync /* Make sure that the real drive cannot be identified.
c553cea6bfe2ce63ff5517ca4ec288502a890e99vboxsync * Motivation: changing the VM configuration should be as
725fba5c64717677ac66072bae37e5b3686f3e6dvboxsync * invisible as possible to the guest. */
725fba5c64717677ac66072bae37e5b3686f3e6dvboxsync ataSCSIPadStr((uint8_t *)pvBuf + 16, "CD-ROM", 16);
c553cea6bfe2ce63ff5517ca4ec288502a890e99vboxsync Log3(("ATAPI PT data read (%d): %.*Rhxs\n", cbTransfer, cbTransfer, (uint8_t *)pvBuf));
c553cea6bfe2ce63ff5517ca4ec288502a890e99vboxsync /* Reply with the same amount of data as the real drive. */
725fba5c64717677ac66072bae37e5b3686f3e6dvboxsync *pcbData = ahciCopyToPrdtl(pAhciPort->pDevInsR3, pAhciReq, pvBuf,
725fba5c64717677ac66072bae37e5b3686f3e6dvboxsync /* don't log superfluous errors */
d3dea25ec07f6546715fe3af943ea863294b392evboxsync LogRel(("PIIX3 ATA: LUN#%d: CD-ROM passthrough cmd=%#04x sense=%d ASC=%#02x ASCQ=%#02x %Rrc\n",
c553cea6bfe2ce63ff5517ca4ec288502a890e99vboxsync pAhciPort->iLUN, u8Cmd, abATAPISense[2] & 0x0f, abATAPISense[12], abATAPISense[13], rc));
d3dea25ec07f6546715fe3af943ea863294b392evboxsync } while (0);
d3dea25ec07f6546715fe3af943ea863294b392evboxsync atapiCmdError(pAhciPort, pAhciReq, abATAPISense, sizeof(abATAPISense));
ad66a27959d7085aa31760f63ce082943be60e89vboxsync/** @todo: Revise ASAP. */
ad66a27959d7085aa31760f63ce082943be60e89vboxsync/* Keep in sync with DevATA.cpp! */
ad66a27959d7085aa31760f63ce082943be60e89vboxsyncstatic int atapiReadDVDStructureSS(PAHCIREQ pAhciReq, PAHCIPort pAhciPort, size_t cbData, size_t *pcbData)
4b8c66482cbc69a01ac399b8588b8bc80b310523vboxsync uint8_t aBuf[25]; /* Counted a maximum of 20 bytes but better be on the safe side. */
ad66a27959d7085aa31760f63ce082943be60e89vboxsync uint16_t max_len = ataBE2H_U16(&pAhciReq->aATAPICmd[8]);
4bf996d915405be92dc4394b2db1395e00e14d58vboxsync buf[5] = 0xf; /* 120mm disc, minimum rate unspecified */
4bf996d915405be92dc4394b2db1395e00e14d58vboxsync buf[6] = 1; /* one layer, read-only (per MMC-2 spec) */
4bf996d915405be92dc4394b2db1395e00e14d58vboxsync /* FIXME: 0x30000 per spec? */
2d8870843ff566fee9bd3a6a5942414254106479vboxsync ataH2BE_U32(buf + 12, total_sectors - 1); /* end sector */
4bf996d915405be92dc4394b2db1395e00e14d58vboxsync ataH2BE_U32(buf + 16, total_sectors - 1); /* l0 end sector */
4bf996d915405be92dc4394b2db1395e00e14d58vboxsync /* Size of buffer, not including 2 byte size field */
4bf996d915405be92dc4394b2db1395e00e14d58vboxsync /* 2k data + 4 byte header */
4bf996d915405be92dc4394b2db1395e00e14d58vboxsync /* Size of buffer, not including 2 byte size field */
4bf996d915405be92dc4394b2db1395e00e14d58vboxsync /* 4 byte header + 4 byte data */
4bf996d915405be92dc4394b2db1395e00e14d58vboxsync case 0x03: /* BCA information - invalid field for no BCA info */
4bf996d915405be92dc4394b2db1395e00e14d58vboxsync case 0x04: /* DVD disc manufacturing information */
4bf996d915405be92dc4394b2db1395e00e14d58vboxsync /* Size of buffer, not including 2 byte size field */
4bf996d915405be92dc4394b2db1395e00e14d58vboxsync /* 2k data + 4 byte header */
4bf996d915405be92dc4394b2db1395e00e14d58vboxsync * This lists all the command capabilities above. Add new ones
4bf996d915405be92dc4394b2db1395e00e14d58vboxsync * in order and update the length and buffer return values.
4bf996d915405be92dc4394b2db1395e00e14d58vboxsync /* Size of buffer, not including 2 byte size field */
4bf996d915405be92dc4394b2db1395e00e14d58vboxsync /* data written + 4 byte header */
4bf996d915405be92dc4394b2db1395e00e14d58vboxsync default: /* TODO: formats beyond DVD-ROM requires */
4bf996d915405be92dc4394b2db1395e00e14d58vboxsync atapiCmdErrorSimple(pAhciPort, pAhciReq, SCSI_SENSE_ILLEGAL_REQUEST, -uASC);
4bf996d915405be92dc4394b2db1395e00e14d58vboxsync return false;
4bf996d915405be92dc4394b2db1395e00e14d58vboxsync /* TODO: BD support, fall through for now */
4bf996d915405be92dc4394b2db1395e00e14d58vboxsync /* Generic disk structures */
4bf996d915405be92dc4394b2db1395e00e14d58vboxsync case 0x90: /* TODO: List of recognized format layers */
4bf996d915405be92dc4394b2db1395e00e14d58vboxsync atapiCmdErrorSimple(pAhciPort, pAhciReq, SCSI_SENSE_ILLEGAL_REQUEST,
4bf996d915405be92dc4394b2db1395e00e14d58vboxsync return false;
4bf996d915405be92dc4394b2db1395e00e14d58vboxsync /* Copy the buffer into the scatter gather list. */
4bf996d915405be92dc4394b2db1395e00e14d58vboxsync *pcbData = ahciCopyToPrdtl(pAhciPort->pDevInsR3, pAhciReq, (void *)&aBuf[0],
4bf996d915405be92dc4394b2db1395e00e14d58vboxsync return false;
4bf996d915405be92dc4394b2db1395e00e14d58vboxsyncstatic int atapiDoTransfer(PAHCIPort pAhciPort, PAHCIREQ pAhciReq, size_t cbMax, ATAPIFN iSourceSink)
4bf996d915405be92dc4394b2db1395e00e14d58vboxsync rcSourceSink = g_apfnAtapiFuncs[iSourceSink](pAhciReq, pAhciPort, cbMax,
c58c758d3642ac45d3f12356c406c631fcd8f538vboxsync /* Write updated command header into memory of the guest. */
c58c758d3642ac45d3f12356c406c631fcd8f538vboxsync PDMDevHlpPCIPhysWrite(pAhciPort->CTX_SUFF(pDevIns), pAhciReq->GCPhysCmdHdrAddr, &pAhciReq->cmdHdr, sizeof(CmdHdr));
c58c758d3642ac45d3f12356c406c631fcd8f538vboxsyncstatic int atapiReadSectors2352PostProcess(PAHCIREQ pAhciReq, void **ppvProc, size_t *pcbProc)
5b0a093ca572a855886faa6747ad46df859dd041vboxsync uint8_t *pbBufSrc = (uint8_t *)pAhciReq->u.Io.DataSeg.pvSeg;
daa94352f51be2329ac8660f70396e03a7cb983bvboxsync size_t cbAlloc = pAhciReq->cbTransfer + cSectors * (1 + 11 + 3 + 1 + 288); /* Per sector data like ECC. */
5b0a093ca572a855886faa6747ad46df859dd041vboxsync for (uint32_t i = iATAPILBA; i < iATAPILBA + cSectors; i++)
5b0a093ca572a855886faa6747ad46df859dd041vboxsync /* sync bytes */
5b0a093ca572a855886faa6747ad46df859dd041vboxsyncstatic int atapiReadSectors(PAHCIPort pAhciPort, PAHCIREQ pAhciReq, uint32_t iATAPILBA, uint32_t cSectors, uint32_t cbSector)
5b0a093ca572a855886faa6747ad46df859dd041vboxsync Log(("%s: %d sectors at LBA %d\n", __FUNCTION__, cSectors, iATAPILBA));
5b0a093ca572a855886faa6747ad46df859dd041vboxsync pAhciReq->uOffset = (uint64_t)iATAPILBA * cbSector;
3bb3e26b3306b9f62b18c17380bdf2ca3a98ca49vboxsync pAhciReq->u.Io.pfnPostProcess = atapiReadSectors2352PostProcess;
c58c758d3642ac45d3f12356c406c631fcd8f538vboxsyncstatic AHCITXDIR atapiParseCmdVirtualATAPI(PAHCIPort pAhciPort, PAHCIREQ pAhciReq)
c58c758d3642ac45d3f12356c406c631fcd8f538vboxsync ahciLog(("%s: ATAPI CMD=%#04x \"%s\"\n", __FUNCTION__, pbPacket[0], SCSICmdText(pbPacket[0])));
5b0a093ca572a855886faa6747ad46df859dd041vboxsync atapiCmdErrorSimple(pAhciPort, pAhciReq, SCSI_SENSE_NOT_READY, SCSI_ASC_MEDIUM_NOT_PRESENT);
5b0a093ca572a855886faa6747ad46df859dd041vboxsync atapiCmdErrorSimple(pAhciPort, pAhciReq, SCSI_SENSE_UNIT_ATTENTION, SCSI_ASC_MEDIUM_MAY_HAVE_CHANGED); /* media changed */
5b0a093ca572a855886faa6747ad46df859dd041vboxsync else if (pAhciPort->pDrvMount->pfnIsMounted(pAhciPort->pDrvMount))
5b0a093ca572a855886faa6747ad46df859dd041vboxsync atapiCmdErrorSimple(pAhciPort, pAhciReq, SCSI_SENSE_NOT_READY, SCSI_ASC_MEDIUM_NOT_PRESENT);
4b8c66482cbc69a01ac399b8588b8bc80b310523vboxsync atapiDoTransfer(pAhciPort, pAhciReq, cbMax, ATAFN_SS_ATAPI_GET_EVENT_STATUS_NOTIFICATION);
5b0a093ca572a855886faa6747ad46df859dd041vboxsync atapiDoTransfer(pAhciPort, pAhciReq, cbMax, ATAFN_SS_ATAPI_MODE_SENSE_ERROR_RECOVERY);
ad66a27959d7085aa31760f63ce082943be60e89vboxsync atapiDoTransfer(pAhciPort, pAhciReq, cbMax, ATAFN_SS_ATAPI_MODE_SENSE_CD_STATUS);
5b0a093ca572a855886faa6747ad46df859dd041vboxsync atapiCmdErrorSimple(pAhciPort, pAhciReq, SCSI_SENSE_ILLEGAL_REQUEST, SCSI_ASC_SAVING_PARAMETERS_NOT_SUPPORTED);
5b0a093ca572a855886faa6747ad46df859dd041vboxsync atapiDoTransfer(pAhciPort, pAhciReq, cbMax, ATAFN_SS_ATAPI_REQUEST_SENSE);
ad66a27959d7085aa31760f63ce082943be60e89vboxsync if (pAhciPort->pDrvMount->pfnIsMounted(pAhciPort->pDrvMount))
c58c758d3642ac45d3f12356c406c631fcd8f538vboxsync pAhciPort->pDrvMount->pfnLock(pAhciPort->pDrvMount);
c58c758d3642ac45d3f12356c406c631fcd8f538vboxsync pAhciPort->pDrvMount->pfnUnlock(pAhciPort->pDrvMount);
c58c758d3642ac45d3f12356c406c631fcd8f538vboxsync atapiCmdErrorSimple(pAhciPort, pAhciReq, SCSI_SENSE_NOT_READY, SCSI_ASC_MEDIUM_NOT_PRESENT);
c58c758d3642ac45d3f12356c406c631fcd8f538vboxsync atapiCmdErrorSimple(pAhciPort, pAhciReq, SCSI_SENSE_UNIT_ATTENTION, SCSI_ASC_MEDIUM_MAY_HAVE_CHANGED); /* media changed */
c58c758d3642ac45d3f12356c406c631fcd8f538vboxsync if (!pAhciPort->pDrvMount->pfnIsMounted(pAhciPort->pDrvMount))
c58c758d3642ac45d3f12356c406c631fcd8f538vboxsync atapiCmdErrorSimple(pAhciPort, pAhciReq, SCSI_SENSE_NOT_READY, SCSI_ASC_MEDIUM_NOT_PRESENT);
c58c758d3642ac45d3f12356c406c631fcd8f538vboxsync if ((uint64_t)iATAPILBA + cSectors > pAhciPort->cTotalSectors)
LogRel(("AHCI ATAPI: LUN#%d: CD-ROM block number %Ld invalid (READ)\n", pAhciPort->iLUN, (uint64_t)iATAPILBA + cSectors));
case SCSI_READ_CD:
atapiCmdErrorSimple(pAhciPort, pAhciReq, SCSI_SENSE_UNIT_ATTENTION, SCSI_ASC_MEDIUM_MAY_HAVE_CHANGED); /* media changed */
if (cSectors == 0)
LogRel(("AHCI ATA: LUN#%d: CD-ROM block number %Ld invalid (READ CD)\n", pAhciPort->iLUN, (uint64_t)iATAPILBA + cSectors));
atapiCmdErrorSimple(pAhciPort, pAhciReq, SCSI_SENSE_ILLEGAL_REQUEST, SCSI_ASC_INV_FIELD_IN_CMD_PACKET);
case SCSI_SEEK_10:
atapiCmdErrorSimple(pAhciPort, pAhciReq, SCSI_SENSE_UNIT_ATTENTION, SCSI_ASC_MEDIUM_MAY_HAVE_CHANGED); /* media changed */
LogRel(("AHCI ATAPI: LUN#%d: CD-ROM block number %Ld invalid (SEEK)\n", pAhciPort->iLUN, (uint64_t)iATAPILBA));
case SCSI_START_STOP_UNIT:
atapiCmdErrorSimple(pAhciPort, pAhciReq, SCSI_SENSE_NOT_READY, SCSI_ASC_MEDIA_LOAD_OR_EJECT_FAILED);
case SCSI_MECHANISM_STATUS:
case SCSI_READ_TOC_PMA_ATIP:
atapiCmdErrorSimple(pAhciPort, pAhciReq, SCSI_SENSE_UNIT_ATTENTION, SCSI_ASC_MEDIUM_MAY_HAVE_CHANGED); /* media changed */
switch (format)
atapiCmdErrorSimple(pAhciPort, pAhciReq, SCSI_SENSE_ILLEGAL_REQUEST, SCSI_ASC_INV_FIELD_IN_CMD_PACKET);
case SCSI_READ_CAPACITY:
atapiCmdErrorSimple(pAhciPort, pAhciReq, SCSI_SENSE_UNIT_ATTENTION, SCSI_ASC_MEDIUM_MAY_HAVE_CHANGED); /* media changed */
atapiCmdErrorSimple(pAhciPort, pAhciReq, SCSI_SENSE_UNIT_ATTENTION, SCSI_ASC_MEDIUM_MAY_HAVE_CHANGED); /* media changed */
atapiCmdErrorSimple(pAhciPort, pAhciReq, SCSI_SENSE_UNIT_ATTENTION, SCSI_ASC_MEDIUM_MAY_HAVE_CHANGED); /* media changed */
case SCSI_GET_CONFIGURATION:
case SCSI_INQUIRY:
case SCSI_READ_DVD_STRUCTURE:
return enmTxDir;
switch (pbPacket[0])
case SCSI_BLANK:
goto sendcmd;
case SCSI_CLOSE_TRACK_SESSION:
goto sendcmd;
case SCSI_ERASE_10:
goto sendcmd;
case SCSI_FORMAT_UNIT:
cbTransfer = pAhciReq->cmdFis[AHCI_CMDFIS_CYLL] | (pAhciReq->cmdFis[AHCI_CMDFIS_CYLH] << 8); /* use ATAPI transfer length */
goto sendcmd;
case SCSI_GET_CONFIGURATION:
goto sendcmd;
atapiDoTransfer(pAhciPort, pAhciReq, pAhciReq->cbTransfer, ATAFN_SS_ATAPI_GET_EVENT_STATUS_NOTIFICATION);
goto sendcmd;
case SCSI_GET_PERFORMANCE:
cbTransfer = pAhciReq->cmdFis[AHCI_CMDFIS_CYLL] | (pAhciReq->cmdFis[AHCI_CMDFIS_CYLH] << 8); /* use ATAPI transfer length */
goto sendcmd;
case SCSI_INQUIRY:
goto sendcmd;
case SCSI_LOAD_UNLOAD_MEDIUM:
goto sendcmd;
case SCSI_MECHANISM_STATUS:
goto sendcmd;
case SCSI_MODE_SELECT_10:
goto sendcmd;
case SCSI_MODE_SENSE_10:
goto sendcmd;
case SCSI_PAUSE_RESUME:
goto sendcmd;
case SCSI_PLAY_AUDIO_10:
goto sendcmd;
case SCSI_PLAY_AUDIO_12:
goto sendcmd;
case SCSI_PLAY_AUDIO_MSF:
goto sendcmd;
goto sendcmd;
case SCSI_READ_10:
goto sendcmd;
case SCSI_READ_12:
goto sendcmd;
case SCSI_READ_BUFFER:
goto sendcmd;
goto sendcmd;
case SCSI_READ_CAPACITY:
goto sendcmd;
case SCSI_READ_CD:
case SCSI_READ_CD_MSF:
pAhciReq->cbATAPISector = ATAPIPassthroughTrackListGetSectorSizeFromLba(pAhciPort->pTrackList, iLbaStart);
cSectors = 32; /* Limit transfer size to 64~74K. Safety first. In any case this can only harm software doing CDDA extraction. */
goto sendcmd;
goto sendcmd;
case SCSI_READ_DVD_STRUCTURE:
goto sendcmd;
goto sendcmd;
case SCSI_READ_SUBCHANNEL:
goto sendcmd;
case SCSI_READ_TOC_PMA_ATIP:
goto sendcmd;
goto sendcmd;
case SCSI_REPAIR_TRACK:
goto sendcmd;
case SCSI_REPORT_KEY:
goto sendcmd;
case SCSI_REQUEST_SENSE:
goto sendcmd;
case SCSI_RESERVE_TRACK:
goto sendcmd;
case SCSI_SCAN:
goto sendcmd;
case SCSI_SEEK_10:
goto sendcmd;
case SCSI_SEND_CUE_SHEET:
goto sendcmd;
case SCSI_SEND_DVD_STRUCTURE:
goto sendcmd;
case SCSI_SEND_EVENT:
goto sendcmd;
case SCSI_SEND_KEY:
goto sendcmd;
goto sendcmd;
case SCSI_SET_CD_SPEED:
goto sendcmd;
case SCSI_SET_READ_AHEAD:
goto sendcmd;
case SCSI_SET_STREAMING:
goto sendcmd;
case SCSI_START_STOP_UNIT:
goto sendcmd;
case SCSI_STOP_PLAY_SCAN:
goto sendcmd;
case SCSI_SYNCHRONIZE_CACHE:
goto sendcmd;
case SCSI_TEST_UNIT_READY:
goto sendcmd;
case SCSI_VERIFY_10:
goto sendcmd;
case SCSI_WRITE_10:
case SCSI_WRITE_AND_VERIFY_10:
pAhciReq->cbATAPISector = ATAPIPassthroughTrackListGetSectorSizeFromLba(pAhciPort->pTrackList, iATAPILBA);
goto sendcmd;
case SCSI_WRITE_12:
pAhciReq->cbATAPISector = ATAPIPassthroughTrackListGetSectorSizeFromLba(pAhciPort->pTrackList, iATAPILBA);
goto sendcmd;
case SCSI_WRITE_BUFFER:
LogRel(("PIIX3 ATA: LUN#%d: CD-ROM passthrough command attempted to update firmware, blocked\n", pAhciPort->iLUN));
atapiCmdErrorSimple(pAhciPort, pAhciReq, SCSI_SENSE_ILLEGAL_REQUEST, SCSI_ASC_INV_FIELD_IN_CMD_PACKET);
goto sendcmd;
goto sendcmd;
case SCSI_REZERO_UNIT:
LogRel(("AHCI: LUN#%d: passthrough unimplemented for command %#x\n", pAhciPort->iLUN, pbPacket[0]));
if (cbTransfer == 0)
return AHCITXDIR_NONE;
Log(("%s: LUN#%d CMD=%#04x \"%s\"\n", __FUNCTION__, pAhciPort->iLUN, pbPacket[0], SCSICmdText(pbPacket[0])));
Log2(("%s: limit=%#x packet: %.*Rhxs\n", __FUNCTION__, pAhciReq->cmdFis[AHCI_CMDFIS_CYLL] | (pAhciReq->cmdFis[AHCI_CMDFIS_CYLH] << 8), ATAPI_PACKET_SIZE, pbPacket));
return enmTxDir;
int rc;
/* As this is the first D2H FIS after the reset update the signature in the SIG register of the port. */
bool fInterrupt)
bool fAssertIntr = false;
if (fInterrupt)
fAssertIntr = true;
if (fAssertIntr)
static void ahciSendD2HFis(PAHCIPort pAhciPort, PAHCIREQ pAhciReq, uint8_t *pCmdFis, bool fInterrupt)
bool fAssertIntr = false;
fAssertIntr = true;
else if (fInterrupt)
fAssertIntr = true;
if (fAssertIntr)
bool fAssertIntr = false;
sdbFis[0] |= (pTaskErr->uATARegStatus & 0x77) << 16; /* Some bits are marked as reserved and thus are masked out. */
sdbFis[0] = 0;
fAssertIntr = true;
if (fInterrupt)
fAssertIntr = true;
if (fAssertIntr)
if (fLBA48)
if (fLBA48)
iLBA = ((pCmdFis[AHCI_CMDFIS_CYLH] << 8) | pCmdFis[AHCI_CMDFIS_CYLL]) * pAhciPort->PCHSGeometry.cHeads * pAhciPort->PCHSGeometry.cSectors +
return iLBA;
return uLBA;
RTGCPHYS GCPhysAddrDataBase = AHCI_RTGCPHYS_FROM_U32(aPrdtlEntries[i].u32DBAUp, aPrdtlEntries[i].u32DBA);
return cbCopied;
RTGCPHYS GCPhysAddrDataBase = AHCI_RTGCPHYS_FROM_U32(aPrdtlEntries[i].u32DBAUp, aPrdtlEntries[i].u32DBA);
return cbCopied;
return VERR_NO_MEMORY;
return VINF_SUCCESS;
bool fCopyToGuest)
&& fCopyToGuest)
bool fXchg = false;
if (fXchg)
return true; /* always true for now because tasks don't use guest memory as the buffer which makes canceling a task impossible. */
#define PDMIBLOCKASYNCPORT_2_PAHCIPORT(pInterface) ( (PAHCIPort)((uintptr_t)pInterface - RT_OFFSETOF(AHCIPort, IPortAsync)) )
int rc;
rc = PDMDevHlpVMSetRuntimeError(pDevIns, VMSETRTERR_FLAGS_SUSPEND | VMSETRTERR_FLAGS_NO_WAIT, "DevAHCI_DISKFULL",
N_("Host system reported disk full. VM execution is suspended. You can resume after freeing some space"));
int rc;
rc = PDMDevHlpVMSetRuntimeError(pDevIns, VMSETRTERR_FLAGS_SUSPEND | VMSETRTERR_FLAGS_NO_WAIT, "DevAHCI_FILETOOBIG",
N_("Host system reported that the file size limit of the host file system has been exceeded. VM execution is suspended. You need to move your virtual hard disk to a filesystem which allows bigger files"));
int rc;
rc = PDMDevHlpVMSetRuntimeError(pDevIns, VMSETRTERR_FLAGS_SUSPEND | VMSETRTERR_FLAGS_NO_WAIT, "DevAHCI_ISCSIDOWN",
N_("The iSCSI target has stopped responding. VM execution is suspended. You can resume when it is available again"));
unsigned cRangesMax;
unsigned cRanges = 0;
AssertMsgReturn(pAhciReq->enmTxDir == AHCITXDIR_TRIM, ("This is not a trim request\n"), VERR_INVALID_PARAMETER);
if (!cPrdtlEntries)
return VINF_SUCCESS;
RTGCPHYS GCPhysAddrDataBase = AHCI_RTGCPHYS_FROM_U32(aPrdtlEntries[i].u32DBAUp, aPrdtlEntries[i].u32DBA);
cRanges++;
} while (cPrdtlEntries);
return VERR_BUFFER_OVERFLOW;
RTGCPHYS GCPhysAddrDataBase = AHCI_RTGCPHYS_FROM_U32(aPrdtlEntries[i].u32DBAUp, aPrdtlEntries[i].u32DBA);
pAhciReq->u.Trim.paRanges[idxRange].offStart = (aRanges[idxRangeSrc] & AHCI_RANGE_LBA_MASK) * pAhciPort->cbSector;
pAhciReq->u.Trim.paRanges[idxRange].cbRange = AHCI_RANGE_LENGTH_GET(aRanges[idxRangeSrc]) * pAhciPort->cbSector;
idxRange++;
return rc;
bool fXchg = false;
bool fRedo = false;
bool fCanceled = false;
case AHCITXDIR_READ:
case AHCITXDIR_WRITE:
case AHCITXDIR_FLUSH:
case AHCITXDIR_TRIM:
pAhciPort->CTX_SUFF(pDevIns)->iInstance, pAhciPort->iLUN, pcszReq, (tsNow - pAhciReq->tsStart) / 1000));
if ( fXchg
if (!fRedo)
PDMDevHlpPCIPhysWrite(pAhciPort->CTX_SUFF(pDevIns), pAhciReq->GCPhysCmdHdrAddr, &pAhciReq->cmdHdr, sizeof(CmdHdr));
if (!fRedo)
fCanceled = true;
if (fFreeReq)
return fCanceled;
static DECLCALLBACK(int) ahciR3TransferCompleteNotify(PPDMIBLOCKASYNCPORT pInterface, void *pvUser, int rcReq)
return VINF_SUCCESS;
bool fLBA48 = false;
AssertMsg(pCmdFis[AHCI_CMDFIS_TYPE] == AHCI_CMDFIS_TYPE_H2D, ("FIS is not a host to device Fis!!\n"));
case ATA_IDENTIFY_DEVICE:
case ATA_SET_FEATURES:
pAhciPort->uATATransferMode = (pCmdFis[AHCI_CMDFIS_SECTC] & 0xf8) | RT_MIN(pCmdFis[AHCI_CMDFIS_SECTC] & 0x07, ATA_MDMA_MODE_MAX);
pAhciPort->uATATransferMode = (pCmdFis[AHCI_CMDFIS_SECTC] & 0xf8) | RT_MIN(pCmdFis[AHCI_CMDFIS_SECTC] & 0x07, ATA_UDMA_MODE_MAX);
case ATA_DEVICE_RESET:
case ATA_FLUSH_CACHE_EXT:
case ATA_FLUSH_CACHE:
case ATA_PACKET:
case ATA_SET_MULTIPLE_MODE:
case ATA_STANDBY_IMMEDIATE:
case ATA_CHECK_POWER_MODE:
case ATA_IDLE_IMMEDIATE:
case ATA_RECALIBRATE:
case ATA_NOP:
case ATA_READ_VERIFY_SECTORS:
case ATA_SLEEP:
case ATA_READ_DMA_EXT:
fLBA48 = true;
case ATA_READ_DMA:
case ATA_WRITE_DMA_EXT:
fLBA48 = true;
case ATA_WRITE_DMA:
case ATA_READ_FPDMA_QUEUED:
case ATA_WRITE_FPDMA_QUEUED:
case ATA_READ_LOG_EXT:
LogFlow(("Trying to read %zu bytes starting at offset %u from page %u\n", cbLogRead, offLogRead, iPage));
switch (iPage)
if (pTaskErr)
case ATA_DATA_SET_MANAGEMENT:
case ATA_SECURITY_FREEZE_LOCK:
case ATA_SMART:
case ATA_NV_CACHE:
case ATA_IDLE:
return enmTxDir;
PDMDevHlpPhysRead(pAhciPort->CTX_SUFF(pDevIns), pAhciReq->GCPhysCmdHdrAddr, &pAhciReq->cmdHdr, sizeof(CmdHdr));
#ifdef LOG_ENABLED
GCPhysAddrCmdTbl = AHCI_RTGCPHYS_FROM_U32(pAhciReq->cmdHdr.u32CmdTblAddrUp, pAhciReq->cmdHdr.u32CmdTblAddr);
AssertMsgReturn((pAhciReq->cmdHdr.u32DescInf & AHCI_CMDHDR_CFL_MASK) * sizeof(uint32_t) == AHCI_CMDFIS_TYPE_H2D_SIZE,
LogFlow(("%s: PDMDevHlpPhysRead GCPhysAddrCmdTbl=%RGp cbCmdFis=%u\n", __FUNCTION__, GCPhysAddrCmdTbl, AHCI_CMDFIS_TYPE_H2D_SIZE));
PDMDevHlpPhysRead(pAhciPort->CTX_SUFF(pDevIns), GCPhysAddrCmdTbl, &pAhciReq->cmdFis[0], AHCI_CMDFIS_TYPE_H2D_SIZE);
pAhciReq->enmTxDir = (pAhciReq->cmdHdr.u32DescInf & AHCI_CMDHDR_W) ? AHCITXDIR_WRITE : AHCITXDIR_READ;
PDMDevHlpPhysRead(pAhciPort->CTX_SUFF(pDevIns), GCPhysAddrCmdTbl, &pAhciReq->aATAPICmd[0], ATAPI_PACKET_SIZE);
* We need to send a FIS which clears the busy bit if this is a queued command so that the guest can queue other commands.
pAhciReq->GCPhysPrdtl = AHCI_RTGCPHYS_FROM_U32(pAhciReq->cmdHdr.u32CmdTblAddrUp, pAhciReq->cmdHdr.u32CmdTblAddr) + AHCI_CMDHDR_PRDT_OFFSET;
#ifdef LOG_ENABLED
ahciLog(("PRDT address %RGp number of entries %u\n", pAhciReq->GCPhysPrdtl, pAhciReq->cPrdtlEntries));
return VINF_SUCCESS;
unsigned idx = 0;
if (!u32Tasks)
while ( idx
bool fReqCanceled = false;
idx--;
bool fXchg;
/* Mark the task as processed by the HBA if this is a queued task so that it doesn't occur in the CI register anymore. */
pAhciReq);
rc = pAhciPort->pDrvBlockAsync->pfnStartDiscard(pAhciPort->pDrvBlockAsync, pAhciReq->u.Trim.paRanges,
pAhciReq);
pAhciReq);
if (fReqCanceled)
&& !cThreadsActive)
return VINF_SUCCESS;
return VINF_SUCCESS;
return VINF_SUCCESS;
static const char *s_apszIdeEmuPortNames[4] = { "PrimaryMaster", "PrimarySlave", "SecondaryMaster", "SecondarySlave" };
return VINF_SSM_DONT_CALL_AGAIN;
uint32_t i;
int rc;
for (i = 0; i < AHCI_MAX_NR_PORTS_IMPL; i++)
int rc;
if (u32IOBuffer)
return rc;
if (u32 != ~0U)
return rc;
return VINF_SUCCESS;
static DECLCALLBACK(int) ahciR3LoadExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
int rc;
uVersion++;
bool fInUse;
N_("The %s VM is missing a device on port %u. Please make sure the source and target VMs have compatible storage configurations"),
bool fHotpluggable;
static const char *s_apszIdeEmuPortNames[4] = { "PrimaryMaster", "PrimarySlave", "SecondaryMaster", "SecondarySlave" };
return rc;
return rc;
return VINF_SUCCESS;
uint32_t i;
switch (OldStatus)
LogRel(("AHCI: LUN#%d: CD/DVD, total number of sectors %Ld, passthrough unchanged\n", pAhciPort->iLUN, pAhciPort->cTotalSectors));
return VERR_PDM_MISSING_INTERFACE;
return VERR_PDM_MISSING_INTERFACE;
AssertMsgFailed(("Configuration error: LUN#%d isn't a disk or cd/dvd. enmType=%d\n", pAhciPort->iLUN, enmType));
return VERR_PDM_UNSUPPORTED_BLOCK_TYPE;
return VERR_INTERNAL_ERROR;
pAhciPort->fATAPIPassthrough = pAhciPort->fATAPI ? (pAhciPort->pDrvBlock->pfnSendCmd != NULL) : false;
LogRel(("AHCI LUN#%d: CD/DVD, total number of sectors %Ld, passthrough %s\n", pAhciPort->iLUN, pAhciPort->cTotalSectors, (pAhciPort->fATAPIPassthrough ? "enabled" : "disabled")));
pAhciPort->cTotalSectors = pAhciPort->pDrvBlock->pfnGetSize(pAhciPort->pDrvBlock) / pAhciPort->cbSector;
return rc;
PDEVPORTNOTIFIERQUEUEITEM pItem = (PDEVPORTNOTIFIERQUEUEITEM)PDMQueueAlloc(pAhci->CTX_SUFF(pNotifierQueue));
rc = CFGMR3QueryStringDef(pCfgNode, "SerialNumber", pAhciPort->szSerialNumber, sizeof(pAhciPort->szSerialNumber),
szSerial);
rc = CFGMR3QueryStringDef(pCfgNode, "FirmwareRevision", pAhciPort->szFirmwareRevision, sizeof(pAhciPort->szFirmwareRevision),
rc = CFGMR3QueryStringDef(pCfgNode, "ModelNumber", pAhciPort->szModelNumber, sizeof(pAhciPort->szModelNumber),
rc = CFGMR3QueryU8Def(pCfgNode, "LogicalSectorsPerPhysical", &pAhciPort->cLogSectorsPerPhysicalExp, 0);
rc = CFGMR3QueryStringDef(pCfgNode, "ATAPIVendorId", pAhciPort->szInquiryVendorId, sizeof(pAhciPort->szInquiryVendorId),
rc = CFGMR3QueryStringDef(pCfgNode, "ATAPIProductId", pAhciPort->szInquiryProductId, sizeof(pAhciPort->szInquiryProductId),
rc = CFGMR3QueryStringDef(pCfgNode, "ATAPIRevision", pAhciPort->szInquiryRevision, sizeof(pAhciPort->szInquiryRevision),
return rc;
int rcThread;
AssertMsgFailed(("%s Failed to destroy async IO thread rc=%Rrc rcThread=%Rrc\n", __FUNCTION__, rc, rcThread));
int rc;
rc = PDMDevHlpDriverAttach(pDevIns, pAhciPort->iLUN, &pAhciPort->IBase, &pAhciPort->pDrvBase, NULL);
rc = PDMDevHlpThreadCreate(pDevIns, &pAhciPort->pAsyncIOThread, pAhciPort, ahciAsyncIOLoop, ahciAsyncIOLoopWakeUp, 0,
return rc;
return rc;
return VINF_SUCCESS;
return rc;
bool fGCEnabled = false;
bool fR0Enabled = false;
rc = CFGMR3QueryBoolDef(pCfg, "UseAsyncInterfaceIfAvailable", &pThis->fUseAsyncInterfaceIfAvailable, true);
#ifdef VBOX_WITH_MSI_DEVICES
for (i = 0; i < AHCI_MAX_NR_PORTS_IMPL; i++)
return rc;
return rc;
return rc;
#ifdef VBOX_WITH_MSI_DEVICES
* No guest should access them anyway because the controller is marked as AHCI in the Programming interface
* and we don't have an option to change to IDE emulation (real hardware provides an option in the BIOS
return rc;
return rc;
for (i = 0; i < AHCI_MAX_NR_PORTS_IMPL; i++)
PDMDevHlpSTAMRegisterF(pDevIns, &pAhciPort->StatDMA, STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES,
PDMDevHlpSTAMRegisterF(pDevIns, &pAhciPort->StatBytesRead, STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_BYTES,
PDMDevHlpSTAMRegisterF(pDevIns, &pAhciPort->StatBytesWritten, STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_BYTES,
PDMDevHlpSTAMRegisterF(pDevIns, &pAhciPort->StatIORequestsPerSecond, STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES,
"Number of processed I/O requests per second.", "/Devices/SATA%d/Port%d/IORequestsPerSecond", iInstance, i);
#ifdef VBOX_WITH_STATISTICS
PDMDevHlpSTAMRegisterF(pDevIns, &pAhciPort->StatProfileProcessTime, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_NS_PER_CALL,
"Amount of time to process one request.", "/Devices/SATA%d/Port%d/ProfileProcessTime", iInstance, i);
PDMDevHlpSTAMRegisterF(pDevIns, &pAhciPort->StatProfileReadWrite, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_NS_PER_CALL,
"Amount of time for the read/write operation to complete.", "/Devices/SATA%d/Port%d/ProfileReadWrite", iInstance, i);
if (pCfgPort)
rc = PDMDevHlpDriverAttach(pDevIns, pAhciPort->iLUN, &pAhciPort->IBase, &pAhciPort->pDrvBase, szName);
return rc;
return rc;
rc = PDMDevHlpSSMRegisterEx(pDevIns, AHCI_SAVED_STATE_VERSION, sizeof(*pThis) + cbTotalBufferSize, NULL,
return rc;
sizeof(AHCI),
NULL,
NULL,
NULL,
NULL,
NULL,