DevParallel.cpp revision 021a33be84282e41b811563b5f60f3ada196af3e
45e9809aff7304721fddb95654901b32195c9c7avboxsync * DevParallel - Parallel (Port) Device Emulation.
45e9809aff7304721fddb95654901b32195c9c7avboxsync * Contributed by: Alexander Eichner
45e9809aff7304721fddb95654901b32195c9c7avboxsync * Copyright (C) 2006-2007 Oracle Corporation
45e9809aff7304721fddb95654901b32195c9c7avboxsync * This file is part of VirtualBox Open Source Edition (OSE), as
45e9809aff7304721fddb95654901b32195c9c7avboxsync * available from http://www.virtualbox.org. This file is free software;
45e9809aff7304721fddb95654901b32195c9c7avboxsync * you can redistribute it and/or modify it under the terms of the GNU
45e9809aff7304721fddb95654901b32195c9c7avboxsync * General Public License (GPL) as published by the Free Software
45e9809aff7304721fddb95654901b32195c9c7avboxsync * Foundation, in version 2 as it comes in the "COPYING" file of the
45e9809aff7304721fddb95654901b32195c9c7avboxsync * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
45e9809aff7304721fddb95654901b32195c9c7avboxsync * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
45e9809aff7304721fddb95654901b32195c9c7avboxsync/*******************************************************************************
45e9809aff7304721fddb95654901b32195c9c7avboxsync* Header Files *
45e9809aff7304721fddb95654901b32195c9c7avboxsync*******************************************************************************/
45e9809aff7304721fddb95654901b32195c9c7avboxsync/*******************************************************************************
45e9809aff7304721fddb95654901b32195c9c7avboxsync* Defined Constants And Macros *
45e9809aff7304721fddb95654901b32195c9c7avboxsync*******************************************************************************/
45e9809aff7304721fddb95654901b32195c9c7avboxsync/* defines for accessing the register bits */
45e9809aff7304721fddb95654901b32195c9c7avboxsync#define LPT_STATUS_BIT1 0x02 /* reserved (only for completeness) */
45e9809aff7304721fddb95654901b32195c9c7avboxsync#define LPT_CONTROL_BIT7 0x80 /* reserved (only for completeness) */
45e9809aff7304721fddb95654901b32195c9c7avboxsync#define LPT_CONTROL_BIT6 0x40 /* reserved (only for completeness) */
45e9809aff7304721fddb95654901b32195c9c7avboxsync/** mode defines for the extended control register */
45e9809aff7304721fddb95654901b32195c9c7avboxsync#define LPT_ECP_ECR_CHIPMODE_GET_BITS(reg) ((reg) >> 5)
45e9809aff7304721fddb95654901b32195c9c7avboxsync#define LPT_ECP_ECR_CHIPMODE_SET_BITS(val) ((val) << 5)
45e9809aff7304721fddb95654901b32195c9c7avboxsync/** FIFO status bits in extended control register */
45e9809aff7304721fddb95654901b32195c9c7avboxsync#define LPT_ECP_CONFIGA_FIFO_WIDTH_GET_BITS(reg) ((reg) >> 4)
45e9809aff7304721fddb95654901b32195c9c7avboxsync#define LPT_ECP_CONFIGA_FIFO_WIDTH_SET_BITS(val) ((val) << 4)
45e9809aff7304721fddb95654901b32195c9c7avboxsync/*******************************************************************************
45e9809aff7304721fddb95654901b32195c9c7avboxsync* Structures and Typedefs *
45e9809aff7304721fddb95654901b32195c9c7avboxsync*******************************************************************************/
45e9809aff7304721fddb95654901b32195c9c7avboxsync * Parallel device state.
45e9809aff7304721fddb95654901b32195c9c7avboxsync * @implements PDMIBASE
45e9809aff7304721fddb95654901b32195c9c7avboxsync * @implements PDMIHOSTPARALLELPORT
45e9809aff7304721fddb95654901b32195c9c7avboxsync /** Access critical section. */
45e9809aff7304721fddb95654901b32195c9c7avboxsync /** Pointer to the device instance - R3 Ptr */
45e9809aff7304721fddb95654901b32195c9c7avboxsync /** Pointer to the device instance - R0 Ptr */
45e9809aff7304721fddb95654901b32195c9c7avboxsync /** Pointer to the device instance - RC Ptr */
45e9809aff7304721fddb95654901b32195c9c7avboxsync /** LUN\#0: The base interface. */
45e9809aff7304721fddb95654901b32195c9c7avboxsync /** LUN\#0: The host device port interface. */
45e9809aff7304721fddb95654901b32195c9c7avboxsync /** Pointer to the attached base driver. */
45e9809aff7304721fddb95654901b32195c9c7avboxsync /** Pointer to the attached host device. */
45e9809aff7304721fddb95654901b32195c9c7avboxsync R3PTRTYPE(PPDMIHOSTPARALLELCONNECTOR) pDrvHostParallelConnector;
45e9809aff7304721fddb95654901b32195c9c7avboxsync /** Unused event semaphore... */
45e9809aff7304721fddb95654901b32195c9c7avboxsync uint8_t reg_ecp_base_plus_400h; /* has different meanings */
45e9809aff7304721fddb95654901b32195c9c7avboxsync /** The ECP FIFO implementation*/
45e9809aff7304721fddb95654901b32195c9c7avboxsync#define PDMIHOSTPARALLELPORT_2_PARALLELSTATE(pInstance) ( (ParallelState *)((uintptr_t)(pInterface) - RT_OFFSETOF(ParallelState, IHostParallelPort)) )
45e9809aff7304721fddb95654901b32195c9c7avboxsync#define PDMIHOSTDEVICEPORT_2_PARALLELSTATE(pInstance) ( (ParallelState *)((uintptr_t)(pInterface) - RT_OFFSETOF(ParallelState, IHostDevicePort)) )
45e9809aff7304721fddb95654901b32195c9c7avboxsync#define PDMIBASE_2_PARALLELSTATE(pInstance) ( (ParallelState *)((uintptr_t)(pInterface) - RT_OFFSETOF(ParallelState, IBase)) )
45e9809aff7304721fddb95654901b32195c9c7avboxsync/*******************************************************************************
45e9809aff7304721fddb95654901b32195c9c7avboxsync* Internal Functions *
45e9809aff7304721fddb95654901b32195c9c7avboxsync*******************************************************************************/
45e9809aff7304721fddb95654901b32195c9c7avboxsyncPDMBOTHCBDECL(int) parallelIOPortRead(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t *pu32, unsigned cb);
45e9809aff7304721fddb95654901b32195c9c7avboxsyncPDMBOTHCBDECL(int) parallelIOPortWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb);
45e9809aff7304721fddb95654901b32195c9c7avboxsyncPDMBOTHCBDECL(int) parallelIOPortReadECP(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t *pu32, unsigned cb);
45e9809aff7304721fddb95654901b32195c9c7avboxsyncPDMBOTHCBDECL(int) parallelIOPortWriteECP(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb);
45e9809aff7304721fddb95654901b32195c9c7avboxsync if (s->reg_control & LPT_CONTROL_ENABLE_IRQ_VIA_ACK)
45e9809aff7304721fddb95654901b32195c9c7avboxsync PDMDevHlpISASetIrqNoWait(s->CTX_SUFF(pDevIns), s->irq, 1);
45e9809aff7304721fddb95654901b32195c9c7avboxsync PDMDevHlpISASetIrqNoWait(s->CTX_SUFF(pDevIns), s->irq, 0);
45e9809aff7304721fddb95654901b32195c9c7avboxsyncstatic int parallel_ioport_write(void *opaque, uint32_t addr, uint32_t val)
45e9809aff7304721fddb95654901b32195c9c7avboxsync unsigned char ch;
45e9809aff7304721fddb95654901b32195c9c7avboxsync LogFlow(("parallel: write addr=0x%02x val=0x%02x\n", addr, val));
45e9809aff7304721fddb95654901b32195c9c7avboxsync int rc = s->pDrvHostParallelConnector->pfnWrite(s->pDrvHostParallelConnector, &ch, &cbWrite);
45e9809aff7304721fddb95654901b32195c9c7avboxsync /* Set the reserved bits to one */
45e9809aff7304721fddb95654901b32195c9c7avboxsync int rc = s->pDrvHostParallelConnector->pfnWriteControl(s->pDrvHostParallelConnector, ch);
return VINF_SUCCESS;
switch(addr) {
#ifndef IN_RING3
int rc = s->pDrvHostParallelConnector->pfnRead(s->pDrvHostParallelConnector, &s->reg_data, &cbRead);
#ifndef IN_RING3
return ret;
unsigned char ch;
switch(addr) {
s->act_fifo_pos_write++;
s->act_fifo_pos_write = 0;
s->act_fifo_pos_write = 0;
s->act_fifo_pos_read = 0;
return VINF_SUCCESS;
switch(addr) {
s->act_fifo_pos_read++;
return ret;
#ifdef IN_RING3
return VINF_SUCCESS;
return rc;
return rc;
return rc;
return rc;
#ifdef IN_RING3
return VINF_SSM_DONT_CALL_AGAIN;
return VINF_SUCCESS;
AssertMsgReturn(uVersion == PARALLEL_SAVED_STATE_VERSION, ("%d\n", uVersion), VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION);
return rc;
return SSMR3SetCfgError(pSSM, RT_SRC_POS, N_("IRQ changed: config=%#x state=%#x"), pThis->irq, iIrq);
return SSMR3SetCfgError(pSSM, RT_SRC_POS, N_("IOBase changed: config=%#x state=%#x"), pThis->base, uIoBase);
return VINF_SUCCESS;
return NULL;
return VINF_SUCCESS;
int iInstance,
int rc;
return rc;
return rc;
return rc;
return rc;
return rc;
return rc;
return rc;
return rc;
return rc;
pThis->pDrvHostParallelConnector = PDMIBASE_QUERY_INTERFACE(pThis->pDrvBase, PDMIHOSTPARALLELCONNECTOR);
pThis->pDrvHostParallelConnector->pfnSetMode(pThis->pDrvHostParallelConnector, PDM_PARALLEL_PORT_MODE_COMPAT);
pThis->pDrvHostParallelConnector->pfnReadControl(pThis->pDrvHostParallelConnector, &pThis->reg_control);
return VINF_SUCCESS;
sizeof(ParallelState),
NULL,
NULL,
NULL,
NULL,
NULL,
NULL,
NULL,
NULL,
NULL,
NULL,
NULL,