DevParallel.cpp revision fe813b3594039ba864493438e78ee0e7132bc445
078c5b8c5c814755aab943bf62cadef7e91c419cvboxsync * DevParallel - Parallel (Port) Device Emulation.
078c5b8c5c814755aab943bf62cadef7e91c419cvboxsync * Contributed by: Alexander Eichner
078c5b8c5c814755aab943bf62cadef7e91c419cvboxsync * Copyright (C) 2006-2007 Sun Microsystems, Inc.
078c5b8c5c814755aab943bf62cadef7e91c419cvboxsync * This file is part of VirtualBox Open Source Edition (OSE), as
078c5b8c5c814755aab943bf62cadef7e91c419cvboxsync * available from http://www.virtualbox.org. This file is free software;
078c5b8c5c814755aab943bf62cadef7e91c419cvboxsync * you can redistribute it and/or modify it under the terms of the GNU
078c5b8c5c814755aab943bf62cadef7e91c419cvboxsync * General Public License (GPL) as published by the Free Software
078c5b8c5c814755aab943bf62cadef7e91c419cvboxsync * Foundation, in version 2 as it comes in the "COPYING" file of the
078c5b8c5c814755aab943bf62cadef7e91c419cvboxsync * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
078c5b8c5c814755aab943bf62cadef7e91c419cvboxsync * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
078c5b8c5c814755aab943bf62cadef7e91c419cvboxsync * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
078c5b8c5c814755aab943bf62cadef7e91c419cvboxsync * Clara, CA 95054 USA or visit http://www.sun.com if you need
078c5b8c5c814755aab943bf62cadef7e91c419cvboxsync * additional information or have any questions.
078c5b8c5c814755aab943bf62cadef7e91c419cvboxsync/*******************************************************************************
078c5b8c5c814755aab943bf62cadef7e91c419cvboxsync* Header Files *
078c5b8c5c814755aab943bf62cadef7e91c419cvboxsync*******************************************************************************/
078c5b8c5c814755aab943bf62cadef7e91c419cvboxsync/*******************************************************************************
078c5b8c5c814755aab943bf62cadef7e91c419cvboxsync* Defined Constants And Macros *
078c5b8c5c814755aab943bf62cadef7e91c419cvboxsync*******************************************************************************/
078c5b8c5c814755aab943bf62cadef7e91c419cvboxsync/* defines for accessing the register bits */
078c5b8c5c814755aab943bf62cadef7e91c419cvboxsync#define LPT_STATUS_BIT1 0x02 /* reserved (only for completeness) */
078c5b8c5c814755aab943bf62cadef7e91c419cvboxsync#define LPT_CONTROL_BIT7 0x80 /* reserved (only for completeness) */
078c5b8c5c814755aab943bf62cadef7e91c419cvboxsync#define LPT_CONTROL_BIT6 0x40 /* reserved (only for completeness) */
078c5b8c5c814755aab943bf62cadef7e91c419cvboxsync/** mode defines for the extended control register */
078c5b8c5c814755aab943bf62cadef7e91c419cvboxsync#define LPT_ECP_ECR_CHIPMODE_GET_BITS(reg) ((reg) >> 5)
078c5b8c5c814755aab943bf62cadef7e91c419cvboxsync#define LPT_ECP_ECR_CHIPMODE_SET_BITS(val) ((val) << 5)
078c5b8c5c814755aab943bf62cadef7e91c419cvboxsync/** FIFO status bits in extended control register */
078c5b8c5c814755aab943bf62cadef7e91c419cvboxsync#define LPT_ECP_CONFIGA_FIFO_WIDTH_GET_BITS(reg) ((reg) >> 4)
078c5b8c5c814755aab943bf62cadef7e91c419cvboxsync#define LPT_ECP_CONFIGA_FIFO_WIDTH_SET_BITS(val) ((val) << 4)
078c5b8c5c814755aab943bf62cadef7e91c419cvboxsync/*******************************************************************************
078c5b8c5c814755aab943bf62cadef7e91c419cvboxsync* Structures and Typedefs *
078c5b8c5c814755aab943bf62cadef7e91c419cvboxsync*******************************************************************************/
078c5b8c5c814755aab943bf62cadef7e91c419cvboxsync /** Access critical section. */
078c5b8c5c814755aab943bf62cadef7e91c419cvboxsync /** Pointer to the device instance - R3 Ptr */
078c5b8c5c814755aab943bf62cadef7e91c419cvboxsync /** Pointer to the device instance - R0 Ptr */
078c5b8c5c814755aab943bf62cadef7e91c419cvboxsync /** Pointer to the device instance - RC Ptr */
078c5b8c5c814755aab943bf62cadef7e91c419cvboxsync /** The base interface. */
078c5b8c5c814755aab943bf62cadef7e91c419cvboxsync /** The host device port interface. */
078c5b8c5c814755aab943bf62cadef7e91c419cvboxsync /** Pointer to the attached base driver. */
078c5b8c5c814755aab943bf62cadef7e91c419cvboxsync /** Pointer to the attached host device. */
078c5b8c5c814755aab943bf62cadef7e91c419cvboxsync R3PTRTYPE(PPDMIHOSTPARALLELCONNECTOR) pDrvHostParallelConnector;
078c5b8c5c814755aab943bf62cadef7e91c419cvboxsync /** Unused event semaphore... */
078c5b8c5c814755aab943bf62cadef7e91c419cvboxsync uint8_t reg_ecp_base_plus_400h; /* has different meanings */
078c5b8c5c814755aab943bf62cadef7e91c419cvboxsync /** The ECP FIFO implementation*/
078c5b8c5c814755aab943bf62cadef7e91c419cvboxsync#define PDMIHOSTPARALLELPORT_2_PARALLELSTATE(pInstance) ( (ParallelState *)((uintptr_t)(pInterface) - RT_OFFSETOF(ParallelState, IHostParallelPort)) )
078c5b8c5c814755aab943bf62cadef7e91c419cvboxsync#define PDMIHOSTDEVICEPORT_2_PARALLELSTATE(pInstance) ( (ParallelState *)((uintptr_t)(pInterface) - RT_OFFSETOF(ParallelState, IHostDevicePort)) )
d82d7a8b44b27420e50f410d8ee5b990bb8b8f12vboxsync#define PDMIBASE_2_PARALLELSTATE(pInstance) ( (ParallelState *)((uintptr_t)(pInterface) - RT_OFFSETOF(ParallelState, IBase)) )
d82d7a8b44b27420e50f410d8ee5b990bb8b8f12vboxsync/*******************************************************************************
d82d7a8b44b27420e50f410d8ee5b990bb8b8f12vboxsync* Internal Functions *
d82d7a8b44b27420e50f410d8ee5b990bb8b8f12vboxsync*******************************************************************************/
078c5b8c5c814755aab943bf62cadef7e91c419cvboxsyncPDMBOTHCBDECL(int) parallelIOPortRead(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t *pu32, unsigned cb);
078c5b8c5c814755aab943bf62cadef7e91c419cvboxsyncPDMBOTHCBDECL(int) parallelIOPortWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb);
d82d7a8b44b27420e50f410d8ee5b990bb8b8f12vboxsyncPDMBOTHCBDECL(int) parallelIOPortReadECP(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t *pu32, unsigned cb);
d82d7a8b44b27420e50f410d8ee5b990bb8b8f12vboxsyncPDMBOTHCBDECL(int) parallelIOPortWriteECP(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb);
078c5b8c5c814755aab943bf62cadef7e91c419cvboxsync if (s->reg_control & LPT_CONTROL_ENABLE_IRQ_VIA_ACK)
078c5b8c5c814755aab943bf62cadef7e91c419cvboxsync PDMDevHlpISASetIrqNoWait(s->CTX_SUFF(pDevIns), s->irq, 1);
d82d7a8b44b27420e50f410d8ee5b990bb8b8f12vboxsync PDMDevHlpISASetIrqNoWait(s->CTX_SUFF(pDevIns), s->irq, 0);
d82d7a8b44b27420e50f410d8ee5b990bb8b8f12vboxsyncstatic int parallel_ioport_write(void *opaque, uint32_t addr, uint32_t val)
078c5b8c5c814755aab943bf62cadef7e91c419cvboxsync unsigned char ch;
078c5b8c5c814755aab943bf62cadef7e91c419cvboxsync LogFlow(("parallel: write addr=0x%02x val=0x%02x\n", addr, val));
078c5b8c5c814755aab943bf62cadef7e91c419cvboxsync int rc = s->pDrvHostParallelConnector->pfnWrite(s->pDrvHostParallelConnector, &ch, &cbWrite);
d82d7a8b44b27420e50f410d8ee5b990bb8b8f12vboxsync /* Set the reserved bits to one */
d82d7a8b44b27420e50f410d8ee5b990bb8b8f12vboxsync int rc = s->pDrvHostParallelConnector->pfnWriteControl(s->pDrvHostParallelConnector, ch);
078c5b8c5c814755aab943bf62cadef7e91c419cvboxsyncstatic uint32_t parallel_ioport_read(void *opaque, uint32_t addr, int *pRC)
078c5b8c5c814755aab943bf62cadef7e91c419cvboxsync if (!(s->reg_control & LPT_CONTROL_ENABLE_BIDIRECT))
int rc = s->pDrvHostParallelConnector->pfnRead(s->pDrvHostParallelConnector, &s->reg_data, &cbRead);
#ifndef IN_RING3
return ret;
unsigned char ch;
switch(addr) {
s->act_fifo_pos_write++;
s->act_fifo_pos_write = 0;
s->act_fifo_pos_write = 0;
s->act_fifo_pos_read = 0;
return VINF_SUCCESS;
switch(addr) {
s->act_fifo_pos_read++;
return ret;
#ifdef IN_RING3
return VINF_SUCCESS;
return rc;
return rc;
return rc;
return rc;
#ifdef IN_RING3
int rc;
return rc;
if (u32 != ~0U)
return VINF_SUCCESS;
switch (enmInterface)
case PDMINTERFACE_BASE:
return NULL;
return VINF_SUCCESS;
int iInstance,
int rc;
return rc;
return rc;
return rc;
return rc;
return rc;
return rc;
return rc;
return rc;
return rc;
pThis->pDrvHostParallelConnector = (PDMIHOSTPARALLELCONNECTOR *)pThis->pDrvBase->pfnQueryInterface(pThis->pDrvBase,
return VERR_PDM_MISSING_INTERFACE;
pThis->pDrvHostParallelConnector->pfnSetMode(pThis->pDrvHostParallelConnector, PDM_PARALLEL_PORT_MODE_COMPAT);
pThis->pDrvHostParallelConnector->pfnReadControl(pThis->pDrvHostParallelConnector, &pThis->reg_control);
return VINF_SUCCESS;
PDM_DEVREG_FLAGS_HOST_BITS_DEFAULT | PDM_DEVREG_FLAGS_GUEST_BITS_DEFAULT | PDM_DEVREG_FLAGS_GC | PDM_DEVREG_FLAGS_R0,
sizeof(ParallelState),
NULL,
NULL,
NULL,
NULL,
NULL,
NULL,
NULL,