DevParallel.cpp revision 590bfe12ce22cd3716448fbb9f4dc51664bfe5e2
3cdf227bdf099f60b22215d6ea7685ec5ec64fe6vboxsync * DevParallel - Parallel (Port) Device Emulation.
3cdf227bdf099f60b22215d6ea7685ec5ec64fe6vboxsync * Contributed by: Alexander Eichner
3cdf227bdf099f60b22215d6ea7685ec5ec64fe6vboxsync * Copyright (C) 2006-2007 Sun Microsystems, Inc.
3cdf227bdf099f60b22215d6ea7685ec5ec64fe6vboxsync * This file is part of VirtualBox Open Source Edition (OSE), as
3cdf227bdf099f60b22215d6ea7685ec5ec64fe6vboxsync * available from http://www.virtualbox.org. This file is free software;
3cdf227bdf099f60b22215d6ea7685ec5ec64fe6vboxsync * you can redistribute it and/or modify it under the terms of the GNU
3cdf227bdf099f60b22215d6ea7685ec5ec64fe6vboxsync * General Public License (GPL) as published by the Free Software
3cdf227bdf099f60b22215d6ea7685ec5ec64fe6vboxsync * Foundation, in version 2 as it comes in the "COPYING" file of the
3cdf227bdf099f60b22215d6ea7685ec5ec64fe6vboxsync * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
3cdf227bdf099f60b22215d6ea7685ec5ec64fe6vboxsync * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
3cdf227bdf099f60b22215d6ea7685ec5ec64fe6vboxsync * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
3cdf227bdf099f60b22215d6ea7685ec5ec64fe6vboxsync * Clara, CA 95054 USA or visit http://www.sun.com if you need
3cdf227bdf099f60b22215d6ea7685ec5ec64fe6vboxsync * additional information or have any questions.
3cdf227bdf099f60b22215d6ea7685ec5ec64fe6vboxsync/*******************************************************************************
3cdf227bdf099f60b22215d6ea7685ec5ec64fe6vboxsync* Header Files *
3cdf227bdf099f60b22215d6ea7685ec5ec64fe6vboxsync*******************************************************************************/
3cdf227bdf099f60b22215d6ea7685ec5ec64fe6vboxsync/*******************************************************************************
3cdf227bdf099f60b22215d6ea7685ec5ec64fe6vboxsync* Defined Constants And Macros *
3cdf227bdf099f60b22215d6ea7685ec5ec64fe6vboxsync*******************************************************************************/
3cdf227bdf099f60b22215d6ea7685ec5ec64fe6vboxsync/* defines for accessing the register bits */
3cdf227bdf099f60b22215d6ea7685ec5ec64fe6vboxsync#define LPT_STATUS_BIT1 0x02 /* reserved (only for completeness) */
3cdf227bdf099f60b22215d6ea7685ec5ec64fe6vboxsync#define LPT_CONTROL_BIT7 0x80 /* reserved (only for completeness) */
3cdf227bdf099f60b22215d6ea7685ec5ec64fe6vboxsync#define LPT_CONTROL_BIT6 0x40 /* reserved (only for completeness) */
3cdf227bdf099f60b22215d6ea7685ec5ec64fe6vboxsync/** mode defines for the extended control register */
3cdf227bdf099f60b22215d6ea7685ec5ec64fe6vboxsync#define LPT_ECP_ECR_CHIPMODE_GET_BITS(reg) ((reg) >> 5)
3cdf227bdf099f60b22215d6ea7685ec5ec64fe6vboxsync#define LPT_ECP_ECR_CHIPMODE_SET_BITS(val) ((val) << 5)
3cdf227bdf099f60b22215d6ea7685ec5ec64fe6vboxsync/** FIFO status bits in extended control register */
3cdf227bdf099f60b22215d6ea7685ec5ec64fe6vboxsync#define LPT_ECP_CONFIGA_FIFO_WIDTH_GET_BITS(reg) ((reg) >> 4)
3cdf227bdf099f60b22215d6ea7685ec5ec64fe6vboxsync#define LPT_ECP_CONFIGA_FIFO_WIDTH_SET_BITS(val) ((val) << 4)
typedef struct ParallelState
int act_fifo_pos_write;
int act_fifo_pos_read;
int irq;
bool fGCEnabled;
bool fR0Enabled;
#ifndef VBOX_DEVICE_STRUCT_TESTCASE
#define PDMIHOSTPARALLELPORT_2_PARALLELSTATE(pInstance) ( (ParallelState *)((uintptr_t)(pInterface) - RT_OFFSETOF(ParallelState, IHostParallelPort)) )
#define PDMIHOSTDEVICEPORT_2_PARALLELSTATE(pInstance) ( (ParallelState *)((uintptr_t)(pInterface) - RT_OFFSETOF(ParallelState, IHostDevicePort)) )
#define PDMIBASE_2_PARALLELSTATE(pInstance) ( (ParallelState *)((uintptr_t)(pInterface) - RT_OFFSETOF(ParallelState, IBase)) )
PDMBOTHCBDECL(int) parallelIOPortRead(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t *pu32, unsigned cb);
PDMBOTHCBDECL(int) parallelIOPortWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb);
PDMBOTHCBDECL(int) parallelIOPortReadECP(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t *pu32, unsigned cb);
PDMBOTHCBDECL(int) parallelIOPortWriteECP(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb);
#ifdef IN_RING3
unsigned char ch;
switch(addr) {
#ifndef IN_RING3
return VINF_IOM_HC_IOPORT_WRITE;
#ifndef IN_RING3
return VINF_IOM_HC_IOPORT_WRITE;
return VINF_SUCCESS;
switch(addr) {
#ifndef IN_RING3
int rc = s->pDrvHostParallelConnector->pfnRead(s->pDrvHostParallelConnector, &s->reg_data, &cbRead);
#ifndef IN_RING3
return ret;
unsigned char ch;
switch(addr) {
s->act_fifo_pos_write++;
s->act_fifo_pos_write = 0;
s->act_fifo_pos_write = 0;
s->act_fifo_pos_read = 0;
return VINF_SUCCESS;
switch(addr) {
s->act_fifo_pos_read++;
return ret;
#ifdef IN_RING3
return VINF_SUCCESS;
return rc;
return rc;
return rc;
return rc;
#ifdef IN_RING3
int rc;
return rc;
if (u32 != ~0U)
return VINF_SUCCESS;
switch (enmInterface)
case PDMINTERFACE_BASE:
return NULL;
return VINF_SUCCESS;
int iInstance,
int rc;
return rc;
return rc;
return rc;
return rc;
return rc;
return rc;
return rc;
return rc;
return rc;
pThis->pDrvHostParallelConnector = (PDMIHOSTPARALLELCONNECTOR *)pThis->pDrvBase->pfnQueryInterface(pThis->pDrvBase,
return VERR_PDM_MISSING_INTERFACE;
pThis->pDrvHostParallelConnector->pfnSetMode(pThis->pDrvHostParallelConnector, PDM_PARALLEL_PORT_MODE_COMPAT);
pThis->pDrvHostParallelConnector->pfnReadControl(pThis->pDrvHostParallelConnector, &pThis->reg_control);
return VINF_SUCCESS;
sizeof(ParallelState),
NULL,
NULL,
NULL,
NULL,
NULL,
NULL,
NULL,
NULL,
NULL,
NULL,
NULL,