a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync#ifndef _INTEL_H
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync#define _INTEL_H
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync/** @file
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync *
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync * Intel 10/100/1000 network card driver
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync *
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync */
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsyncFILE_LICENCE ( GPL2_OR_LATER );
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync#include <stdint.h>
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync#include <ipxe/if_ether.h>
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync#include <ipxe/nvs.h>
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync/** Intel BAR size */
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync#define INTEL_BAR_SIZE ( 128 * 1024 )
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync/** A packet descriptor */
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsyncstruct intel_descriptor {
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync /** Buffer address */
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync uint64_t address;
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync /** Length */
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync uint16_t length;
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync /** Reserved */
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync uint8_t reserved_a;
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync /** Command */
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync uint8_t command;
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync /** Status */
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync uint8_t status;
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync /** Errors */
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync uint8_t errors;
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync /** Reserved */
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync uint16_t reserved_b;
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync} __attribute__ (( packed ));
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync/** Packet descriptor command bits */
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsyncenum intel_descriptor_command {
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync /** Report status */
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync INTEL_DESC_CMD_RS = 0x08,
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync /** Insert frame checksum (CRC) */
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync INTEL_DESC_CMD_IFCS = 0x02,
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync /** End of packet */
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync INTEL_DESC_CMD_EOP = 0x01,
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync};
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync/** Packet descriptor status bits */
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsyncenum intel_descriptor_status {
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync /** Descriptor done */
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync INTEL_DESC_STATUS_DD = 0x01,
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync};
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync/** Device Control Register */
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync#define INTEL_CTRL 0x00000UL
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync#define INTEL_CTRL_LRST 0x00000008UL /**< Link reset */
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync#define INTEL_CTRL_ASDE 0x00000020UL /**< Auto-speed detection */
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync#define INTEL_CTRL_SLU 0x00000040UL /**< Set link up */
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync#define INTEL_CTRL_FRCSPD 0x00000800UL /**< Force speed */
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync#define INTEL_CTRL_FRCDPLX 0x00001000UL /**< Force duplex */
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync#define INTEL_CTRL_RST 0x04000000UL /**< Device reset */
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync#define INTEL_CTRL_PHY_RST 0x80000000UL /**< PHY reset */
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync/** Time to delay for device reset, in milliseconds */
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync#define INTEL_RESET_DELAY_MS 20
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync/** Device Status Register */
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync#define INTEL_STATUS 0x00008UL
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync#define INTEL_STATUS_LU 0x00000002UL /**< Link up */
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync/** EEPROM Read Register */
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync#define INTEL_EERD 0x00014UL
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync#define INTEL_EERD_START 0x00000001UL /**< Start read */
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync#define INTEL_EERD_DONE_SMALL 0x00000010UL /**< Read done (small EERD) */
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync#define INTEL_EERD_DONE_LARGE 0x00000002UL /**< Read done (large EERD) */
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync#define INTEL_EERD_ADDR_SHIFT_SMALL 8 /**< Address shift (small) */
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync#define INTEL_EERD_ADDR_SHIFT_LARGE 2 /**< Address shift (large) */
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync#define INTEL_EERD_DATA(value) ( (value) >> 16 ) /**< Read data */
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync/** Maximum time to wait for EEPROM read, in milliseconds */
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync#define INTEL_EEPROM_MAX_WAIT_MS 100
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync/** EEPROM word length */
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync#define INTEL_EEPROM_WORD_LEN_LOG2 1
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync/** Minimum EEPROM size, in words */
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync#define INTEL_EEPROM_MIN_SIZE_WORDS 64
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync/** Offset of MAC address within EEPROM */
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync#define INTEL_EEPROM_MAC 0x00
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync/** Interrupt Cause Read Register */
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync#define INTEL_ICR 0x000c0UL
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync#define INTEL_IRQ_TXDW 0x00000001UL /**< Transmit descriptor done */
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync#define INTEL_IRQ_LSC 0x00000004UL /**< Link status change */
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync#define INTEL_IRQ_RXT0 0x00000080UL /**< Receive timer */
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync/** Interrupt Mask Set/Read Register */
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync#define INTEL_IMS 0x000d0UL
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync/** Interrupt Mask Clear Register */
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync#define INTEL_IMC 0x000d8UL
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync/** Receive Control Register */
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync#define INTEL_RCTL 0x00100UL
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync#define INTEL_RCTL_EN 0x00000002UL /**< Receive enable */
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync#define INTEL_RCTL_UPE 0x00000008UL /**< Unicast promiscuous mode */
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync#define INTEL_RCTL_MPE 0x00000010UL /**< Multicast promiscuous */
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync#define INTEL_RCTL_BAM 0x00008000UL /**< Broadcast accept mode */
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync#define INTEL_RCTL_BSIZE_BSEX(bsex,bsize) \
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync ( ( (bsize) << 16 ) | ( (bsex) << 25 ) ) /**< Buffer size */
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync#define INTEL_RCTL_BSIZE_2048 INTEL_RCTL_BSIZE_BSEX ( 0, 0 )
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync#define INTEL_RCTL_BSIZE_BSEX_MASK INTEL_RCTL_BSIZE_BSEX ( 1, 3 )
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync#define INTEL_RCTL_SECRC 0x04000000UL /**< Strip CRC */
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync/** Transmit Control Register */
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync#define INTEL_TCTL 0x00400UL
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync#define INTEL_TCTL_EN 0x00000002UL /**< Transmit enable */
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync#define INTEL_TCTL_PSP 0x00000008UL /**< Pad short packets */
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync#define INTEL_TCTL_CT(x) ( (x) << 4 ) /**< Collision threshold */
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync#define INTEL_TCTL_CT_DEFAULT INTEL_TCTL_CT ( 0x0f )
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync#define INTEL_TCTL_CT_MASK INTEL_TCTL_CT ( 0xff )
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync#define INTEL_TCTL_COLD(x) ( (x) << 12 ) /**< Collision distance */
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync#define INTEL_TCTL_COLD_DEFAULT INTEL_TCTL_COLD ( 0x040 )
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync#define INTEL_TCTL_COLD_MASK INTEL_TCTL_COLD ( 0x3ff )
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync/** Packet Buffer Allocation */
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync#define INTEL_PBA 0x01000UL
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync/** Packet Buffer Size */
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync#define INTEL_PBS 0x01008UL
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync/** Receive Descriptor register block */
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync#define INTEL_RD 0x02800UL
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync/** Number of receive descriptors
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync *
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync * Minimum value is 8, since the descriptor ring length must be a
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync * multiple of 128.
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync */
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync#define INTEL_NUM_RX_DESC 8
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync/** Receive descriptor ring fill level */
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync#define INTEL_RX_FILL 4
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync/** Receive buffer length */
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync#define INTEL_RX_MAX_LEN 2048
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync/** Transmit Descriptor register block */
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync#define INTEL_TD 0x03800UL
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync/** Number of transmit descriptors
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync *
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync * Descriptor ring length must be a multiple of 16. ICH8/9/10
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync * requires a minimum of 16 TX descriptors.
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync */
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync#define INTEL_NUM_TX_DESC 16
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync/** Receive/Transmit Descriptor Base Address Low (offset) */
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync#define INTEL_xDBAL 0x00
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync/** Receive/Transmit Descriptor Base Address High (offset) */
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync#define INTEL_xDBAH 0x04
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync/** Receive/Transmit Descriptor Length (offset) */
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync#define INTEL_xDLEN 0x08
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync/** Receive/Transmit Descriptor Head (offset) */
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync#define INTEL_xDH 0x10
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync/** Receive/Transmit Descriptor Tail (offset) */
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync#define INTEL_xDT 0x18
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync/** Receive Descriptor Head */
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync#define INTEL_RDH ( INTEL_RD + INTEL_xDH )
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync/** Receive Descriptor Tail */
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync#define INTEL_RDT ( INTEL_RD + INTEL_xDT )
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync/** Transmit Descriptor Head */
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync#define INTEL_TDH ( INTEL_TD + INTEL_xDH )
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync/** Transmit Descriptor Tail */
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync#define INTEL_TDT ( INTEL_TD + INTEL_xDT )
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync/** Receive Address Low */
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync#define INTEL_RAL0 0x05400UL
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync/** Receive Address High */
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync#define INTEL_RAH0 0x05404UL
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync#define INTEL_RAH0_AV 0x80000000UL /**< Address valid */
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync/** Receive address */
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsyncunion intel_receive_address {
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync struct {
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync uint32_t low;
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync uint32_t high;
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync } __attribute__ (( packed )) reg;
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync uint8_t raw[ETH_ALEN];
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync};
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync/** An Intel descriptor ring */
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsyncstruct intel_ring {
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync /** Descriptors */
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync struct intel_descriptor *desc;
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync /** Producer index */
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync unsigned int prod;
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync /** Consumer index */
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync unsigned int cons;
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync /** Register block */
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync unsigned int reg;
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync /** Length (in bytes) */
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync size_t len;
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync};
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync/**
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync * Initialise descriptor ring
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync *
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync * @v ring Descriptor ring
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync * @v count Number of descriptors
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync * @v reg Descriptor register block
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync */
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsyncstatic inline __attribute__ (( always_inline)) void
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsyncintel_init_ring ( struct intel_ring *ring, unsigned int count,
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync unsigned int reg ) {
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync ring->len = ( count * sizeof ( ring->desc[0] ) );
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync ring->reg = reg;
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync}
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync/** An Intel network card */
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsyncstruct intel_nic {
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync /** Registers */
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync void *regs;
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync /** Port number (for multi-port devices) */
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync unsigned int port;
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync /** EEPROM */
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync struct nvs_device eeprom;
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync /** EEPROM done flag */
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync uint32_t eerd_done;
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync /** EEPROM address shift */
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync unsigned int eerd_addr_shift;
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync /** Transmit descriptor ring */
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync struct intel_ring tx;
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync /** Receive descriptor ring */
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync struct intel_ring rx;
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync /** Receive I/O buffers */
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync struct io_buffer *rx_iobuf[INTEL_NUM_RX_DESC];
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync};
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync#endif /* _INTEL_H */