drivers/net/forcedeth.h

a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync/*
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync *    forcedeth.h -- Driver for NVIDIA nForce media access controllers for iPXE
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync *    Copyright (c) 2010 Andrei Faur <da3drus@gmail.com>
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync *
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync *    This program is free software; you can redistribute it and/or
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync *    modify it under the terms of the GNU General Public License as
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync *    published by the Free Software Foundation; either version 2 of the
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync *    License, or any later version.
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync *
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync *    This program is distributed in the hope that it will be useful, but
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync *    WITHOUT ANY WARRANTY; without even the implied warranty of
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync *    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync *    General Public License for more details.
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync *
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync *    You should have received a copy of the GNU General Public License
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync *    along with this program; if not, write to the Free Software
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync *    Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync *
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync * Portions of this code are taken from the Linux forcedeth driver that was
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync * based on a cleanroom reimplementation which was based on reverse engineered
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync * documentation written by Carl-Daniel Hailfinger and Andrew de Quincey:
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync * Copyright (C) 2003,4,5 Manfred Spraul
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync * Copyright (C) 2004 Andrew de Quincey (wol support)
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync * Copyright (C) 2004 Carl-Daniel Hailfinger (invalid MAC handling, insane
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync *      IRQ rate fixes, bigendian fixes, cleanups, verification)
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync * Copyright (c) 2004,2005,2006,2007,2008,2009 NVIDIA Corporation
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync *
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync * This header is a direct copy of #define lines and structs found in the
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync * above mentioned driver, modified where necessary to make them work for iPXE.
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync *
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync */
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsyncFILE_LICENCE ( GPL2_OR_LATER );
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync#ifndef _FORCEDETH_H_
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync#define _FORCEDETH_H_
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsyncstruct ring_desc {
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync    u32 buf;
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync    u32 flaglen;
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync};
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsyncstruct ring_desc_ex {
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync    u32 bufhigh;
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync    u32 buflow;
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync    u32 txvlan;
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync    u32 flaglen;
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync};
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync#define DESC_VER_1  1
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync#define DESC_VER_2  2
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync#define DESC_VER_3  3
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync#define RX_RING_SIZE        16
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync#define TX_RING_SIZE        16
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync#define RXTX_RING_SIZE      ( ( RX_RING_SIZE ) + ( TX_RING_SIZE ) )
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync#define RX_RING_MIN     128
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync#define TX_RING_MIN     64
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync#define RING_MAX_DESC_VER_1 1024
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync#define RING_MAX_DESC_VER_2_3   16384
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync#define NV_RX_ALLOC_PAD (64)
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync#define NV_RX_HEADERS   (64)
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync#define RX_BUF_SZ       ( ( ETH_FRAME_LEN ) + ( NV_RX_HEADERS ) )
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync#define NV_PKTLIMIT_1   1500
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync#define NV_PKTLIMIT_2   9100
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync#define NV_LINK_POLL_FREQUENCY  128
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync/* PHY defines */
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync#define PHY_OUI_MARVELL     0x5043
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync#define PHY_OUI_CICADA      0x03f1
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync#define PHY_OUI_VITESSE     0x01c1
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync#define PHY_OUI_REALTEK     0x0732
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync#define PHY_OUI_REALTEK2    0x0020
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync#define PHYID1_OUI_MASK 0x03ff
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync#define PHYID1_OUI_SHFT 6
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync#define PHYID2_OUI_MASK 0xfc00
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync#define PHYID2_OUI_SHFT 10
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync#define PHYID2_MODEL_MASK       0x03f0
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync#define PHY_MODEL_REALTEK_8211      0x0110
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync#define PHY_REV_MASK            0x0001
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync#define PHY_REV_REALTEK_8211B       0x0000
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync#define PHY_REV_REALTEK_8211C       0x0001
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync#define PHY_MODEL_REALTEK_8201      0x0200
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync#define PHY_MODEL_MARVELL_E3016     0x0220
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync#define PHY_MARVELL_E3016_INITMASK  0x0300
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync#define PHY_CICADA_INIT1    0x0f000
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync#define PHY_CICADA_INIT2    0x0e00
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync#define PHY_CICADA_INIT3    0x01000
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync#define PHY_CICADA_INIT4    0x0200
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync#define PHY_CICADA_INIT5    0x0004
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync#define PHY_CICADA_INIT6    0x02000
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync#define PHY_VITESSE_INIT_REG1   0x1f
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync#define PHY_VITESSE_INIT_REG2   0x10
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync#define PHY_VITESSE_INIT_REG3   0x11
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync#define PHY_VITESSE_INIT_REG4   0x12
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync#define PHY_VITESSE_INIT_MSK1   0xc
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync#define PHY_VITESSE_INIT_MSK2   0x0180
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync#define PHY_VITESSE_INIT1   0x52b5
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync#define PHY_VITESSE_INIT2   0xaf8a
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync#define PHY_VITESSE_INIT3   0x8
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync#define PHY_VITESSE_INIT4   0x8f8a
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync#define PHY_VITESSE_INIT5   0xaf86
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync#define PHY_VITESSE_INIT6   0x8f86
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync#define PHY_VITESSE_INIT7   0xaf82
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync#define PHY_VITESSE_INIT8   0x0100
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync#define PHY_VITESSE_INIT9   0x8f82
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync#define PHY_VITESSE_INIT10  0x0
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync#define PHY_REALTEK_INIT_REG1   0x1f
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync#define PHY_REALTEK_INIT_REG2   0x19
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync#define PHY_REALTEK_INIT_REG3   0x13
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync#define PHY_REALTEK_INIT_REG4   0x14
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync#define PHY_REALTEK_INIT_REG5   0x18
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync#define PHY_REALTEK_INIT_REG6   0x11
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync#define PHY_REALTEK_INIT_REG7   0x01
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync#define PHY_REALTEK_INIT1   0x0000
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync#define PHY_REALTEK_INIT2   0x8e00
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync#define PHY_REALTEK_INIT3   0x0001
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync#define PHY_REALTEK_INIT4   0xad17
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync#define PHY_REALTEK_INIT5   0xfb54
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync#define PHY_REALTEK_INIT6   0xf5c7
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync#define PHY_REALTEK_INIT7   0x1000
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync#define PHY_REALTEK_INIT8   0x0003
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync#define PHY_REALTEK_INIT9   0x0008
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync#define PHY_REALTEK_INIT10  0x0005
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync#define PHY_REALTEK_INIT11  0x0200
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync#define PHY_REALTEK_INIT_MSK1   0x0003
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync#define PHY_GIGABIT 0x0100
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync#define PHY_TIMEOUT 0x1
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync#define PHY_ERROR   0x2
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync#define PHY_100 0x1
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync#define PHY_1000    0x2
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync#define PHY_HALF    0x100
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync#define NV_PAUSEFRAME_RX_CAPABLE    0x0001
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync#define NV_PAUSEFRAME_TX_CAPABLE    0x0002
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync#define NV_PAUSEFRAME_RX_ENABLE     0x0004
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync#define NV_PAUSEFRAME_TX_ENABLE     0x0008
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync#define NV_PAUSEFRAME_RX_REQ        0x0010
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync#define NV_PAUSEFRAME_TX_REQ        0x0020
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync#define NV_PAUSEFRAME_AUTONEG       0x0040
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync/* MSI/MSI-X defines */
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync#define NV_MSI_X_MAX_VECTORS  8
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync#define NV_MSI_X_VECTORS_MASK 0x000f
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync#define NV_MSI_CAPABLE        0x0010
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync#define NV_MSI_X_CAPABLE      0x0020
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync#define NV_MSI_ENABLED        0x0040
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync#define NV_MSI_X_ENABLED      0x0080
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync#define NV_MSI_X_VECTOR_ALL   0x0
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync#define NV_MSI_X_VECTOR_RX    0x0
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync#define NV_MSI_X_VECTOR_TX    0x1
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync#define NV_MSI_X_VECTOR_OTHER 0x2
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync#define NV_MSI_PRIV_OFFSET 0x68
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync#define NV_MSI_PRIV_VALUE  0xffffffff
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync#define NV_MIIBUSY_DELAY    50
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync#define NV_MIIPHY_DELAY     10
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync#define NV_MIIPHY_DELAYMAX  10000
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync/* Hardware access */
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync#define DEV_NEED_TIMERIRQ          0x0000001  /* set the timer irq flag in the irq mask */
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync#define DEV_NEED_LINKTIMER         0x0000002  /* poll link settings. Relies on the timer irq */
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync#define DEV_HAS_LARGEDESC          0x0000004  /* device supports jumbo frames and needs packet format 2 */
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync#define DEV_HAS_HIGH_DMA           0x0000008  /* device supports 64bit dma */
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync#define DEV_HAS_CHECKSUM           0x0000010  /* device supports tx and rx checksum offloads */
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync#define DEV_HAS_VLAN               0x0000020  /* device supports vlan tagging and striping */
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync#define DEV_HAS_MSI                0x0000040  /* device supports MSI */
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync#define DEV_HAS_MSI_X              0x0000080  /* device supports MSI-X */
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync#define DEV_HAS_POWER_CNTRL        0x0000100  /* device supports power savings */
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync#define DEV_HAS_STATISTICS_V1      0x0000200  /* device supports hw statistics version 1 */
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync#define DEV_HAS_STATISTICS_V2      0x0000600  /* device supports hw statistics version 2 */
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync#define DEV_HAS_STATISTICS_V3      0x0000e00  /* device supports hw statistics version 3 */
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync#define DEV_HAS_TEST_EXTENDED      0x0001000  /* device supports extended diagnostic test */
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync#define DEV_HAS_MGMT_UNIT          0x0002000  /* device supports management unit */
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync#define DEV_HAS_CORRECT_MACADDR    0x0004000  /* device supports correct mac address order */
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync#define DEV_HAS_COLLISION_FIX      0x0008000  /* device supports tx collision fix */
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync#define DEV_HAS_PAUSEFRAME_TX_V1   0x0010000  /* device supports tx pause frames version 1 */
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync#define DEV_HAS_PAUSEFRAME_TX_V2   0x0020000  /* device supports tx pause frames version 2 */
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync#define DEV_HAS_PAUSEFRAME_TX_V3   0x0040000  /* device supports tx pause frames version 3 */
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync#define DEV_NEED_TX_LIMIT          0x0080000  /* device needs to limit tx */
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync#define DEV_NEED_TX_LIMIT2         0x0180000  /* device needs to limit tx, expect for some revs */
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync#define DEV_HAS_GEAR_MODE          0x0200000  /* device supports gear mode */
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync#define DEV_NEED_PHY_INIT_FIX      0x0400000  /* device needs specific phy workaround */
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync#define DEV_NEED_LOW_POWER_FIX     0x0800000  /* device needs special power up workaround */
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync#define DEV_NEED_MSI_FIX           0x1000000  /* device needs msi workaround */
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync#define FLAG_MASK_V1 0xffff0000
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync#define FLAG_MASK_V2 0xffffc000
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync#define LEN_MASK_V1 (0xffffffff ^ FLAG_MASK_V1)
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync#define LEN_MASK_V2 (0xffffffff ^ FLAG_MASK_V2)
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync#define NV_TX_LASTPACKET    (1<<16)
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync#define NV_TX_RETRYERROR    (1<<19)
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync#define NV_TX_RETRYCOUNT_MASK   (0xF<<20)
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync#define NV_TX_FORCED_INTERRUPT  (1<<24)
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync#define NV_TX_DEFERRED      (1<<26)
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync#define NV_TX_CARRIERLOST   (1<<27)
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync#define NV_TX_LATECOLLISION (1<<28)
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync#define NV_TX_UNDERFLOW     (1<<29)
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync#define NV_TX_ERROR     (1<<30)
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync#define NV_TX_VALID     (1<<31)
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync#define NV_TX2_LASTPACKET   (1<<29)
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync#define NV_TX2_RETRYERROR   (1<<18)
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync#define NV_TX2_RETRYCOUNT_MASK  (0xF<<19)
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync#define NV_TX2_FORCED_INTERRUPT (1<<30)
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync#define NV_TX2_DEFERRED     (1<<25)
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync#define NV_TX2_CARRIERLOST  (1<<26)
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync#define NV_TX2_LATECOLLISION    (1<<27)
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync#define NV_TX2_UNDERFLOW    (1<<28)
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync/* error and valid are the same for both */
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync#define NV_TX2_ERROR        (1<<30)
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync#define NV_TX2_VALID        (1<<31)
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync#define NV_TX2_TSO      (1<<28)
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync#define NV_TX2_TSO_SHIFT    14
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync#define NV_TX2_TSO_MAX_SHIFT    14
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync#define NV_TX2_TSO_MAX_SIZE (1<<NV_TX2_TSO_MAX_SHIFT)
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync#define NV_TX2_CHECKSUM_L3  (1<<27)
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync#define NV_TX2_CHECKSUM_L4  (1<<26)
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync#define NV_TX3_VLAN_TAG_PRESENT (1<<18)
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync#define NV_RX_DESCRIPTORVALID   (1<<16)
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync#define NV_RX_MISSEDFRAME   (1<<17)
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync#define NV_RX_SUBSTRACT1    (1<<18)
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync#define NV_RX_ERROR1        (1<<23)
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync#define NV_RX_ERROR2        (1<<24)
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync#define NV_RX_ERROR3        (1<<25)
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync#define NV_RX_ERROR4        (1<<26)
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync#define NV_RX_CRCERR        (1<<27)
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync#define NV_RX_OVERFLOW      (1<<28)
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync#define NV_RX_FRAMINGERR    (1<<29)
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync#define NV_RX_ERROR     (1<<30)
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync#define NV_RX_AVAIL     (1<<31)
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync#define NV_RX_ERROR_MASK    (NV_RX_ERROR1|NV_RX_ERROR2|NV_RX_ERROR3|NV_RX_ERROR4|NV_RX_CRCERR|NV_RX_OVERFLOW|NV_RX_FRAMINGERR)
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync#define NV_RX2_CHECKSUMMASK (0x1C000000)
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync#define NV_RX2_CHECKSUM_IP  (0x10000000)
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync#define NV_RX2_CHECKSUM_IP_TCP  (0x14000000)
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync#define NV_RX2_CHECKSUM_IP_UDP  (0x18000000)
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync#define NV_RX2_DESCRIPTORVALID  (1<<29)
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync#define NV_RX2_SUBSTRACT1   (1<<25)
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync#define NV_RX2_ERROR1       (1<<18)
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync#define NV_RX2_ERROR2       (1<<19)
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync#define NV_RX2_ERROR3       (1<<20)
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync#define NV_RX2_ERROR4       (1<<21)
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync#define NV_RX2_CRCERR       (1<<22)
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync#define NV_RX2_OVERFLOW     (1<<23)
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync#define NV_RX2_FRAMINGERR   (1<<24)
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync/* error and avail are the same for both */
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync#define NV_RX2_ERROR        (1<<30)
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync#define NV_RX2_AVAIL        (1<<31)
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync#define NV_RX2_ERROR_MASK   (NV_RX2_ERROR1|NV_RX2_ERROR2|NV_RX2_ERROR3|NV_RX2_ERROR4|NV_RX2_CRCERR|NV_RX2_OVERFLOW|NV_RX2_FRAMINGERR)
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync#define NV_RX3_VLAN_TAG_PRESENT (1<<16)
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync#define NV_RX3_VLAN_TAG_MASK    (0x0000FFFF)
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync/* Miscellaneous hardware related defines */
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync#define NV_PCI_REGSZ_VER1   0x270
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync#define NV_PCI_REGSZ_VER2   0x2d4
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync#define NV_PCI_REGSZ_VER3   0x604
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync#define NV_PCI_REGSZ_MAX    0x604
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync/* various timeout delays: all in usec */
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync#define NV_TXRX_RESET_DELAY 4
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync#define NV_TXSTOP_DELAY1    10
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync#define NV_TXSTOP_DELAY1MAX 500000
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync#define NV_TXSTOP_DELAY2    100
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync#define NV_RXSTOP_DELAY1    10
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync#define NV_RXSTOP_DELAY1MAX 500000
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync#define NV_RXSTOP_DELAY2    100
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync#define NV_SETUP5_DELAY     5
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync#define NV_SETUP5_DELAYMAX  50000
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync#define NV_POWERUP_DELAY    5
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync#define NV_POWERUP_DELAYMAX 5000
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync#define NV_MIIBUSY_DELAY    50
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync#define NV_MIIPHY_DELAY 10
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync#define NV_MIIPHY_DELAYMAX  10000
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync#define NV_MAC_RESET_DELAY  64
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync#define NV_MSI_X_CAPABLE    0x0020
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync#define MII_READ    (-1)
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsyncstruct forcedeth_private {
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync    struct pci_device *pci_dev;
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync    struct net_device *netdev;
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync    void *mmio_addr;
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync    u32 linkspeed;
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync    int duplex;
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync    int phyaddr;
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync    unsigned int phy_oui;
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync    unsigned int phy_rev;
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync    unsigned int phy_model;
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync    u16 gigabit;
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync    u32 mac_in_use;
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync    int mgmt_version;
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync    int mgmt_sema;
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync    /* rx specific fields */
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync    struct ring_desc *rx_ring;
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync    struct io_buffer *rx_iobuf[RX_RING_SIZE];
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync    int rx_curr;
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync    /* tx specific fields */
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync    struct ring_desc *tx_ring;
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync    struct io_buffer *tx_iobuf[TX_RING_SIZE];
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync    int tx_fill_ctr;
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync    int tx_curr;
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync    int tx_tail;
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync    /* flow control */
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync    u32 pause_flags;
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync    unsigned long driver_data;
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync};
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsyncenum {
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync    NvRegIrqStatus = 0x000,
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync#define NVREG_IRQSTAT_MIIEVENT  0x040
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync#define NVREG_IRQSTAT_MASK      0x83ff
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync    NvRegIrqMask = 0x004,
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync#define NVREG_IRQ_RX_ERROR      0x0001
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync#define NVREG_IRQ_RX            0x0002
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync#define NVREG_IRQ_RX_NOBUF      0x0004
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync#define NVREG_IRQ_TX_ERR        0x0008
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync#define NVREG_IRQ_TX_OK         0x0010
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync#define NVREG_IRQ_TIMER         0x0020
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync#define NVREG_IRQ_LINK          0x0040
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync#define NVREG_IRQ_RX_FORCED     0x0080
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync#define NVREG_IRQ_TX_FORCED     0x0100
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync#define NVREG_IRQ_RECOVER_ERROR     0x8200
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync#define NVREG_IRQMASK_THROUGHPUT    0x00df
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync#define NVREG_IRQMASK_CPU       0x0060
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync#define NVREG_IRQ_TX_ALL        (NVREG_IRQ_TX_ERR|NVREG_IRQ_TX_OK|NVREG_IRQ_TX_FORCED)
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync#define NVREG_IRQ_RX_ALL        (NVREG_IRQ_RX_ERROR|NVREG_IRQ_RX|NVREG_IRQ_RX_NOBUF|NVREG_IRQ_RX_FORCED)
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync#define NVREG_IRQ_OTHER         (NVREG_IRQ_TIMER|NVREG_IRQ_LINK|NVREG_IRQ_RECOVER_ERROR)
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync    NvRegUnknownSetupReg6 = 0x008,
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync#define NVREG_UNKSETUP6_VAL     3
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync/*
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync * NVREG_POLL_DEFAULT is the interval length of the timer source on the nic
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync * NVREG_POLL_DEFAULT=97 would result in an interval length of 1 ms
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync */
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync    NvRegPollingInterval = 0x00c,
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync#define NVREG_POLL_DEFAULT_THROUGHPUT   65535 /* backup tx cleanup if loop max reached */
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync#define NVREG_POLL_DEFAULT_CPU  13
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync    NvRegMSIMap0 = 0x020,
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync    NvRegMSIMap1 = 0x024,
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync    NvRegMSIIrqMask = 0x030,
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync#define NVREG_MSI_VECTOR_0_ENABLED 0x01
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync    NvRegMisc1 = 0x080,
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync#define NVREG_MISC1_PAUSE_TX    0x01
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync#define NVREG_MISC1_HD      0x02
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync#define NVREG_MISC1_FORCE   0x3b0f3c
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync    NvRegMacReset = 0x34,
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync#define NVREG_MAC_RESET_ASSERT  0x0F3
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync    NvRegTransmitterControl = 0x084,
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync#define NVREG_XMITCTL_START 0x01
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync#define NVREG_XMITCTL_MGMT_ST   0x40000000
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync#define NVREG_XMITCTL_SYNC_MASK     0x000f0000
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync#define NVREG_XMITCTL_SYNC_NOT_READY    0x0
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync#define NVREG_XMITCTL_SYNC_PHY_INIT 0x00040000
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync#define NVREG_XMITCTL_MGMT_SEMA_MASK    0x00000f00
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync#define NVREG_XMITCTL_MGMT_SEMA_FREE    0x0
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync#define NVREG_XMITCTL_HOST_SEMA_MASK    0x0000f000
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync#define NVREG_XMITCTL_HOST_SEMA_ACQ 0x0000f000
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync#define NVREG_XMITCTL_HOST_LOADED   0x00004000
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync#define NVREG_XMITCTL_TX_PATH_EN    0x01000000
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync#define NVREG_XMITCTL_DATA_START    0x00100000
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync#define NVREG_XMITCTL_DATA_READY    0x00010000
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync#define NVREG_XMITCTL_DATA_ERROR    0x00020000
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync    NvRegTransmitterStatus = 0x088,
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync#define NVREG_XMITSTAT_BUSY 0x01
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync    NvRegPacketFilterFlags = 0x8c,
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync#define NVREG_PFF_PAUSE_RX  0x08
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync#define NVREG_PFF_ALWAYS    0x7F0000
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync#define NVREG_PFF_PROMISC   0x80
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync#define NVREG_PFF_MYADDR    0x20
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync#define NVREG_PFF_LOOPBACK  0x10
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync    NvRegOffloadConfig = 0x90,
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync#define NVREG_OFFLOAD_HOMEPHY   0x601
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync#define NVREG_OFFLOAD_NORMAL    RX_NIC_BUFSIZE
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync    NvRegReceiverControl = 0x094,
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync#define NVREG_RCVCTL_START  0x01
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync#define NVREG_RCVCTL_RX_PATH_EN 0x01000000
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync    NvRegReceiverStatus = 0x98,
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync#define NVREG_RCVSTAT_BUSY  0x01
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync    NvRegSlotTime = 0x9c,
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync#define NVREG_SLOTTIME_LEGBF_ENABLED    0x80000000
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync#define NVREG_SLOTTIME_10_100_FULL  0x00007f00
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync#define NVREG_SLOTTIME_1000_FULL    0x0003ff00
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync#define NVREG_SLOTTIME_HALF     0x0000ff00
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync#define NVREG_SLOTTIME_DEFAULT      0x00007f00
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync#define NVREG_SLOTTIME_MASK     0x000000ff
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync    NvRegTxDeferral = 0xA0,
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync#define NVREG_TX_DEFERRAL_DEFAULT       0x15050f
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync#define NVREG_TX_DEFERRAL_RGMII_10_100      0x16070f
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync#define NVREG_TX_DEFERRAL_RGMII_1000        0x14050f
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync#define NVREG_TX_DEFERRAL_RGMII_STRETCH_10  0x16190f
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync#define NVREG_TX_DEFERRAL_RGMII_STRETCH_100 0x16300f
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync#define NVREG_TX_DEFERRAL_MII_STRETCH       0x152000
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync    NvRegRxDeferral = 0xA4,
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync#define NVREG_RX_DEFERRAL_DEFAULT   0x16
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync    NvRegMacAddrA = 0xA8,
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync    NvRegMacAddrB = 0xAC,
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync    NvRegMulticastAddrA = 0xB0,
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync#define NVREG_MCASTADDRA_FORCE  0x01
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync    NvRegMulticastAddrB = 0xB4,
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync    NvRegMulticastMaskA = 0xB8,
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync#define NVREG_MCASTMASKA_NONE       0xffffffff
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync    NvRegMulticastMaskB = 0xBC,
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync#define NVREG_MCASTMASKB_NONE       0xffff
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync    NvRegPhyInterface = 0xC0,
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync#define PHY_RGMII       0x10000000
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync    NvRegBackOffControl = 0xC4,
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync#define NVREG_BKOFFCTRL_DEFAULT         0x70000000
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync#define NVREG_BKOFFCTRL_SEED_MASK       0x000003ff
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync#define NVREG_BKOFFCTRL_SELECT          24
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync#define NVREG_BKOFFCTRL_GEAR            12
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync    NvRegTxRingPhysAddr = 0x100,
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync    NvRegRxRingPhysAddr = 0x104,
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync    NvRegRingSizes = 0x108,
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync#define NVREG_RINGSZ_TXSHIFT 0
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync#define NVREG_RINGSZ_RXSHIFT 16
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync    NvRegTransmitPoll = 0x10c,
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync#define NVREG_TRANSMITPOLL_MAC_ADDR_REV 0x00008000
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync    NvRegLinkSpeed = 0x110,
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync#define NVREG_LINKSPEED_FORCE 0x10000
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync#define NVREG_LINKSPEED_10  1000
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync#define NVREG_LINKSPEED_100 100
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync#define NVREG_LINKSPEED_1000    50
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync#define NVREG_LINKSPEED_MASK    (0xFFF)
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync    NvRegUnknownSetupReg5 = 0x130,
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync#define NVREG_UNKSETUP5_BIT31   (1<<31)
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync    NvRegTxWatermark = 0x13c,
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync#define NVREG_TX_WM_DESC1_DEFAULT   0x0200010
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync#define NVREG_TX_WM_DESC2_3_DEFAULT 0x1e08000
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync#define NVREG_TX_WM_DESC2_3_1000    0xfe08000
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync    NvRegTxRxControl = 0x144,
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync#define NVREG_TXRXCTL_KICK  0x0001
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync#define NVREG_TXRXCTL_BIT1  0x0002
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync#define NVREG_TXRXCTL_BIT2  0x0004
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync#define NVREG_TXRXCTL_IDLE  0x0008
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync#define NVREG_TXRXCTL_RESET 0x0010
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync#define NVREG_TXRXCTL_RXCHECK   0x0400
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync#define NVREG_TXRXCTL_DESC_1    0
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync#define NVREG_TXRXCTL_DESC_2    0x002100
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync#define NVREG_TXRXCTL_DESC_3    0xc02200
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync#define NVREG_TXRXCTL_VLANSTRIP 0x00040
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync#define NVREG_TXRXCTL_VLANINS   0x00080
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync    NvRegTxRingPhysAddrHigh = 0x148,
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync    NvRegRxRingPhysAddrHigh = 0x14C,
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync    NvRegTxPauseFrame = 0x170,
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync#define NVREG_TX_PAUSEFRAME_DISABLE 0x0fff0080
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync#define NVREG_TX_PAUSEFRAME_ENABLE_V1   0x01800010
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync#define NVREG_TX_PAUSEFRAME_ENABLE_V2   0x056003f0
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync#define NVREG_TX_PAUSEFRAME_ENABLE_V3   0x09f00880
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync    NvRegTxPauseFrameLimit = 0x174,
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync#define NVREG_TX_PAUSEFRAMELIMIT_ENABLE 0x00010000
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync    NvRegMIIStatus = 0x180,
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync#define NVREG_MIISTAT_ERROR     0x0001
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync#define NVREG_MIISTAT_LINKCHANGE    0x0008
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync#define NVREG_MIISTAT_MASK_RW       0x0007
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync#define NVREG_MIISTAT_MASK_ALL      0x000f
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync    NvRegMIIMask = 0x184,
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync#define NVREG_MII_LINKCHANGE        0x0008
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync    NvRegAdapterControl = 0x188,
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync#define NVREG_ADAPTCTL_START    0x02
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync#define NVREG_ADAPTCTL_LINKUP   0x04
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync#define NVREG_ADAPTCTL_PHYVALID 0x40000
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync#define NVREG_ADAPTCTL_RUNNING  0x100000
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync#define NVREG_ADAPTCTL_PHYSHIFT 24
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync    NvRegMIISpeed = 0x18c,
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync#define NVREG_MIISPEED_BIT8 (1<<8)
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync#define NVREG_MIIDELAY  5
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync    NvRegMIIControl = 0x190,
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync#define NVREG_MIICTL_INUSE  0x08000
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync#define NVREG_MIICTL_WRITE  0x00400
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync#define NVREG_MIICTL_ADDRSHIFT  5
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync    NvRegMIIData = 0x194,
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync    NvRegTxUnicast = 0x1a0,
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync    NvRegTxMulticast = 0x1a4,
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync    NvRegTxBroadcast = 0x1a8,
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync    NvRegWakeUpFlags = 0x200,
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync#define NVREG_WAKEUPFLAGS_VAL       0x7770
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync#define NVREG_WAKEUPFLAGS_BUSYSHIFT 24
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync#define NVREG_WAKEUPFLAGS_ENABLESHIFT   16
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync#define NVREG_WAKEUPFLAGS_D3SHIFT   12
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync#define NVREG_WAKEUPFLAGS_D2SHIFT   8
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync#define NVREG_WAKEUPFLAGS_D1SHIFT   4
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync#define NVREG_WAKEUPFLAGS_D0SHIFT   0
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync#define NVREG_WAKEUPFLAGS_ACCEPT_MAGPAT     0x01
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync#define NVREG_WAKEUPFLAGS_ACCEPT_WAKEUPPAT  0x02
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync#define NVREG_WAKEUPFLAGS_ACCEPT_LINKCHANGE 0x04
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync#define NVREG_WAKEUPFLAGS_ENABLE    0x1111
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync    NvRegMgmtUnitGetVersion = 0x204,
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync#define NVREG_MGMTUNITGETVERSION        0x01
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync    NvRegMgmtUnitVersion = 0x208,
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync#define NVREG_MGMTUNITVERSION       0x08
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync    NvRegPowerCap = 0x268,
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync#define NVREG_POWERCAP_D3SUPP   (1<<30)
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync#define NVREG_POWERCAP_D2SUPP   (1<<26)
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync#define NVREG_POWERCAP_D1SUPP   (1<<25)
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync    NvRegPowerState = 0x26c,
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync#define NVREG_POWERSTATE_POWEREDUP  0x8000
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync#define NVREG_POWERSTATE_VALID      0x0100
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync#define NVREG_POWERSTATE_MASK       0x0003
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync#define NVREG_POWERSTATE_D0     0x0000
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync#define NVREG_POWERSTATE_D1     0x0001
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync#define NVREG_POWERSTATE_D2     0x0002
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync#define NVREG_POWERSTATE_D3     0x0003
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync    NvRegMgmtUnitControl = 0x278,
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync#define NVREG_MGMTUNITCONTROL_INUSE 0x20000
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync    NvRegTxCnt = 0x280,
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync    NvRegTxZeroReXmt = 0x284,
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync    NvRegTxOneReXmt = 0x288,
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync    NvRegTxManyReXmt = 0x28c,
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync    NvRegTxLateCol = 0x290,
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync    NvRegTxUnderflow = 0x294,
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync    NvRegTxLossCarrier = 0x298,
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync    NvRegTxExcessDef = 0x29c,
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync    NvRegTxRetryErr = 0x2a0,
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync    NvRegRxFrameErr = 0x2a4,
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync    NvRegRxExtraByte = 0x2a8,
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync    NvRegRxLateCol = 0x2ac,
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync    NvRegRxRunt = 0x2b0,
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync    NvRegRxFrameTooLong = 0x2b4,
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync    NvRegRxOverflow = 0x2b8,
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync    NvRegRxFCSErr = 0x2bc,
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync    NvRegRxFrameAlignErr = 0x2c0,
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync    NvRegRxLenErr = 0x2c4,
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync    NvRegRxUnicast = 0x2c8,
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync    NvRegRxMulticast = 0x2cc,
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync    NvRegRxBroadcast = 0x2d0,
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync    NvRegTxDef = 0x2d4,
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync    NvRegTxFrame = 0x2d8,
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync    NvRegRxCnt = 0x2dc,
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync    NvRegTxPause = 0x2e0,
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync    NvRegRxPause = 0x2e4,
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync    NvRegRxDropFrame = 0x2e8,
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync    NvRegVlanControl = 0x300,
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync#define NVREG_VLANCONTROL_ENABLE    0x2000
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync    NvRegMSIXMap0 = 0x3e0,
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync    NvRegMSIXMap1 = 0x3e4,
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync    NvRegMSIXIrqStatus = 0x3f0,
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync    NvRegPowerState2 = 0x600,
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync#define NVREG_POWERSTATE2_POWERUP_MASK      0x0F15
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync#define NVREG_POWERSTATE2_POWERUP_REV_A3    0x0001
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync#define NVREG_POWERSTATE2_PHY_RESET     0x0004
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync#define NVREG_POWERSTATE2_GATE_CLOCKS       0x0F00
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync};
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsyncenum {
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync    NV_OPTIMIZATION_MODE_THROUGHPUT,
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync    NV_OPTIMIZATION_MODE_CPU,
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync    NV_OPTIMIZATION_MODE_DYNAMIC
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync};
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsyncenum {
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync    NV_CROSSOVER_DETECTION_DISABLED,
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync    NV_CROSSOVER_DETECTION_ENABLED
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync};
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync#define NV_SETUP_RX_RING    0x01
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync#define NV_SETUP_TX_RING    0x02
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync#define NV_RESTART_TX       0x1
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync#define NV_RESTART_RX       0x2
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync
a734c64bff58bda2fa48c2795453e092167b0ff7vboxsync#endif /* _FORCEDETH_H_ */