hw.h revision a734c64bff58bda2fa48c2795453e092167b0ff7
/*
* Copyright (c) 2008-2011 Atheros Communications Inc.
*
* Modified for iPXE by Scott K Logan <logans@cottsay.net> July 2011
* Original from Linux kernel 3.0.1
*
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
#ifndef HW_H
#define HW_H
#include <errno.h>
#include "mac.h"
#include "ani.h"
#include "eeprom.h"
#include "calib.h"
#include "reg.h"
#include "phy.h"
#include "../regd.h"
/* Keep all ath9k files under one errfile ID */
#define ERRFILE ERRFILE_ath9k
#define ATHEROS_VENDOR_ID 0x168c
#define AR5416_DEVID_PCI 0x0023
#define AR5416_DEVID_PCIE 0x0024
#define AR9160_DEVID_PCI 0x0027
#define AR9280_DEVID_PCI 0x0029
#define AR9280_DEVID_PCIE 0x002a
#define AR9285_DEVID_PCIE 0x002b
#define AR2427_DEVID_PCIE 0x002c
#define AR9287_DEVID_PCI 0x002d
#define AR9287_DEVID_PCIE 0x002e
#define AR9300_DEVID_PCIE 0x0030
#define AR9300_DEVID_AR9340 0x0031
#define AR9300_DEVID_AR9485_PCIE 0x0032
#define AR5416_AR9100_DEVID 0x000b
#define AR_SUBVENDOR_ID_NOG 0x0e11
#define AR_SUBVENDOR_ID_NEW_A 0x7065
#define AR5416_MAGIC 0x19641014
#define AR9280_COEX2WIRE_SUBSYSID 0x309b
#define AT9285_COEX3WIRE_SA_SUBSYSID 0x30aa
#define AT9285_COEX3WIRE_DA_SUBSYSID 0x30ab
#define AR9300_NUM_BT_WEIGHTS 4
#define AR9300_NUM_WLAN_WEIGHTS 4
#define ATH_DEFAULT_NOISE_FLOOR -95
#define ATH9K_RSSI_BAD -128
#define ATH9K_NUM_CHANNELS 38
#define ENABLE_REGWRITE_BUFFER(_ah) \
do { \
} while (0)
#define REGWRITE_BUFFER_FLUSH(_ah) \
do { \
} while (0)
#define DO_DELAY(x) do { \
if (((++(x) % 64) == 0) && \
!= ATH_USB)) \
udelay(1); \
} while (0)
#define AR_GPIO_OUTPUT_MUX_AS_OUTPUT 0
#define AR_GPIO_OUTPUT_MUX_AS_PCIE_ATTENTION_LED 1
#define AR_GPIO_OUTPUT_MUX_AS_PCIE_POWER_LED 2
#define AR_GPIO_OUTPUT_MUX_AS_TX_FRAME 3
#define AR_GPIO_OUTPUT_MUX_AS_RX_CLEAR_EXTERNAL 4
#define AR_GPIO_OUTPUT_MUX_AS_MAC_NETWORK_LED 5
#define AR_GPIO_OUTPUT_MUX_AS_MAC_POWER_LED 6
#define AR_GPIOD_MASK 0x00001FFF
#define BASE_ACTIVATE_DELAY 100
#define COEF_SCALE_S 24
#define HT40_CHANNEL_CENTER_SHIFT 10
#define ATH9K_ANTENNA0_CHAINMASK 0x1
#define ATH9K_ANTENNA1_CHAINMASK 0x2
#define ATH9K_NUM_DMA_DEBUG_REGS 8
#define ATH9K_NUM_QUEUES 10
#define MAX_RATE_POWER 63
#define AH_TIME_QUANTUM 10
#define AR_KEYTABLE_SIZE 128
#define POWER_UP_TIME 10000
#define SPUR_RSSI_THRESH 40
#define CAB_TIMEOUT_VAL 10
#define BEACON_TIMEOUT_VAL 10
#define MIN_BEACON_TIMEOUT_VAL 1
#define SLEEP_SLOP 3
#define INIT_CONFIG_STATUS 0x00000000
#define INIT_RSSI_THR 0x00000700
#define INIT_BCON_CNTRL_REG 0x00000000
#define ATH9K_HW_RX_HP_QDEPTH 16
#define ATH9K_HW_RX_LP_QDEPTH 128
#define PAPRD_GAIN_TABLE_ENTRIES 32
#define PAPRD_TABLE_SZ 24
enum ath_hw_txq_subtype {
ATH_TXQ_AC_BE = 0,
};
enum ath_ini_subsys {
ATH_INI_PRE = 0,
};
enum ath9k_hw_caps {
ATH9K_HW_CAP_HT = BIT(0),
};
struct ath9k_hw_capabilities {
int pcie_lcr_extsync_en;
};
struct ath9k_ops_config {
int ack_6mb;
int pcieSerDesWrite;
int serialize_regmode;
int rx_intr_mitigation;
int tx_intr_mitigation;
#define SPUR_DISABLE 0
#define SPUR_ENABLE_IOCTL 1
#define SPUR_ENABLE_EEPROM 2
#define AR_SPUR_5413_1 1640
#define AR_SPUR_5413_2 1200
#define AR_NO_SPUR 0x8000
#define AR_BASE_FREQ_2GHZ 2300
#define AR_BASE_FREQ_5GHZ 4900
#define AR_SPUR_FEEQ_BOUND_HT40 19
#define AR_SPUR_FEEQ_BOUND_HT20 10
int spurmode;
};
enum ath9k_int {
ATH9K_INT_RX = 0x00000001,
ATH9K_INT_RXDESC = 0x00000002,
ATH9K_INT_RXHP = 0x00000001,
ATH9K_INT_RXLP = 0x00000002,
ATH9K_INT_RXNOFRM = 0x00000008,
ATH9K_INT_RXEOL = 0x00000010,
ATH9K_INT_RXORN = 0x00000020,
ATH9K_INT_TX = 0x00000040,
ATH9K_INT_TXDESC = 0x00000080,
ATH9K_INT_TIM_TIMER = 0x00000100,
ATH9K_INT_BB_WATCHDOG = 0x00000400,
ATH9K_INT_TXURN = 0x00000800,
ATH9K_INT_MIB = 0x00001000,
ATH9K_INT_RXPHY = 0x00004000,
ATH9K_INT_RXKCM = 0x00008000,
ATH9K_INT_SWBA = 0x00010000,
ATH9K_INT_BMISS = 0x00040000,
ATH9K_INT_BNR = 0x00100000,
ATH9K_INT_TIM = 0x00200000,
ATH9K_INT_DTIM = 0x00400000,
ATH9K_INT_DTIMSYNC = 0x00800000,
ATH9K_INT_GPIO = 0x01000000,
ATH9K_INT_CABEND = 0x02000000,
ATH9K_INT_TSFOOR = 0x04000000,
ATH9K_INT_GENTIMER = 0x08000000,
ATH9K_INT_CST = 0x10000000,
ATH9K_INT_GTT = 0x20000000,
ATH9K_INT_FATAL = 0x40000000,
ATH9K_INT_GLOBAL = 0x80000000,
ATH9K_INT_NOCARD = 0xffffffff
};
#define CHANNEL_CW_INT 0x00002
#define CHANNEL_CCK 0x00020
#define CHANNEL_OFDM 0x00040
#define CHANNEL_2GHZ 0x00080
#define CHANNEL_5GHZ 0x00100
#define CHANNEL_PASSIVE 0x00200
#define CHANNEL_DYN 0x00400
#define CHANNEL_HALF 0x04000
#define CHANNEL_QUARTER 0x08000
#define CHANNEL_HT20 0x10000
#define CHANNEL_HT40PLUS 0x20000
#define CHANNEL_HT40MINUS 0x40000
#define CHANNEL_ALL \
(CHANNEL_OFDM| \
CHANNEL_CCK| \
CHANNEL_2GHZ | \
CHANNEL_5GHZ | \
CHANNEL_HT20 | \
CHANNEL_HT40PLUS | \
struct ath9k_hw_cal_data {
int paprd_done;
int nfcal_pending;
int nfcal_interference;
};
struct ath9k_channel {
struct net80211_channel *chan;
struct ar5416AniState ani;
};
/* These macros check chanmode and not channelFlags */
enum ath9k_power_mode {
ATH9K_PM_AWAKE = 0,
};
enum ath9k_tp_scale {
ATH9K_TP_SCALE_MAX = 0,
};
enum ser_reg_mode {
SER_REG_MODE_OFF = 0,
SER_REG_MODE_ON = 1,
SER_REG_MODE_AUTO = 2,
};
enum ath9k_rx_qtype {
};
struct ath9k_beacon_state {
#define ATH9K_BEACON_PERIOD 0x0000ffff
};
struct chan_centers {
};
enum {
};
struct ath9k_hw_version {
enum ath_usb_dev usbdev;
};
/* Generic TSF timer definitions */
#define ATH_MAX_GEN_TIMER 16
/*
* Using de Bruijin sequence to look up 1's index in a 32 bit number
* debruijn32 = 0000 0111 0111 1100 1011 0101 0011 0001
*/
#define debruijn32 0x077CB531U
struct ath_gen_timer_configuration {
};
struct ath_gen_timer {
void *arg;
};
struct ath_gen_timer_table {
union {
unsigned long timer_bits;
} timer_mask;
};
struct ath_hw_antcomb_conf {
int lna1_lna2_delta;
};
/**
* struct ath_hw_radar_conf - radar detection initialization parameters
*
* @pulse_inband: threshold for checking the ratio of in-band power
* to total power for short radar pulses (half dB steps)
* @pulse_inband_step: threshold for checking an in-band power to total
* power ratio increase for short radar pulses (half dB steps)
* @pulse_height: threshold for detecting the beginning of a short
* radar pulse (dB step)
* @pulse_rssi: threshold for detecting if a short radar pulse is
* gone (dB step)
* @pulse_maxlen: maximum pulse length (0.8 us steps)
*
* @radar_rssi: RSSI threshold for starting long radar detection (dB steps)
* @radar_inband: threshold for checking the ratio of in-band power
* to total power for long radar pulses (half dB steps)
* @fir_power: threshold for detecting the end of a long radar pulse (dB)
*
* @ext_channel: enable extension channel radar detection
*/
struct ath_hw_radar_conf {
unsigned int pulse_inband;
unsigned int pulse_inband_step;
unsigned int pulse_height;
unsigned int pulse_rssi;
unsigned int pulse_maxlen;
unsigned int radar_rssi;
unsigned int radar_inband;
int fir_power;
int ext_channel;
};
/**
* struct ath_hw_private_ops - callbacks used internally by hardware code
*
* This structure contains private callbacks designed to only be used internally
* by the hardware core.
*
* @init_cal_settings: setup types of calibrations supported
* @init_cal: starts actual calibration
*
* @init_mode_regs: Initializes mode registers
*
* @rf_set_freq: change frequency
* @spur_mitigate_freq: spur mitigation
* @rf_alloc_ext_banks:
* @rf_free_ext_banks:
* @set_rf_regs:
* @compute_pll_control: compute the PLL control value to use for
* AR_RTC_PLL_CONTROL for a given channel
* @setup_calibration: set up calibration
* @iscal_supported: used to query if a type of calibration is supported
*
* @ani_cache_ini_regs: cache the values for ANI from the initial
* register settings through the register initialization.
*/
struct ath_hw_private_ops {
/* Calibration ops */
struct ath9k_cal_list *currCal);
/* PHY ops */
struct ath9k_channel *chan);
struct ath9k_channel *chan);
struct ath9k_channel *chan,
struct ath9k_channel *chan);
struct ath9k_channel *chan);
int param);
struct ath_hw_radar_conf *conf);
/* ANI */
};
/**
* struct ath_hw_ops - callbacks used by hardware code and driver code
*
* This structure contains callbacks designed to to be used internally by
* hardware code and also by the lower level driver.
*
* @config_pci_powersave:
* @calibrate: periodic calibration for NF, ANI, IQ, ADC gain, ADC-DC
*/
struct ath_hw_ops {
int restore,
int power_off);
struct ath9k_channel *chan,
int longcal);
int is_firstseg, int is_is_lastseg,
unsigned int qcu);
struct ath_tx_status *ts);
enum ath9k_key_type keyType,
void *lastds,
struct ath9k_11n_rate_series series[],
struct ath_hw_antcomb_conf *antconf);
struct ath_hw_antcomb_conf *antconf);
};
struct ath_nf_limits {
};
/* ah_flags */
#define AH_USE_EEPROM 0x1
struct ath_hw {
struct net80211_device *dev;
struct ath_common common;
struct ath9k_hw_version hw_version;
struct ath9k_ops_config config;
struct ath9k_hw_capabilities caps;
struct ath9k_channel *curchan;
union {
struct ar5416_eeprom_def def;
struct ar5416_eeprom_4k map4k;
struct ar9287_eeprom map9287;
struct ar9300_eeprom ar9300_eep;
} eeprom;
const struct eeprom_ops *eep_ops;
int sw_mgmt_crypto;
int is_pciexpress;
int is_monitoring;
int need_an_top2_fixup;
struct ath_nf_limits nf_2g;
struct ath_nf_limits nf_5g;
int htc_reset_init;
enum ath9k_power_mode power_mode;
struct ath9k_hw_cal_data *caldata;
struct ath9k_pacal_info pacal_info;
struct ar5416Stats stats;
int ah_ier;
int chip_fullsleep;
/* Calibration */
struct ath9k_cal_list iq_caldata;
struct ath9k_cal_list adcgain_caldata;
struct ath9k_cal_list adcdc_caldata;
struct ath9k_cal_list tempCompCalData;
struct ath9k_cal_list *cal_list;
struct ath9k_cal_list *cal_list_last;
struct ath9k_cal_list *cal_list_curr;
union {
} meas0;
union {
} meas1;
union {
} meas2;
union {
} meas3;
enum {
/* Private to hardware code */
struct ath_hw_private_ops private_ops;
/* Accessed by the lower level driver */
struct ath_hw_ops ops;
/* Used to program the radio on non single-chip devices */
int coverage_class;
/* ANI */
int totalSizeDesired[5];
int coarse_high[5];
int coarse_low[5];
int firpwr[5];
enum ath9k_ani_cmd ani_function;
struct ath_hw_radar_conf radar_conf;
int initPDADC;
int PDADCdelta;
int led_pin;
struct ar5416IniArray iniModes;
struct ar5416IniArray iniCommon;
struct ar5416IniArray iniBank0;
struct ar5416IniArray iniBB_RfGain;
struct ar5416IniArray iniBank1;
struct ar5416IniArray iniBank2;
struct ar5416IniArray iniBank3;
struct ar5416IniArray iniBank6;
struct ar5416IniArray iniBank6TPC;
struct ar5416IniArray iniBank7;
struct ar5416IniArray iniAddac;
struct ar5416IniArray iniPcieSerdes;
struct ar5416IniArray iniPcieSerdesLowPower;
struct ar5416IniArray iniModesAdditional;
struct ar5416IniArray iniModesAdditional_40M;
struct ar5416IniArray iniModesRxGain;
struct ar5416IniArray iniModesTxGain;
struct ar5416IniArray iniModes_9271_1_0_only;
struct ar5416IniArray iniCckfirNormal;
struct ar5416IniArray iniCckfirJapan2484;
struct ar5416IniArray iniModes_9271_ANI_reg;
struct ath_gen_timer_table hw_gen_timers;
struct ar9003_txs *ts_ring;
void *ts_start;
unsigned int paprd_target_power;
unsigned int paprd_training_power;
unsigned int paprd_ratemask;
unsigned int paprd_ratemask_ht40;
/*
* Store the permanent value of Reg 0x4004in WARegVal
* so we dont have to R/M/W. We should not be reading
* this register when in sleep states.
*/
/* Enterprise mode cap */
int is_clk_25mhz;
};
struct ath_bus_ops {
enum ath_bus_type ath_bus_type;
};
{
}
{
}
{
return &ah->private_ops;
}
{
}
{
}
/* Initialization, Detach, Reset */
/* GPIO / RFKILL / Antennae */
/* General Operation */
struct ath9k_channel *chan,
struct chan_centers *centers);
/* HTC */
/* PHY */
/*
* Code Specific to AR5008, AR9001 or AR9002,
* we stuff these here to avoid callbacks for AR9003.
*/
/*
* Code specific to AR9003, we stuff these here to avoid callbacks
* for older families
*/
/* Hardware family op attach helpers */
/*
* ANI work can be shared between all families but a next
* generation implementation of ANI will be used only for AR9003 only
* for now as the other families still need to be tested with the same
* next generation ANI. Feel free to start testing it though for the
* older families (AR5008, AR9001, AR9002) by using modparam_force_new_ani.
*/
extern int modparam_force_new_ani;
#define ATH_PCIE_CAP_LINK_CTRL 0x70
#define ATH_PCIE_CAP_LINK_L0S 1
#define ATH_PCIE_CAP_LINK_L1 2
#define ATH9K_CLOCK_RATE_CCK 22
#define ATH9K_CLOCK_RATE_5GHZ_OFDM 40
#define ATH9K_CLOCK_RATE_2GHZ_OFDM 44
#define ATH9K_CLOCK_FAST_RATE_5GHZ_OFDM 44
#endif