ath9k_init.c revision a734c64bff58bda2fa48c2795453e092167b0ff7
/*
* Copyright (c) 2008-2011 Atheros Communications Inc.
*
* Modified for iPXE by Scott K Logan <logans@cottsay.net> July 2011
* Original from Linux kernel 3.0.1
*
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
#include "ath9k.h"
int is_ath9k_unloaded;
/* We use the hw_value as an index into our private channel structure */
.band = NET80211_BAND_2GHZ, \
.center_freq = (_freq), \
.maxpower = 20, \
}
.band = NET80211_BAND_5GHZ, \
.center_freq = (_freq), \
.maxpower = 20, \
}
/* Some 2 GHz radios are actually tunable on 2312-2732
* on 5 MHz steps, we support the channels which we know
* we have calibration data for all cards though to make
* this static */
static const struct net80211_channel ath9k_2ghz_chantable[] = {
};
/* Some 5 GHz radios are actually tunable on XXXX-YYYY
* on 5 MHz steps, we support the channels which we know
* we have calibration data for all cards though to make
* this static */
static const struct net80211_channel ath9k_5ghz_chantable[] = {
/* _We_ call this UNII 1 */
/* _We_ call this UNII 2 */
/* _We_ call this "Middle band" */
/* _We_ call this UNII 3 */
};
/* Atheros hardware rate code addition for short premble */
}
static struct ath9k_legacy_rate ath9k_legacy_rates[] = {
};
/*
* Read and write, they both share the same lock. We do this to serialize
* reads and writes on Atheros 802.11n PCI devices only. This is required
* as the FIFO on these devices can only accept sanely 2 requests.
*/
{
}
{
return val;
}
{
return val;
}
/**************************/
/* Initialization */
/**************************/
/*
* This function will allocate both the DMA descriptor structure, and the
* buffers it contains. These are used to contain the descriptors used
* by the system.
*/
{
if (is_tx)
else
/* ath_desc must be a multiple of DWORDs */
if ((desc_len % 4) != 0) {
DBG("ath9k: ath_desc not DWORD aligned\n");
goto fail;
}
/*
* Need additional DMA memory because we can't use
* descriptors that cross the 4K page boundary.
* However, iPXE only utilizes 16 buffers, which
* will never make up more than half of one page,
* so we will only ever skip 1 descriptor, if that.
*/
}
/* allocate descriptors */
goto fail;
}
DBG2("ath9k: %s DMA map: %p (%d) -> %llx (%d)\n",
/* allocate buffers */
goto fail2;
}
/*
* Skip descriptor addresses which can cause 4KB
* boundary crossing (addr + length) with a 32 dword
* descriptor fetch.
*/
}
}
}
return 0;
fail:
return error;
}
{
unsigned int i = 0;
/* Get the hardware key cache size. */
/*
* Reset the key cache since some parts do not
* reset the contents on initial power up.
*/
/*
* Check whether the separate key cache entries
* are required to handle both tx+rx MIC keys.
* With split mic keys the number of stations is limited
* to 27 otherwise 59.
*/
}
{
int i = 0;
for (i = 0; i < WME_NUM_AC; i++) {
}
return 0;
}
{
unsigned int i;
memcpy(&sc->hwinfo->channels[sc->hwinfo->nr_channels], ath9k_2ghz_chantable, sizeof(ath9k_2ghz_chantable));
for (i = 0; i < ARRAY_SIZE(ath9k_legacy_rates); i++)
}
memcpy(&sc->hwinfo->channels[sc->hwinfo->nr_channels], ath9k_5ghz_chantable, sizeof(ath9k_5ghz_chantable));
}
return 0;
}
{
}
const struct ath_bus_ops *bus_ops)
{
struct ath_common *common;
int ret = 0, i;
int csz = 0;
if (!ah)
return -ENOMEM;
DBG("ath9k: cannot allocate 802.11 hardware info structure\n");
return -ENOMEM;
}
/*
* Cache line size is used to size and align various
* structures used to communicate with the hardware.
*/
/* Initializes the hardware for all supported chipsets */
if (ret)
goto err_hw;
if (ret)
goto err_queues;
if (ret)
goto err_btcoex;
return 0;
for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
if (ATH_TXQ_SETUP(sc, i))
return ret;
}
{
struct net80211_channel *chan;
int i;
continue;
}
}
{
}
{
{
}
{
}
}
const struct ath_bus_ops *bus_ops)
{
/*struct ath_common *common;
struct ath_hw *ah;*/
int error = 0;
/*struct ath_regulatory *reg;*/
/* Bring up device */
if (error != 0)
goto error_init;
/*ah = sc->sc_ah;
common = ath9k_hw_common(ah);*/
/* TODO Cottsay: reg */
/* Initialize regulatory */
/*error = ath_regd_init(&common->regulatory, sc->dev->wiphy,
ath9k_reg_notifier);
if (error)
goto error_regd;
reg = &common->regulatory;*/
/* Setup TX DMA */
if (error != 0)
goto error_tx;
/* Setup RX DMA */
if (error != 0)
goto error_rx;
/* Register with mac80211 */
if (error)
goto error_register;
/* TODO Cottsay: reg */
/* Handle world regulatory */
/*if (!ath_is_world_regd(reg)) {
error = regulatory_hint(hw->wiphy, reg->alpha2);
if (error)
goto error_world;
}*/
/* TODO Cottsay: rfkill */
/*ath_start_rfkill_poll(sc);*/
return 0;
//error_world:
// net80211_unregister(dev);
return error;
}
/*****************************/
/* De-Initialization */
/*****************************/
{
int i = 0;
for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
if (ATH_TXQ_SETUP(sc, i))
}
{
}
struct ath_descdma *dd,
{
}