ath9k_ar9002_phy.c revision a734c64bff58bda2fa48c2795453e092167b0ff7
/*
* Copyright (c) 2008-2011 Atheros Communications Inc.
*
* Modified for iPXE by Scott K Logan <logans@cottsay.net> July 2011
* Original from Linux kernel 3.0.1
*
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
/**
* DOC: Programming Atheros 802.11n analog front end radios
*
* AR5416 MAC based PCI devices and AR518 MAC based PCI-Express
* devices have either an external AR2133 analog front end radio for single
* band 2.4 GHz communication or an AR5133 analog front end radio for dual
* band 2.4 GHz / 5 GHz communication.
*
* All devices after the AR5416 and AR5418 family starting with the AR9280
* into a single-chip and require less programming.
*
* The following single-chips exist with a respective embedded radio:
*
* AR9280 - 11n dual-band 2x2 MIMO for PCIe
* AR9281 - 11n single-band 1x2 MIMO for PCIe
* AR9285 - 11n single-band 1x1 for PCIe
* AR9287 - 11n single-band 2x2 MIMO for PCIe
*
* AR9220 - 11n dual-band 2x2 MIMO for PCI
* AR9223 - 11n single-band 2x2 MIMO for PCI
*
* AR9287 - 11n single-band 1x1 MIMO for USB
*/
#include "hw.h"
#include "ar9002_phy.h"
/**
* ar9002_hw_set_channel - set channel on single-chip device
* @ah: atheros hardware structure
* @chan:
*
* This is the function to change channel on single-chip devices, that is
* all devices after ar9280.
*
* This function takes the channel value in MHz and sets
* hardware channel value. Assumes writes have been enabled to analog bus.
*
* Actual Expression,
*
* For 2GHz channel,
* Channel Frequency = (3/4) * freq_ref * (chansel[8:0] + chanfrac[16:0]/2^17)
* (freq_ref = 40MHz)
*
* For 5GHz channel,
* Channel Frequency = (3/2) * freq_ref * (chansel[8:0] + chanfrac[16:0]/2^10)
* (freq_ref = 40MHz/(24>>amodeRefSel))
*/
{
struct chan_centers centers;
reg32 &= 0xc0000000;
unsigned int regWrites = 0;
bMode = 1;
fracMode = 1;
aModeRefSel = 0;
if (AR_SREV_9287_11_OR_LATER(ah)) {
if (freq == 2484) {
/* Enable channel spreading for channel 14 */
1, regWrites);
} else {
1, regWrites);
}
} else {
if (freq == 2484) {
/* Enable channel spreading for channel 14 */
} else {
}
}
} else {
bMode = 0;
fracMode = 0;
case 0:
if ((freq % 20) == 0)
aModeRefSel = 3;
else if ((freq % 10) == 0)
aModeRefSel = 2;
if (aModeRefSel)
break;
case 1:
default:
aModeRefSel = 0;
/*
* Enable 2G (fractional) mode for channels
* which are 5MHz spaced.
*/
fracMode = 1;
refDivA = 1;
/* RefDivA setting */
}
if (!fracMode) {
}
}
(bMode << 29) |
return 0;
}
/**
* ar9002_hw_spur_mitigate - convert baseband spur frequency
* @ah: atheros hardware structure
* @chan:
*
* For single-chip solutions. Converts to baseband spur frequency given the
* input channel frequency and compute register settings below.
*/
struct ath9k_channel *chan)
{
int bb_spur = AR_NO_SPUR;
int freq;
int spur_freq_sd;
int spur_delta_phase;
int denominator;
int i;
static const int pilot_mask_reg[4] = {
};
static const int chan_mask_reg[4] = {
};
struct chan_centers centers;
int tmp_mask;
int cur_bb_spur;
for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
if (AR_NO_SPUR == cur_bb_spur)
break;
if (is2GHz)
else
if (IS_CHAN_HT40(chan)) {
if ((cur_bb_spur > -AR_SPUR_FEEQ_BOUND_HT40) &&
break;
}
} else if ((cur_bb_spur > -AR_SPUR_FEEQ_BOUND_HT20) &&
break;
}
}
if (AR_NO_SPUR == bb_spur) {
return;
} else {
}
if (IS_CHAN_HT40(chan)) {
if (bb_spur < 0) {
spur_subchannel_sd = 1;
} else {
spur_subchannel_sd = 0;
}
} else {
spur_subchannel_sd = 0;
}
if (IS_CHAN_HT40(chan))
((bb_spur * 262144) /
else
((bb_spur * 524288) /
cur_bin = -6000;
for (i = 0; i < 4; i++) {
int pilot_mask = 0;
int chan_mask = 0;
int bp = 0;
}
cur_bin += 100;
}
}
cur_vit_mask = 6100;
for (i = 0; i < 123; i++) {
/* workaround for gcc bug #37014 */
if (tmp_v < 75)
mask_amt = 1;
else
mask_amt = 0;
if (cur_vit_mask < 0)
else
}
cur_vit_mask -= 100;
}
}
{
u32 i;
if (!OLC_FOR_AR9280_20_LATER)
return;
if (OLC_FOR_AR9287_10_LATER) {
udelay(100);
} else {
for (i = 0; i < AR9280_TX_GAIN_TABLE_SIZE; i++)
ah->originalGain[i] =
ah->PDADCdelta = 0;
}
}
struct ath9k_channel *chan)
{
pll = 0x142c;
else if (AR_SREV_9280_20(ah))
pll = 0x2850;
else
} else {
}
return pll;
}
{
return;
}
{
if (AR_SREV_9285(ah)) {
} else if (AR_SREV_9287(ah)) {
} else if (AR_SREV_9271(ah)) {
} else {
}
}
struct ath_hw_antcomb_conf *antconf)
{
}
struct ath_hw_antcomb_conf *antconf)
{
}
{
}