pci.c revision d65680efa46fa49e8bf14e67b29b782510ff934c
#ifdef CONFIG_PCI
/*
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2, or (at
* your option) any later version.
*/
/*
* Sun GPL Disclaimer: For the avoidance of doubt, except that if any license choice
* other than GPL or LGPL is available it will apply instead, Sun elects to use only
* the General Public License version 2 (GPLv2) at this time for any software where
* a choice of GPL license versions is made available with the language indicating
* that GPLv2 or any later version may be used, or where a choice of which version
* of the GPL is applied is otherwise unspecified.
*/
#include "etherboot.h"
#include "pci.h"
/*#define DEBUG 1*/
static void scan_drivers(
int type,
{
/* Assume there is only one match of the correct type */
const struct pci_driver *driver;
int i;
continue;
if (skip_driver) {
if (skip_driver == driver)
skip_driver = 0;
continue;
}
goto out;
}
}
}
if (!class) {
goto out;
}
continue;
if (skip_driver) {
if (skip_driver == driver)
skip_driver = 0;
continue;
}
if (last_driver == driver)
continue;
goto out;
}
}
out:
return;
}
{
unsigned int first_bus, first_devfn;
const struct pci_driver *first_driver;
unsigned char hdr_type = 0;
int reg;
first_bus = 0;
first_devfn = 0;
first_driver = 0;
/* Re read the header type on a restart */
}
/* Scan all PCI buses, until we find our card.
* We could be smart only scan the required buses but that
* is error prone, and tricky.
* By scanning all possible pci buses in order we should find
* our card eventually.
*/
buses=256;
continue;
/* some broken boards return 0 if a slot is empty: */
if (l == 0xffffffff || l == 0x00000000) {
continue;
}
vendor = l & 0xffff;
#if DEBUG
{
int i;
printf("%hhx:%hhx.%hhx [%hX/%hX] Class %hX\n",
#if DEBUG > 1
for(i = 0; i < 256; i++) {
unsigned char byte;
if ((i & 0xf) == 0) {
printf("%hhx: ", i);
}
if ((i & 0xf) == 0xf) {
printf("\n");
}
}
#endif
}
#endif
continue;
/* Get the ROM base address */
romaddr >>= 10;
/* Get the ``membase'' */
/* Get the ``ioaddr'' */
continue;
/* Strip the I/O address out of the returned value */
/* Take the first one or the one that matches in boot ROM address */
}
/* Get the irq */
if (irq) {
&irq);
}
#if DEBUG > 2
printf("Found %s ROM address %#hx\n",
#endif
return;
}
first_devfn = 0;
}
first_bus = 0;
}
/*
* Set device to be a busmaster in case BIOS neglected to do so.
* Also adjust PCI latency timer to a reasonable value, 32.
*/
void adjust_pci_device(struct pci_device *p)
{
unsigned short new_command, pci_command;
unsigned char pci_latency;
if (pci_command != new_command) {
#if DEBUG > 0
"The PCI BIOS has not enabled this device!\n"
"Updating PCI command %hX->%hX. pci_bus %hhX pci_device_fn %hhX\n",
#endif
}
if (pci_latency < 32) {
#if DEBUG > 0
printf("PCI latency timer (CFLT) is unreasonably low at %d. Setting to 32 clocks.\n",
#endif
}
}
/*
* Find the start of a pci resource.
*/
{
unsigned long bar;
if (lo & PCI_BASE_ADDRESS_SPACE_IO) {
} else {
bar = 0;
if (hi) {
#if ULONG_MAX > 0xffffffff
bar <<=32;
#else
printf ( "Unhandled 64bit BAR %08x:%08x\n",
return -1UL;
#endif
}
}
}
}
/*
* Find the size of a pci resource.
*/
{
/* Save the original bar */
/* Compute which bits can be set */
/* Restore the original size */
/* Find the significant bits */
if (start & PCI_BASE_ADDRESS_SPACE_IO) {
} else {
}
/* Find the lowest bit set */
return size;
}
/**
* pci_find_capability - query for devices' capabilities
* @dev: PCI device to query
* @cap: capability code
*
* Tell if a device supports a given PCI capability.
* Returns the address of the requested capability structure within the
* device's PCI configuration space or 0 in case the device does not
* support it. Possible values for @cap:
*
* %PCI_CAP_ID_PM Power Management
*
* %PCI_CAP_ID_AGP Accelerated Graphics Port
*
* %PCI_CAP_ID_VPD Vital Product Data
*
* %PCI_CAP_ID_SLOTID Slot Identification
*
* %PCI_CAP_ID_MSI Message Signalled Interrupts
*
* %PCI_CAP_ID_CHSWP CompactPCI HotSwap
*/
{
int ttl = 48;
if (!(status & PCI_STATUS_CAP_LIST))
return 0;
switch (hdr_type & 0x7F) {
case PCI_HEADER_TYPE_NORMAL:
case PCI_HEADER_TYPE_BRIDGE:
default:
break;
case PCI_HEADER_TYPE_CARDBUS:
break;
}
pos &= ~3;
#if DEBUG > 0
#endif
if (id == 0xff)
break;
return pos;
}
return 0;
}
#endif /* CONFIG_PCI */