DevHPET.cpp revision 601d153b9b7960b2a58cc013b6ac3aa00b95bdea
016096e367cd20c3d3c3fd9a6650b55935c2e31dvboxsync * HPET virtual device - high precision event timer emulation
b2bc8de1367ae24e1b27b53921d0b32ee3df7acdvboxsync * Copyright (C) 2009-2011 Oracle Corporation
016096e367cd20c3d3c3fd9a6650b55935c2e31dvboxsync * This file is part of VirtualBox Open Source Edition (OSE), as
016096e367cd20c3d3c3fd9a6650b55935c2e31dvboxsync * available from http://www.virtualbox.org. This file is free software;
016096e367cd20c3d3c3fd9a6650b55935c2e31dvboxsync * you can redistribute it and/or modify it under the terms of the GNU
016096e367cd20c3d3c3fd9a6650b55935c2e31dvboxsync * General Public License (GPL) as published by the Free Software
016096e367cd20c3d3c3fd9a6650b55935c2e31dvboxsync * Foundation, in version 2 as it comes in the "COPYING" file of the
016096e367cd20c3d3c3fd9a6650b55935c2e31dvboxsync * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
016096e367cd20c3d3c3fd9a6650b55935c2e31dvboxsync * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
016096e367cd20c3d3c3fd9a6650b55935c2e31dvboxsync/*******************************************************************************
016096e367cd20c3d3c3fd9a6650b55935c2e31dvboxsync* Header Files *
016096e367cd20c3d3c3fd9a6650b55935c2e31dvboxsync*******************************************************************************/
2f0d866e126dd288169fed591c259c1c6b4016e5vboxsync/*******************************************************************************
2f0d866e126dd288169fed591c259c1c6b4016e5vboxsync* Defined Constants And Macros *
2f0d866e126dd288169fed591c259c1c6b4016e5vboxsync*******************************************************************************/
016096e367cd20c3d3c3fd9a6650b55935c2e31dvboxsync * Current limitations:
016096e367cd20c3d3c3fd9a6650b55935c2e31dvboxsync * - not entirely correct time of interrupt, i.e. never
016096e367cd20c3d3c3fd9a6650b55935c2e31dvboxsync * schedule interrupt earlier than in 1ms
016096e367cd20c3d3c3fd9a6650b55935c2e31dvboxsync * - statistics not implemented
9b7ab382b3f9667e8847020e1e58f7143c4d2334vboxsync * - level-triggered mode not implemented
016096e367cd20c3d3c3fd9a6650b55935c2e31dvboxsync * Base address for MMIO
016096e367cd20c3d3c3fd9a6650b55935c2e31dvboxsync * Number of available timers, cannot be changed without
016096e367cd20c3d3c3fd9a6650b55935c2e31dvboxsync * breaking saved states.
016096e367cd20c3d3c3fd9a6650b55935c2e31dvboxsync * 10000000 femtoseconds == 10ns
7697e43970d863558b6c168a55e8948ccb18d8d1vboxsync * 69841279 femtoseconds == 69.84 ns (1 / 14.31818MHz)
016096e367cd20c3d3c3fd9a6650b55935c2e31dvboxsync * Femptosecods in nanosecond
016096e367cd20c3d3c3fd9a6650b55935c2e31dvboxsync * Interrupt type
016096e367cd20c3d3c3fd9a6650b55935c2e31dvboxsync/* Delivery mode */
016096e367cd20c3d3c3fd9a6650b55935c2e31dvboxsync/* Via APIC */
016096e367cd20c3d3c3fd9a6650b55935c2e31dvboxsync/* Via FSB */
016096e367cd20c3d3c3fd9a6650b55935c2e31dvboxsync#define HPET_TN_CFG_BITS_READONLY_OR_RESERVED 0xffff80b1U
016096e367cd20c3d3c3fd9a6650b55935c2e31dvboxsync/** The version of the saved state. */
b2bc8de1367ae24e1b27b53921d0b32ee3df7acdvboxsync/** Empty saved state */
c060166f65b9dd2f1ed53e6e4cffdad948e01722vboxsync * Acquires the HPET lock or returns.
c060166f65b9dd2f1ed53e6e4cffdad948e01722vboxsync int rcLock = PDMCritSectEnter(&(a_pThis)->csLock, (a_rcBusy)); \
c060166f65b9dd2f1ed53e6e4cffdad948e01722vboxsync } while (0)
c060166f65b9dd2f1ed53e6e4cffdad948e01722vboxsync * Releases the HPET lock.
c060166f65b9dd2f1ed53e6e4cffdad948e01722vboxsync do { PDMCritSectLeave(&(a_pThis)->csLock); } while (0)
e562a8bb17c0dfa1c316708e085a3a92fcc80521vboxsync * Acquires the TM lock and HPET lock, returns on failure.
e562a8bb17c0dfa1c316708e085a3a92fcc80521vboxsync#define DEVHPET_LOCK_BOTH_RETURN(a_pThis, a_rcBusy) \
e562a8bb17c0dfa1c316708e085a3a92fcc80521vboxsync int rcLock = TMTimerLock((a_pThis)->aTimers[0].CTX_SUFF(pTimer), (a_rcBusy)); \
e562a8bb17c0dfa1c316708e085a3a92fcc80521vboxsync rcLock = PDMCritSectEnter(&(a_pThis)->csLock, (a_rcBusy)); \
e562a8bb17c0dfa1c316708e085a3a92fcc80521vboxsync TMTimerUnlock((a_pThis)->aTimers[0].CTX_SUFF(pTimer)); \
e562a8bb17c0dfa1c316708e085a3a92fcc80521vboxsync } while (0)
e562a8bb17c0dfa1c316708e085a3a92fcc80521vboxsync * Releases the HPET lock and TM lock.
e562a8bb17c0dfa1c316708e085a3a92fcc80521vboxsync TMTimerUnlock((a_pThis)->aTimers[0].CTX_SUFF(pTimer)); \
e562a8bb17c0dfa1c316708e085a3a92fcc80521vboxsync } while (0)
2f0d866e126dd288169fed591c259c1c6b4016e5vboxsync/*******************************************************************************
2f0d866e126dd288169fed591c259c1c6b4016e5vboxsync* Structures and Typedefs *
2f0d866e126dd288169fed591c259c1c6b4016e5vboxsync*******************************************************************************/
016096e367cd20c3d3c3fd9a6650b55935c2e31dvboxsynctypedef struct HpetTimer
016096e367cd20c3d3c3fd9a6650b55935c2e31dvboxsync /** The HPET timer - R3 Ptr. */
016096e367cd20c3d3c3fd9a6650b55935c2e31dvboxsync /** Pointer to the instance data - R3 Ptr. */
016096e367cd20c3d3c3fd9a6650b55935c2e31dvboxsync /** The HPET timer - R0 Ptr. */
016096e367cd20c3d3c3fd9a6650b55935c2e31dvboxsync /** Pointer to the instance data - R0 Ptr. */
016096e367cd20c3d3c3fd9a6650b55935c2e31dvboxsync /** The HPET timer - RC Ptr. */
016096e367cd20c3d3c3fd9a6650b55935c2e31dvboxsync /** Pointer to the instance data - RC Ptr. */
b2bc8de1367ae24e1b27b53921d0b32ee3df7acdvboxsync /** Timer index. */
b2bc8de1367ae24e1b27b53921d0b32ee3df7acdvboxsync /** Wrap. */
b2bc8de1367ae24e1b27b53921d0b32ee3df7acdvboxsync /** Alignment. */
b2bc8de1367ae24e1b27b53921d0b32ee3df7acdvboxsync /** @name Memory-mapped, software visible timer registers.
b2bc8de1367ae24e1b27b53921d0b32ee3df7acdvboxsync /** Comparator. */
b2bc8de1367ae24e1b27b53921d0b32ee3df7acdvboxsync /** FSB route, not supported now. */
b2bc8de1367ae24e1b27b53921d0b32ee3df7acdvboxsync /** @name Hidden register state.
b2bc8de1367ae24e1b27b53921d0b32ee3df7acdvboxsync /** Last value written to comparator. */
b2bc8de1367ae24e1b27b53921d0b32ee3df7acdvboxsyncAssertCompileMemberAlignment(HpetTimer, u64Config, sizeof(uint64_t));
016096e367cd20c3d3c3fd9a6650b55935c2e31dvboxsynctypedef struct HpetState
016096e367cd20c3d3c3fd9a6650b55935c2e31dvboxsync /** Pointer to the device instance. - R3 ptr. */
016096e367cd20c3d3c3fd9a6650b55935c2e31dvboxsync /** The HPET helpers - R3 Ptr. */
016096e367cd20c3d3c3fd9a6650b55935c2e31dvboxsync /** Pointer to the device instance. - R0 ptr. */
016096e367cd20c3d3c3fd9a6650b55935c2e31dvboxsync /** The HPET helpers - R0 Ptr. */
016096e367cd20c3d3c3fd9a6650b55935c2e31dvboxsync /** Pointer to the device instance. - RC ptr. */
016096e367cd20c3d3c3fd9a6650b55935c2e31dvboxsync /** The HPET helpers - RC Ptr. */
8287c906b9b1d215824d4cdf6c1eaf40681ebfa8vboxsync /** Timer structures. */
8287c906b9b1d215824d4cdf6c1eaf40681ebfa8vboxsync /** Offset realtive to the virtual sync clock. */
8287c906b9b1d215824d4cdf6c1eaf40681ebfa8vboxsync /** @name Memory-mapped, software visible registers
8287c906b9b1d215824d4cdf6c1eaf40681ebfa8vboxsync /** Capabilities. */
8287c906b9b1d215824d4cdf6c1eaf40681ebfa8vboxsync /** Configuration. */
8287c906b9b1d215824d4cdf6c1eaf40681ebfa8vboxsync /** Interrupt status register. */
8287c906b9b1d215824d4cdf6c1eaf40681ebfa8vboxsync /** Main counter. */
8287c906b9b1d215824d4cdf6c1eaf40681ebfa8vboxsync /** Global device lock. */
8287c906b9b1d215824d4cdf6c1eaf40681ebfa8vboxsync /** If we emulate ICH9 HPET (different frequency).
3ebd5757516d21eccdad25ddd456d2913c2fb215vboxsync * @todo different number of timers */
b2bc8de1367ae24e1b27b53921d0b32ee3df7acdvboxsyncDECLINLINE(bool) hpet32bitTimer(HpetTimer *pHpetTimer)
7c48fdac0546978ed14617c8096734ce2d18c8e5vboxsync return ((u64Cfg & HPET_TN_SIZE_CAP) == 0) || ((u64Cfg & HPET_TN_32BIT) != 0);
b2bc8de1367ae24e1b27b53921d0b32ee3df7acdvboxsyncDECLINLINE(uint64_t) hpetInvalidValue(HpetTimer *pHpetTimer)
b2bc8de1367ae24e1b27b53921d0b32ee3df7acdvboxsync return hpet32bitTimer(pHpetTimer) ? UINT32_MAX : UINT64_MAX;
7c48fdac0546978ed14617c8096734ce2d18c8e5vboxsyncDECLINLINE(uint32_t) hpetTimeAfter32(uint64_t a, uint64_t b)
7c48fdac0546978ed14617c8096734ce2d18c8e5vboxsyncDECLINLINE(uint32_t) hpetTimeAfter64(uint64_t a, uint64_t b)
3ebd5757516d21eccdad25ddd456d2913c2fb215vboxsyncDECLINLINE(uint64_t) hpetTicksToNs(HpetState *pThis, uint64_t value)
fe554d9c0e3a6de4ba221610ac95a44c7d288e01vboxsync return (ASMMultU64ByU32DivByU32(value, (uint32_t)(pThis->u64Capabilities >> 32), FS_PER_NS));
3ebd5757516d21eccdad25ddd456d2913c2fb215vboxsyncDECLINLINE(uint64_t) nsToHpetTicks(HpetState const *pThis, uint64_t u64Value)
fe554d9c0e3a6de4ba221610ac95a44c7d288e01vboxsync return (ASMMultU64ByU32DivByU32(u64Value, FS_PER_NS, (uint32_t)(pThis->u64Capabilities >> 32)));
3ebd5757516d21eccdad25ddd456d2913c2fb215vboxsyncDECLINLINE(uint64_t) hpetGetTicks(HpetState const *pThis)
016096e367cd20c3d3c3fd9a6650b55935c2e31dvboxsync * We can use any timer to get current time, they all go
016096e367cd20c3d3c3fd9a6650b55935c2e31dvboxsync * with the same speed.
7c48fdac0546978ed14617c8096734ce2d18c8e5vboxsyncDECLINLINE(uint64_t) hpetUpdateMasked(uint64_t u64NewValue,
7c48fdac0546978ed14617c8096734ce2d18c8e5vboxsyncDECLINLINE(bool) hpetBitJustSet(uint64_t u64OldValue,
7c48fdac0546978ed14617c8096734ce2d18c8e5vboxsyncDECLINLINE(bool) hpetBitJustCleared(uint64_t u64OldValue,
b2bc8de1367ae24e1b27b53921d0b32ee3df7acdvboxsyncDECLINLINE(uint64_t) hpetComputeDiff(HpetTimer *pHpetTimer,
b2bc8de1367ae24e1b27b53921d0b32ee3df7acdvboxsync u32Diff = (uint32_t)pHpetTimer->u64Cmp - (uint32_t)u64Now;
016096e367cd20c3d3c3fd9a6650b55935c2e31dvboxsync u32Diff = ((int32_t)u32Diff > 0) ? u32Diff : (uint32_t)0;
016096e367cd20c3d3c3fd9a6650b55935c2e31dvboxsync u64Diff = ((int64_t)u64Diff > 0) ? u64Diff : (uint64_t)0;
b2bc8de1367ae24e1b27b53921d0b32ee3df7acdvboxsyncstatic void hpetAdjustComparator(HpetTimer *pHpetTimer, uint64_t u64Now)
016096e367cd20c3d3c3fd9a6650b55935c2e31dvboxsync /* While loop is suboptimal */
b2bc8de1367ae24e1b27b53921d0b32ee3df7acdvboxsync while (hpetTimeAfter32(u64Now, pHpetTimer->u64Cmp))
b2bc8de1367ae24e1b27b53921d0b32ee3df7acdvboxsync pHpetTimer->u64Cmp = (uint32_t)(pHpetTimer->u64Cmp + u64Period);
b2bc8de1367ae24e1b27b53921d0b32ee3df7acdvboxsync while (hpetTimeAfter64(u64Now, pHpetTimer->u64Cmp))
016096e367cd20c3d3c3fd9a6650b55935c2e31dvboxsync /* no wrapping on new timers */
e562a8bb17c0dfa1c316708e085a3a92fcc80521vboxsync uint64_t u64Ticks = hpetGetTicks(pHpetTimer->CTX_SUFF(pHpet));
e562a8bb17c0dfa1c316708e085a3a92fcc80521vboxsync uint64_t u64Diff = hpetComputeDiff(pHpetTimer, u64Ticks);
7c48fdac0546978ed14617c8096734ce2d18c8e5vboxsync * HPET spec says in one-shot 32-bit mode, generate an interrupt when
016096e367cd20c3d3c3fd9a6650b55935c2e31dvboxsync * counter wraps in addition to an interrupt with comparator match.
e562a8bb17c0dfa1c316708e085a3a92fcc80521vboxsync uint32_t u32TillWrap = 0xffffffff - (uint32_t)u64Ticks + 1;
3956d0151065a11e49d2213b38a5efdad46807e0vboxsync Log(("wrap on timer %d: till=%u ticks=%lld diff64=%lld\n",
b2bc8de1367ae24e1b27b53921d0b32ee3df7acdvboxsync pHpetTimer->idxTimer, u32TillWrap, u64Ticks, u64Diff));
e562a8bb17c0dfa1c316708e085a3a92fcc80521vboxsync * HACK ALERT! Avoid killing VM with interrupts.
e562a8bb17c0dfa1c316708e085a3a92fcc80521vboxsync#if 1 /** @todo: HACK, rethink, may have negative impact on the guest */
b2bc8de1367ae24e1b27b53921d0b32ee3df7acdvboxsync Log4(("HPET: next IRQ in %lld ticks (%lld ns)\n", u64Diff, hpetTicksToNs(pHpetTimer->CTX_SUFF(pHpet), u64Diff)));
b2bc8de1367ae24e1b27b53921d0b32ee3df7acdvboxsync TMTimerSetNano(pHpetTimer->CTX_SUFF(pTimer), hpetTicksToNs(pHpetTimer->CTX_SUFF(pHpet), u64Diff));
3b1aa24d99d0f9cc157cf72ca76444b2feca3277vboxsync/* -=-=-=-=-=- Timer register accesses -=-=-=-=-=- */
3ebd5757516d21eccdad25ddd456d2913c2fb215vboxsync * Reads a HPET timer register.
3ebd5757516d21eccdad25ddd456d2913c2fb215vboxsync * @returns VBox strict status code.
3ebd5757516d21eccdad25ddd456d2913c2fb215vboxsync * @param pThis The HPET instance.
3ebd5757516d21eccdad25ddd456d2913c2fb215vboxsync * @param iTimerNo The timer index.
3ebd5757516d21eccdad25ddd456d2913c2fb215vboxsync * @param iTimerReg The index of the timer register to read.
3ebd5757516d21eccdad25ddd456d2913c2fb215vboxsync * @param pu32Value Where to return the register value.
3ebd5757516d21eccdad25ddd456d2913c2fb215vboxsync * @remarks ASSUMES the caller does holds the HPET lock.
3ebd5757516d21eccdad25ddd456d2913c2fb215vboxsyncstatic int hpetTimerRegRead32(HpetState const *pThis, uint32_t iTimerNo, uint32_t iTimerReg, uint32_t *pu32Value)
3ebd5757516d21eccdad25ddd456d2913c2fb215vboxsync static unsigned s_cOccurences = 0;
3ebd5757516d21eccdad25ddd456d2913c2fb215vboxsync LogRel(("HPET: using timer above configured range: %d\n", iTimerNo));
3ebd5757516d21eccdad25ddd456d2913c2fb215vboxsync HpetTimer const *pHpetTimer = &pThis->aTimers[iTimerNo];
3ebd5757516d21eccdad25ddd456d2913c2fb215vboxsync Log(("read HPET_TN_CFG on %d: %#x\n", iTimerNo, u32Value));
3ebd5757516d21eccdad25ddd456d2913c2fb215vboxsync u32Value = (uint32_t)(pHpetTimer->u64Config >> 32);
3ebd5757516d21eccdad25ddd456d2913c2fb215vboxsync Log(("read HPET_TN_CFG+4 on %d: %#x\n", iTimerNo, u32Value));
3ebd5757516d21eccdad25ddd456d2913c2fb215vboxsync Log(("read HPET_TN_CMP on %d: %#x (%#llx)\n", pHpetTimer->idxTimer, u32Value, pHpetTimer->u64Cmp));
3ebd5757516d21eccdad25ddd456d2913c2fb215vboxsync Log(("read HPET_TN_CMP+4 on %d: %#x (%#llx)\n", pHpetTimer->idxTimer, u32Value, pHpetTimer->u64Cmp));
3ebd5757516d21eccdad25ddd456d2913c2fb215vboxsync u32Value = (uint32_t)(pHpetTimer->u64Fsb >> 32); /** @todo Looks wrong, but since it's not supported, who cares. */
3ebd5757516d21eccdad25ddd456d2913c2fb215vboxsync Log(("read HPET_TN_ROUTE on %d: %#x\n", iTimerNo, u32Value));
3ebd5757516d21eccdad25ddd456d2913c2fb215vboxsync static unsigned s_cOccurences = 0;
3ebd5757516d21eccdad25ddd456d2913c2fb215vboxsync LogRel(("invalid HPET register read %d on %d\n", iTimerReg, pHpetTimer->idxTimer));
3ebd5757516d21eccdad25ddd456d2913c2fb215vboxsync * 32-bit write to a HPET timer register.
3ebd5757516d21eccdad25ddd456d2913c2fb215vboxsync * @returns Strict VBox status code.
3ebd5757516d21eccdad25ddd456d2913c2fb215vboxsync * @param pThis The HPET state.
3ebd5757516d21eccdad25ddd456d2913c2fb215vboxsync * @param idxReg The register being written to.
3ebd5757516d21eccdad25ddd456d2913c2fb215vboxsync * @param u32NewValue The value being written.
e562a8bb17c0dfa1c316708e085a3a92fcc80521vboxsync * @remarks The caller should not hold the device lock, unless it also holds
e562a8bb17c0dfa1c316708e085a3a92fcc80521vboxsync * the TM lock.
3ebd5757516d21eccdad25ddd456d2913c2fb215vboxsyncstatic int hpetTimerRegWrite32(HpetState *pThis, uint32_t iTimerNo, uint32_t iTimerReg, uint32_t u32NewValue)
e562a8bb17c0dfa1c316708e085a3a92fcc80521vboxsync Assert(!PDMCritSectIsOwner(&pThis->csLock) || TMTimerIsLockOwner(pThis->aTimers[0].CTX_SUFF(pTimer)));
016096e367cd20c3d3c3fd9a6650b55935c2e31dvboxsync LogRel(("HPET: using timer above configured range: %d\n", iTimerNo));
e562a8bb17c0dfa1c316708e085a3a92fcc80521vboxsync DEVHPET_LOCK_RETURN(pThis, VINF_IOM_HC_MMIO_WRITE);
3ebd5757516d21eccdad25ddd456d2913c2fb215vboxsync Log(("write HPET_TN_CFG: %d: %x\n", iTimerNo, u32NewValue));
067712a8118321d460f98b437ecafb6b8dbce301vboxsync uint64_t const iOldValue = (uint32_t)pHpetTimer->u64Config;
b2bc8de1367ae24e1b27b53921d0b32ee3df7acdvboxsync if ((pHpetTimer->u64Config & HPET_TN_PERIODIC_CAP) != 0)
b2bc8de1367ae24e1b27b53921d0b32ee3df7acdvboxsync if ((pHpetTimer->u64Config & HPET_TN_SIZE_CAP) != 0)
7c48fdac0546978ed14617c8096734ce2d18c8e5vboxsync Log(("setting timer %d to 32-bit mode\n", iTimerNo));
b2bc8de1367ae24e1b27b53921d0b32ee3df7acdvboxsync pHpetTimer->u64Period = (uint32_t)pHpetTimer->u64Period;
3ebd5757516d21eccdad25ddd456d2913c2fb215vboxsync if ((u32NewValue & HPET_TN_INT_TYPE) == HPET_TIMER_TYPE_LEVEL)
016096e367cd20c3d3c3fd9a6650b55935c2e31dvboxsync LogRel(("level-triggered config not yet supported\n"));
b2bc8de1367ae24e1b27b53921d0b32ee3df7acdvboxsync /* We only care about lower 32-bits so far */
3ebd5757516d21eccdad25ddd456d2913c2fb215vboxsync pHpetTimer->u64Config = hpetUpdateMasked(u32NewValue, iOldValue, u64Mask);
016096e367cd20c3d3c3fd9a6650b55935c2e31dvboxsync case HPET_TN_CMP: /* lower bits of comparator register */
e562a8bb17c0dfa1c316708e085a3a92fcc80521vboxsync DEVHPET_LOCK_BOTH_RETURN(pThis, VINF_IOM_HC_MMIO_WRITE);
e562a8bb17c0dfa1c316708e085a3a92fcc80521vboxsync Log(("write HPET_TN_CMP on %d: %#x\n", iTimerNo, u32NewValue));
b2bc8de1367ae24e1b27b53921d0b32ee3df7acdvboxsync pHpetTimer->u64Period = (pHpetTimer->u64Period & UINT64_C(0xffffffff00000000))
b2bc8de1367ae24e1b27b53921d0b32ee3df7acdvboxsync pHpetTimer->u64Cmp = (pHpetTimer->u64Cmp & UINT64_C(0xffffffff00000000))
e562a8bb17c0dfa1c316708e085a3a92fcc80521vboxsync Log2(("after HPET_TN_CMP cmp=%#llx per=%#llx\n", pHpetTimer->u64Cmp, pHpetTimer->u64Period));
36fbf6dcd3e6b2e5891456b730577ff0eb355c9fvboxsync case HPET_TN_CMP + 4: /* upper bits of comparator register */
e562a8bb17c0dfa1c316708e085a3a92fcc80521vboxsync DEVHPET_LOCK_BOTH_RETURN(pThis, VINF_IOM_HC_MMIO_WRITE);
e562a8bb17c0dfa1c316708e085a3a92fcc80521vboxsync Log(("write HPET_TN_CMP + 4 on %d: %#x\n", iTimerNo, u32NewValue));
e562a8bb17c0dfa1c316708e085a3a92fcc80521vboxsync pHpetTimer->u64Period = RT_MAKE_U64(pHpetTimer->u64Period, u32NewValue);
e562a8bb17c0dfa1c316708e085a3a92fcc80521vboxsync pHpetTimer->u64Cmp = RT_MAKE_U64(pHpetTimer->u64Cmp, u32NewValue);
e562a8bb17c0dfa1c316708e085a3a92fcc80521vboxsync Log2(("after HPET_TN_CMP+4 cmp=%llx per=%llx tmr=%d\n", pHpetTimer->u64Cmp, pHpetTimer->u64Period, iTimerNo));
e562a8bb17c0dfa1c316708e085a3a92fcc80521vboxsync static unsigned s_cOccurences = 0;
e562a8bb17c0dfa1c316708e085a3a92fcc80521vboxsync LogRel(("invalid timer register write: %d\n", iTimerReg));
3b1aa24d99d0f9cc157cf72ca76444b2feca3277vboxsync/* -=-=-=-=-=- Non-timer register accesses -=-=-=-=-=- */
8a54ed337392872c7cfcfb96f173468bbbb0f7fcvboxsync * Read a 32-bit HPET register.
8a54ed337392872c7cfcfb96f173468bbbb0f7fcvboxsync * @returns Strict VBox status code.
8a54ed337392872c7cfcfb96f173468bbbb0f7fcvboxsync * @param pThis The HPET state.
8a54ed337392872c7cfcfb96f173468bbbb0f7fcvboxsync * @param idxReg The register to read.
8a54ed337392872c7cfcfb96f173468bbbb0f7fcvboxsync * @param pu32Value Where to return the register value.
e562a8bb17c0dfa1c316708e085a3a92fcc80521vboxsync * @remarks The caller must not own the device lock if HPET_COUNTER is read.
e562a8bb17c0dfa1c316708e085a3a92fcc80521vboxsyncstatic int hpetConfigRegRead32(HpetState *pThis, uint32_t idxReg, uint32_t *pu32Value)
e562a8bb17c0dfa1c316708e085a3a92fcc80521vboxsync Assert(!PDMCritSectIsOwner(&pThis->csLock) || (idxReg != HPET_COUNTER && idxReg != HPET_COUNTER + 4));
8a54ed337392872c7cfcfb96f173468bbbb0f7fcvboxsync u32Value = (uint32_t)(pThis->u64Capabilities >> 32);
e562a8bb17c0dfa1c316708e085a3a92fcc80521vboxsync DEVHPET_LOCK_BOTH_RETURN(pThis, VINF_IOM_HC_MMIO_READ);
8a54ed337392872c7cfcfb96f173468bbbb0f7fcvboxsync /** @todo is it correct? */
8a54ed337392872c7cfcfb96f173468bbbb0f7fcvboxsync u32Value = (idxReg == HPET_COUNTER) ? (uint32_t)u64Ticks : (uint32_t)(u64Ticks >> 32);
8a54ed337392872c7cfcfb96f173468bbbb0f7fcvboxsync Log(("read HPET_COUNTER: %s part value %x (%#llx)\n",
8a54ed337392872c7cfcfb96f173468bbbb0f7fcvboxsync (idxReg == HPET_COUNTER) ? "low" : "high", u32Value, u64Ticks));
3ebd5757516d21eccdad25ddd456d2913c2fb215vboxsync * 32-bit write to a config register.
3ebd5757516d21eccdad25ddd456d2913c2fb215vboxsync * @returns Strict VBox status code.
3ebd5757516d21eccdad25ddd456d2913c2fb215vboxsync * @param pThis The HPET state.
3ebd5757516d21eccdad25ddd456d2913c2fb215vboxsync * @param idxReg The register being written to.
3ebd5757516d21eccdad25ddd456d2913c2fb215vboxsync * @param u32NewValue The value being written.
e562a8bb17c0dfa1c316708e085a3a92fcc80521vboxsync * @remarks The caller should not hold the device lock, unless it also holds
e562a8bb17c0dfa1c316708e085a3a92fcc80521vboxsync * the TM lock.
3ebd5757516d21eccdad25ddd456d2913c2fb215vboxsyncstatic int hpetConfigRegWrite32(HpetState *pThis, uint32_t idxReg, uint32_t u32NewValue)
e562a8bb17c0dfa1c316708e085a3a92fcc80521vboxsync Assert(!PDMCritSectIsOwner(&pThis->csLock) || TMTimerIsLockOwner(pThis->aTimers[0].CTX_SUFF(pTimer)));
e562a8bb17c0dfa1c316708e085a3a92fcc80521vboxsync DEVHPET_LOCK_BOTH_RETURN(pThis, VINF_IOM_HC_MMIO_WRITE);
b2bc8de1367ae24e1b27b53921d0b32ee3df7acdvboxsync uint32_t const iOldValue = (uint32_t)(pThis->u64HpetConfig);
3ebd5757516d21eccdad25ddd456d2913c2fb215vboxsync Log(("write HPET_CFG: %x (old %x)\n", u32NewValue, iOldValue));
3614117c1132a61599e6190939e775cafe549411vboxsync * This check must be here, before actual update, as hpetLegacyMode
3614117c1132a61599e6190939e775cafe549411vboxsync * may request retry in R3 - so we must keep state intact.
3ebd5757516d21eccdad25ddd456d2913c2fb215vboxsync rc = pThis->pHpetHlpR3->pfnSetLegacyMode(pThis->pDevInsR3, RT_BOOL(u32NewValue & HPET_CFG_LEGACY));
3ebd5757516d21eccdad25ddd456d2913c2fb215vboxsync pThis->u64HpetConfig = hpetUpdateMasked(u32NewValue, iOldValue, HPET_CFG_WRITE_MASK);
3ebd5757516d21eccdad25ddd456d2913c2fb215vboxsync if (hpetBitJustSet(iOldValue, u32NewValue, HPET_CFG_ENABLE))
3ebd5757516d21eccdad25ddd456d2913c2fb215vboxsync/** @todo Only get the time stamp once when reprogramming? */
016096e367cd20c3d3c3fd9a6650b55935c2e31dvboxsync /* Enable main counter and interrupt generation. */
fe554d9c0e3a6de4ba221610ac95a44c7d288e01vboxsync pThis->u64HpetOffset = hpetTicksToNs(pThis, pThis->u64HpetCounter)
7c48fdac0546978ed14617c8096734ce2d18c8e5vboxsync if (pThis->aTimers[i].u64Cmp != hpetInvalidValue(&pThis->aTimers[i]))
3ebd5757516d21eccdad25ddd456d2913c2fb215vboxsync else if (hpetBitJustCleared(iOldValue, u32NewValue, HPET_CFG_ENABLE))
016096e367cd20c3d3c3fd9a6650b55935c2e31dvboxsync /* Halt main counter and disable interrupt generation. */
e562a8bb17c0dfa1c316708e085a3a92fcc80521vboxsync DEVHPET_LOCK_RETURN(pThis, VINF_IOM_HC_MMIO_WRITE);
3ebd5757516d21eccdad25ddd456d2913c2fb215vboxsync pThis->u64HpetConfig = hpetUpdateMasked((uint64_t)u32NewValue << 32,
3ebd5757516d21eccdad25ddd456d2913c2fb215vboxsync Log(("write HPET_CFG + 4: %x -> %#llx\n", u32NewValue, pThis->u64HpetConfig));
e562a8bb17c0dfa1c316708e085a3a92fcc80521vboxsync DEVHPET_LOCK_RETURN(pThis, VINF_IOM_HC_MMIO_WRITE);
3ebd5757516d21eccdad25ddd456d2913c2fb215vboxsync /* Clear ISR for all set bits in u32NewValue, see p. 14 of the HPET spec. */
3ebd5757516d21eccdad25ddd456d2913c2fb215vboxsync Log(("write HPET_STATUS: %x -> ISR=%#llx\n", u32NewValue, pThis->u64Isr));
3ebd5757516d21eccdad25ddd456d2913c2fb215vboxsync static unsigned s_cOccurrences = 0;
3ebd5757516d21eccdad25ddd456d2913c2fb215vboxsync LogRel(("Writing HPET_STATUS + 4 with non-zero, ignored\n"));
e562a8bb17c0dfa1c316708e085a3a92fcc80521vboxsync DEVHPET_LOCK_RETURN(pThis, VINF_IOM_HC_MMIO_WRITE);
3ebd5757516d21eccdad25ddd456d2913c2fb215vboxsync pThis->u64HpetCounter = RT_MAKE_U64(u32NewValue, pThis->u64HpetCounter);
3ebd5757516d21eccdad25ddd456d2913c2fb215vboxsync Log(("write HPET_COUNTER: %#x -> %llx\n", u32NewValue, pThis->u64HpetCounter));
e562a8bb17c0dfa1c316708e085a3a92fcc80521vboxsync DEVHPET_LOCK_RETURN(pThis, VINF_IOM_HC_MMIO_WRITE);
3ebd5757516d21eccdad25ddd456d2913c2fb215vboxsync pThis->u64HpetCounter = RT_MAKE_U64(pThis->u64HpetCounter, u32NewValue);
3ebd5757516d21eccdad25ddd456d2913c2fb215vboxsync Log(("write HPET_COUNTER + 4: %#x -> %llx\n", u32NewValue, pThis->u64HpetCounter));
e562a8bb17c0dfa1c316708e085a3a92fcc80521vboxsync static unsigned s_cOccurences = 0;
e562a8bb17c0dfa1c316708e085a3a92fcc80521vboxsync LogRel(("invalid HPET config write: %x\n", idxReg));
3ebd5757516d21eccdad25ddd456d2913c2fb215vboxsync/* -=-=-=-=-=- MMIO callbacks -=-=-=-=-=- */
3ebd5757516d21eccdad25ddd456d2913c2fb215vboxsync * @callback_method_impl{FNIOMMMIOREAD}
3ebd5757516d21eccdad25ddd456d2913c2fb215vboxsyncPDMBOTHCBDECL(int) hpetMMIORead(PPDMDEVINS pDevIns, void *pvUser, RTGCPHYS GCPhysAddr, void *pv, unsigned cb)
3ebd5757516d21eccdad25ddd456d2913c2fb215vboxsync HpetState *pThis = PDMINS_2_DATA(pDevIns, HpetState*);
3ebd5757516d21eccdad25ddd456d2913c2fb215vboxsync uint32_t const idxReg = (uint32_t)(GCPhysAddr - HPET_BASE);
3ebd5757516d21eccdad25ddd456d2913c2fb215vboxsync LogFlow(("hpetMMIORead (%d): %llx (%x)\n", cb, (uint64_t)GCPhysAddr, idxReg));
3ebd5757516d21eccdad25ddd456d2913c2fb215vboxsync rc = hpetConfigRegRead32(pThis, idxReg, (uint32_t *)pv);
3ebd5757516d21eccdad25ddd456d2913c2fb215vboxsync /* Unaligned accesses not allowed */
3ebd5757516d21eccdad25ddd456d2913c2fb215vboxsync rc = PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "idxReg=%#x cb=8\n", idxReg);
3ebd5757516d21eccdad25ddd456d2913c2fb215vboxsync /* Split the access except for timing sensitive registers. The
3ebd5757516d21eccdad25ddd456d2913c2fb215vboxsync others assume the protection of the lock. */
3ebd5757516d21eccdad25ddd456d2913c2fb215vboxsync /* When reading HPET counter we must read it in a single read,
3ebd5757516d21eccdad25ddd456d2913c2fb215vboxsync to avoid unexpected time jumps on 32-bit overflow. */
e562a8bb17c0dfa1c316708e085a3a92fcc80521vboxsync DEVHPET_LOCK_BOTH_RETURN(pThis, VINF_IOM_HC_MMIO_READ);
e562a8bb17c0dfa1c316708e085a3a92fcc80521vboxsync rc = hpetTimerRegRead32(pThis, iTimer, iTimerReg, &pValue->s.Lo);
e562a8bb17c0dfa1c316708e085a3a92fcc80521vboxsync rc = hpetTimerRegRead32(pThis, iTimer, iTimerReg + 4, &pValue->s.Hi);
e562a8bb17c0dfa1c316708e085a3a92fcc80521vboxsync /* for most 8-byte accesses we just split them, happens under lock anyway. */
e562a8bb17c0dfa1c316708e085a3a92fcc80521vboxsync rc = hpetConfigRegRead32(pThis, idxReg, &pValue->s.Lo);
e562a8bb17c0dfa1c316708e085a3a92fcc80521vboxsync rc = hpetConfigRegRead32(pThis, idxReg + 4, &pValue->s.Hi);
016096e367cd20c3d3c3fd9a6650b55935c2e31dvboxsync AssertReleaseMsgFailed(("cb=%d\n", cb)); /* for now we assume simple accesses. */
3ebd5757516d21eccdad25ddd456d2913c2fb215vboxsync * @callback_method_impl{FNIOMMMIOWRITE}
3ebd5757516d21eccdad25ddd456d2913c2fb215vboxsyncPDMBOTHCBDECL(int) hpetMMIOWrite(PPDMDEVINS pDevIns, void *pvUser, RTGCPHYS GCPhysAddr, void *pv, unsigned cb)
b2bc8de1367ae24e1b27b53921d0b32ee3df7acdvboxsync HpetState *pThis = PDMINS_2_DATA(pDevIns, HpetState*);
3ebd5757516d21eccdad25ddd456d2913c2fb215vboxsync uint32_t idxReg = (uint32_t)(GCPhysAddr - HPET_BASE);
3ebd5757516d21eccdad25ddd456d2913c2fb215vboxsync LogFlow(("hpetMMIOWrite: cb=%u reg=%03x (%RGp) val=%llx\n",
3ebd5757516d21eccdad25ddd456d2913c2fb215vboxsync cb, idxReg, GCPhysAddr, cb == 4 ? *(uint32_t *)pv : cb == 8 ? *(uint64_t *)pv : 0xdeadbeef));
3ebd5757516d21eccdad25ddd456d2913c2fb215vboxsync rc = hpetConfigRegWrite32(pThis, idxReg, *(uint32_t const *)pv);
3ebd5757516d21eccdad25ddd456d2913c2fb215vboxsync /* Unaligned accesses are not allowed. */
3ebd5757516d21eccdad25ddd456d2913c2fb215vboxsync rc = PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "idxReg=%#x cb=8\n", idxReg);
3ebd5757516d21eccdad25ddd456d2913c2fb215vboxsync /* Split the access and rely on the locking to prevent trouble. */
e562a8bb17c0dfa1c316708e085a3a92fcc80521vboxsync DEVHPET_LOCK_BOTH_RETURN(pThis, VINF_IOM_HC_MMIO_WRITE);
3ebd5757516d21eccdad25ddd456d2913c2fb215vboxsync/** @todo Consider handling iTimerReg == HPET_TN_CMP specially here */
3ebd5757516d21eccdad25ddd456d2913c2fb215vboxsync rc = hpetTimerRegWrite32(pThis, iTimer, iTimerReg, uValue.s.Lo);
3ebd5757516d21eccdad25ddd456d2913c2fb215vboxsync rc = hpetTimerRegWrite32(pThis, iTimer, iTimerReg + 4, uValue.s.Hi);
3ebd5757516d21eccdad25ddd456d2913c2fb215vboxsync rc = hpetConfigRegWrite32(pThis, idxReg, uValue.s.Lo);
3ebd5757516d21eccdad25ddd456d2913c2fb215vboxsync rc = hpetConfigRegWrite32(pThis, idxReg + 4, uValue.s.Hi);
016096e367cd20c3d3c3fd9a6650b55935c2e31dvboxsync AssertReleaseMsgFailed(("cb=%d\n", cb)); /* for now we assume simple accesses. */
3ebd5757516d21eccdad25ddd456d2913c2fb215vboxsync/* -=-=-=-=-=- Timer Callback Processing -=-=-=-=-=- */
3ebd5757516d21eccdad25ddd456d2913c2fb215vboxsync * Gets the IRQ of an HPET timer.
3ebd5757516d21eccdad25ddd456d2913c2fb215vboxsync * @returns IRQ number.
3ebd5757516d21eccdad25ddd456d2913c2fb215vboxsync * @param pHpetTimer The HPET timer.
3ebd5757516d21eccdad25ddd456d2913c2fb215vboxsyncstatic uint32_t hpetTimerCbGetIrq(struct HpetTimer const *pHpetTimer)
3ebd5757516d21eccdad25ddd456d2913c2fb215vboxsync * Per spec, in legacy mode HPET timers wired as:
3ebd5757516d21eccdad25ddd456d2913c2fb215vboxsync * timer 0: IRQ0 for PIC and IRQ2 for APIC
3ebd5757516d21eccdad25ddd456d2913c2fb215vboxsync * timer 1: IRQ8 for both PIC and APIC
3ebd5757516d21eccdad25ddd456d2913c2fb215vboxsync * ISA IRQ delivery logic will take care of correct delivery
3ebd5757516d21eccdad25ddd456d2913c2fb215vboxsync * to the different ICs.
3ebd5757516d21eccdad25ddd456d2913c2fb215vboxsync && (pHpetTimer->CTX_SUFF(pHpet)->u64HpetConfig & HPET_CFG_LEGACY))
3ebd5757516d21eccdad25ddd456d2913c2fb215vboxsync return (pHpetTimer->u64Config & HPET_TN_INT_ROUTE_MASK) >> HPET_TN_INT_ROUTE_SHIFT;
3ebd5757516d21eccdad25ddd456d2913c2fb215vboxsync * Used by hpetTimerCb to update the IRQ status.
3ebd5757516d21eccdad25ddd456d2913c2fb215vboxsync * @param pThis The HPET device state.
3ebd5757516d21eccdad25ddd456d2913c2fb215vboxsync * @param pHpetTimer The HPET timer.
3ebd5757516d21eccdad25ddd456d2913c2fb215vboxsyncstatic void hpetTimerCbUpdateIrq(HpetState *pThis, struct HpetTimer *pHpetTimer)
23603ed361f22874964e3a841add2c58ec2bb1eavboxsync /** @todo: is it correct? */
3ebd5757516d21eccdad25ddd456d2913c2fb215vboxsync /* ISR bits are only set in level-triggered mode. */
b2bc8de1367ae24e1b27b53921d0b32ee3df7acdvboxsync if ((pHpetTimer->u64Config & HPET_TN_INT_TYPE) == HPET_TIMER_TYPE_LEVEL)
b2bc8de1367ae24e1b27b53921d0b32ee3df7acdvboxsync pThis->u64Isr |= (uint64_t)(1 << pHpetTimer->idxTimer);
3ebd5757516d21eccdad25ddd456d2913c2fb215vboxsync /* We trigger flip/flop in edge-triggered mode and do nothing in
3ebd5757516d21eccdad25ddd456d2913c2fb215vboxsync level-triggered mode yet. */
b2bc8de1367ae24e1b27b53921d0b32ee3df7acdvboxsync if ((pHpetTimer->u64Config & HPET_TN_INT_TYPE) == HPET_TIMER_TYPE_EDGE)
23603ed361f22874964e3a841add2c58ec2bb1eavboxsync pThis->pHpetHlpR3->pfnSetIrq(pThis->CTX_SUFF(pDevIns), irq, PDM_IRQ_LEVEL_FLIP_FLOP);
3ebd5757516d21eccdad25ddd456d2913c2fb215vboxsync /** @todo: implement IRQs in level-triggered mode */
016096e367cd20c3d3c3fd9a6650b55935c2e31dvboxsync * Device timer callback function.
016096e367cd20c3d3c3fd9a6650b55935c2e31dvboxsync * @param pDevIns Device instance of the device which registered the timer.
016096e367cd20c3d3c3fd9a6650b55935c2e31dvboxsync * @param pTimer The timer handle.
016096e367cd20c3d3c3fd9a6650b55935c2e31dvboxsync * @param pvUser Pointer to the HPET timer state.
3ebd5757516d21eccdad25ddd456d2913c2fb215vboxsyncstatic DECLCALLBACK(void) hpetTimerCb(PPDMDEVINS pDevIns, PTMTIMER pTimer, void *pvUser)
016096e367cd20c3d3c3fd9a6650b55935c2e31dvboxsync HpetState *pThis = PDMINS_2_DATA(pDevIns, HpetState *);
b2bc8de1367ae24e1b27b53921d0b32ee3df7acdvboxsync if ((pHpetTimer->u64Config & HPET_TN_PERIODIC) && (u64Period != 0))
b2bc8de1367ae24e1b27b53921d0b32ee3df7acdvboxsync Log4(("HPET: periodical: next in %llu\n", hpetTicksToNs(pThis, u64Diff)));
b2bc8de1367ae24e1b27b53921d0b32ee3df7acdvboxsync TMTimerSetNano(pTimer, hpetTicksToNs(pThis, u64Diff));
b2bc8de1367ae24e1b27b53921d0b32ee3df7acdvboxsync TMTimerSetNano(pTimer, hpetTicksToNs(pThis, u64Diff));
016096e367cd20c3d3c3fd9a6650b55935c2e31dvboxsync /* Should it really be under lock, does it really matter? */
3ebd5757516d21eccdad25ddd456d2913c2fb215vboxsync/* -=-=-=-=-=- DBGF Info Handlers -=-=-=-=-=- */
3ebd5757516d21eccdad25ddd456d2913c2fb215vboxsync * @callback_method_impl{FNDBGFHANDLERDEV}
3ebd5757516d21eccdad25ddd456d2913c2fb215vboxsyncstatic DECLCALLBACK(void) hpetInfo(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
3ebd5757516d21eccdad25ddd456d2913c2fb215vboxsync HpetState *pThis = PDMINS_2_DATA(pDevIns, HpetState *);
3ebd5757516d21eccdad25ddd456d2913c2fb215vboxsync "HPET status:\n"
3ebd5757516d21eccdad25ddd456d2913c2fb215vboxsync " config = %016RX64\n"
3ebd5757516d21eccdad25ddd456d2913c2fb215vboxsync " offset = %016RX64 counter = %016RX64 isr = %016RX64\n"
3ebd5757516d21eccdad25ddd456d2913c2fb215vboxsync " legacy mode is %s\n",
3ebd5757516d21eccdad25ddd456d2913c2fb215vboxsync pThis->u64HpetOffset, pThis->u64HpetCounter, pThis->u64Isr,
3ebd5757516d21eccdad25ddd456d2913c2fb215vboxsync !!(pThis->u64HpetConfig & HPET_CFG_LEGACY) ? "on" : "off");
3ebd5757516d21eccdad25ddd456d2913c2fb215vboxsync "Timers:\n");
3ebd5757516d21eccdad25ddd456d2913c2fb215vboxsync for (unsigned i = 0; i < HPET_NUM_TIMERS; i++)
3ebd5757516d21eccdad25ddd456d2913c2fb215vboxsync pHlp->pfnPrintf(pHlp, " %d: comparator=%016RX64 period(hidden)=%016RX64 cfg=%016RX64\n",
3ebd5757516d21eccdad25ddd456d2913c2fb215vboxsync/* -=-=-=-=-=- Saved State -=-=-=-=-=- */
3ebd5757516d21eccdad25ddd456d2913c2fb215vboxsync * @callback_method_impl{FNSSMDEVLIVEEXEC}
3ebd5757516d21eccdad25ddd456d2913c2fb215vboxsyncstatic DECLCALLBACK(int) hpetLiveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uPass)
3ebd5757516d21eccdad25ddd456d2913c2fb215vboxsync HpetState *pThis = PDMINS_2_DATA(pDevIns, HpetState *);
3ebd5757516d21eccdad25ddd456d2913c2fb215vboxsync * @callback_method_impl{FNSSMDEVSAVEEXEC}
3ebd5757516d21eccdad25ddd456d2913c2fb215vboxsyncstatic DECLCALLBACK(int) hpetSaveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
3ebd5757516d21eccdad25ddd456d2913c2fb215vboxsync HpetState *pThis = PDMINS_2_DATA(pDevIns, HpetState *);
3ebd5757516d21eccdad25ddd456d2913c2fb215vboxsync * The config.
3ebd5757516d21eccdad25ddd456d2913c2fb215vboxsync * The state.
3ebd5757516d21eccdad25ddd456d2913c2fb215vboxsync for (uint32_t iTimer = 0; iTimer < HPET_NUM_TIMERS; iTimer++)
3ebd5757516d21eccdad25ddd456d2913c2fb215vboxsync * @callback_method_impl{FNSSMDEVLOADEXEC}
3ebd5757516d21eccdad25ddd456d2913c2fb215vboxsyncstatic DECLCALLBACK(int) hpetLoadExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
3ebd5757516d21eccdad25ddd456d2913c2fb215vboxsync HpetState *pThis = PDMINS_2_DATA(pDevIns, HpetState *);
3ebd5757516d21eccdad25ddd456d2913c2fb215vboxsync * Version checks.
3ebd5757516d21eccdad25ddd456d2913c2fb215vboxsync * The config.
3ebd5757516d21eccdad25ddd456d2913c2fb215vboxsync return SSMR3SetCfgError(pSSM, RT_SRC_POS, N_("Config mismatch - wrong number of timers: saved=%#x config=%#x"),
3ebd5757516d21eccdad25ddd456d2913c2fb215vboxsync * The state.
3ebd5757516d21eccdad25ddd456d2913c2fb215vboxsync for (uint32_t iTimer = 0; iTimer < HPET_NUM_TIMERS; iTimer++)
3ebd5757516d21eccdad25ddd456d2913c2fb215vboxsync/* -=-=-=-=-=- PDMDEVREG -=-=-=-=-=- */
3ebd5757516d21eccdad25ddd456d2913c2fb215vboxsync * @interface_method_impl{PDMDEVREG,pfnRelocate}
016096e367cd20c3d3c3fd9a6650b55935c2e31dvboxsyncstatic DECLCALLBACK(void) hpetRelocate(PPDMDEVINS pDevIns, RTGCINTPTR offDelta)
016096e367cd20c3d3c3fd9a6650b55935c2e31dvboxsync HpetState *pThis = PDMINS_2_DATA(pDevIns, HpetState *);
016096e367cd20c3d3c3fd9a6650b55935c2e31dvboxsync pThis->pHpetHlpRC = pThis->pHpetHlpR3->pfnGetRCHelpers(pDevIns);
8287c906b9b1d215824d4cdf6c1eaf40681ebfa8vboxsync for (unsigned i = 0; i < RT_ELEMENTS(pThis->aTimers); i++)
3ebd5757516d21eccdad25ddd456d2913c2fb215vboxsync * @interface_method_impl{PDMDEVREG,pfnReset}
016096e367cd20c3d3c3fd9a6650b55935c2e31dvboxsyncstatic DECLCALLBACK(void) hpetReset(PPDMDEVINS pDevIns)
016096e367cd20c3d3c3fd9a6650b55935c2e31dvboxsync HpetState *pThis = PDMINS_2_DATA(pDevIns, HpetState *);
8287c906b9b1d215824d4cdf6c1eaf40681ebfa8vboxsync for (unsigned i = 0; i < HPET_NUM_TIMERS; i++)
016096e367cd20c3d3c3fd9a6650b55935c2e31dvboxsync /* capable of periodic operations and 64-bits */
b2bc8de1367ae24e1b27b53921d0b32ee3df7acdvboxsync pHpetTimer->u64Config = HPET_TN_PERIODIC_CAP | HPET_TN_SIZE_CAP;
016096e367cd20c3d3c3fd9a6650b55935c2e31dvboxsync /* We can do all IRQs */
b2bc8de1367ae24e1b27b53921d0b32ee3df7acdvboxsync pHpetTimer->u64Config |= ((uint64_t)u32RoutingCap) << 32;
fe554d9c0e3a6de4ba221610ac95a44c7d288e01vboxsync /* 64-bit main counter; 3 timers supported; LegacyReplacementRoute. */
8287c906b9b1d215824d4cdf6c1eaf40681ebfa8vboxsync uint32_t u32Caps = (1 << 15) /* LEG_RT_CAP - LegacyReplacementRoute capable. */
8287c906b9b1d215824d4cdf6c1eaf40681ebfa8vboxsync | (1 << 13) /* COUNTER_SIZE_CAP - Main counter is 64-bit capable. */
8287c906b9b1d215824d4cdf6c1eaf40681ebfa8vboxsync | (HPET_NUM_TIMERS << 8) /* NUM_TIM_CAP - Number of timers -1.
8287c906b9b1d215824d4cdf6c1eaf40681ebfa8vboxsync Actually ICH9 has 4 timers, but to avoid breaking
8287c906b9b1d215824d4cdf6c1eaf40681ebfa8vboxsync saved state we'll stick with 3 so far. */ /** @todo fix this ICH9 timer count bug. */
016096e367cd20c3d3c3fd9a6650b55935c2e31dvboxsync pThis->u64Capabilities = (u32Vendor << 16) | u32Caps;
fe554d9c0e3a6de4ba221610ac95a44c7d288e01vboxsync pThis->u64Capabilities |= ((uint64_t)(pThis->fIch9 ? HPET_CLK_PERIOD_ICH9 : HPET_CLK_PERIOD) << 32);
762a68c2bb3ccde807330e3d1cb05f8b244a5f72vboxsync /* Notify PIT/RTC devices */
3ebd5757516d21eccdad25ddd456d2913c2fb215vboxsync pThis->pHpetHlpR3->pfnSetLegacyMode(pDevIns, false /*fActive*/);
016096e367cd20c3d3c3fd9a6650b55935c2e31dvboxsync * @interface_method_impl{PDMDEVREG,pfnConstruct}
016096e367cd20c3d3c3fd9a6650b55935c2e31dvboxsyncstatic DECLCALLBACK(int) hpetConstruct(PPDMDEVINS pDevIns, int iInstance, PCFGMNODE pCfg)
016096e367cd20c3d3c3fd9a6650b55935c2e31dvboxsync HpetState *pThis = PDMINS_2_DATA(pDevIns, HpetState *);
fe554d9c0e3a6de4ba221610ac95a44c7d288e01vboxsync /* Only one HPET device now, as we use fixed MMIO region. */
3ebd5757516d21eccdad25ddd456d2913c2fb215vboxsync * Validate and read the configuration.
3ebd5757516d21eccdad25ddd456d2913c2fb215vboxsync PDMDEV_VALIDATE_CONFIG_RETURN(pDevIns, "GCEnabled|R0Enabled|ICH9", "");
3ebd5757516d21eccdad25ddd456d2913c2fb215vboxsync int rc = CFGMR3QueryBoolDef(pCfg, "GCEnabled", &fRCEnabled, true);
016096e367cd20c3d3c3fd9a6650b55935c2e31dvboxsync N_("Configuration error: Querying \"GCEnabled\" as a bool failed"));
016096e367cd20c3d3c3fd9a6650b55935c2e31dvboxsync rc = CFGMR3QueryBoolDef(pCfg, "R0Enabled", &fR0Enabled, true);
016096e367cd20c3d3c3fd9a6650b55935c2e31dvboxsync N_("Configuration error: failed to read R0Enabled as boolean"));
3ebd5757516d21eccdad25ddd456d2913c2fb215vboxsync rc = CFGMR3QueryBoolDef(pCfg, "ICH9", &pThis->fIch9, false);
fe554d9c0e3a6de4ba221610ac95a44c7d288e01vboxsync N_("Configuration error: failed to read ICH9 as boolean"));
8287c906b9b1d215824d4cdf6c1eaf40681ebfa8vboxsync * Initialize the device state
8287c906b9b1d215824d4cdf6c1eaf40681ebfa8vboxsync rc = PDMDevHlpCritSectInit(pDevIns, &pThis->csLock, RT_SRC_POS, "HPET#%u", pDevIns->iInstance);
3ebd5757516d21eccdad25ddd456d2913c2fb215vboxsync /* Init the HPET timers. */
8287c906b9b1d215824d4cdf6c1eaf40681ebfa8vboxsync for (unsigned i = 0; i < HPET_NUM_TIMERS; i++)
8287c906b9b1d215824d4cdf6c1eaf40681ebfa8vboxsync pHpetTimer->pHpetR0 = PDMINS_2_DATA_R0PTR(pDevIns);
8287c906b9b1d215824d4cdf6c1eaf40681ebfa8vboxsync pHpetTimer->pHpetRC = PDMINS_2_DATA_RCPTR(pDevIns);
3ebd5757516d21eccdad25ddd456d2913c2fb215vboxsync rc = PDMDevHlpTMTimerCreate(pDevIns, TMCLOCK_VIRTUAL_SYNC, hpetTimerCb, pHpetTimer,
8287c906b9b1d215824d4cdf6c1eaf40681ebfa8vboxsync pThis->aTimers[i].pTimerRC = TMTimerRCPtr(pThis->aTimers[i].pTimerR3);
8287c906b9b1d215824d4cdf6c1eaf40681ebfa8vboxsync pThis->aTimers[i].pTimerR0 = TMTimerR0Ptr(pThis->aTimers[i].pTimerR3);
601d153b9b7960b2a58cc013b6ac3aa00b95bdeavboxsync rc = TMR3TimerSetCritSect(pThis->aTimers[i].pTimerR3, &pThis->csLock);
3ebd5757516d21eccdad25ddd456d2913c2fb215vboxsync /* This must be done prior to registering the HPET, right? */
016096e367cd20c3d3c3fd9a6650b55935c2e31dvboxsync * Register the HPET and get helpers.
016096e367cd20c3d3c3fd9a6650b55935c2e31dvboxsync rc = PDMDevHlpHPETRegister(pDevIns, &HpetReg, &pThis->pHpetHlpR3);
016096e367cd20c3d3c3fd9a6650b55935c2e31dvboxsync * Register the MMIO range, PDM API requests page aligned
016096e367cd20c3d3c3fd9a6650b55935c2e31dvboxsync * addresses and sizes.
016096e367cd20c3d3c3fd9a6650b55935c2e31dvboxsync rc = PDMDevHlpMMIORegister(pDevIns, HPET_BASE, 0x1000, pThis,
016096e367cd20c3d3c3fd9a6650b55935c2e31dvboxsync rc = PDMDevHlpMMIORegisterRC(pDevIns, HPET_BASE, 0x1000, 0,
016096e367cd20c3d3c3fd9a6650b55935c2e31dvboxsync pThis->pHpetHlpRC = pThis->pHpetHlpR3->pfnGetRCHelpers(pDevIns);
8287c906b9b1d215824d4cdf6c1eaf40681ebfa8vboxsync AssertReturn(pThis->pHpetHlpRC != NIL_RTRCPTR, VERR_INTERNAL_ERROR);
016096e367cd20c3d3c3fd9a6650b55935c2e31dvboxsync rc = PDMDevHlpMMIORegisterR0(pDevIns, HPET_BASE, 0x1000, 0,
016096e367cd20c3d3c3fd9a6650b55935c2e31dvboxsync pThis->pHpetHlpR0 = pThis->pHpetHlpR3->pfnGetR0Helpers(pDevIns);
8287c906b9b1d215824d4cdf6c1eaf40681ebfa8vboxsync AssertReturn(pThis->pHpetHlpR0 != NIL_RTR0PTR, VERR_INTERNAL_ERROR);
016096e367cd20c3d3c3fd9a6650b55935c2e31dvboxsync /* Register SSM callbacks */
016096e367cd20c3d3c3fd9a6650b55935c2e31dvboxsync rc = PDMDevHlpSSMRegister3(pDevIns, HPET_SAVED_STATE_VERSION, sizeof(*pThis), hpetLiveExec, hpetSaveExec, hpetLoadExec);
3ebd5757516d21eccdad25ddd456d2913c2fb215vboxsync /* Register an info callback. */
016096e367cd20c3d3c3fd9a6650b55935c2e31dvboxsync PDMDevHlpDBGFInfoRegister(pDevIns, "hpet", "Display HPET status. (no arguments)", hpetInfo);
016096e367cd20c3d3c3fd9a6650b55935c2e31dvboxsync * The device registration structure.
016096e367cd20c3d3c3fd9a6650b55935c2e31dvboxsync /* u32Version */
016096e367cd20c3d3c3fd9a6650b55935c2e31dvboxsync /* szName */
016096e367cd20c3d3c3fd9a6650b55935c2e31dvboxsync /* szRCMod */
016096e367cd20c3d3c3fd9a6650b55935c2e31dvboxsync "VBoxDDGC.gc",
016096e367cd20c3d3c3fd9a6650b55935c2e31dvboxsync /* szR0Mod */
016096e367cd20c3d3c3fd9a6650b55935c2e31dvboxsync "VBoxDDR0.r0",
016096e367cd20c3d3c3fd9a6650b55935c2e31dvboxsync /* pszDescription */
016096e367cd20c3d3c3fd9a6650b55935c2e31dvboxsync " High Precision Event Timer (HPET) Device",
016096e367cd20c3d3c3fd9a6650b55935c2e31dvboxsync /* fFlags */
016096e367cd20c3d3c3fd9a6650b55935c2e31dvboxsync PDM_DEVREG_FLAGS_HOST_BITS_DEFAULT | PDM_DEVREG_FLAGS_GUEST_BITS_32_64 | PDM_DEVREG_FLAGS_PAE36 | PDM_DEVREG_FLAGS_RC | PDM_DEVREG_FLAGS_R0,
016096e367cd20c3d3c3fd9a6650b55935c2e31dvboxsync /* fClass */
016096e367cd20c3d3c3fd9a6650b55935c2e31dvboxsync /* cMaxInstances */
016096e367cd20c3d3c3fd9a6650b55935c2e31dvboxsync /* cbInstance */
016096e367cd20c3d3c3fd9a6650b55935c2e31dvboxsync /* pfnConstruct */
016096e367cd20c3d3c3fd9a6650b55935c2e31dvboxsync /* pfnDestruct */
016096e367cd20c3d3c3fd9a6650b55935c2e31dvboxsync /* pfnRelocate */
016096e367cd20c3d3c3fd9a6650b55935c2e31dvboxsync /* pfnIOCtl */
016096e367cd20c3d3c3fd9a6650b55935c2e31dvboxsync /* pfnPowerOn */
016096e367cd20c3d3c3fd9a6650b55935c2e31dvboxsync /* pfnReset */
016096e367cd20c3d3c3fd9a6650b55935c2e31dvboxsync /* pfnSuspend */
016096e367cd20c3d3c3fd9a6650b55935c2e31dvboxsync /* pfnResume */
016096e367cd20c3d3c3fd9a6650b55935c2e31dvboxsync /* pfnAttach */
016096e367cd20c3d3c3fd9a6650b55935c2e31dvboxsync /* pfnDetach */
016096e367cd20c3d3c3fd9a6650b55935c2e31dvboxsync /* pfnQueryInterface. */
016096e367cd20c3d3c3fd9a6650b55935c2e31dvboxsync /* pfnInitComplete */
016096e367cd20c3d3c3fd9a6650b55935c2e31dvboxsync /* pfnPowerOff */
016096e367cd20c3d3c3fd9a6650b55935c2e31dvboxsync /* pfnSoftReset */
016096e367cd20c3d3c3fd9a6650b55935c2e31dvboxsync /* u32VersionEnd */
016096e367cd20c3d3c3fd9a6650b55935c2e31dvboxsync#endif /* IN_RING3 */
b2bc8de1367ae24e1b27b53921d0b32ee3df7acdvboxsync#endif /* !VBOX_DEVICE_STRUCT_TESTCASE */