70fc9d0c972c749656d6fb2ffafcdeec3d8874ecvboxsync * HPET virtual device - High Precision Event Timer emulation.
70fc9d0c972c749656d6fb2ffafcdeec3d8874ecvboxsync * Copyright (C) 2009-2013 Oracle Corporation
016096e367cd20c3d3c3fd9a6650b55935c2e31dvboxsync * This file is part of VirtualBox Open Source Edition (OSE), as
016096e367cd20c3d3c3fd9a6650b55935c2e31dvboxsync * available from http://www.virtualbox.org. This file is free software;
016096e367cd20c3d3c3fd9a6650b55935c2e31dvboxsync * you can redistribute it and/or modify it under the terms of the GNU
016096e367cd20c3d3c3fd9a6650b55935c2e31dvboxsync * General Public License (GPL) as published by the Free Software
016096e367cd20c3d3c3fd9a6650b55935c2e31dvboxsync * Foundation, in version 2 as it comes in the "COPYING" file of the
016096e367cd20c3d3c3fd9a6650b55935c2e31dvboxsync * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
016096e367cd20c3d3c3fd9a6650b55935c2e31dvboxsync * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
90a3b100d6364b9956ab5155b48b91e2d930f4a4vboxsync/* This implementation is based on the (generic) Intel IA-PC HPET specification
90a3b100d6364b9956ab5155b48b91e2d930f4a4vboxsync * and the Intel ICH9 datasheet.
016096e367cd20c3d3c3fd9a6650b55935c2e31dvboxsync/*******************************************************************************
016096e367cd20c3d3c3fd9a6650b55935c2e31dvboxsync* Header Files *
016096e367cd20c3d3c3fd9a6650b55935c2e31dvboxsync*******************************************************************************/
2f0d866e126dd288169fed591c259c1c6b4016e5vboxsync/*******************************************************************************
2f0d866e126dd288169fed591c259c1c6b4016e5vboxsync* Defined Constants And Macros *
2f0d866e126dd288169fed591c259c1c6b4016e5vboxsync*******************************************************************************/
016096e367cd20c3d3c3fd9a6650b55935c2e31dvboxsync * Current limitations:
016096e367cd20c3d3c3fd9a6650b55935c2e31dvboxsync * - not entirely correct time of interrupt, i.e. never
016096e367cd20c3d3c3fd9a6650b55935c2e31dvboxsync * schedule interrupt earlier than in 1ms
016096e367cd20c3d3c3fd9a6650b55935c2e31dvboxsync * - statistics not implemented
9b7ab382b3f9667e8847020e1e58f7143c4d2334vboxsync * - level-triggered mode not implemented
70fc9d0c972c749656d6fb2ffafcdeec3d8874ecvboxsync/** Base address for MMIO.
70fc9d0c972c749656d6fb2ffafcdeec3d8874ecvboxsync * On ICH9, it is 0xFED0x000 where 'x' is 0-3, default 0. We do not support
e95a7aab825fd803ca1f09d072d74fe1bedfbadbvboxsync * relocation as the platform firmware is responsible for configuring the
e95a7aab825fd803ca1f09d072d74fe1bedfbadbvboxsync * HPET base address and the OS isn't expected to move it.
e95a7aab825fd803ca1f09d072d74fe1bedfbadbvboxsync * WARNING: This has to match the ACPI tables! */
70fc9d0c972c749656d6fb2ffafcdeec3d8874ecvboxsync/** HPET reserves a 1K range. */
8742e4a4ddb7b62d21d96d56dd1baf01c9f22cecvboxsync/** The number of timers for PIIX4 / PIIX3. */
90a3b100d6364b9956ab5155b48b91e2d930f4a4vboxsync#define HPET_NUM_TIMERS_PIIX 3 /* Minimal implementation. */
8742e4a4ddb7b62d21d96d56dd1baf01c9f22cecvboxsync/** The number of timers for ICH9. */
63787aca0a2a16ec959a5294148726ccf898ddf1vboxsync/** HPET clock period for PIIX4 / PIIX3.
63787aca0a2a16ec959a5294148726ccf898ddf1vboxsync * 10000000 femtoseconds == 10ns.
63787aca0a2a16ec959a5294148726ccf898ddf1vboxsync/** HPET clock period for ICH9.
63787aca0a2a16ec959a5294148726ccf898ddf1vboxsync * 69841279 femtoseconds == 69.84 ns (1 / 14.31818MHz).
424a17baac7954212256747726f9c9d5a9d03f5avboxsync * Femtosecods in a nanosecond
70fc9d0c972c749656d6fb2ffafcdeec3d8874ecvboxsync/** @name Interrupt type
70fc9d0c972c749656d6fb2ffafcdeec3d8874ecvboxsync/** @name Delivery mode
70fc9d0c972c749656d6fb2ffafcdeec3d8874ecvboxsync#define HPET_TIMER_DELIVERY_APIC 0 /**< Delivery through APIC. */
70fc9d0c972c749656d6fb2ffafcdeec3d8874ecvboxsync#define HPET_TIMER_DELIVERY_FSB 1 /**< Delivery through FSB. */
70fc9d0c972c749656d6fb2ffafcdeec3d8874ecvboxsync/** @name Register offsets in HPET space.
70fc9d0c972c749656d6fb2ffafcdeec3d8874ecvboxsync#define HPET_PERIOD 0x004 /**< Clock period in femtoseconds. */
70fc9d0c972c749656d6fb2ffafcdeec3d8874ecvboxsync#define HPET_CFG 0x010 /**< Configuration register. */
70fc9d0c972c749656d6fb2ffafcdeec3d8874ecvboxsync#define HPET_COUNTER 0x0f0 /**< Main HPET counter. */
70fc9d0c972c749656d6fb2ffafcdeec3d8874ecvboxsync/** @name Timer N offsets (within each timer's space).
70fc9d0c972c749656d6fb2ffafcdeec3d8874ecvboxsync#define HPET_TN_CFG 0x000 /**< Timer N configuration. */
70fc9d0c972c749656d6fb2ffafcdeec3d8874ecvboxsync#define HPET_TN_CMP 0x008 /**< Timer N comparator. */
70fc9d0c972c749656d6fb2ffafcdeec3d8874ecvboxsync#define HPET_TN_ROUTE 0x010 /**< Timer N interrupt route. */
016096e367cd20c3d3c3fd9a6650b55935c2e31dvboxsync#define HPET_TN_CFG_BITS_READONLY_OR_RESERVED 0xffff80b1U
90a3b100d6364b9956ab5155b48b91e2d930f4a4vboxsync/** Extract the timer count from the capabilities. */
90a3b100d6364b9956ab5155b48b91e2d930f4a4vboxsync#define HPET_CAP_GET_TIMERS(a_u32) ( ((a_u32) >> 8) & 0x1f )
016096e367cd20c3d3c3fd9a6650b55935c2e31dvboxsync/** The version of the saved state. */
b2bc8de1367ae24e1b27b53921d0b32ee3df7acdvboxsync/** Empty saved state */
c060166f65b9dd2f1ed53e6e4cffdad948e01722vboxsync * Acquires the HPET lock or returns.
70fc9d0c972c749656d6fb2ffafcdeec3d8874ecvboxsync int rcLock = PDMCritSectEnter(&(a_pThis)->CritSect, (a_rcBusy)); \
c060166f65b9dd2f1ed53e6e4cffdad948e01722vboxsync } while (0)
c060166f65b9dd2f1ed53e6e4cffdad948e01722vboxsync * Releases the HPET lock.
70fc9d0c972c749656d6fb2ffafcdeec3d8874ecvboxsync do { PDMCritSectLeave(&(a_pThis)->CritSect); } while (0)
e562a8bb17c0dfa1c316708e085a3a92fcc80521vboxsync * Acquires the TM lock and HPET lock, returns on failure.
e562a8bb17c0dfa1c316708e085a3a92fcc80521vboxsync#define DEVHPET_LOCK_BOTH_RETURN(a_pThis, a_rcBusy) \
e562a8bb17c0dfa1c316708e085a3a92fcc80521vboxsync int rcLock = TMTimerLock((a_pThis)->aTimers[0].CTX_SUFF(pTimer), (a_rcBusy)); \
70fc9d0c972c749656d6fb2ffafcdeec3d8874ecvboxsync rcLock = PDMCritSectEnter(&(a_pThis)->CritSect, (a_rcBusy)); \
e562a8bb17c0dfa1c316708e085a3a92fcc80521vboxsync TMTimerUnlock((a_pThis)->aTimers[0].CTX_SUFF(pTimer)); \
e562a8bb17c0dfa1c316708e085a3a92fcc80521vboxsync } while (0)
e562a8bb17c0dfa1c316708e085a3a92fcc80521vboxsync * Releases the HPET lock and TM lock.
e562a8bb17c0dfa1c316708e085a3a92fcc80521vboxsync TMTimerUnlock((a_pThis)->aTimers[0].CTX_SUFF(pTimer)); \
e562a8bb17c0dfa1c316708e085a3a92fcc80521vboxsync } while (0)
2f0d866e126dd288169fed591c259c1c6b4016e5vboxsync/*******************************************************************************
2f0d866e126dd288169fed591c259c1c6b4016e5vboxsync* Structures and Typedefs *
2f0d866e126dd288169fed591c259c1c6b4016e5vboxsync*******************************************************************************/
70fc9d0c972c749656d6fb2ffafcdeec3d8874ecvboxsync * A HPET timer.
016096e367cd20c3d3c3fd9a6650b55935c2e31dvboxsync /** The HPET timer - R3 Ptr. */
016096e367cd20c3d3c3fd9a6650b55935c2e31dvboxsync /** Pointer to the instance data - R3 Ptr. */
016096e367cd20c3d3c3fd9a6650b55935c2e31dvboxsync /** The HPET timer - R0 Ptr. */
016096e367cd20c3d3c3fd9a6650b55935c2e31dvboxsync /** Pointer to the instance data - R0 Ptr. */
016096e367cd20c3d3c3fd9a6650b55935c2e31dvboxsync /** The HPET timer - RC Ptr. */
016096e367cd20c3d3c3fd9a6650b55935c2e31dvboxsync /** Pointer to the instance data - RC Ptr. */
b2bc8de1367ae24e1b27b53921d0b32ee3df7acdvboxsync /** Timer index. */
b2bc8de1367ae24e1b27b53921d0b32ee3df7acdvboxsync /** Wrap. */
b2bc8de1367ae24e1b27b53921d0b32ee3df7acdvboxsync /** Alignment. */
b2bc8de1367ae24e1b27b53921d0b32ee3df7acdvboxsync /** @name Memory-mapped, software visible timer registers.
b2bc8de1367ae24e1b27b53921d0b32ee3df7acdvboxsync /** Comparator. */
b2bc8de1367ae24e1b27b53921d0b32ee3df7acdvboxsync /** FSB route, not supported now. */
b2bc8de1367ae24e1b27b53921d0b32ee3df7acdvboxsync /** @name Hidden register state.
b2bc8de1367ae24e1b27b53921d0b32ee3df7acdvboxsync /** Last value written to comparator. */
70fc9d0c972c749656d6fb2ffafcdeec3d8874ecvboxsyncAssertCompileMemberAlignment(HPETTIMER, u64Config, sizeof(uint64_t));
70fc9d0c972c749656d6fb2ffafcdeec3d8874ecvboxsync * The HPET state.
016096e367cd20c3d3c3fd9a6650b55935c2e31dvboxsync /** Pointer to the device instance. - R3 ptr. */
016096e367cd20c3d3c3fd9a6650b55935c2e31dvboxsync /** The HPET helpers - R3 Ptr. */
016096e367cd20c3d3c3fd9a6650b55935c2e31dvboxsync /** Pointer to the device instance. - R0 ptr. */
016096e367cd20c3d3c3fd9a6650b55935c2e31dvboxsync /** The HPET helpers - R0 Ptr. */
016096e367cd20c3d3c3fd9a6650b55935c2e31dvboxsync /** Pointer to the device instance. - RC ptr. */
016096e367cd20c3d3c3fd9a6650b55935c2e31dvboxsync /** The HPET helpers - RC Ptr. */
8287c906b9b1d215824d4cdf6c1eaf40681ebfa8vboxsync /** Timer structures. */
70fc9d0c972c749656d6fb2ffafcdeec3d8874ecvboxsync HPETTIMER aTimers[RT_MAX(HPET_NUM_TIMERS_PIIX, HPET_NUM_TIMERS_ICH9)];
8287c906b9b1d215824d4cdf6c1eaf40681ebfa8vboxsync /** Offset realtive to the virtual sync clock. */
8287c906b9b1d215824d4cdf6c1eaf40681ebfa8vboxsync /** @name Memory-mapped, software visible registers
8287c906b9b1d215824d4cdf6c1eaf40681ebfa8vboxsync /** Capabilities. */
63787aca0a2a16ec959a5294148726ccf898ddf1vboxsync /** HPET_PERIOD - . */
8287c906b9b1d215824d4cdf6c1eaf40681ebfa8vboxsync /** Configuration. */
8287c906b9b1d215824d4cdf6c1eaf40681ebfa8vboxsync /** Interrupt status register. */
8287c906b9b1d215824d4cdf6c1eaf40681ebfa8vboxsync /** Main counter. */
8287c906b9b1d215824d4cdf6c1eaf40681ebfa8vboxsync /** Global device lock. */
424a17baac7954212256747726f9c9d5a9d03f5avboxsync /** Whether we emulate ICH9 HPET (different frequency & timer count). */
70fc9d0c972c749656d6fb2ffafcdeec3d8874ecvboxsync /** Size alignment padding. */
70fc9d0c972c749656d6fb2ffafcdeec3d8874ecvboxsyncDECLINLINE(bool) hpet32bitTimer(HPETTIMER *pHpetTimer)
7c48fdac0546978ed14617c8096734ce2d18c8e5vboxsync return ((u64Cfg & HPET_TN_SIZE_CAP) == 0) || ((u64Cfg & HPET_TN_32BIT) != 0);
70fc9d0c972c749656d6fb2ffafcdeec3d8874ecvboxsyncDECLINLINE(uint64_t) hpetInvalidValue(HPETTIMER *pHpetTimer)
b2bc8de1367ae24e1b27b53921d0b32ee3df7acdvboxsync return hpet32bitTimer(pHpetTimer) ? UINT32_MAX : UINT64_MAX;
70fc9d0c972c749656d6fb2ffafcdeec3d8874ecvboxsyncDECLINLINE(uint64_t) hpetTicksToNs(HPET *pThis, uint64_t value)
63787aca0a2a16ec959a5294148726ccf898ddf1vboxsync return ASMMultU64ByU32DivByU32(value, pThis->u32Period, FS_PER_NS);
70fc9d0c972c749656d6fb2ffafcdeec3d8874ecvboxsyncDECLINLINE(uint64_t) nsToHpetTicks(HPET const *pThis, uint64_t u64Value)
63787aca0a2a16ec959a5294148726ccf898ddf1vboxsync return ASMMultU64ByU32DivByU32(u64Value, FS_PER_NS, pThis->u32Period);
70fc9d0c972c749656d6fb2ffafcdeec3d8874ecvboxsyncDECLINLINE(uint64_t) hpetGetTicks(HPET const *pThis)
016096e367cd20c3d3c3fd9a6650b55935c2e31dvboxsync * We can use any timer to get current time, they all go
016096e367cd20c3d3c3fd9a6650b55935c2e31dvboxsync * with the same speed.
70fc9d0c972c749656d6fb2ffafcdeec3d8874ecvboxsyncDECLINLINE(uint64_t) hpetUpdateMasked(uint64_t u64NewValue, uint64_t u64OldValue, uint64_t u64Mask)
70fc9d0c972c749656d6fb2ffafcdeec3d8874ecvboxsyncDECLINLINE(bool) hpetBitJustSet(uint64_t u64OldValue, uint64_t u64NewValue, uint64_t u64Mask)
70fc9d0c972c749656d6fb2ffafcdeec3d8874ecvboxsyncDECLINLINE(bool) hpetBitJustCleared(uint64_t u64OldValue, uint64_t u64NewValue, uint64_t u64Mask)
70fc9d0c972c749656d6fb2ffafcdeec3d8874ecvboxsyncDECLINLINE(uint64_t) hpetComputeDiff(HPETTIMER *pHpetTimer, uint64_t u64Now)
b2bc8de1367ae24e1b27b53921d0b32ee3df7acdvboxsync u32Diff = (uint32_t)pHpetTimer->u64Cmp - (uint32_t)u64Now;
016096e367cd20c3d3c3fd9a6650b55935c2e31dvboxsync u32Diff = ((int32_t)u32Diff > 0) ? u32Diff : (uint32_t)0;
016096e367cd20c3d3c3fd9a6650b55935c2e31dvboxsync u64Diff = ((int64_t)u64Diff > 0) ? u64Diff : (uint64_t)0;
70fc9d0c972c749656d6fb2ffafcdeec3d8874ecvboxsyncstatic void hpetAdjustComparator(HPETTIMER *pHpetTimer, uint64_t u64Now)
9fe808d44daf9a34cd07713c0c254719e5e8d4f7vboxsync if ((pHpetTimer->u64Config & HPET_TN_PERIODIC) && u64Period)
9fe808d44daf9a34cd07713c0c254719e5e8d4f7vboxsync uint64_t cPeriods = (u64Now - pHpetTimer->u64Cmp) / u64Period;
9674ed871d32468dd791ad601151f46d2e843350vboxsync * Sets the frequency hint if it's a periodic timer.
9674ed871d32468dd791ad601151f46d2e843350vboxsync * @param pThis The HPET state.
9674ed871d32468dd791ad601151f46d2e843350vboxsync * @param pHpetTimer The timer.
70fc9d0c972c749656d6fb2ffafcdeec3d8874ecvboxsyncDECLINLINE(void) hpetTimerSetFrequencyHint(HPET *pThis, HPETTIMER *pHpetTimer)
9674ed871d32468dd791ad601151f46d2e843350vboxsync TMTimerSetFrequencyHint(pHpetTimer->CTX_SUFF(pTimer), u32Freq / (uint32_t)u64Period);
016096e367cd20c3d3c3fd9a6650b55935c2e31dvboxsync /* no wrapping on new timers */
e562a8bb17c0dfa1c316708e085a3a92fcc80521vboxsync uint64_t u64Ticks = hpetGetTicks(pHpetTimer->CTX_SUFF(pHpet));
e562a8bb17c0dfa1c316708e085a3a92fcc80521vboxsync uint64_t u64Diff = hpetComputeDiff(pHpetTimer, u64Ticks);
7c48fdac0546978ed14617c8096734ce2d18c8e5vboxsync * HPET spec says in one-shot 32-bit mode, generate an interrupt when
016096e367cd20c3d3c3fd9a6650b55935c2e31dvboxsync * counter wraps in addition to an interrupt with comparator match.
e562a8bb17c0dfa1c316708e085a3a92fcc80521vboxsync uint32_t u32TillWrap = 0xffffffff - (uint32_t)u64Ticks + 1;
3956d0151065a11e49d2213b38a5efdad46807e0vboxsync Log(("wrap on timer %d: till=%u ticks=%lld diff64=%lld\n",
b2bc8de1367ae24e1b27b53921d0b32ee3df7acdvboxsync pHpetTimer->idxTimer, u32TillWrap, u64Ticks, u64Diff));
e562a8bb17c0dfa1c316708e085a3a92fcc80521vboxsync * HACK ALERT! Avoid killing VM with interrupts.
e562a8bb17c0dfa1c316708e085a3a92fcc80521vboxsync#if 1 /** @todo: HACK, rethink, may have negative impact on the guest */
b2bc8de1367ae24e1b27b53921d0b32ee3df7acdvboxsync Log4(("HPET: next IRQ in %lld ticks (%lld ns)\n", u64Diff, hpetTicksToNs(pHpetTimer->CTX_SUFF(pHpet), u64Diff)));
b2bc8de1367ae24e1b27b53921d0b32ee3df7acdvboxsync TMTimerSetNano(pHpetTimer->CTX_SUFF(pTimer), hpetTicksToNs(pHpetTimer->CTX_SUFF(pHpet), u64Diff));
9674ed871d32468dd791ad601151f46d2e843350vboxsync hpetTimerSetFrequencyHint(pHpetTimer->CTX_SUFF(pHpet), pHpetTimer);
3b1aa24d99d0f9cc157cf72ca76444b2feca3277vboxsync/* -=-=-=-=-=- Timer register accesses -=-=-=-=-=- */
3ebd5757516d21eccdad25ddd456d2913c2fb215vboxsync * Reads a HPET timer register.
3ebd5757516d21eccdad25ddd456d2913c2fb215vboxsync * @returns VBox strict status code.
3ebd5757516d21eccdad25ddd456d2913c2fb215vboxsync * @param pThis The HPET instance.
3ebd5757516d21eccdad25ddd456d2913c2fb215vboxsync * @param iTimerNo The timer index.
3ebd5757516d21eccdad25ddd456d2913c2fb215vboxsync * @param iTimerReg The index of the timer register to read.
3ebd5757516d21eccdad25ddd456d2913c2fb215vboxsync * @param pu32Value Where to return the register value.
424a17baac7954212256747726f9c9d5a9d03f5avboxsync * @remarks ASSUMES the caller holds the HPET lock.
70fc9d0c972c749656d6fb2ffafcdeec3d8874ecvboxsyncstatic int hpetTimerRegRead32(HPET const *pThis, uint32_t iTimerNo, uint32_t iTimerReg, uint32_t *pu32Value)
90a3b100d6364b9956ab5155b48b91e2d930f4a4vboxsync if ( iTimerNo >= HPET_CAP_GET_TIMERS(pThis->u32Capabilities) /* The second check is only to satisfy Parfait; */
90a3b100d6364b9956ab5155b48b91e2d930f4a4vboxsync || iTimerNo >= RT_ELEMENTS(pThis->aTimers) ) /* in practice, the number of configured timers */
90a3b100d6364b9956ab5155b48b91e2d930f4a4vboxsync { /* will always be <= aTimers elements. */
f52a6d21b2651bcb372e468cae910590f6daa3dcvboxsync LogRelMax(10, ("HPET: using timer above configured range: %d\n", iTimerNo));
70fc9d0c972c749656d6fb2ffafcdeec3d8874ecvboxsync HPETTIMER const *pHpetTimer = &pThis->aTimers[iTimerNo];
3ebd5757516d21eccdad25ddd456d2913c2fb215vboxsync Log(("read HPET_TN_CFG on %d: %#x\n", iTimerNo, u32Value));
3ebd5757516d21eccdad25ddd456d2913c2fb215vboxsync u32Value = (uint32_t)(pHpetTimer->u64Config >> 32);
3ebd5757516d21eccdad25ddd456d2913c2fb215vboxsync Log(("read HPET_TN_CFG+4 on %d: %#x\n", iTimerNo, u32Value));
3ebd5757516d21eccdad25ddd456d2913c2fb215vboxsync Log(("read HPET_TN_CMP on %d: %#x (%#llx)\n", pHpetTimer->idxTimer, u32Value, pHpetTimer->u64Cmp));
3ebd5757516d21eccdad25ddd456d2913c2fb215vboxsync Log(("read HPET_TN_CMP+4 on %d: %#x (%#llx)\n", pHpetTimer->idxTimer, u32Value, pHpetTimer->u64Cmp));
3ebd5757516d21eccdad25ddd456d2913c2fb215vboxsync u32Value = (uint32_t)(pHpetTimer->u64Fsb >> 32); /** @todo Looks wrong, but since it's not supported, who cares. */
3ebd5757516d21eccdad25ddd456d2913c2fb215vboxsync Log(("read HPET_TN_ROUTE on %d: %#x\n", iTimerNo, u32Value));
f52a6d21b2651bcb372e468cae910590f6daa3dcvboxsync LogRelMax(10, ("invalid HPET register read %d on %d\n", iTimerReg, pHpetTimer->idxTimer));
3ebd5757516d21eccdad25ddd456d2913c2fb215vboxsync * 32-bit write to a HPET timer register.
3ebd5757516d21eccdad25ddd456d2913c2fb215vboxsync * @returns Strict VBox status code.
3ebd5757516d21eccdad25ddd456d2913c2fb215vboxsync * @param pThis The HPET state.
3ebd5757516d21eccdad25ddd456d2913c2fb215vboxsync * @param idxReg The register being written to.
3ebd5757516d21eccdad25ddd456d2913c2fb215vboxsync * @param u32NewValue The value being written.
e562a8bb17c0dfa1c316708e085a3a92fcc80521vboxsync * @remarks The caller should not hold the device lock, unless it also holds
e562a8bb17c0dfa1c316708e085a3a92fcc80521vboxsync * the TM lock.
70fc9d0c972c749656d6fb2ffafcdeec3d8874ecvboxsyncstatic int hpetTimerRegWrite32(HPET *pThis, uint32_t iTimerNo, uint32_t iTimerReg, uint32_t u32NewValue)
70fc9d0c972c749656d6fb2ffafcdeec3d8874ecvboxsync Assert(!PDMCritSectIsOwner(&pThis->CritSect) || TMTimerIsLockOwner(pThis->aTimers[0].CTX_SUFF(pTimer)));
90a3b100d6364b9956ab5155b48b91e2d930f4a4vboxsync if ( iTimerNo >= HPET_CAP_GET_TIMERS(pThis->u32Capabilities)
90a3b100d6364b9956ab5155b48b91e2d930f4a4vboxsync || iTimerNo >= RT_ELEMENTS(pThis->aTimers) ) /* Parfait - see above. */
f52a6d21b2651bcb372e468cae910590f6daa3dcvboxsync LogRelMax(10, ("HPET: using timer above configured range: %d\n", iTimerNo));
648b0a0e189323afe4d836f1848f82c7dded0e58vboxsync DEVHPET_LOCK_RETURN(pThis, VINF_IOM_R3_MMIO_WRITE);
e95a7aab825fd803ca1f09d072d74fe1bedfbadbvboxsync Log(("write HPET_TN_CFG: %d: %x\n", iTimerNo, u32NewValue));
7c48fdac0546978ed14617c8096734ce2d18c8e5vboxsync Log(("setting timer %d to 32-bit mode\n", iTimerNo));
b2bc8de1367ae24e1b27b53921d0b32ee3df7acdvboxsync pHpetTimer->u64Period = (uint32_t)pHpetTimer->u64Period;
3ebd5757516d21eccdad25ddd456d2913c2fb215vboxsync if ((u32NewValue & HPET_TN_INT_TYPE) == HPET_TIMER_TYPE_LEVEL)
f52a6d21b2651bcb372e468cae910590f6daa3dcvboxsync LogRelMax(10, ("level-triggered config not yet supported\n"));
b2bc8de1367ae24e1b27b53921d0b32ee3df7acdvboxsync /* We only care about lower 32-bits so far */
e95a7aab825fd803ca1f09d072d74fe1bedfbadbvboxsync pHpetTimer->u64Config = hpetUpdateMasked(u32NewValue, pHpetTimer->u64Config, u64Mask);
e95a7aab825fd803ca1f09d072d74fe1bedfbadbvboxsync case HPET_TN_CFG + 4: /* Interrupt capabilities - read only. */
016096e367cd20c3d3c3fd9a6650b55935c2e31dvboxsync case HPET_TN_CMP: /* lower bits of comparator register */
648b0a0e189323afe4d836f1848f82c7dded0e58vboxsync DEVHPET_LOCK_BOTH_RETURN(pThis, VINF_IOM_R3_MMIO_WRITE);
e562a8bb17c0dfa1c316708e085a3a92fcc80521vboxsync Log(("write HPET_TN_CMP on %d: %#x\n", iTimerNo, u32NewValue));
973e7aa10bdb6c998d3b26b9f6f9d184d42fb4cevboxsync pHpetTimer->u64Period = RT_MAKE_U64(u32NewValue, RT_HI_U32(pHpetTimer->u64Period));
973e7aa10bdb6c998d3b26b9f6f9d184d42fb4cevboxsync pHpetTimer->u64Cmp = RT_MAKE_U64(u32NewValue, RT_HI_U32(pHpetTimer->u64Cmp));
e562a8bb17c0dfa1c316708e085a3a92fcc80521vboxsync Log2(("after HPET_TN_CMP cmp=%#llx per=%#llx\n", pHpetTimer->u64Cmp, pHpetTimer->u64Period));
36fbf6dcd3e6b2e5891456b730577ff0eb355c9fvboxsync case HPET_TN_CMP + 4: /* upper bits of comparator register */
648b0a0e189323afe4d836f1848f82c7dded0e58vboxsync DEVHPET_LOCK_BOTH_RETURN(pThis, VINF_IOM_R3_MMIO_WRITE);
e562a8bb17c0dfa1c316708e085a3a92fcc80521vboxsync Log(("write HPET_TN_CMP + 4 on %d: %#x\n", iTimerNo, u32NewValue));
973e7aa10bdb6c998d3b26b9f6f9d184d42fb4cevboxsync pHpetTimer->u64Period = RT_MAKE_U64(RT_LO_U32(pHpetTimer->u64Period), u32NewValue);
973e7aa10bdb6c998d3b26b9f6f9d184d42fb4cevboxsync pHpetTimer->u64Cmp = RT_MAKE_U64(RT_LO_U32(pHpetTimer->u64Cmp), u32NewValue);
e562a8bb17c0dfa1c316708e085a3a92fcc80521vboxsync Log2(("after HPET_TN_CMP+4 cmp=%llx per=%llx tmr=%d\n", pHpetTimer->u64Cmp, pHpetTimer->u64Period, iTimerNo));
f52a6d21b2651bcb372e468cae910590f6daa3dcvboxsync LogRelMax(10, ("invalid timer register write: %d\n", iTimerReg));
3b1aa24d99d0f9cc157cf72ca76444b2feca3277vboxsync/* -=-=-=-=-=- Non-timer register accesses -=-=-=-=-=- */
8a54ed337392872c7cfcfb96f173468bbbb0f7fcvboxsync * Read a 32-bit HPET register.
8a54ed337392872c7cfcfb96f173468bbbb0f7fcvboxsync * @returns Strict VBox status code.
8a54ed337392872c7cfcfb96f173468bbbb0f7fcvboxsync * @param pThis The HPET state.
8a54ed337392872c7cfcfb96f173468bbbb0f7fcvboxsync * @param idxReg The register to read.
8a54ed337392872c7cfcfb96f173468bbbb0f7fcvboxsync * @param pu32Value Where to return the register value.
e562a8bb17c0dfa1c316708e085a3a92fcc80521vboxsync * @remarks The caller must not own the device lock if HPET_COUNTER is read.
70fc9d0c972c749656d6fb2ffafcdeec3d8874ecvboxsyncstatic int hpetConfigRegRead32(HPET *pThis, uint32_t idxReg, uint32_t *pu32Value)
70fc9d0c972c749656d6fb2ffafcdeec3d8874ecvboxsync Assert(!PDMCritSectIsOwner(&pThis->CritSect) || (idxReg != HPET_COUNTER && idxReg != HPET_COUNTER + 4));
648b0a0e189323afe4d836f1848f82c7dded0e58vboxsync DEVHPET_LOCK_BOTH_RETURN(pThis, VINF_IOM_R3_MMIO_READ);
8a54ed337392872c7cfcfb96f173468bbbb0f7fcvboxsync /** @todo is it correct? */
8a54ed337392872c7cfcfb96f173468bbbb0f7fcvboxsync u32Value = (idxReg == HPET_COUNTER) ? (uint32_t)u64Ticks : (uint32_t)(u64Ticks >> 32);
8a54ed337392872c7cfcfb96f173468bbbb0f7fcvboxsync Log(("read HPET_COUNTER: %s part value %x (%#llx)\n",
8a54ed337392872c7cfcfb96f173468bbbb0f7fcvboxsync (idxReg == HPET_COUNTER) ? "low" : "high", u32Value, u64Ticks));
3ebd5757516d21eccdad25ddd456d2913c2fb215vboxsync * 32-bit write to a config register.
3ebd5757516d21eccdad25ddd456d2913c2fb215vboxsync * @returns Strict VBox status code.
3ebd5757516d21eccdad25ddd456d2913c2fb215vboxsync * @param pThis The HPET state.
3ebd5757516d21eccdad25ddd456d2913c2fb215vboxsync * @param idxReg The register being written to.
3ebd5757516d21eccdad25ddd456d2913c2fb215vboxsync * @param u32NewValue The value being written.
e562a8bb17c0dfa1c316708e085a3a92fcc80521vboxsync * @remarks The caller should not hold the device lock, unless it also holds
e562a8bb17c0dfa1c316708e085a3a92fcc80521vboxsync * the TM lock.
70fc9d0c972c749656d6fb2ffafcdeec3d8874ecvboxsyncstatic int hpetConfigRegWrite32(HPET *pThis, uint32_t idxReg, uint32_t u32NewValue)
70fc9d0c972c749656d6fb2ffafcdeec3d8874ecvboxsync Assert(!PDMCritSectIsOwner(&pThis->CritSect) || TMTimerIsLockOwner(pThis->aTimers[0].CTX_SUFF(pTimer)));
648b0a0e189323afe4d836f1848f82c7dded0e58vboxsync DEVHPET_LOCK_BOTH_RETURN(pThis, VINF_IOM_R3_MMIO_WRITE);
b2bc8de1367ae24e1b27b53921d0b32ee3df7acdvboxsync uint32_t const iOldValue = (uint32_t)(pThis->u64HpetConfig);
3ebd5757516d21eccdad25ddd456d2913c2fb215vboxsync Log(("write HPET_CFG: %x (old %x)\n", u32NewValue, iOldValue));
3614117c1132a61599e6190939e775cafe549411vboxsync * This check must be here, before actual update, as hpetLegacyMode
3614117c1132a61599e6190939e775cafe549411vboxsync * may request retry in R3 - so we must keep state intact.
3ebd5757516d21eccdad25ddd456d2913c2fb215vboxsync rc = pThis->pHpetHlpR3->pfnSetLegacyMode(pThis->pDevInsR3, RT_BOOL(u32NewValue & HPET_CFG_LEGACY));
3ebd5757516d21eccdad25ddd456d2913c2fb215vboxsync pThis->u64HpetConfig = hpetUpdateMasked(u32NewValue, iOldValue, HPET_CFG_WRITE_MASK);
63787aca0a2a16ec959a5294148726ccf898ddf1vboxsync uint32_t const cTimers = HPET_CAP_GET_TIMERS(pThis->u32Capabilities);
3ebd5757516d21eccdad25ddd456d2913c2fb215vboxsync if (hpetBitJustSet(iOldValue, u32NewValue, HPET_CFG_ENABLE))
3ebd5757516d21eccdad25ddd456d2913c2fb215vboxsync/** @todo Only get the time stamp once when reprogramming? */
016096e367cd20c3d3c3fd9a6650b55935c2e31dvboxsync /* Enable main counter and interrupt generation. */
fe554d9c0e3a6de4ba221610ac95a44c7d288e01vboxsync pThis->u64HpetOffset = hpetTicksToNs(pThis, pThis->u64HpetCounter)
7c48fdac0546978ed14617c8096734ce2d18c8e5vboxsync if (pThis->aTimers[i].u64Cmp != hpetInvalidValue(&pThis->aTimers[i]))
3ebd5757516d21eccdad25ddd456d2913c2fb215vboxsync else if (hpetBitJustCleared(iOldValue, u32NewValue, HPET_CFG_ENABLE))
016096e367cd20c3d3c3fd9a6650b55935c2e31dvboxsync /* Halt main counter and disable interrupt generation. */
648b0a0e189323afe4d836f1848f82c7dded0e58vboxsync DEVHPET_LOCK_RETURN(pThis, VINF_IOM_R3_MMIO_WRITE);
3ebd5757516d21eccdad25ddd456d2913c2fb215vboxsync pThis->u64HpetConfig = hpetUpdateMasked((uint64_t)u32NewValue << 32,
3ebd5757516d21eccdad25ddd456d2913c2fb215vboxsync Log(("write HPET_CFG + 4: %x -> %#llx\n", u32NewValue, pThis->u64HpetConfig));
648b0a0e189323afe4d836f1848f82c7dded0e58vboxsync DEVHPET_LOCK_RETURN(pThis, VINF_IOM_R3_MMIO_WRITE);
3ebd5757516d21eccdad25ddd456d2913c2fb215vboxsync /* Clear ISR for all set bits in u32NewValue, see p. 14 of the HPET spec. */
3ebd5757516d21eccdad25ddd456d2913c2fb215vboxsync Log(("write HPET_STATUS: %x -> ISR=%#llx\n", u32NewValue, pThis->u64Isr));
f52a6d21b2651bcb372e468cae910590f6daa3dcvboxsync LogRelMax(10, ("Writing HPET_STATUS + 4 with non-zero, ignored\n"));
648b0a0e189323afe4d836f1848f82c7dded0e58vboxsync DEVHPET_LOCK_RETURN(pThis, VINF_IOM_R3_MMIO_WRITE);
973e7aa10bdb6c998d3b26b9f6f9d184d42fb4cevboxsync pThis->u64HpetCounter = RT_MAKE_U64(u32NewValue, RT_HI_U32(pThis->u64HpetCounter));
3ebd5757516d21eccdad25ddd456d2913c2fb215vboxsync Log(("write HPET_COUNTER: %#x -> %llx\n", u32NewValue, pThis->u64HpetCounter));
648b0a0e189323afe4d836f1848f82c7dded0e58vboxsync DEVHPET_LOCK_RETURN(pThis, VINF_IOM_R3_MMIO_WRITE);
973e7aa10bdb6c998d3b26b9f6f9d184d42fb4cevboxsync pThis->u64HpetCounter = RT_MAKE_U64(RT_LO_U32(pThis->u64HpetCounter), u32NewValue);
3ebd5757516d21eccdad25ddd456d2913c2fb215vboxsync Log(("write HPET_COUNTER + 4: %#x -> %llx\n", u32NewValue, pThis->u64HpetCounter));
f52a6d21b2651bcb372e468cae910590f6daa3dcvboxsync LogRelMax(10, ("invalid HPET config write: %x\n", idxReg));
3ebd5757516d21eccdad25ddd456d2913c2fb215vboxsync/* -=-=-=-=-=- MMIO callbacks -=-=-=-=-=- */
3ebd5757516d21eccdad25ddd456d2913c2fb215vboxsync * @callback_method_impl{FNIOMMMIOREAD}
3ebd5757516d21eccdad25ddd456d2913c2fb215vboxsyncPDMBOTHCBDECL(int) hpetMMIORead(PPDMDEVINS pDevIns, void *pvUser, RTGCPHYS GCPhysAddr, void *pv, unsigned cb)
3ebd5757516d21eccdad25ddd456d2913c2fb215vboxsync uint32_t const idxReg = (uint32_t)(GCPhysAddr - HPET_BASE);
3ebd5757516d21eccdad25ddd456d2913c2fb215vboxsync LogFlow(("hpetMMIORead (%d): %llx (%x)\n", cb, (uint64_t)GCPhysAddr, idxReg));
70fc9d0c972c749656d6fb2ffafcdeec3d8874ecvboxsync * 4-byte access.
70fc9d0c972c749656d6fb2ffafcdeec3d8874ecvboxsync rc = hpetConfigRegRead32(pThis, idxReg, (uint32_t *)pv);
70fc9d0c972c749656d6fb2ffafcdeec3d8874ecvboxsync * 8-byte access - Split the access except for timing sensitive registers.
70fc9d0c972c749656d6fb2ffafcdeec3d8874ecvboxsync * The others assume the protection of the lock.
70fc9d0c972c749656d6fb2ffafcdeec3d8874ecvboxsync /* When reading HPET counter we must read it in a single read,
70fc9d0c972c749656d6fb2ffafcdeec3d8874ecvboxsync to avoid unexpected time jumps on 32-bit overflow. */
70fc9d0c972c749656d6fb2ffafcdeec3d8874ecvboxsync DEVHPET_LOCK_BOTH_RETURN(pThis, VINF_IOM_R3_MMIO_READ);
70fc9d0c972c749656d6fb2ffafcdeec3d8874ecvboxsync rc = hpetTimerRegRead32(pThis, iTimer, iTimerReg, &pValue->s.Lo);
70fc9d0c972c749656d6fb2ffafcdeec3d8874ecvboxsync rc = hpetTimerRegRead32(pThis, iTimer, iTimerReg + 4, &pValue->s.Hi);
70fc9d0c972c749656d6fb2ffafcdeec3d8874ecvboxsync /* for most 8-byte accesses we just split them, happens under lock anyway. */
70fc9d0c972c749656d6fb2ffafcdeec3d8874ecvboxsync rc = hpetConfigRegRead32(pThis, idxReg, &pValue->s.Lo);
70fc9d0c972c749656d6fb2ffafcdeec3d8874ecvboxsync rc = hpetConfigRegRead32(pThis, idxReg + 4, &pValue->s.Hi);
3ebd5757516d21eccdad25ddd456d2913c2fb215vboxsync * @callback_method_impl{FNIOMMMIOWRITE}
6826c1a65f586b47c2abbbabab801950c9a0bb75vboxsyncPDMBOTHCBDECL(int) hpetMMIOWrite(PPDMDEVINS pDevIns, void *pvUser, RTGCPHYS GCPhysAddr, void const *pv, unsigned cb)
3ebd5757516d21eccdad25ddd456d2913c2fb215vboxsync uint32_t idxReg = (uint32_t)(GCPhysAddr - HPET_BASE);
3ebd5757516d21eccdad25ddd456d2913c2fb215vboxsync LogFlow(("hpetMMIOWrite: cb=%u reg=%03x (%RGp) val=%llx\n",
3ebd5757516d21eccdad25ddd456d2913c2fb215vboxsync cb, idxReg, GCPhysAddr, cb == 4 ? *(uint32_t *)pv : cb == 8 ? *(uint64_t *)pv : 0xdeadbeef));
70fc9d0c972c749656d6fb2ffafcdeec3d8874ecvboxsync rc = hpetConfigRegWrite32(pThis, idxReg, *(uint32_t const *)pv);
70fc9d0c972c749656d6fb2ffafcdeec3d8874ecvboxsync * 8-byte access.
70fc9d0c972c749656d6fb2ffafcdeec3d8874ecvboxsync /* Split the access and rely on the locking to prevent trouble. */
70fc9d0c972c749656d6fb2ffafcdeec3d8874ecvboxsync DEVHPET_LOCK_BOTH_RETURN(pThis, VINF_IOM_R3_MMIO_WRITE);
70fc9d0c972c749656d6fb2ffafcdeec3d8874ecvboxsync /** @todo Consider handling iTimerReg == HPET_TN_CMP specially here */
70fc9d0c972c749656d6fb2ffafcdeec3d8874ecvboxsync rc = hpetTimerRegWrite32(pThis, iTimer, iTimerReg, uValue.s.Lo);
70fc9d0c972c749656d6fb2ffafcdeec3d8874ecvboxsync rc = hpetTimerRegWrite32(pThis, iTimer, iTimerReg + 4, uValue.s.Hi);
70fc9d0c972c749656d6fb2ffafcdeec3d8874ecvboxsync rc = hpetConfigRegWrite32(pThis, idxReg, uValue.s.Lo);
70fc9d0c972c749656d6fb2ffafcdeec3d8874ecvboxsync rc = hpetConfigRegWrite32(pThis, idxReg + 4, uValue.s.Hi);
3ebd5757516d21eccdad25ddd456d2913c2fb215vboxsync/* -=-=-=-=-=- Timer Callback Processing -=-=-=-=-=- */
3ebd5757516d21eccdad25ddd456d2913c2fb215vboxsync * Gets the IRQ of an HPET timer.
3ebd5757516d21eccdad25ddd456d2913c2fb215vboxsync * @returns IRQ number.
3ebd5757516d21eccdad25ddd456d2913c2fb215vboxsync * @param pHpetTimer The HPET timer.
70fc9d0c972c749656d6fb2ffafcdeec3d8874ecvboxsyncstatic uint32_t hpetR3TimerGetIrq(struct HPETTIMER const *pHpetTimer)
424a17baac7954212256747726f9c9d5a9d03f5avboxsync * Per spec, in legacy mode the HPET timers are wired as follows:
3ebd5757516d21eccdad25ddd456d2913c2fb215vboxsync * timer 0: IRQ0 for PIC and IRQ2 for APIC
3ebd5757516d21eccdad25ddd456d2913c2fb215vboxsync * timer 1: IRQ8 for both PIC and APIC
3ebd5757516d21eccdad25ddd456d2913c2fb215vboxsync * ISA IRQ delivery logic will take care of correct delivery
3ebd5757516d21eccdad25ddd456d2913c2fb215vboxsync * to the different ICs.
3ebd5757516d21eccdad25ddd456d2913c2fb215vboxsync && (pHpetTimer->CTX_SUFF(pHpet)->u64HpetConfig & HPET_CFG_LEGACY))
3ebd5757516d21eccdad25ddd456d2913c2fb215vboxsync return (pHpetTimer->u64Config & HPET_TN_INT_ROUTE_MASK) >> HPET_TN_INT_ROUTE_SHIFT;
70fc9d0c972c749656d6fb2ffafcdeec3d8874ecvboxsync * Used by hpetR3Timer to update the IRQ status.
3ebd5757516d21eccdad25ddd456d2913c2fb215vboxsync * @param pThis The HPET device state.
3ebd5757516d21eccdad25ddd456d2913c2fb215vboxsync * @param pHpetTimer The HPET timer.
70fc9d0c972c749656d6fb2ffafcdeec3d8874ecvboxsyncstatic void hpetR3TimerUpdateIrq(HPET *pThis, struct HPETTIMER *pHpetTimer)
23603ed361f22874964e3a841add2c58ec2bb1eavboxsync /** @todo: is it correct? */
3ebd5757516d21eccdad25ddd456d2913c2fb215vboxsync /* ISR bits are only set in level-triggered mode. */
b2bc8de1367ae24e1b27b53921d0b32ee3df7acdvboxsync if ((pHpetTimer->u64Config & HPET_TN_INT_TYPE) == HPET_TIMER_TYPE_LEVEL)
b2bc8de1367ae24e1b27b53921d0b32ee3df7acdvboxsync pThis->u64Isr |= (uint64_t)(1 << pHpetTimer->idxTimer);
3ebd5757516d21eccdad25ddd456d2913c2fb215vboxsync /* We trigger flip/flop in edge-triggered mode and do nothing in
3ebd5757516d21eccdad25ddd456d2913c2fb215vboxsync level-triggered mode yet. */
b2bc8de1367ae24e1b27b53921d0b32ee3df7acdvboxsync if ((pHpetTimer->u64Config & HPET_TN_INT_TYPE) == HPET_TIMER_TYPE_EDGE)
23603ed361f22874964e3a841add2c58ec2bb1eavboxsync pThis->pHpetHlpR3->pfnSetIrq(pThis->CTX_SUFF(pDevIns), irq, PDM_IRQ_LEVEL_FLIP_FLOP);
3ebd5757516d21eccdad25ddd456d2913c2fb215vboxsync /** @todo: implement IRQs in level-triggered mode */
016096e367cd20c3d3c3fd9a6650b55935c2e31dvboxsync * Device timer callback function.
016096e367cd20c3d3c3fd9a6650b55935c2e31dvboxsync * @param pDevIns Device instance of the device which registered the timer.
016096e367cd20c3d3c3fd9a6650b55935c2e31dvboxsync * @param pTimer The timer handle.
016096e367cd20c3d3c3fd9a6650b55935c2e31dvboxsync * @param pvUser Pointer to the HPET timer state.
70fc9d0c972c749656d6fb2ffafcdeec3d8874ecvboxsyncstatic DECLCALLBACK(void) hpetR3Timer(PPDMDEVINS pDevIns, PTMTIMER pTimer, void *pvUser)
90a3b100d6364b9956ab5155b48b91e2d930f4a4vboxsync Log4(("HPET: periodic: next in %llu\n", hpetTicksToNs(pThis, u64Diff)));
90a3b100d6364b9956ab5155b48b91e2d930f4a4vboxsync TMTimerSetNano(pTimer, hpetTicksToNs(pThis, u64Diff));
90a3b100d6364b9956ab5155b48b91e2d930f4a4vboxsync /* For 32-bit non-periodic timers, generate wrap-around interrupts. */
b2bc8de1367ae24e1b27b53921d0b32ee3df7acdvboxsync TMTimerSetNano(pTimer, hpetTicksToNs(pThis, u64Diff));
016096e367cd20c3d3c3fd9a6650b55935c2e31dvboxsync /* Should it really be under lock, does it really matter? */
3ebd5757516d21eccdad25ddd456d2913c2fb215vboxsync/* -=-=-=-=-=- DBGF Info Handlers -=-=-=-=-=- */
3ebd5757516d21eccdad25ddd456d2913c2fb215vboxsync * @callback_method_impl{FNDBGFHANDLERDEV}
70fc9d0c972c749656d6fb2ffafcdeec3d8874ecvboxsyncstatic DECLCALLBACK(void) hpetR3Info(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
3ebd5757516d21eccdad25ddd456d2913c2fb215vboxsync "HPET status:\n"
d5a801e98910a0c3c9c65cfc7cf8826f0b0b4450vboxsync " config=%016RX64 isr=%016RX64\n"
d5a801e98910a0c3c9c65cfc7cf8826f0b0b4450vboxsync " offset=%016RX64 counter=%016RX64 frequency=%08x\n"
d5a801e98910a0c3c9c65cfc7cf8826f0b0b4450vboxsync " legacy-mode=%s timer-count=%u\n",
63787aca0a2a16ec959a5294148726ccf898ddf1vboxsync pThis->u64HpetOffset, pThis->u64HpetCounter, pThis->u32Period,
d5a801e98910a0c3c9c65cfc7cf8826f0b0b4450vboxsync !!(pThis->u64HpetConfig & HPET_CFG_LEGACY) ? "on " : "off",
3ebd5757516d21eccdad25ddd456d2913c2fb215vboxsync "Timers:\n");
63e3a547845f7c31bb4e892a66684b560dc63611vboxsync for (unsigned i = 0; i < RT_ELEMENTS(pThis->aTimers); i++)
3ebd5757516d21eccdad25ddd456d2913c2fb215vboxsync pHlp->pfnPrintf(pHlp, " %d: comparator=%016RX64 period(hidden)=%016RX64 cfg=%016RX64\n",
3ebd5757516d21eccdad25ddd456d2913c2fb215vboxsync/* -=-=-=-=-=- Saved State -=-=-=-=-=- */
3ebd5757516d21eccdad25ddd456d2913c2fb215vboxsync * @callback_method_impl{FNSSMDEVLIVEEXEC}
70fc9d0c972c749656d6fb2ffafcdeec3d8874ecvboxsyncstatic DECLCALLBACK(int) hpetR3LiveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uPass)
63787aca0a2a16ec959a5294148726ccf898ddf1vboxsync SSMR3PutU8(pSSM, HPET_CAP_GET_TIMERS(pThis->u32Capabilities));
3ebd5757516d21eccdad25ddd456d2913c2fb215vboxsync * @callback_method_impl{FNSSMDEVSAVEEXEC}
70fc9d0c972c749656d6fb2ffafcdeec3d8874ecvboxsyncstatic DECLCALLBACK(int) hpetR3SaveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
3ebd5757516d21eccdad25ddd456d2913c2fb215vboxsync * The config.
3ebd5757516d21eccdad25ddd456d2913c2fb215vboxsync * The state.
63787aca0a2a16ec959a5294148726ccf898ddf1vboxsync uint32_t const cTimers = HPET_CAP_GET_TIMERS(pThis->u32Capabilities);
63e3a547845f7c31bb4e892a66684b560dc63611vboxsync for (uint32_t iTimer = 0; iTimer < cTimers; iTimer++)
63787aca0a2a16ec959a5294148726ccf898ddf1vboxsync uint64_t u64CapPer = RT_MAKE_U64(pThis->u32Capabilities, pThis->u32Period);
3ebd5757516d21eccdad25ddd456d2913c2fb215vboxsync * @callback_method_impl{FNSSMDEVLOADEXEC}
70fc9d0c972c749656d6fb2ffafcdeec3d8874ecvboxsyncstatic DECLCALLBACK(int) hpetR3LoadExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
3ebd5757516d21eccdad25ddd456d2913c2fb215vboxsync * Version checks.
3ebd5757516d21eccdad25ddd456d2913c2fb215vboxsync * The config.
63e3a547845f7c31bb4e892a66684b560dc63611vboxsync return SSMR3SetCfgError(pSSM, RT_SRC_POS, N_("Config mismatch - too many timers: saved=%#x config=%#x"),
3ebd5757516d21eccdad25ddd456d2913c2fb215vboxsync * The state.
63e3a547845f7c31bb4e892a66684b560dc63611vboxsync for (uint32_t iTimer = 0; iTimer < cTimers; iTimer++)
63787aca0a2a16ec959a5294148726ccf898ddf1vboxsync if (HPET_CAP_GET_TIMERS(RT_LO_U32(u64CapPer)) != cTimers)
63e3a547845f7c31bb4e892a66684b560dc63611vboxsync return SSMR3SetCfgError(pSSM, RT_SRC_POS, N_("Capabilities does not match timer count: cTimers=%#x caps=%#x"),
63787aca0a2a16ec959a5294148726ccf898ddf1vboxsync cTimers, (unsigned)HPET_CAP_GET_TIMERS(u64CapPer));
d5a801e98910a0c3c9c65cfc7cf8826f0b0b4450vboxsync * Set the timer frequency hints.
63e3a547845f7c31bb4e892a66684b560dc63611vboxsync for (uint32_t iTimer = 0; iTimer < cTimers; iTimer++)
3ebd5757516d21eccdad25ddd456d2913c2fb215vboxsync/* -=-=-=-=-=- PDMDEVREG -=-=-=-=-=- */
3ebd5757516d21eccdad25ddd456d2913c2fb215vboxsync * @interface_method_impl{PDMDEVREG,pfnRelocate}
70fc9d0c972c749656d6fb2ffafcdeec3d8874ecvboxsyncstatic DECLCALLBACK(void) hpetR3Relocate(PPDMDEVINS pDevIns, RTGCINTPTR offDelta)
016096e367cd20c3d3c3fd9a6650b55935c2e31dvboxsync pThis->pHpetHlpRC = pThis->pHpetHlpR3->pfnGetRCHelpers(pDevIns);
8287c906b9b1d215824d4cdf6c1eaf40681ebfa8vboxsync for (unsigned i = 0; i < RT_ELEMENTS(pThis->aTimers); i++)
3ebd5757516d21eccdad25ddd456d2913c2fb215vboxsync * @interface_method_impl{PDMDEVREG,pfnReset}
70fc9d0c972c749656d6fb2ffafcdeec3d8874ecvboxsyncstatic DECLCALLBACK(void) hpetR3Reset(PPDMDEVINS pDevIns)
04cdb3815f28f5dbf0e7dffc7957fec59260e76fvboxsync * The timers first.
04cdb3815f28f5dbf0e7dffc7957fec59260e76fvboxsync TMTimerLock(pThis->aTimers[0].pTimerR3, VERR_IGNORED);
63e3a547845f7c31bb4e892a66684b560dc63611vboxsync for (unsigned i = 0; i < RT_ELEMENTS(pThis->aTimers); i++)
016096e367cd20c3d3c3fd9a6650b55935c2e31dvboxsync /* capable of periodic operations and 64-bits */
b2bc8de1367ae24e1b27b53921d0b32ee3df7acdvboxsync pHpetTimer->u64Config = HPET_TN_PERIODIC_CAP | HPET_TN_SIZE_CAP;
016096e367cd20c3d3c3fd9a6650b55935c2e31dvboxsync /* We can do all IRQs */
b2bc8de1367ae24e1b27b53921d0b32ee3df7acdvboxsync pHpetTimer->u64Config |= ((uint64_t)u32RoutingCap) << 32;
04cdb3815f28f5dbf0e7dffc7957fec59260e76fvboxsync * The HPET state.
fe554d9c0e3a6de4ba221610ac95a44c7d288e01vboxsync /* 64-bit main counter; 3 timers supported; LegacyReplacementRoute. */
63787aca0a2a16ec959a5294148726ccf898ddf1vboxsync pThis->u32Capabilities = (1 << 15) /* LEG_RT_CAP - LegacyReplacementRoute capable. */
63787aca0a2a16ec959a5294148726ccf898ddf1vboxsync | (1 << 13) /* COUNTER_SIZE_CAP - Main counter is 64-bit capable. */
8742e4a4ddb7b62d21d96d56dd1baf01c9f22cecvboxsync if (pThis->fIch9) /* NUM_TIM_CAP - Number of timers -1. */
63787aca0a2a16ec959a5294148726ccf898ddf1vboxsync pThis->u32Capabilities |= (HPET_NUM_TIMERS_ICH9 - 1) << 8;
63787aca0a2a16ec959a5294148726ccf898ddf1vboxsync pThis->u32Capabilities |= (HPET_NUM_TIMERS_PIIX - 1) << 8;
63787aca0a2a16ec959a5294148726ccf898ddf1vboxsync pThis->u32Capabilities |= UINT32_C(0x80860000); /* VENDOR */
8742e4a4ddb7b62d21d96d56dd1baf01c9f22cecvboxsync AssertCompile(HPET_NUM_TIMERS_ICH9 <= RT_ELEMENTS(pThis->aTimers));
8742e4a4ddb7b62d21d96d56dd1baf01c9f22cecvboxsync AssertCompile(HPET_NUM_TIMERS_PIIX <= RT_ELEMENTS(pThis->aTimers));
63787aca0a2a16ec959a5294148726ccf898ddf1vboxsync pThis->u32Period = pThis->fIch9 ? HPET_CLK_PERIOD_ICH9 : HPET_CLK_PERIOD_PIIX;
04cdb3815f28f5dbf0e7dffc7957fec59260e76fvboxsync * Notify the PIT/RTC devices.
3ebd5757516d21eccdad25ddd456d2913c2fb215vboxsync pThis->pHpetHlpR3->pfnSetLegacyMode(pDevIns, false /*fActive*/);
016096e367cd20c3d3c3fd9a6650b55935c2e31dvboxsync * @interface_method_impl{PDMDEVREG,pfnConstruct}
70fc9d0c972c749656d6fb2ffafcdeec3d8874ecvboxsyncstatic DECLCALLBACK(int) hpetR3Construct(PPDMDEVINS pDevIns, int iInstance, PCFGMNODE pCfg)
fe554d9c0e3a6de4ba221610ac95a44c7d288e01vboxsync /* Only one HPET device now, as we use fixed MMIO region. */
70fc9d0c972c749656d6fb2ffafcdeec3d8874ecvboxsync * Initialize the device state.
70fc9d0c972c749656d6fb2ffafcdeec3d8874ecvboxsync /* Init the HPET timers (init all regardless of how many we expose). */
70fc9d0c972c749656d6fb2ffafcdeec3d8874ecvboxsync for (unsigned i = 0; i < RT_ELEMENTS(pThis->aTimers); i++)
70fc9d0c972c749656d6fb2ffafcdeec3d8874ecvboxsync pHpetTimer->pHpetR0 = PDMINS_2_DATA_R0PTR(pDevIns);
70fc9d0c972c749656d6fb2ffafcdeec3d8874ecvboxsync pHpetTimer->pHpetRC = PDMINS_2_DATA_RCPTR(pDevIns);
3ebd5757516d21eccdad25ddd456d2913c2fb215vboxsync * Validate and read the configuration.
3ebd5757516d21eccdad25ddd456d2913c2fb215vboxsync PDMDEV_VALIDATE_CONFIG_RETURN(pDevIns, "GCEnabled|R0Enabled|ICH9", "");
3ebd5757516d21eccdad25ddd456d2913c2fb215vboxsync int rc = CFGMR3QueryBoolDef(pCfg, "GCEnabled", &fRCEnabled, true);
016096e367cd20c3d3c3fd9a6650b55935c2e31dvboxsync N_("Configuration error: Querying \"GCEnabled\" as a bool failed"));
016096e367cd20c3d3c3fd9a6650b55935c2e31dvboxsync rc = CFGMR3QueryBoolDef(pCfg, "R0Enabled", &fR0Enabled, true);
016096e367cd20c3d3c3fd9a6650b55935c2e31dvboxsync N_("Configuration error: failed to read R0Enabled as boolean"));
3ebd5757516d21eccdad25ddd456d2913c2fb215vboxsync rc = CFGMR3QueryBoolDef(pCfg, "ICH9", &pThis->fIch9, false);
fe554d9c0e3a6de4ba221610ac95a44c7d288e01vboxsync N_("Configuration error: failed to read ICH9 as boolean"));
70fc9d0c972c749656d6fb2ffafcdeec3d8874ecvboxsync * Create critsect and timers.
70fc9d0c972c749656d6fb2ffafcdeec3d8874ecvboxsync * Note! We don't use the default critical section of the device, but our own.
70fc9d0c972c749656d6fb2ffafcdeec3d8874ecvboxsync rc = PDMDevHlpCritSectInit(pDevIns, &pThis->CritSect, RT_SRC_POS, "HPET");
572f495840b063427930dbb6f5a81f3147286effvboxsync rc = PDMDevHlpSetDeviceCritSect(pDevIns, PDMDevHlpCritSectGetNop(pDevIns));
63e3a547845f7c31bb4e892a66684b560dc63611vboxsync /* Init the HPET timers (init all regardless of how many we expose). */
63e3a547845f7c31bb4e892a66684b560dc63611vboxsync for (unsigned i = 0; i < RT_ELEMENTS(pThis->aTimers); i++)
70fc9d0c972c749656d6fb2ffafcdeec3d8874ecvboxsync rc = PDMDevHlpTMTimerCreate(pDevIns, TMCLOCK_VIRTUAL_SYNC, hpetR3Timer, pHpetTimer,
8287c906b9b1d215824d4cdf6c1eaf40681ebfa8vboxsync pThis->aTimers[i].pTimerRC = TMTimerRCPtr(pThis->aTimers[i].pTimerR3);
8287c906b9b1d215824d4cdf6c1eaf40681ebfa8vboxsync pThis->aTimers[i].pTimerR0 = TMTimerR0Ptr(pThis->aTimers[i].pTimerR3);
70fc9d0c972c749656d6fb2ffafcdeec3d8874ecvboxsync rc = TMR3TimerSetCritSect(pThis->aTimers[i].pTimerR3, &pThis->CritSect);
70fc9d0c972c749656d6fb2ffafcdeec3d8874ecvboxsync * This must be done prior to registering the HPET, right?
016096e367cd20c3d3c3fd9a6650b55935c2e31dvboxsync * Register the HPET and get helpers.
016096e367cd20c3d3c3fd9a6650b55935c2e31dvboxsync rc = PDMDevHlpHPETRegister(pDevIns, &HpetReg, &pThis->pHpetHlpR3);
016096e367cd20c3d3c3fd9a6650b55935c2e31dvboxsync * Register the MMIO range, PDM API requests page aligned
016096e367cd20c3d3c3fd9a6650b55935c2e31dvboxsync * addresses and sizes.
e95a7aab825fd803ca1f09d072d74fe1bedfbadbvboxsync rc = PDMDevHlpMMIORegister(pDevIns, HPET_BASE, HPET_BAR_SIZE, pThis,
70fc9d0c972c749656d6fb2ffafcdeec3d8874ecvboxsync IOMMMIO_FLAGS_READ_DWORD_QWORD | IOMMMIO_FLAGS_WRITE_ONLY_DWORD_QWORD,
e95a7aab825fd803ca1f09d072d74fe1bedfbadbvboxsync rc = PDMDevHlpMMIORegisterRC(pDevIns, HPET_BASE, HPET_BAR_SIZE, NIL_RTRCPTR /*pvUser*/, "hpetMMIOWrite", "hpetMMIORead");
016096e367cd20c3d3c3fd9a6650b55935c2e31dvboxsync pThis->pHpetHlpRC = pThis->pHpetHlpR3->pfnGetRCHelpers(pDevIns);
e95a7aab825fd803ca1f09d072d74fe1bedfbadbvboxsync rc = PDMDevHlpMMIORegisterR0(pDevIns, HPET_BASE, HPET_BAR_SIZE, NIL_RTR0PTR /*pvUser*/,
016096e367cd20c3d3c3fd9a6650b55935c2e31dvboxsync pThis->pHpetHlpR0 = pThis->pHpetHlpR3->pfnGetR0Helpers(pDevIns);
8287c906b9b1d215824d4cdf6c1eaf40681ebfa8vboxsync AssertReturn(pThis->pHpetHlpR0 != NIL_RTR0PTR, VERR_INTERNAL_ERROR);
016096e367cd20c3d3c3fd9a6650b55935c2e31dvboxsync /* Register SSM callbacks */
70fc9d0c972c749656d6fb2ffafcdeec3d8874ecvboxsync rc = PDMDevHlpSSMRegister3(pDevIns, HPET_SAVED_STATE_VERSION, sizeof(*pThis), hpetR3LiveExec, hpetR3SaveExec, hpetR3LoadExec);
3ebd5757516d21eccdad25ddd456d2913c2fb215vboxsync /* Register an info callback. */
70fc9d0c972c749656d6fb2ffafcdeec3d8874ecvboxsync PDMDevHlpDBGFInfoRegister(pDevIns, "hpet", "Display HPET status. (no arguments)", hpetR3Info);
016096e367cd20c3d3c3fd9a6650b55935c2e31dvboxsync * The device registration structure.
016096e367cd20c3d3c3fd9a6650b55935c2e31dvboxsync /* u32Version */
016096e367cd20c3d3c3fd9a6650b55935c2e31dvboxsync /* szName */
016096e367cd20c3d3c3fd9a6650b55935c2e31dvboxsync /* szRCMod */
016096e367cd20c3d3c3fd9a6650b55935c2e31dvboxsync "VBoxDDGC.gc",
016096e367cd20c3d3c3fd9a6650b55935c2e31dvboxsync /* szR0Mod */
016096e367cd20c3d3c3fd9a6650b55935c2e31dvboxsync "VBoxDDR0.r0",
016096e367cd20c3d3c3fd9a6650b55935c2e31dvboxsync /* pszDescription */
016096e367cd20c3d3c3fd9a6650b55935c2e31dvboxsync " High Precision Event Timer (HPET) Device",
016096e367cd20c3d3c3fd9a6650b55935c2e31dvboxsync /* fFlags */
70fc9d0c972c749656d6fb2ffafcdeec3d8874ecvboxsync PDM_DEVREG_FLAGS_HOST_BITS_DEFAULT | PDM_DEVREG_FLAGS_GUEST_BITS_32_64 | PDM_DEVREG_FLAGS_PAE36
016096e367cd20c3d3c3fd9a6650b55935c2e31dvboxsync /* fClass */
016096e367cd20c3d3c3fd9a6650b55935c2e31dvboxsync /* cMaxInstances */
016096e367cd20c3d3c3fd9a6650b55935c2e31dvboxsync /* cbInstance */
016096e367cd20c3d3c3fd9a6650b55935c2e31dvboxsync /* pfnConstruct */
016096e367cd20c3d3c3fd9a6650b55935c2e31dvboxsync /* pfnDestruct */
016096e367cd20c3d3c3fd9a6650b55935c2e31dvboxsync /* pfnRelocate */
24ca3d27f14cf8a03b8448f6d0898110e915d46avboxsync /* pfnMemSetup */
016096e367cd20c3d3c3fd9a6650b55935c2e31dvboxsync /* pfnPowerOn */
016096e367cd20c3d3c3fd9a6650b55935c2e31dvboxsync /* pfnReset */
016096e367cd20c3d3c3fd9a6650b55935c2e31dvboxsync /* pfnSuspend */
016096e367cd20c3d3c3fd9a6650b55935c2e31dvboxsync /* pfnResume */
016096e367cd20c3d3c3fd9a6650b55935c2e31dvboxsync /* pfnAttach */
016096e367cd20c3d3c3fd9a6650b55935c2e31dvboxsync /* pfnDetach */
016096e367cd20c3d3c3fd9a6650b55935c2e31dvboxsync /* pfnQueryInterface. */
016096e367cd20c3d3c3fd9a6650b55935c2e31dvboxsync /* pfnInitComplete */
016096e367cd20c3d3c3fd9a6650b55935c2e31dvboxsync /* pfnPowerOff */
016096e367cd20c3d3c3fd9a6650b55935c2e31dvboxsync /* pfnSoftReset */
016096e367cd20c3d3c3fd9a6650b55935c2e31dvboxsync /* u32VersionEnd */
016096e367cd20c3d3c3fd9a6650b55935c2e31dvboxsync#endif /* IN_RING3 */
b2bc8de1367ae24e1b27b53921d0b32ee3df7acdvboxsync#endif /* !VBOX_DEVICE_STRUCT_TESTCASE */