DevAPIC.cpp revision f209e4ec6b14c01f53aba13c9a40e78d21323f06
/* $Id$ */
/** @file
* Advanced Programmable Interrupt Controller (APIC) Device and
* I/O Advanced Programmable Interrupt Controller (IO-APIC) Device.
*/
/*
* Copyright (C) 2006-2010 Oracle Corporation
*
* This file is part of VirtualBox Open Source Edition (OSE), as
* available from http://www.virtualbox.org. This file is free software;
* General Public License (GPL) as published by the Free Software
* Foundation, in version 2 as it comes in the "COPYING" file of the
* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
* --------------------------------------------------------------------
*
* This code is based on:
*
* apic.c revision 1.5 @@OSETODO
*/
/*******************************************************************************
* Header Files *
*******************************************************************************/
#define LOG_GROUP LOG_GROUP_DEV_APIC
#include "Builtins2.h"
#define MSR_IA32_APICBASE 0x1b
#ifdef _MSC_VER
#endif
/** The current saved state version.*/
#define APIC_SAVED_STATE_VERSION 3
/** The saved state version used by VirtualBox v3 and earlier.
* This does not include the config. */
#define APIC_SAVED_STATE_VERSION_VBOX_30 2
/** Some ancient version... */
#define APIC_SAVED_STATE_VERSION_ANCIENT 1
/* version 0x14: Pentium 4, Xeon; LVT count depends on that */
#define APIC_HW_VERSION 0x14
/** @def APIC_LOCK
* Acquires the PDM lock. */
do { \
if (rc2 != VINF_SUCCESS) \
return rc2; \
} while (0)
/** @def APIC_LOCK_VOID
* Acquires the PDM lock and does not expect failure (i.e. ring-3 only!). */
do { \
} while (0)
/** @def APIC_UNLOCK
* Releases the PDM lock. */
#define APIC_UNLOCK(pThis) \
/** @def IOAPIC_LOCK
* Acquires the PDM lock. */
do { \
if (rc2 != VINF_SUCCESS) \
return rc2; \
} while (0)
/** @def IOAPIC_UNLOCK
* Releases the PDM lock. */
do { \
uint32_t i; \
{ \
{ \
code; \
} \
apic++; \
} \
} while (0)
/*
* APIC support
*
* Copyright (c) 2004-2005 Fabrice Bellard
*
* modify it under the terms of the GNU Lesser General Public
* License as published by the Free Software Foundation; either
* version 2 of the License, or (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
* Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public
* License along with this library; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#define DEBUG_APIC
#define DEBUG_IOAPIC
/* APIC Local Vector Table */
#define APIC_LVT_TIMER 0
#define APIC_LVT_THERMAL 1
#define APIC_LVT_PERFORM 2
#define APIC_LVT_LINT0 3
#define APIC_LVT_LINT1 4
#define APIC_LVT_ERROR 5
#define APIC_LVT_NB 6
/* APIC delivery modes */
#define APIC_DM_FIXED 0
#define APIC_DM_LOWPRI 1
#define APIC_DM_SMI 2
#define APIC_DM_NMI 4
#define APIC_DM_INIT 5
#define APIC_DM_SIPI 6
#define APIC_DM_EXTINT 7
/* APIC destination mode */
#define APIC_DESTMODE_FLAT 0xf
#define APIC_DESTMODE_CLUSTER 0x0
#define APIC_TRIGGER_EDGE 0
#define APIC_TRIGGER_LEVEL 1
#define IOAPIC_NUM_PINS 0x18
#define APIC_MAX_PATCH_ATTEMPTS 100
typedef uint32_t PhysApicId;
typedef struct APICState {
/* Task priority register (interrupt level) */
/* Logical APIC id - user programmable */
/* Physical APIC id - not visible to user, constant */
/** @todo: is it logical or physical? Not really used anyway now. */
int count_shift;
/** The time stamp of the initial_count load, i.e. when it was started. */
/** The time stamp of the next timer callback. */
/** The APIC timer - R3 Ptr. */
/** The APIC timer - R0 Ptr. */
/** The APIC timer - RC Ptr. */
/** Whether the timer is armed or not */
bool fTimerArmed;
/** Alignment */
bool afAlignment[3];
/** The initial_count value used for the current frequency hint. */
/** The count_shift value used for the current frequency hint. */
/** Timer description timer. */
# ifdef VBOX_WITH_STATISTICS
# if HC_ARCH_BITS == 32
# endif
# endif
} APICState;
# ifdef VBOX_WITH_STATISTICS
# endif
struct IOAPICState {
/** The device instance - R3 Ptr. */
/** The IOAPIC helpers - R3 Ptr. */
/** The device instance - R0 Ptr. */
/** The IOAPIC helpers - R0 Ptr. */
/** The device instance - RC Ptr. */
/** The IOAPIC helpers - RC Ptr. */
# ifdef VBOX_WITH_STATISTICS
# endif
};
typedef struct IOAPICState IOAPICState;
typedef struct
{
/** The device instance - R3 Ptr. */
/** The APIC helpers - R3 Ptr. */
/** LAPICs states - R3 Ptr */
/** The critical section - R3 Ptr. */
/** The device instance - R0 Ptr. */
/** The APIC helpers - R0 Ptr. */
/** LAPICs states - R0 Ptr */
/** The critical section - R3 Ptr. */
/** The device instance - RC Ptr. */
/** The APIC helpers - RC Ptr. */
/** LAPICs states - RC Ptr */
/** The critical section - R3 Ptr. */
/** APIC specification version in this virtual hardware configuration. */
/** Number of attempts made to optimize TPR accesses. */
/** Number of CPUs on the system (same as LAPIC count). */
/** Whether we've got an IO APIC or not. */
bool fIoApic;
/** Alignment padding. */
bool afPadding[3];
# ifdef VBOX_WITH_STATISTICS
# endif
# ifdef VBOX_WITH_STATISTICS
# endif
#ifndef VBOX_DEVICE_STRUCT_TESTCASE
/*******************************************************************************
* Internal Functions *
*******************************************************************************/
PDMBOTHCBDECL(int) apicMMIORead(PPDMDEVINS pDevIns, void *pvUser, RTGCPHYS GCPhysAddr, void *pv, unsigned cb);
PDMBOTHCBDECL(int) apicMMIOWrite(PPDMDEVINS pDevIns, void *pvUser, RTGCPHYS GCPhysAddr, void *pv, unsigned cb);
PDMBOTHCBDECL(int) apicWriteMSR(PPDMDEVINS pDevIns, VMCPUID iCpu, uint32_t u32Reg, uint64_t u64Value);
PDMBOTHCBDECL(int) apicReadMSR(PPDMDEVINS pDevIns, VMCPUID iCpu, uint32_t u32Reg, uint64_t *pu64Value);
PDMBOTHCBDECL(int) ioapicMMIORead(PPDMDEVINS pDevIns, void *pvUser, RTGCPHYS GCPhysAddr, void *pv, unsigned cb);
PDMBOTHCBDECL(int) ioapicMMIOWrite(PPDMDEVINS pDevIns, void *pvUser, RTGCPHYS GCPhysAddr, void *pv, unsigned cb);
static int apic_get_arb_pri(APICState *s);
static int apic_get_ppr(APICState *s);
{
}
{
/* LAPIC's array is indexed by CPU id */
}
{
/* for now we assume LAPIC physical id == CPU id */
}
DECLINLINE(void) cpuSetInterrupt(APICDeviceInfo* dev, APICState *s, PDMAPICIRQ enmType = PDMAPICIRQ_HARDWARE)
{
getCpuFromLapic(dev, s));
}
DECLINLINE(void) cpuClearInterrupt(APICDeviceInfo* dev, APICState *s, PDMAPICIRQ enmType = PDMAPICIRQ_HARDWARE)
{
LogFlow(("apic: clear interrupt flag\n"));
getCpuFromLapic(dev, s));
}
# ifdef IN_RING3
{
getCpuFromLapic(dev, s),
vector);
}
{
Log2(("apic: send init IPI\n"));
getCpuFromLapic(dev, s));
}
# endif /* IN_RING3 */
{
switch (dev->enmVersion)
{
case PDMAPICVERSION_NONE:
return 0;
case PDMAPICVERSION_APIC:
return MSR_IA32_APICBASE_ENABLE;
case PDMAPICVERSION_X2APIC:
default:
return 0;
}
}
{
{
case 0:
return PDMAPICVERSION_NONE;
case 1:
default:
/* Invalid */
return PDMAPICVERSION_NONE;
case 2:
return PDMAPICVERSION_APIC;
case 3:
return PDMAPICVERSION_X2APIC;
}
}
{
LogFlow(("apic_bus_deliver mask=%x mode=%x vector=%x polarity=%x trigger_mode=%x\n", deliver_bitmask, delivery_mode, vector_num, polarity, trigger_mode));
switch (delivery_mode) {
case APIC_DM_LOWPRI:
{
int d = -1;
if (deliver_bitmask)
d = ffs_bit(deliver_bitmask);
if (d >= 0)
{
}
return VINF_SUCCESS;
}
case APIC_DM_FIXED:
/* XXX: arbitration */
break;
case APIC_DM_SMI:
return VINF_SUCCESS;
case APIC_DM_NMI:
return VINF_SUCCESS;
case APIC_DM_INIT:
/* normal INIT IPI sent to processors */
#ifdef IN_RING3
return VINF_SUCCESS;
#else
/* We shall send init IPI only in R3, R0 calls should be
rescheduled to R3 */
return VINF_IOM_HC_MMIO_READ_WRITE;
#endif /* IN_RING3 */
case APIC_DM_EXTINT:
/* handled in I/O APIC code */
break;
default:
return VINF_SUCCESS;
}
return VINF_SUCCESS;
}
{
/** @todo: do we need to lock here ? */
/* APIC_LOCK_VOID(dev, VERR_INTERNAL_ERROR); */
/** @todo If this change is valid immediately, then we should change the MMIO registration! */
/* We cannot change if this CPU is BSP or not by writing to MSR - it's hardwired */
s->apicbase =
{
switch (newMode)
{
case PDMAPICVERSION_NONE:
{
s->spurious_vec &= ~APIC_SV_ENABLE;
/* Clear any pending APIC interrupt action flag. */
cpuClearInterrupt(dev, s);
/** @todo: why do we do that? */
break;
}
case PDMAPICVERSION_APIC:
/** @todo: map MMIO ranges, if needed */
break;
case PDMAPICVERSION_X2APIC:
/** @todo: unmap MMIO ranges of this APIC, according to the spec */
break;
default:
break;
}
}
/* APIC_UNLOCK(dev); */
}
{
return s->apicbase;
}
{
}
{
return s->tpr;
}
/**
* x2APIC MSR write interface.
*
* @returns VBox status code.
*
* @param pDevIns The device instance.
* @param idCpu The ID of the virtual CPU and thereby APIC index.
* @param u32Reg Register to write (ecx).
* @param u64Value The value to write (eax:edx / rax).
*
*/
PDMBOTHCBDECL(int) apicWriteMSR(PPDMDEVINS pDevIns, VMCPUID idCpu, uint32_t u32Reg, uint64_t u64Value)
{
int rc = VINF_SUCCESS;
return VERR_EM_INTERPRETER;
switch (index)
{
case 0x02:
break;
case 0x03:
break;
case 0x08:
break;
case 0x09: case 0x0a:
break;
case 0x0b: /* EOI */
break;
case 0x0d:
break;
case 0x0e:
break;
case 0x0f:
break;
case 0x10: case 0x11: case 0x12: case 0x13: case 0x14: case 0x15: case 0x16: case 0x17:
case 0x18: case 0x19: case 0x1a: case 0x1b: case 0x1c: case 0x1d: case 0x1e: case 0x1f:
case 0x20: case 0x21: case 0x22: case 0x23: case 0x24: case 0x25: case 0x26: case 0x27:
case 0x28:
break;
case 0x30:
/* Here one of the differences with regular APIC: ICR is single 64-bit register */
break;
case 0x32 + APIC_LVT_TIMER:
AssertCompile(APIC_LVT_TIMER == 0);
break;
case 0x33: case 0x34: case 0x35: case 0x36: case 0x37:
break;
case 0x38:
break;
case 0x39:
break;
case 0x3e:
{
int v;
break;
}
case 0x3f:
{
/* Self IPI, see x2APIC book 2.4.5 */
0 /* Delivery mode - fixed */,
0 /* Polarity - conform to the bus */,
0 /* Trigger mode - edge */);
break;
}
default:
break;
}
return rc;
}
/**
* x2APIC MSR read interface.
*
* @returns VBox status code.
*
* @param pDevIns The device instance.
* @param idCpu The ID of the virtual CPU and thereby APIC index.
* @param u32Reg Register to write (ecx).
* @param pu64Value Where to return the value (eax:edx / rax).
*/
PDMBOTHCBDECL(int) apicReadMSR(PPDMDEVINS pDevIns, VMCPUID idCpu, uint32_t u32Reg, uint64_t *pu64Value)
{
return VERR_EM_INTERPRETER;
switch (index)
{
case 0x02: /* id */
break;
case 0x03: /* version */
val = APIC_HW_VERSION |
(0 << 24) /* Support for EOI broadcast supression */;
break;
case 0x08:
break;
case 0x09:
break;
case 0x0a:
/* ppr */
break;
case 0x0b:
val = 0;
break;
case 0x0d:
break;
case 0x0e:
/* Bottom 28 bits are always 1 */
break;
case 0x0f:
break;
case 0x10: case 0x11: case 0x12: case 0x13: case 0x14: case 0x15: case 0x16: case 0x17:
break;
case 0x18: case 0x19: case 0x1a: case 0x1b: case 0x1c: case 0x1d: case 0x1e: case 0x1f:
break;
case 0x20: case 0x21: case 0x22: case 0x23: case 0x24: case 0x25: case 0x26: case 0x27:
break;
case 0x28:
break;
case 0x30:
/* Here one of the differences with regular APIC: ICR is single 64-bit register */
break;
case 0x32: case 0x33: case 0x34: case 0x35: case 0x36: case 0x37:
break;
case 0x38:
break;
case 0x39:
break;
case 0x3e:
break;
case 0x3f:
/* Self IPI register is write only */
break;
case 0x2f:
/**
* Correctable machine check exception vector, @todo: implement me!
*/
default:
/**
* @todo: according to spec when APIC writes to ESR it msut raise error interrupt,
* i.e. LVT[5]
*/
val = 0;
break;
}
return VINF_SUCCESS;
}
/**
* More or less private interface between IOAPIC, only PDM is responsible
* for connecting the two devices.
*/
{
LogFlow(("apicBusDeliverCallback: pDevIns=%p u8Dest=%#x u8DestMode=%#x u8DeliveryMode=%#x iVector=%#x u8Polarity=%#x u8TriggerMode=%#x\n",
}
/**
* Normally used for 8259A PIC and NMI.
*/
{
/* If LAPIC is disabled, go straight to the CPU. */
if (!(s->spurious_vec & APIC_SV_ENABLE))
{
LogFlow(("apicLocalInterrupt: LAPIC disabled, delivering directly to CPU core.\n"));
if (u8Level)
else
return VINF_SUCCESS;
}
/* If LAPIC is enabled, interrupts are subject to LVT programming. */
/* There are only two local interrupt pins. */
/* NB: We currently only deliver local interrupts to the first CPU. In theory they
* should be delivered to all CPUs and it is the guest's responsibility to ensure
* no more than one CPU has the interrupt unmasked.
*/
/* Drop int if entry is masked. May not be correct for level-triggered interrupts. */
if (!(u32Lvec & APIC_LVT_MASKED))
switch (u8Delivery)
{
case APIC_DM_EXTINT:
if (u8Level)
else
return VINF_SUCCESS;
case APIC_DM_NMI:
/* External NMI should be wired to LINT1, but Linux sometimes programs
* LVT0 to NMI delivery mode as well.
*/
/* Currently delivering NMIs through here causes problems with NMI watchdogs
* on certain Linux kernels, e.g. 64-bit CentOS 5.3. Disable NMIs for now.
*/
return VINF_SUCCESS;
case APIC_DM_SMI:
break;
case APIC_DM_FIXED:
{
/** @todo implement APIC_DM_FIXED! */
static unsigned s_c = 0;
if (s_c++ < 5)
return VINF_SUCCESS;
}
case APIC_DM_INIT:
/** @todo implement APIC_DM_INIT? */
default:
{
static unsigned s_c = 0;
if (s_c++ < 100)
AssertLogRelMsgFailed(("delivery type %d not implemented. u8Pin=%d u8Level=%d\n", u8Delivery, u8Pin, u8Level));
return VERR_INTERNAL_ERROR_4;
}
}
}
return VINF_SUCCESS;
}
/* return -1 if no bit is set */
{
int i;
for(i = 7; i >= 0; i--) {
if (tab[i] != 0) {
}
}
return -1;
}
static int apic_get_ppr(APICState *s)
{
if (isrv < 0)
isrv = 0;
isrv >>= 4;
else
return ppr;
}
static int apic_get_ppr_zero_tpr(APICState *s)
{
int isrv;
if (isrv < 0)
isrv = 0;
return isrv;
}
static int apic_get_arb_pri(APICState *s)
{
/* XXX: arbitration */
return 0;
}
/* signal the CPU if an irq is pending */
{
if (!(s->spurious_vec & APIC_SV_ENABLE))
{
/* Clear any pending APIC interrupt action flag. */
cpuClearInterrupt(dev, s);
return false;
}
if (irrv < 0)
return false;
ppr = apic_get_ppr(s);
return false;
cpuSetInterrupt(dev, s);
return true;
}
{
if (!dev)
return false;
/*
* All our callbacks now come from single IOAPIC, thus locking
* seems to be excessive now (@todo: check)
*/
if (irrv < 0)
return false;
ppr = apic_get_ppr_zero_tpr(s);
return false;
return true;
}
{
bool fIrqIsActive = false;
bool fIrqWasActive = false;
/* If an interrupt is pending and now masked, then clear the FF flag. */
if (fIrqWasActive && !fIrqIsActive)
{
cpuClearInterrupt(dev, s);
}
}
{
LogFlow(("CPU%d: apic_set_irq vector=%x, trigger_mode=%x\n", s->phys_id, vector_num, trigger_mode));
if (trigger_mode)
else
apic_update_irq(dev, s);
}
{
int isrv;
if (isrv < 0)
return;
/* XXX: send the EOI packet to the APIC bus to allow the I/O APIC to
set the remote IRR bit for level triggered interrupts. */
apic_update_irq(dev, s);
}
{
if (dest_mode == 0)
{
if (dest == 0xff)
mask = 0xff;
else
}
else
{
uint32_t i;
/* XXX: cluster mode */
{
{
mask |= (1 << i);
}
{
&&
{
mask |= (1 << i);
}
}
apic++;
}
}
return mask;
}
#ifdef IN_RING3
{
int i;
for(i = 0; i < APIC_LVT_NB; i++)
s->tpr = 0;
s->spurious_vec = 0xff;
s->log_dest = 0;
s->dest_mode = 0xff;
s->esr = 0;
s->divide_conf = 0;
s->count_shift = 0;
s->initial_count = 0;
s->initial_count_load_time = 0;
s->next_time = 0;
}
{
apic_init_ipi(dev, s);
cpuSendInitIpi(dev, s);
}
/* send a SIPI message to the CPU to start it */
{
}
#endif /* IN_RING3 */
{
uint32_t deliver_bitmask = 0;
LogFlow(("apic_deliver dest=%x dest_mode=%x dest_shorthand=%x delivery_mode=%x vector_num=%x polarity=%x trigger_mode=%x\n", dest, dest_mode, dest_shorthand, delivery_mode, vector_num, polarity, trigger_mode));
switch (dest_shorthand) {
case 0:
break;
case 1:
break;
case 2:
deliver_bitmask = 0xffffffff;
break;
case 3:
break;
}
switch (delivery_mode) {
case APIC_DM_INIT:
{
return VINF_SUCCESS;
}
}
break;
case APIC_DM_SIPI:
# ifdef IN_RING3
return VINF_SUCCESS;
# else
/* We shall send SIPI only in R3, R0 calls should be
rescheduled to R3 */
return VINF_IOM_HC_MMIO_WRITE;
# endif
}
}
{
/* if the APIC is not installed or enabled, we let the 8259 handle the
IRQs */
if (!dev)
{
Log(("apic_get_interrupt: returns -1 (!s)\n"));
return -1;
}
int intno;
if (!(s->spurious_vec & APIC_SV_ENABLE)) {
return -1;
}
/* XXX: spurious IRQ handling */
if (intno < 0) {
return -1;
}
return s->spurious_vec & 0xff;
}
apic_update_irq(dev, s);
return intno;
}
{
int64_t d;
s->count_shift;
/* periodic */
} else {
if (d >= s->initial_count)
val = 0;
else
val = s->initial_count - d;
}
return val;
}
/**
* Does the frequency hinting and logging.
*
* @param pThis The device state.
*/
{
{
: 100 /*whatever*/;
}
}
/**
* Implementation of the 0380h access: Timer reset + new initial count.
*
* @param dev The device state.
* @param pThis The APIC sub-device state.
* @param u32NewInitialCount The new initial count for the timer.
*/
static void apicTimerSetInitialCount(APICDeviceInfo *dev, APICState *pThis, uint32_t u32NewInitialCount)
{
/*
* Don't (re-)arm the timer if the it's masked or if it's
* a zero length one-shot timer.
*/
/** @todo check the correct behavior of setting a 0 initial_count for a one-shot
* timer. This is just copying the behavior of the original code. */
|| u32NewInitialCount != 0))
{
/*
* operation. This avoids racing the clock between get and set.
*/
cTicksNext += 1;
pThis->fTimerArmed = true;
}
else
{
/* Stop it if necessary and record the load time for unmasking. */
if (pThis->fTimerArmed)
{
pThis->fTimerArmed = false;
}
}
}
/**
* Implementation of the 0320h access: change the LVT flags.
*
* @param dev The device state.
* @param pThis The APIC sub-device state to operate on.
* @param fNew The new flags.
*/
{
/*
* Make the flag change, saving the old ones so we can avoid
* unnecessary work.
*/
/* Only the masked and peridic bits are relevant (see apic_timer_update). */
{
/*
* If changed to one-shot from periodic, stop the timer if we're not
* in the first period.
*/
/** @todo check how clearing the periodic flag really should behave when not
* in period 1. The current code just mirrors the behavior of the
* original implementation. */
if ( (fOld & APIC_LVT_TIMER_PERIODIC)
&& !(fNew & APIC_LVT_TIMER_PERIODIC))
{
{
/* not first period, stop it. */
pThis->fTimerArmed = false;
}
/* else: first period, let it fire normally. */
}
/*
* We postpone stopping the timer when it's masked, this way we can
* avoid some timer work when the guest temporarily masks the timer.
* (apicTimerCallback will stop it if still masked.)
*/
if (fNew & APIC_LVT_MASKED)
else if (pThis->fTimerArmed)
/*
* If unmasked and not armed, we have to rearm the timer so it will
* fire at the end of the current period.
* This is code is currently RACING the virtual sync clock!
*/
else if (fOld & APIC_LVT_MASKED)
{
{
uint64_t cTicks = (TMTimerGet(pThis->CTX_SUFF(pTimer)) - pThis->initial_count_load_time) >> pThis->count_shift;
if (fNew & APIC_LVT_TIMER_PERIODIC)
NextTS = ((cTicks / ((uint64_t)pThis->initial_count + 1)) + 1) * ((uint64_t)pThis->initial_count + 1);
else
{
break;
}
/* Try avoid the assertion in TM.cpp... this isn't perfect! */
|| cTries > 10)
{
pThis->fTimerArmed = true;
break;
}
}
}
}
else
}
# ifdef IN_RING3
/**
* Timer callback function.
*
* @param pDevIns The device state.
* @param pTimer The timer handle.
* @param pvUser User argument pointing to the APIC instance.
*/
{
LogFlow(("apic_timer: trigger irq\n"));
/* new interval. */
pThis->fTimerArmed = true;
} else {
/* single shot. */
pThis->fTimerArmed = false;
}
} else {
/* masked, do not rearm. */
pThis->fTimerArmed = false;
}
}
# endif /* IN_RING3 */
{
int index;
switch(index) {
case 0x02: /* id */
break;
case 0x03: /* version */
break;
case 0x08:
break;
case 0x09:
val = apic_get_arb_pri(s);
break;
case 0x0a:
/* ppr */
val = apic_get_ppr(s);
break;
case 0x0b:
val = 0;
break;
case 0x0d:
break;
case 0x0e:
/* Bottom 28 bits are always 1 */
break;
case 0x0f:
val = s->spurious_vec;
break;
case 0x10: case 0x11: case 0x12: case 0x13: case 0x14: case 0x15: case 0x16: case 0x17:
break;
case 0x18: case 0x19: case 0x1a: case 0x1b: case 0x1c: case 0x1d: case 0x1e: case 0x1f:
break;
case 0x20: case 0x21: case 0x22: case 0x23: case 0x24: case 0x25: case 0x26: case 0x27:
break;
case 0x28:
break;
case 0x30:
case 0x31:
break;
case 0x32: case 0x33: case 0x34: case 0x35: case 0x36: case 0x37:
break;
case 0x38:
val = s->initial_count;
break;
case 0x39:
break;
case 0x3e:
val = s->divide_conf;
break;
case 0x2f:
/**
* Correctable machine check exception vector, @todo: implement me!
*/
default:
s->esr |= ESR_ILLEGAL_ADDRESS;
val = 0;
break;
}
#ifdef DEBUG_APIC
#endif
return val;
}
{
}
{
int rc = VINF_SUCCESS;
int index;
#ifdef DEBUG_APIC
#endif
switch(index) {
case 0x02:
break;
case 0x03:
Log(("apic_mem_writel: write to version register; ignored\n"));
break;
case 0x08:
break;
case 0x09:
case 0x0a:
break;
case 0x0b: /* EOI */
break;
case 0x0d:
break;
case 0x0e:
break;
case 0x0f:
apic_update_irq(dev, s);
break;
case 0x10: case 0x11: case 0x12: case 0x13: case 0x14: case 0x15: case 0x16: case 0x17:
case 0x18: case 0x19: case 0x1a: case 0x1b: case 0x1c: case 0x1d: case 0x1e: case 0x1f:
case 0x20: case 0x21: case 0x22: case 0x23: case 0x24: case 0x25: case 0x26: case 0x27:
case 0x28:
break;
case 0x30:
break;
case 0x31:
break;
case 0x32 + APIC_LVT_TIMER:
AssertCompile(APIC_LVT_TIMER == 0);
break;
case 0x33: case 0x34: case 0x35: case 0x36: case 0x37:
{
int n = index - 0x32;
}
break;
case 0x38:
break;
case 0x39:
break;
case 0x3e:
{
int v;
}
break;
default:
s->esr |= ESR_ILLEGAL_ADDRESS;
break;
}
return rc;
}
#ifdef IN_RING3
{
int i;
SSMR3PutU32(f, s->apicbase);
SSMR3PutU32(f, s->id);
SSMR3PutU32(f, s->phys_id);
SSMR3PutU32(f, s->arb_id);
SSMR3PutU32(f, s->tpr);
SSMR3PutU32(f, s->spurious_vec);
SSMR3PutU8(f, s->log_dest);
SSMR3PutU8(f, s->dest_mode);
for (i = 0; i < 8; i++) {
SSMR3PutU32(f, s->isr[i]);
SSMR3PutU32(f, s->tmr[i]);
SSMR3PutU32(f, s->irr[i]);
}
for (i = 0; i < APIC_LVT_NB; i++) {
SSMR3PutU32(f, s->lvt[i]);
}
SSMR3PutU32(f, s->esr);
SSMR3PutU32(f, s->icr[0]);
SSMR3PutU32(f, s->divide_conf);
SSMR3PutU32(f, s->count_shift);
SSMR3PutU32(f, s->initial_count);
SSMR3PutU64(f, s->initial_count_load_time);
SSMR3PutU64(f, s->next_time);
}
{
int i;
/* XXX: what if the base changes? (registered memory regions) */
SSMR3GetU32(f, &s->apicbase);
switch (version_id)
{
{
SSMR3GetU8(f, &val);
/* UP only in old saved states */
s->phys_id = 0;
SSMR3GetU8(f, &val);
break;
}
case APIC_SAVED_STATE_VERSION:
SSMR3GetU32(f, &s->id);
SSMR3GetU32(f, &s->phys_id);
SSMR3GetU32(f, &s->arb_id);
break;
default:
}
SSMR3GetU32(f, &s->tpr);
SSMR3GetU32(f, &s->spurious_vec);
SSMR3GetU8(f, &s->log_dest);
SSMR3GetU8(f, &s->dest_mode);
for (i = 0; i < 8; i++) {
SSMR3GetU32(f, &s->isr[i]);
SSMR3GetU32(f, &s->tmr[i]);
SSMR3GetU32(f, &s->irr[i]);
}
for (i = 0; i < APIC_LVT_NB; i++) {
SSMR3GetU32(f, &s->lvt[i]);
}
SSMR3GetU32(f, &s->esr);
SSMR3GetU32(f, &s->icr[0]);
SSMR3GetU32(f, &s->divide_conf);
s->uHintedCountShift = s->uHintedInitialCount = 0;
if (s->fTimerArmed)
return VINF_SUCCESS; /** @todo darn mess! */
}
#endif /* IN_RING3 */
static void ioapic_service(IOAPICState *s)
{
uint8_t i;
for (i = 0; i < IOAPIC_NUM_PINS; i++) {
mask = 1 << i;
if (!(entry & APIC_LVT_MASKED)) {
if (trig_mode == APIC_TRIGGER_EDGE)
if (delivery_mode == APIC_DM_EXTINT)
/* malc: i'm still not so sure about ExtINT delivery */
{
AssertMsgFailed(("Delivery mode ExtINT"));
}
else
dest,
/* We must be sure that attempts to reschedule in R3
never get here */
}
}
}
}
{
/* level triggered */
if (level) {
ioapic_service(s);
}
} else {
}
} else {
/* edge triggered */
if (level) {
ioapic_service(s);
}
}
}
}
{
int index;
addr &= 0xff;
if (addr == 0x00) {
} else if (addr == 0x10) {
switch (s->ioregsel) {
case 0x00:
break;
case 0x01:
break;
case 0x02:
val = 0;
break;
default:
if (s->ioregsel & 1)
else
}
}
#ifdef DEBUG_IOAPIC
#endif
}
return val;
}
{
int index;
addr &= 0xff;
if (addr == 0x00) {
return;
} else if (addr == 0x10) {
#ifdef DEBUG_IOAPIC
#endif
switch (s->ioregsel) {
case 0x00:
return;
case 0x01:
case 0x02:
return;
default:
if (s->ioregsel & 1) {
} else {
/* According to IOAPIC spec, vectors should be from 0x10 to 0xfe */
if ((val & APIC_LVT_MASKED) ||
{
}
else
{
/*
* Linux 2.6 kernels has pretty strange function
* unlock_ExtINT_logic() which writes
* absolutely bogus (all 0) value into the vector
* with pretty vague explanation why.
* So we just ignore such writes.
*/
}
}
ioapic_service(s);
}
}
}
}
#ifdef IN_RING3
{
int i;
SSMR3PutU8(f, s->id);
SSMR3PutU8(f, s->ioregsel);
for (i = 0; i < IOAPIC_NUM_PINS; i++) {
SSMR3PutU64(f, s->ioredtbl[i]);
}
}
{
int i;
if (version_id != 1)
SSMR3GetU8(f, &s->id);
SSMR3GetU8(f, &s->ioregsel);
for (i = 0; i < IOAPIC_NUM_PINS; i++) {
SSMR3GetU64(f, &s->ioredtbl[i]);
}
return 0;
}
static void ioapic_reset(void *opaque)
{
int i;
memset(s, 0, sizeof(*s));
for(i = 0; i < IOAPIC_NUM_PINS; i++)
if (pDevIns)
{
}
if (pIoApicHlp)
{
s->pIoApicHlpR3 = pIoApicHlp;
}
}
#endif /* IN_RING3 */
/* LAPIC */
PDMBOTHCBDECL(int) apicMMIORead(PPDMDEVINS pDevIns, void *pvUser, RTGCPHYS GCPhysAddr, void *pv, unsigned cb)
{
/** @todo: add LAPIC range validity checks (different LAPICs can theoretically have
different physical addresses, see #3092) */
switch (cb)
{
case 1:
break;
case 2:
break;
case 4:
{
#if 0 /** @note experimental */
#ifndef IN_RING3
&& ++s->cTPRPatchAttempts < APIC_MAX_PATCH_ATTEMPTS)
{
#ifdef IN_RC
#else
pDevIns->pHlpR0->pfnPATMSetMMIOPatchInfo(pDevIns, GCPhysAddr, pDevIns + RT_OFFSETOF(APICState, tpr));
#endif
return VINF_PATM_HC_MMIO_PATCH_READ;
}
#endif
#endif /* experimental */
break;
}
default:
return VERR_INTERNAL_ERROR;
}
return VINF_SUCCESS;
}
PDMBOTHCBDECL(int) apicMMIOWrite(PPDMDEVINS pDevIns, void *pvUser, RTGCPHYS GCPhysAddr, void *pv, unsigned cb)
{
/** @todo: add LAPIC range validity checks (multiple LAPICs can theoretically have
different physical addresses, see #3092) */
switch (cb)
{
case 1:
case 2:
/* ignore */
break;
case 4:
{
int rc;
return rc;
}
default:
return VERR_INTERNAL_ERROR;
}
return VINF_SUCCESS;
}
#ifdef IN_RING3
/* Print a 8-dword LAPIC bit map (256 bits). */
{
unsigned i;
for (i = 0; i < 8; ++i)
{
}
}
/* Print basic LAPIC state. */
{
unsigned max_lvt;
}
/* Print the more interesting LAPIC LVT entries. */
{
"NMI", "INIT", "Reserved", "ExtINT" };
}
/* Print LAPIC timer state. */
{
unsigned divider;
}
/**
* Info handler, device version. Dumps Local APIC(s) state according to given argument.
*
* @param pDevIns Device instance which registered the info.
* @param pHlp Callback functions for doing output.
* @param pszArgs Argument string. Optional.
*/
{
{
}
{
}
{
}
else
{
}
}
/**
* @copydoc FNSSMDEVLIVEEXEC
*/
{
return VINF_SSM_DONT_CALL_AGAIN;
}
/**
* @copydoc FNSSMDEVSAVEEXEC
*/
{
/* config */
/* save all APICs data, @todo: is it correct? */
return VINF_SUCCESS;
}
/**
* @copydoc FNSSMDEVLOADEXEC
*/
static DECLCALLBACK(int) apicLoadExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
{
if ( uVersion != APIC_SAVED_STATE_VERSION
/* config */
if (uVersion > APIC_SAVED_STATE_VERSION_VBOX_30) {
return SSMR3SetCfgError(pSSM, RT_SRC_POS, N_("Config mismatch - cCpus: saved=%#x config=%#x"), cCpus, pThis->cCpus);
bool fIoApic;
return SSMR3SetCfgError(pSSM, RT_SRC_POS, N_("Config mismatch - fIoApic: saved=%RTbool config=%RTbool"), fIoApic, pThis->fIoApic);
return SSMR3SetCfgError(pSSM, RT_SRC_POS, N_("Config mismatch - uApicVersion: saved=%#x config=%#x"), uApicVersion, pThis->enmVersion);
}
if (uPass != SSM_PASS_FINAL)
return VINF_SUCCESS;
/* load all APICs data */ /** @todo: is it correct? */
AssertFailed();
}
);
return VINF_SUCCESS;
}
/**
* @copydoc FNPDMDEVRESET
*/
{
unsigned i;
/* Reset all APICs. */
/* Clear LAPIC state as if an INIT IPI was sent. */
/* The IDs are not touched by apic_init_ipi() and must be reset now. */
/* Reset should re-enable the APIC, see comment in msi.h */
/* Clear any pending APIC interrupt action flag. */
}
/** @todo r=bird: Why is this done everytime, while the constructor first
* checks the CPUID? Who is right? */
}
/**
* @copydoc FNPDMDEVRELOCATE
*/
{
}
{
int i;
/* See comment in msi.h for LAPIC base info */
/* Mark first CPU as BSP */
if (id == 0)
for (i = 0; i < APIC_LVT_NB; i++)
}
/**
* @copydoc FNPDMDEVCONSTRUCT
*/
{
int rc;
uint32_t i;
bool fIoApic;
bool fGCEnabled;
bool fR0Enabled;
/*
* Only single device instance.
*/
/*
* Validate configuration.
*/
if (!CFGMR3AreValuesValid(pCfg,
"IOAPIC\0"
"GCEnabled\0"
"R0Enabled\0"
"NumCPUs\0"))
if (RT_FAILURE(rc))
N_("Configuration error: Failed to read \"IOAPIC\""));
if (RT_FAILURE(rc))
N_("Configuration error: Failed to query boolean value \"GCEnabled\""));
if (RT_FAILURE(rc))
N_("Configuration error: Failed to query boolean value \"R0Enabled\""));
if (RT_FAILURE(rc))
N_("Configuration error: Failed to query integer value \"NumCPUs\""));
Log(("APIC: cCpus=%d fR0Enabled=%RTbool fGCEnabled=%RTbool fIoApic=%RTbool\n", cCpus, fR0Enabled, fGCEnabled, fIoApic));
/** @todo Current implementation is limited to 32 CPUs due to the use of 32
* bits bitmasks. */
if (cCpus > 32)
N_("Configuration error: Invalid value for \"NumCPUs\""));
/*
* Init the data.
*/
/* Use PDMAPICVERSION_X2APIC to activate x2APIC mode */
/*
* We are not freeing this memory, as it's automatically released when guest exits.
*/
rc = MMHyperAlloc(pVM, cCpus * sizeof(APICState), 1, MM_TAG_PDM_DEVICE_USER, (void **)&pThis->paLapicsR3);
if (RT_FAILURE(rc))
return VERR_NO_MEMORY;
for (i = 0; i < cCpus; i++)
/*
* Register the APIC.
*/
if (fGCEnabled) {
} else {
}
if (fR0Enabled) {
} else {
}
/*
* The the CPUID feature bit.
*/
/** @todo r=bird: See remark in the apicReset. */
if (u32Eax >= 1) {
if ( fIoApic /* If IOAPIC is enabled, enable Local APIC in any case */
|| ( u32Ebx == X86_CPUID_VENDOR_INTEL_EBX
|| ( u32Ebx == X86_CPUID_VENDOR_AMD_EBX
LogRel(("Activating Local APIC\n"));
}
}
/*
* Register the MMIO range.
* @todo: shall reregister, if base changes.
*/
/* See comment in msi.h, on why LAPIC and MSI share same region */
if (RT_FAILURE(rc))
return rc;
if (fGCEnabled) {
if (RT_FAILURE(rc))
return rc;
}
if (fR0Enabled) {
if (RT_FAILURE(rc))
return rc;
}
/*
* Create the APIC timers.
*/
for (i = 0; i < cCpus; i++) {
if (RT_FAILURE(rc))
return rc;
}
/*
* Saved state.
*/
if (RT_FAILURE(rc))
return rc;
/*
* Register debugger info callback.
*/
"Recognizes 'basic', 'lvt', 'timer' as arguments, defaulting to 'basic'.", lapicInfo);
#ifdef VBOX_WITH_STATISTICS
/*
* Statistics.
*/
PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMMIOReadGC, STAMTYPE_COUNTER, "/Devices/APIC/MMIOReadGC", STAMUNIT_OCCURENCES, "Number of APIC MMIO reads in GC.");
PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMMIOReadHC, STAMTYPE_COUNTER, "/Devices/APIC/MMIOReadHC", STAMUNIT_OCCURENCES, "Number of APIC MMIO reads in HC.");
PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMMIOWriteGC, STAMTYPE_COUNTER, "/Devices/APIC/MMIOWriteGC", STAMUNIT_OCCURENCES, "Number of APIC MMIO writes in GC.");
PDMDevHlpSTAMRegister(pDevIns, &pThis->StatMMIOWriteHC, STAMTYPE_COUNTER, "/Devices/APIC/MMIOWriteHC", STAMUNIT_OCCURENCES, "Number of APIC MMIO writes in HC.");
PDMDevHlpSTAMRegister(pDevIns, &pThis->StatClearedActiveIrq,STAMTYPE_COUNTER, "/Devices/APIC/MaskedActiveIRQ", STAMUNIT_OCCURENCES, "Number of cleared irqs.");
for (i = 0; i < cCpus; i++) {
PDMDevHlpSTAMRegisterF(pDevIns, &pApic->StatTimerSetInitialCount, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, "Calls to apicTimerSetInitialCount.", "/Devices/APIC/%u/TimerSetInitialCount", i);
PDMDevHlpSTAMRegisterF(pDevIns, &pApic->StatTimerSetInitialCountArm, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, "TMTimerSetRelative calls.", "/Devices/APIC/%u/TimerSetInitialCount/Arm", i);
PDMDevHlpSTAMRegisterF(pDevIns, &pApic->StatTimerSetInitialCountDisarm, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, "TMTimerStop calls.", "/Devices/APIC/%u/TimerSetInitialCount/Disasm", i);
PDMDevHlpSTAMRegisterF(pDevIns, &pApic->StatTimerSetLvt, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, "Calls to apicTimerSetLvt.", "/Devices/APIC/%u/TimerSetLvt", i);
PDMDevHlpSTAMRegisterF(pDevIns, &pApic->StatTimerSetLvtClearPeriodic, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, "Clearing APIC_LVT_TIMER_PERIODIC.", "/Devices/APIC/%u/TimerSetLvt/ClearPeriodic", i);
PDMDevHlpSTAMRegisterF(pDevIns, &pApic->StatTimerSetLvtPostponed, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, "TMTimerStop postponed.", "/Devices/APIC/%u/TimerSetLvt/Postponed", i);
PDMDevHlpSTAMRegisterF(pDevIns, &pApic->StatTimerSetLvtArmed, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, "TMTimerSet avoided.", "/Devices/APIC/%u/TimerSetLvt/Armed", i);
PDMDevHlpSTAMRegisterF(pDevIns, &pApic->StatTimerSetLvtArm, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, "TMTimerSet necessary.", "/Devices/APIC/%u/TimerSetLvt/Arm", i);
PDMDevHlpSTAMRegisterF(pDevIns, &pApic->StatTimerSetLvtArmRetries, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, "TMTimerSet retries.", "/Devices/APIC/%u/TimerSetLvt/ArmRetries", i);
PDMDevHlpSTAMRegisterF(pDevIns, &pApic->StatTimerSetLvtNoRelevantChange,STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, "No relevant flags changed.", "/Devices/APIC/%u/TimerSetLvt/NoRelevantChange", i);
}
#endif
return VINF_SUCCESS;
}
/**
* APIC device registration structure.
*/
const PDMDEVREG g_DeviceAPIC =
{
/* u32Version */
/* szName */
"apic",
/* szRCMod */
"VBoxDD2GC.gc",
/* szR0Mod */
"VBoxDD2R0.r0",
/* pszDescription */
"Advanced Programmable Interrupt Controller (APIC) Device",
/* fFlags */
PDM_DEVREG_FLAGS_HOST_BITS_DEFAULT | PDM_DEVREG_FLAGS_GUEST_BITS_32_64 | PDM_DEVREG_FLAGS_PAE36 | PDM_DEVREG_FLAGS_RC | PDM_DEVREG_FLAGS_R0,
/* fClass */
/* cMaxInstances */
1,
/* cbInstance */
sizeof(APICState),
/* pfnConstruct */
/* pfnDestruct */
NULL,
/* pfnRelocate */
/* pfnIOCtl */
NULL,
/* pfnPowerOn */
NULL,
/* pfnReset */
/* pfnSuspend */
NULL,
/* pfnResume */
NULL,
/* pfnAttach */
NULL,
/* pfnDetach */
NULL,
/* pfnQueryInterface. */
NULL,
/* pfnInitComplete */
NULL,
/* pfnPowerOff */
NULL,
/* pfnSoftReset */
NULL,
/* u32VersionEnd */
};
#endif /* IN_RING3 */
/* IOAPIC */
PDMBOTHCBDECL(int) ioapicMMIORead(PPDMDEVINS pDevIns, void *pvUser, RTGCPHYS GCPhysAddr, void *pv, unsigned cb)
{
switch (cb) {
case 1:
break;
case 2:
break;
case 4:
break;
default:
IOAPIC_UNLOCK(s);
return VERR_INTERNAL_ERROR;
}
IOAPIC_UNLOCK(s);
return VINF_SUCCESS;
}
PDMBOTHCBDECL(int) ioapicMMIOWrite(PPDMDEVINS pDevIns, void *pvUser, RTGCPHYS GCPhysAddr, void *pv, unsigned cb)
{
switch (cb) {
case 1:
case 2:
case 4:
IOAPIC_UNLOCK(s);
break;
default:
return VERR_INTERNAL_ERROR;
}
return VINF_SUCCESS;
}
{
/* PDM lock is taken here; @todo add assertion */
}
#ifdef IN_RING3
/**
* Info handler, device version. Dumps I/O APIC state.
*
* @param pDevIns Device instance which registered the info.
* @param pHlp Callback functions for doing output.
* @param pszArgs Argument string. Optional and specific to the handler.
*/
{
unsigned i;
unsigned max_redir;
val = s->id << 24; /* Would be nice to call ioapic_mem_readl() directly, but that's not so simple. */
val = 0;
pHlp->pfnPrintf(pHlp, " idx dst_mode dst_addr mask trigger rirr polarity dlvr_st dlvr_mode vector\n");
for (i = 0; i <= max_redir; ++i)
{
"NMI ", "INIT ", "Resrvd", "ExtINT" };
i,
s->ioredtbl[i] /* entire register */
);
}
}
/**
* @copydoc FNSSMDEVSAVEEXEC
*/
{
ioapic_save(pSSM, s);
return VINF_SUCCESS;
}
/**
* @copydoc FNSSMDEVLOADEXEC
*/
static DECLCALLBACK(int) ioapicLoadExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
{
AssertFailed();
}
return VINF_SUCCESS;
}
/**
* @copydoc FNPDMDEVRESET
*/
{
ioapic_reset(s);
IOAPIC_UNLOCK(s);
}
/**
* @copydoc FNPDMDEVRELOCATE
*/
{
}
/**
* @copydoc FNPDMDEVCONSTRUCT
*/
{
bool fGCEnabled;
bool fR0Enabled;
int rc;
/*
* Validate and read the configuration.
*/
if (RT_FAILURE(rc))
N_("Configuration error: Failed to query boolean value \"GCEnabled\""));
if (RT_FAILURE(rc))
N_("Configuration error: Failed to query boolean value \"R0Enabled\""));
/*
* Initialize the state data.
*/
ioapic_reset(s);
s->id = 0;
/*
* Register the IOAPIC and get helpers.
*/
if (RT_FAILURE(rc))
{
return rc;
}
/*
* Register MMIO callbacks and saved state.
*/
if (RT_FAILURE(rc))
return rc;
if (fGCEnabled) {
if (RT_FAILURE(rc))
return rc;
}
if (fR0Enabled) {
if (RT_FAILURE(rc))
return rc;
}
if (RT_FAILURE(rc))
return rc;
/*
* Register debugger info callback.
*/
#ifdef VBOX_WITH_STATISTICS
/*
* Statistics.
*/
PDMDevHlpSTAMRegister(pDevIns, &s->StatMMIOReadGC, STAMTYPE_COUNTER, "/Devices/IOAPIC/MMIOReadGC", STAMUNIT_OCCURENCES, "Number of IOAPIC MMIO reads in GC.");
PDMDevHlpSTAMRegister(pDevIns, &s->StatMMIOReadHC, STAMTYPE_COUNTER, "/Devices/IOAPIC/MMIOReadHC", STAMUNIT_OCCURENCES, "Number of IOAPIC MMIO reads in HC.");
PDMDevHlpSTAMRegister(pDevIns, &s->StatMMIOWriteGC, STAMTYPE_COUNTER, "/Devices/IOAPIC/MMIOWriteGC", STAMUNIT_OCCURENCES, "Number of IOAPIC MMIO writes in GC.");
PDMDevHlpSTAMRegister(pDevIns, &s->StatMMIOWriteHC, STAMTYPE_COUNTER, "/Devices/IOAPIC/MMIOWriteHC", STAMUNIT_OCCURENCES, "Number of IOAPIC MMIO writes in HC.");
PDMDevHlpSTAMRegister(pDevIns, &s->StatSetIrqGC, STAMTYPE_COUNTER, "/Devices/IOAPIC/SetIrqGC", STAMUNIT_OCCURENCES, "Number of IOAPIC SetIrq calls in GC.");
PDMDevHlpSTAMRegister(pDevIns, &s->StatSetIrqHC, STAMTYPE_COUNTER, "/Devices/IOAPIC/SetIrqHC", STAMUNIT_OCCURENCES, "Number of IOAPIC SetIrq calls in HC.");
#endif
return VINF_SUCCESS;
}
/**
* IO APIC device registration structure.
*/
const PDMDEVREG g_DeviceIOAPIC =
{
/* u32Version */
/* szName */
"ioapic",
/* szRCMod */
"VBoxDD2GC.gc",
/* szR0Mod */
"VBoxDD2R0.r0",
/* pszDescription */
"I/O Advanced Programmable Interrupt Controller (IO-APIC) Device",
/* fFlags */
PDM_DEVREG_FLAGS_HOST_BITS_DEFAULT | PDM_DEVREG_FLAGS_GUEST_BITS_32_64 | PDM_DEVREG_FLAGS_PAE36 | PDM_DEVREG_FLAGS_RC | PDM_DEVREG_FLAGS_R0,
/* fClass */
/* cMaxInstances */
1,
/* cbInstance */
sizeof(IOAPICState),
/* pfnConstruct */
/* pfnDestruct */
NULL,
/* pfnRelocate */
/* pfnIOCtl */
NULL,
/* pfnPowerOn */
NULL,
/* pfnReset */
/* pfnSuspend */
NULL,
/* pfnResume */
NULL,
/* pfnAttach */
NULL,
/* pfnDetach */
NULL,
/* pfnQueryInterface. */
NULL,
/* pfnInitComplete */
NULL,
/* pfnPowerOff */
NULL,
/* pfnSoftReset */
NULL,
/* u32VersionEnd */
};
#endif /* IN_RING3 */
#endif /* !VBOX_DEVICE_STRUCT_TESTCASE */