timepci.c revision c58f1213e628a545081c70e26c6b67a841cff880
/*
* Copyright (C) 2006-2012 Oracle Corporation
*
* This file is part of VirtualBox Open Source Edition (OSE), as
* available from http://www.virtualbox.org. This file is free software;
* General Public License (GPL) as published by the Free Software
* Foundation, in version 2 as it comes in the "COPYING" file of the
* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
* --------------------------------------------------------------------
*
* This code is based on:
*
*
* Copyright (C) 2002 MandrakeSoft S.A.
*
* MandrakeSoft S.A.
* 43, rue d'Aboukir
* 75002 Paris - France
*
* modify it under the terms of the GNU Lesser General Public
* License as published by the Free Software Foundation; either
* version 2 of the License, or (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
* Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public
* License along with this library; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
*
*/
#include <stdint.h>
#include "biosint.h"
#include "inlines.h"
#if DEBUG_INT1A
#else
# define BX_DEBUG_INT1A(...)
#endif
// for access to RAM area which is used by interrupt vectors
// and BIOS Data Area
typedef struct {
} bios_data_t;
void init_rtc(void)
{
inb_cmos(0x0c);
inb_cmos(0x0d);
}
bx_bool rtc_updating(void)
{
// This function checks to see if the update-in-progress bit
// is set in CMOS Status Register A. If not, it returns 0.
// If it is set, it tries to wait until there is a transition
// to 0, and will return 0 if such a transition occurs. A 1
// is returned only after timing out. The maximum period
// that this bit should be set is constrained to 244useconds.
// The count I use below guarantees coverage or more than
// this time, with any reasonable IPS setting.
iter = 25000;
while (--iter != 0) {
return 0;
}
return 1; // update-in-progress never transitioned to 0
}
extern void eoi_both_pics(void); /* in assembly code */
void call_int_4a(void);
{
// INT 70h: IRQ 8 - CMOS RTC interrupt from periodic or alarm modes
// Check which modes are enabled and have occurred.
if( ( registerB & 0x60 ) != 0 ) {
if( ( registerC & 0x20 ) != 0 ) {
// Handle Alarm Interrupt.
int_enable();
call_int_4a();
int_disable();
}
if( ( registerC & 0x40 ) != 0 ) {
// Handle Periodic Interrupt.
// Wait Interval (Int 15, AH=83) active.
if( time < 0x3D1 ) {
// Done waiting.
} else {
// Continue waiting.
time -= 0x3D1;
}
}
}
}
}
// @todo: the coding style WRT register access is totally inconsistent
// in the following routines
{
BX_DEBUG_INT1A("int1a: AX=%04x BX=%04x CX=%04x DX=%04x DS=%04x\n",
int_enable();
case 0: // get current clock count
int_disable();
int_enable();
// AH already 0
break;
case 1: // Set Current Clock Count
int_disable();
int_enable();
break;
case 2: // Read CMOS Time
if (rtc_updating()) {
break;
}
break;
case 3: // Set CMOS Time
// of bits in Status Register B, by setting Reg B to
// a few values and getting its value after INT 1A was called.
//
// try#1 try#2 try#3
// before 1111 1101 0111 1101 0000 0000
// after 0110 0010 0110 0010 0000 0010
//
// Bit4 in try#1 flipped in hardware (forced low) due to bit7=1
// My assumption: RegB = ((RegB & 01100000b) | 00000010b)
if (rtc_updating()) {
init_rtc();
// fall through as if an update were not in progress
}
// Set Daylight Savings time enabled bit to requested value
// (reg B already selected)
break;
case 4: // Read CMOS Date
if (rtc_updating()) {
break;
}
break;
case 5: // Set CMOS Date
// of bits in Status Register B, by setting Reg B to
// a few values and getting its value after INT 1A was called.
//
// try#1 try#2 try#3 try#4
// before 1111 1101 0111 1101 0000 0010 0000 0000
// after 0110 1101 0111 1101 0000 0010 0000 0000
//
// Bit4 in try#1 flipped in hardware (forced low) due to bit7=1
// My assumption: RegB = (RegB & 01111111b)
if (rtc_updating()) {
init_rtc();
break;
}
break;
case 6: // Set Alarm Time in CMOS
// of bits in Status Register B, by setting Reg B to
// a few values and getting its value after INT 1A was called.
//
// try#1 try#2 try#3
// before 1101 1111 0101 1111 0000 0000
// after 0110 1111 0111 1111 0010 0000
//
// Bit4 in try#1 flipped in hardware (forced low) due to bit7=1
// My assumption: RegB = ((RegB & 01111111b) | 00100000b)
if (val8 & 0x20) {
// Alarm interrupt enabled already
break;
}
if (rtc_updating()) {
init_rtc();
// fall through as if an update were not in progress
}
// enable Status Reg B alarm bit, clear halt clock bit
break;
case 7: // Turn off Alarm
// of bits in Status Register B, by setting Reg B to
// a few values and getting its value after INT 1A was called.
//
// try#1 try#2 try#3 try#4
// before 1111 1101 0111 1101 0010 0000 0010 0010
// after 0100 0101 0101 0101 0000 0000 0000 0010
//
// Bit4 in try#1 flipped in hardware (forced low) due to bit7=1
// My assumption: RegB = (RegB & 01010111b)
// clear clock-halt bit, disable alarm bit
break;
default:
}
}