#define LOG_GROUP LOG_GROUP_DEV_PCNET

#include <VBox/pdmdev.h>

#include <VBox/pgm.h>

#include <VBox/vm.h> /* for VM_IS_EMT */

#include <VBox/DevPCNet.h>

#include <iprt/asm.h>

#include <iprt/assert.h>

#include <iprt/critsect.h>

#include <iprt/string.h>

#include <iprt/time.h>

#include <iprt/net.h>

#ifdef IN_RING3

# include <iprt/mem.h>

# include <iprt/semaphore.h>

#endif

#include "../Builtins.h"

#define PCNET_GC_ENABLED

#if defined(LOG_ENABLED)

#define PCNET_DEBUG_IO

#define PCNET_DEBUG_BCR

#define PCNET_DEBUG_CSR

#define PCNET_DEBUG_RMD

#define PCNET_DEBUG_TMD

#define PCNET_DEBUG_MATCH

#define PCNET_DEBUG_MII

#endif

#define PCNET_IOPORT_SIZE 0x20

#define PCNET_PNPMMIO_SIZE 0x20

#define PCNET_SAVEDSTATE_VERSION 10

#define BCR_MAX_RAP 50

#define MII_MAX_REG 32

#define CSR_MAX_REG 128

#define PCNET_MAX_LINKDOWN_REPORTED 3

#define MAX_FRAME 1536

typedef struct PCNetState_st PCNetState;

struct PCNetState_st

{

PCIDEVICE PciDev;

#ifndef PCNET_NO_POLLING

/** Poll timer - R3. */

PTMTIMERR3 pTimerPollR3;

/** Poll timer - R0. */

PTMTIMERR0 pTimerPollR0;

/** Poll timer - RC. */

PTMTIMERRC pTimerPollRC;

#endif

#if HC_ARCH_BITS == 64

uint32_t Alignment1;

#endif

/** Software Interrupt timer - R3. */

PTMTIMERR3 pTimerSoftIntR3;

/** Software Interrupt timer - R0. */

PTMTIMERR0 pTimerSoftIntR0;

/** Software Interrupt timer - RC. */

PTMTIMERRC pTimerSoftIntRC;

/** Register Address Pointer */

uint32_t u32RAP;

/** Internal interrupt service */

int32_t iISR;

/** ??? */

uint32_t u32Lnkst;

/** Address of the RX descriptor table (ring). Loaded at init. */

RTGCPHYS32 GCRDRA;

/** Address of the TX descriptor table (ring). Loaded at init. */

RTGCPHYS32 GCTDRA;

uint8_t aPROM[16];

uint16_t aCSR[CSR_MAX_REG];

uint16_t aBCR[BCR_MAX_RAP];

uint16_t aMII[MII_MAX_REG];

uint16_t u16CSR0LastSeenByGuest;

uint16_t Alignment2[HC_ARCH_BITS == 32 ? 2 : 4];

/** Last time we polled the queues */

uint64_t u64LastPoll;

/** Size of current send frame */

uint32_t cbSendFrame;

#if HC_ARCH_BITS == 64

uint32_t Alignment3;

#endif

/** Buffer address of current send frame */

R3PTRTYPE(uint8_t *) pvSendFrame;

/** The xmit buffer. */

uint8_t abSendBuf[4096];

/** The recv buffer. */

uint8_t abRecvBuf[4096];

/** Pending send packet counter. */

uint32_t cPendingSends;

/** Size of a RX/TX descriptor (8 or 16 bytes according to SWSTYLE */

int iLog2DescSize;

/** Bits 16..23 in 16-bit mode */

RTGCPHYS32 GCUpperPhys;

/** Transmit signaller - RC. */

RCPTRTYPE(PPDMQUEUE) pXmitQueueRC;

/** Transmit signaller - R3. */

R3PTRTYPE(PPDMQUEUE) pXmitQueueR3;

/** Transmit signaller - R0. */

R0PTRTYPE(PPDMQUEUE) pXmitQueueR0;

/** Receive signaller - R3. */

R3PTRTYPE(PPDMQUEUE) pCanRxQueueR3;

/** Receive signaller - R0. */

R0PTRTYPE(PPDMQUEUE) pCanRxQueueR0;

/** Receive signaller - RC. */

RCPTRTYPE(PPDMQUEUE) pCanRxQueueRC;

/** Pointer to the device instance - RC. */

PPDMDEVINSRC pDevInsRC;

/** Pointer to the device instance - R3. */

PPDMDEVINSR3 pDevInsR3;

/** Pointer to the device instance - R0. */

PPDMDEVINSR0 pDevInsR0;

/** Restore timer.

PTMTIMERR3 pTimerRestore;

/** Pointer to the connector of the attached network driver. */

R3PTRTYPE(PPDMINETWORKCONNECTOR) pDrv;

/** Pointer to the attached network driver. */

R3PTRTYPE(PPDMIBASE) pDrvBase;

/** The base interface. */

PDMIBASE IBase;

/** The network port interface. */

PDMINETWORKPORT INetworkPort;

/** The network config port interface. */

PDMINETWORKCONFIG INetworkConfig;

/** Base address of the MMIO region. */

RTGCPHYS32 MMIOBase;

/** Base port of the I/O space region. */

RTIOPORT IOPortBase;

/** If set the link is currently up. */

bool fLinkUp;

/** If set the link is temporarily down because of a saved state load. */

bool fLinkTempDown;

/** Number of times we've reported the link down. */

RTUINT cLinkDownReported;

/** The configured MAC address. */

RTMAC MacConfigured;

/** Alignment padding. */

uint8_t Alignment4[HC_ARCH_BITS == 64 ? 6 : 2];

/** The LED. */

PDMLED Led;

/** The LED ports. */

PDMILEDPORTS ILeds;

/** Partner of ILeds. */

R3PTRTYPE(PPDMILEDCONNECTORS) pLedsConnector;

/** Async send thread */

RTSEMEVENT hSendEventSem;

/** The Async send thread. */

PPDMTHREAD pSendThread;

/** Access critical section. */

PDMCRITSECT CritSect;

/** Event semaphore for blocking on receive. */

RTSEMEVENT hEventOutOfRxSpace;

/** We are waiting/about to start waiting for more receive buffers. */

bool volatile fMaybeOutOfSpace;

/** True if we signal the guest that RX packets are missing. */

bool fSignalRxMiss;

uint8_t Alignment5[HC_ARCH_BITS == 64 ? 6 : 2];

#ifdef PCNET_NO_POLLING

RTGCPHYS32 TDRAPhysOld;

uint32_t cbTDRAOld;

RTGCPHYS32 RDRAPhysOld;

uint32_t cbRDRAOld;

DECLRCCALLBACKMEMBER(int, pfnEMInterpretInstructionRC, (PVM pVM, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize));

DECLR0CALLBACKMEMBER(int, pfnEMInterpretInstructionR0, (PVM pVM, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, uint32_t *pcbSize));

#endif

/** The shared memory used for the private interface - R3. */

R3PTRTYPE(PPCNETGUESTSHAREDMEMORY) pSharedMMIOR3;

/** The shared memory used for the private interface - R0. */

R0PTRTYPE(PPCNETGUESTSHAREDMEMORY) pSharedMMIOR0;

/** The shared memory used for the private interface - RC. */

RCPTRTYPE(PPCNETGUESTSHAREDMEMORY) pSharedMMIORC;

/** Error counter for bad receive descriptors. */

uint32_t uCntBadRMD;

/** True if host and guest admitted to use the private interface. */

bool fPrivIfEnabled;

bool fGCEnabled;

bool fR0Enabled;

bool fAm79C973;

uint32_t u32LinkSpeed;

#ifdef PCNET_QUEUE_SEND_PACKETS

# define PCNET_MAX_XMIT_SLOTS 128

# define PCNET_MAX_XMIT_SLOTS_MASK (PCNET_MAX_XMIT_SLOTS - 1)

uint32_t iXmitRingBufProd;

uint32_t iXmitRingBufCons;

/** @todo XXX currently atomic operations on this variable are overkill */

volatile int32_t cXmitRingBufPending;

uint16_t cbXmitRingBuffer[PCNET_MAX_XMIT_SLOTS];

R3PTRTYPE(uint8_t *) apXmitRingBuffer[PCNET_MAX_XMIT_SLOTS];

#endif

STAMCOUNTER StatReceiveBytes;

STAMCOUNTER StatTransmitBytes;

#ifdef VBOX_WITH_STATISTICS

STAMPROFILEADV StatMMIOReadGC;

STAMPROFILEADV StatMMIOReadHC;

STAMPROFILEADV StatMMIOWriteGC;

STAMPROFILEADV StatMMIOWriteHC;

STAMPROFILEADV StatAPROMRead;

STAMPROFILEADV StatAPROMWrite;

STAMPROFILEADV StatIOReadGC;

STAMPROFILEADV StatIOReadHC;

STAMPROFILEADV StatIOWriteGC;

STAMPROFILEADV StatIOWriteHC;

STAMPROFILEADV StatTimer;

STAMPROFILEADV StatReceive;

STAMPROFILEADV StatTransmit;

STAMPROFILEADV StatTransmitSend;

STAMPROFILEADV StatTdtePollGC;

STAMPROFILEADV StatTdtePollHC;

STAMPROFILEADV StatTmdStoreGC;

STAMPROFILEADV StatTmdStoreHC;

STAMPROFILEADV StatRdtePollGC;

STAMPROFILEADV StatRdtePollHC;

STAMPROFILE StatRxOverflow;

STAMCOUNTER StatRxOverflowWakeup;

STAMCOUNTER aStatXmitFlush[16];

STAMCOUNTER aStatXmitChainCounts[16];

STAMCOUNTER StatXmitSkipCurrent;

STAMPROFILEADV StatInterrupt;

STAMPROFILEADV StatPollTimer;

STAMCOUNTER StatMIIReads;

# ifdef PCNET_NO_POLLING

STAMCOUNTER StatRCVRingWrite;

STAMCOUNTER StatTXRingWrite;

STAMCOUNTER StatRingWriteHC;

STAMCOUNTER StatRingWriteR0;

STAMCOUNTER StatRingWriteGC;

STAMCOUNTER StatRingWriteFailedHC;

STAMCOUNTER StatRingWriteFailedR0;

STAMCOUNTER StatRingWriteFailedGC;

STAMCOUNTER StatRingWriteOutsideHC;

STAMCOUNTER StatRingWriteOutsideR0;

STAMCOUNTER StatRingWriteOutsideGC;

# endif

#endif /* VBOX_WITH_STATISTICS */

};

AssertCompileMemberAlignment(PCNetState, StatReceiveBytes, 8);

#define PCNETSTATE_2_DEVINS(pPCNet) ((pPCNet)->CTX_SUFF(pDevIns))

#define PCIDEV_2_PCNETSTATE(pPciDev) ((PCNetState *)(pPciDev))

#define PCNET_INST_NR (PCNETSTATE_2_DEVINS(pThis)->iInstance)

#define BCR_MSRDA 0

#define BCR_MSWRA 1

#define BCR_MC 2

#define BCR_RESERVED3 3

#define BCR_LNKST 4

#define BCR_LED1 5

#define BCR_LED2 6

#define BCR_LED3 7

#define BCR_RESERVED8 8

#define BCR_FDC 9

#define BCR_IOBASEL 16 /* Reserved */

#define BCR_IOBASEU 16 /* Reserved */

#define BCR_BSBC 18

#define BCR_EECAS 19

#define BCR_SWS 20

#define BCR_INTCON 21 /* Reserved */

#define BCR_PLAT 22

#define BCR_PCISVID 23

#define BCR_PCISID 24

#define BCR_SRAMSIZ 25

#define BCR_SRAMB 26

#define BCR_SRAMIC 27

#define BCR_EBADDRL 28

#define BCR_EBADDRU 29

#define BCR_EBD 30

#define BCR_STVAL 31

#define BCR_MIICAS 32

#define BCR_MIIADDR 33

#define BCR_MIIMDR 34

#define BCR_PCIVID 35

#define BCR_PMC_A 36

#define BCR_DATA0 37

#define BCR_DATA1 38

#define BCR_DATA2 39

#define BCR_DATA3 40

#define BCR_DATA4 41

#define BCR_DATA5 42

#define BCR_DATA6 43

#define BCR_DATA7 44

#define BCR_PMR1 45

#define BCR_PMR2 46

#define BCR_PMR3 47

#define BCR_DWIO(S) !!((S)->aBCR[BCR_BSBC] & 0x0080)

#define BCR_SSIZE32(S) !!((S)->aBCR[BCR_SWS ] & 0x0100)

#define BCR_SWSTYLE(S) ((S)->aBCR[BCR_SWS ] & 0x00FF)

#define CSR_INIT(S) !!((S)->aCSR[0] & 0x0001) /**< Init assertion */

#define CSR_STRT(S) !!((S)->aCSR[0] & 0x0002) /**< Start assertion */

#define CSR_STOP(S) !!((S)->aCSR[0] & 0x0004) /**< Stop assertion */

#define CSR_TDMD(S) !!((S)->aCSR[0] & 0x0008) /**< Transmit demand. (perform xmit poll now (readable, settable, not clearable) */

#define CSR_TXON(S) !!((S)->aCSR[0] & 0x0010) /**< Transmit on (readonly) */

#define CSR_RXON(S) !!((S)->aCSR[0] & 0x0020) /**< Receive On */

#define CSR_INEA(S) !!((S)->aCSR[0] & 0x0040) /**< Interrupt Enable */

#define CSR_LAPPEN(S) !!((S)->aCSR[3] & 0x0020) /**< Look Ahead Packet Processing Enable */

#define CSR_DXSUFLO(S) !!((S)->aCSR[3] & 0x0040) /**< Disable Transmit Stop on Underflow error */

#define CSR_ASTRP_RCV(S) !!((S)->aCSR[4] & 0x0400) /**< Auto Strip Receive */

#define CSR_DPOLL(S) !!((S)->aCSR[4] & 0x1000) /**< Disable Transmit Polling */

#define CSR_SPND(S) !!((S)->aCSR[5] & 0x0001) /**< Suspend */

#define CSR_LTINTEN(S) !!((S)->aCSR[5] & 0x4000) /**< Last Transmit Interrupt Enable */

#define CSR_TOKINTD(S) !!((S)->aCSR[5] & 0x8000) /**< Transmit OK Interrupt Disable */

#define CSR_STINT !!((S)->aCSR[7] & 0x0800) /**< Software Timer Interrupt */

#define CSR_STINTE !!((S)->aCSR[7] & 0x0400) /**< Software Timer Interrupt Enable */

#define CSR_DRX(S) !!((S)->aCSR[15] & 0x0001) /**< Disable Receiver */

#define CSR_DTX(S) !!((S)->aCSR[15] & 0x0002) /**< Disable Transmit */

#define CSR_LOOP(S) !!((S)->aCSR[15] & 0x0004) /**< Loopback Enable */

#define CSR_DRCVPA(S) !!((S)->aCSR[15] & 0x2000) /**< Disable Receive Physical Address */

#define CSR_DRCVBC(S) !!((S)->aCSR[15] & 0x4000) /**< Disable Receive Broadcast */

#define CSR_PROM(S) !!((S)->aCSR[15] & 0x8000) /**< Promiscuous Mode */

#if !defined(RT_ARCH_X86) && !defined(RT_ARCH_AMD64)

#error fix macros (and more in this file) for big-endian machines

#endif

#define CSR_IADR(S) (*(uint32_t*)((S)->aCSR + 1)) /**< Initialization Block Address */

#define CSR_CRBA(S) (*(uint32_t*)((S)->aCSR + 18)) /**< Current Receive Buffer Address */

#define CSR_CXBA(S) (*(uint32_t*)((S)->aCSR + 20)) /**< Current Transmit Buffer Address */

#define CSR_NRBA(S) (*(uint32_t*)((S)->aCSR + 22)) /**< Next Receive Buffer Address */

#define CSR_BADR(S) (*(uint32_t*)((S)->aCSR + 24)) /**< Base Address of Receive Ring */

#define CSR_NRDA(S) (*(uint32_t*)((S)->aCSR + 26)) /**< Next Receive Descriptor Address */

#define CSR_CRDA(S) (*(uint32_t*)((S)->aCSR + 28)) /**< Current Receive Descriptor Address */

#define CSR_BADX(S) (*(uint32_t*)((S)->aCSR + 30)) /**< Base Address of Transmit Descriptor */

#define CSR_NXDA(S) (*(uint32_t*)((S)->aCSR + 32)) /**< Next Transmit Descriptor Address */

#define CSR_CXDA(S) (*(uint32_t*)((S)->aCSR + 34)) /**< Current Transmit Descriptor Address */

#define CSR_NNRD(S) (*(uint32_t*)((S)->aCSR + 36)) /**< Next Next Receive Descriptor Address */

#define CSR_NNXD(S) (*(uint32_t*)((S)->aCSR + 38)) /**< Next Next Transmit Descriptor Address */

#define CSR_CRBC(S) ((S)->aCSR[40]) /**< Current Receive Byte Count */

#define CSR_CRST(S) ((S)->aCSR[41]) /**< Current Receive Status */

#define CSR_CXBC(S) ((S)->aCSR[42]) /**< Current Transmit Byte Count */

#define CSR_CXST(S) ((S)->aCSR[43]) /**< Current transmit status */

#define CSR_NRBC(S) ((S)->aCSR[44]) /**< Next Receive Byte Count */

#define CSR_NRST(S) ((S)->aCSR[45]) /**< Next Receive Status */

#define CSR_POLL(S) ((S)->aCSR[46]) /**< Transmit Poll Time Counter */

#define CSR_PINT(S) ((S)->aCSR[47]) /**< Transmit Polling Interval */

#define CSR_PXDA(S) (*(uint32_t*)((S)->aCSR + 60)) /**< Previous Transmit Descriptor Address*/

#define CSR_PXBC(S) ((S)->aCSR[62]) /**< Previous Transmit Byte Count */

#define CSR_PXST(S) ((S)->aCSR[63]) /**< Previous Transmit Status */

#define CSR_NXBA(S) (*(uint32_t*)((S)->aCSR + 64)) /**< Next Transmit Buffer Address */

#define CSR_NXBC(S) ((S)->aCSR[66]) /**< Next Transmit Byte Count */

#define CSR_NXST(S) ((S)->aCSR[67]) /**< Next Transmit Status */

#define CSR_RCVRC(S) ((S)->aCSR[72]) /**< Receive Descriptor Ring Counter */

#define CSR_XMTRC(S) ((S)->aCSR[74]) /**< Transmit Descriptor Ring Counter */

#define CSR_RCVRL(S) ((S)->aCSR[76]) /**< Receive Descriptor Ring Length */

#define CSR_XMTRL(S) ((S)->aCSR[78]) /**< Transmit Descriptor Ring Length */

#define CSR_MISSC(S) ((S)->aCSR[112]) /**< Missed Frame Count */

#define PHYSADDR(S,A) ((A) | (S)->GCUpperPhys)

#define CSR_VERSION_LOW_79C973 0x5003 /* the lower two bits must be 11b for AMD */

#define CSR_VERSION_LOW_79C970A 0x1003 /* the lower two bits must be 11b for AMD */

#define CSR_VERSION_HIGH 0x0262

struct INITBLK16

{

uint16_t mode; /**< copied into csr15 */

uint16_t padr1; /**< MAC 0..15 */

uint16_t padr2; /**< MAC 16..32 */

uint16_t padr3; /**< MAC 33..47 */

uint16_t ladrf1; /**< logical address filter 0..15 */

uint16_t ladrf2; /**< logical address filter 16..31 */

uint16_t ladrf3; /**< logical address filter 32..47 */

uint16_t ladrf4; /**< logical address filter 48..63 */

uint32_t rdra:24; /**< address of receive descriptor ring */

uint32_t res1:5; /**< reserved */

uint32_t rlen:3; /**< number of receive descriptor ring entries */

uint32_t tdra:24; /**< address of transmit descriptor ring */

uint32_t res2:5; /**< reserved */

uint32_t tlen:3; /**< number of transmit descriptor ring entries */

};

AssertCompileSize(INITBLK16, 24);

struct INITBLK32

{

uint16_t mode; /**< copied into csr15 */

uint16_t res1:4; /**< reserved */

uint16_t rlen:4; /**< number of receive descriptor ring entries */

uint16_t res2:4; /**< reserved */

uint16_t tlen:4; /**< number of transmit descriptor ring entries */

uint16_t padr1; /**< MAC 0..15 */

uint16_t padr2; /**< MAC 16..31 */

uint16_t padr3; /**< MAC 32..47 */

uint16_t res3; /**< reserved */

uint16_t ladrf1; /**< logical address filter 0..15 */

uint16_t ladrf2; /**< logical address filter 16..31 */

uint16_t ladrf3; /**< logibal address filter 32..47 */

uint16_t ladrf4; /**< logical address filter 48..63 */

uint32_t rdra; /**< address of receive descriptor ring */

uint32_t tdra; /**< address of transmit descriptor ring */

};

AssertCompileSize(INITBLK32, 28);

typedef struct TMD

{

struct

{

uint32_t tbadr; /**< transmit buffer address */

} tmd0;

struct

{

uint32_t bcnt:12; /**< buffer byte count (two's complement) */

uint32_t ones:4; /**< must be 1111b */

uint32_t res:7; /**< reserved */

uint32_t bpe:1; /**< bus parity error */

uint32_t enp:1; /**< end of packet */

uint32_t stp:1; /**< start of packet */

uint32_t def:1; /**< deferred */

uint32_t one:1; /**< exactly one retry was needed to transmit a frame */

uint32_t ltint:1; /**< suppress interrupts after successful transmission */

uint32_t nofcs:1; /**< when set, the state of DXMTFCS is ignored and

uint32_t err:1; /**< error occurred */

uint32_t own:1; /**< 0=owned by guest driver, 1=owned by controller */

} tmd1;

struct

{

uint32_t trc:4; /**< transmit retry count */

uint32_t res:12; /**< reserved */

uint32_t tdr:10; /**< ??? */

uint32_t rtry:1; /**< retry error */

uint32_t lcar:1; /**< loss of carrier */

uint32_t lcol:1; /**< late collision */

uint32_t exdef:1; /**< excessive deferral */

uint32_t uflo:1; /**< underflow error */

uint32_t buff:1; /**< out of buffers (ENP not found) */

} tmd2;

struct

{

uint32_t res; /**< reserved for user defined space */

} tmd3;

} TMD;

AssertCompileSize(TMD, 16);

typedef struct RMD

{

struct

{

uint32_t rbadr; /**< receive buffer address */

} rmd0;

struct

{

uint32_t bcnt:12; /**< buffer byte count (two's complement) */

uint32_t ones:4; /**< must be 1111b */

uint32_t res:4; /**< reserved */

uint32_t bam:1; /**< broadcast address match */

uint32_t lafm:1; /**< logical filter address match */

uint32_t pam:1; /**< physcial address match */

uint32_t bpe:1; /**< bus parity error */

uint32_t enp:1; /**< end of packet */

uint32_t stp:1; /**< start of packet */

uint32_t buff:1; /**< buffer error */

uint32_t crc:1; /**< crc error on incoming frame */

uint32_t oflo:1; /**< overflow error (lost all or part of incoming frame) */

uint32_t fram:1; /**< frame error */

uint32_t err:1; /**< error occurred */

uint32_t own:1; /**< 0=owned by guest driver, 1=owned by controller */

} rmd1;

struct

{

uint32_t mcnt:12; /**< message byte count */

uint32_t zeros:4; /**< 0000b */

uint32_t rpc:8; /**< receive frame tag */

uint32_t rcc:8; /**< receive frame tag + reserved */

} rmd2;

struct

{

uint32_t res; /**< reserved for user defined space */

} rmd3;

} RMD;

AssertCompileSize(RMD, 16);

#ifndef VBOX_DEVICE_STRUCT_TESTCASE

#define PRINT_TMD(T) Log2(( \

"TMD0 : TBADR=%#010x\n" \

"TMD1 : OWN=%d, ERR=%d, FCS=%d, LTI=%d, " \

"ONE=%d, DEF=%d, STP=%d, ENP=%d,\n" \

" BPE=%d, BCNT=%d\n" \

"TMD2 : BUF=%d, UFL=%d, EXD=%d, LCO=%d, " \

"LCA=%d, RTR=%d,\n" \

" TDR=%d, TRC=%d\n", \

(T)->tmd0.tbadr, \

(T)->tmd1.own, (T)->tmd1.err, (T)->tmd1.nofcs, \

(T)->tmd1.ltint, (T)->tmd1.one, (T)->tmd1.def, \

(T)->tmd1.stp, (T)->tmd1.enp, (T)->tmd1.bpe, \

4096-(T)->tmd1.bcnt, \

(T)->tmd2.buff, (T)->tmd2.uflo, (T)->tmd2.exdef,\

(T)->tmd2.lcol, (T)->tmd2.lcar, (T)->tmd2.rtry, \

(T)->tmd2.tdr, (T)->tmd2.trc))

#define PRINT_RMD(R) Log2(( \

"RMD0 : RBADR=%#010x\n" \

"RMD1 : OWN=%d, ERR=%d, FRAM=%d, OFLO=%d, " \

"CRC=%d, BUFF=%d, STP=%d, ENP=%d,\n " \

"BPE=%d, PAM=%d, LAFM=%d, BAM=%d, ONES=%d, BCNT=%d\n" \

"RMD2 : RCC=%d, RPC=%d, MCNT=%d, ZEROS=%d\n", \

(R)->rmd0.rbadr, \

(R)->rmd1.own, (R)->rmd1.err, (R)->rmd1.fram, \

(R)->rmd1.oflo, (R)->rmd1.crc, (R)->rmd1.buff, \

(R)->rmd1.stp, (R)->rmd1.enp, (R)->rmd1.bpe, \

(R)->rmd1.pam, (R)->rmd1.lafm, (R)->rmd1.bam, \

(R)->rmd1.ones, 4096-(R)->rmd1.bcnt, \

(R)->rmd2.rcc, (R)->rmd2.rpc, (R)->rmd2.mcnt, \

(R)->rmd2.zeros))

#if defined(PCNET_QUEUE_SEND_PACKETS) && defined(IN_RING3)

static int pcnetSyncTransmit(PCNetState *pThis);

#endif

static void pcnetPollTimerStart(PCNetState *pThis);

DECLINLINE(bool) pcnetTmdLoad(PCNetState *pThis, TMD *tmd, RTGCPHYS32 addr, bool fRetIfNotOwn)

{

PPDMDEVINS pDevIns = PCNETSTATE_2_DEVINS(pThis);

uint8_t ownbyte;

if (pThis->fPrivIfEnabled)

{

/* RX/TX descriptors shared between host and guest => direct copy */

uint8_t *pv = (uint8_t*)pThis->CTX_SUFF(pSharedMMIO)

+ (addr - pThis->GCTDRA)

+ pThis->CTX_SUFF(pSharedMMIO)->V.V1.offTxDescriptors;

if (!(pv[7] & 0x80) && fRetIfNotOwn)

return false;

memcpy(tmd, pv, 16);

return true;

}

else if (RT_UNLIKELY(BCR_SWSTYLE(pThis) == 0))

{

uint16_t xda[4];

PDMDevHlpPhysRead(pDevIns, addr+3, &ownbyte, 1);

if (!(ownbyte & 0x80) && fRetIfNotOwn)

return false;

PDMDevHlpPhysRead(pDevIns, addr, (void*)&xda[0], sizeof(xda));

((uint32_t *)tmd)[0] = (uint32_t)xda[0] | ((uint32_t)(xda[1] & 0x00ff) << 16);

((uint32_t *)tmd)[1] = (uint32_t)xda[2] | ((uint32_t)(xda[1] & 0xff00) << 16);

((uint32_t *)tmd)[2] = (uint32_t)xda[3] << 16;

((uint32_t *)tmd)[3] = 0;

}

else if (RT_LIKELY(BCR_SWSTYLE(pThis) != 3))

{

PDMDevHlpPhysRead(pDevIns, addr+7, &ownbyte, 1);

if (!(ownbyte & 0x80) && fRetIfNotOwn)

return false;

PDMDevHlpPhysRead(pDevIns, addr, (void*)tmd, 16);

}

else

{

uint32_t xda[4];

PDMDevHlpPhysRead(pDevIns, addr+7, &ownbyte, 1);

if (!(ownbyte & 0x80) && fRetIfNotOwn)

return false;

PDMDevHlpPhysRead(pDevIns, addr, (void*)&xda[0], sizeof(xda));

((uint32_t *)tmd)[0] = xda[2];

((uint32_t *)tmd)[1] = xda[1];

((uint32_t *)tmd)[2] = xda[0];

((uint32_t *)tmd)[3] = xda[3];

}

/* Double check the own bit; guest drivers might be buggy and lock prefixes in the recompiler are ignored by other threads. */

#ifdef DEBUG

if (tmd->tmd1.own == 1 && !(ownbyte & 0x80))

Log(("pcnetTmdLoad: own bit flipped while reading!!\n"));

#endif

if (!(ownbyte & 0x80))

tmd->tmd1.own = 0;

return !!tmd->tmd1.own;

}

DECLINLINE(void) pcnetTmdStorePassHost(PCNetState *pThis, TMD *tmd, RTGCPHYS32 addr)

{

STAM_PROFILE_ADV_START(&pThis->CTXSUFF(StatTmdStore), a);

PPDMDEVINS pDevIns = PCNETSTATE_2_DEVINS(pThis);

if (pThis->fPrivIfEnabled)

{

/* RX/TX descriptors shared between host and guest => direct copy */

uint8_t *pv = (uint8_t*)pThis->CTX_SUFF(pSharedMMIO)

+ (addr - pThis->GCTDRA)

+ pThis->CTX_SUFF(pSharedMMIO)->V.V1.offTxDescriptors;

memcpy(pv, tmd, 16);

pv[7] &= ~0x80;

}

else if (RT_UNLIKELY(BCR_SWSTYLE(pThis) == 0))

{

uint16_t xda[4];

xda[0] = ((uint32_t *)tmd)[0] & 0xffff;

xda[1] = ((((uint32_t *)tmd)[0] >> 16) & 0xff) | ((((uint32_t *)tmd)[1]>>16) & 0xff00);

xda[2] = ((uint32_t *)tmd)[1] & 0xffff;

xda[3] = ((uint32_t *)tmd)[2] >> 16;

xda[1] |= 0x8000;

PDMDevHlpPhysWrite(pDevIns, addr, (void*)&xda[0], sizeof(xda));

xda[1] &= ~0x8000;

PDMDevHlpPhysWrite(pDevIns, addr+3, (uint8_t*)xda + 3, 1);

}

else if (RT_LIKELY(BCR_SWSTYLE(pThis) != 3))

{

((uint32_t*)tmd)[1] |= 0x80000000;

PDMDevHlpPhysWrite(pDevIns, addr, (void*)tmd, 16);

((uint32_t*)tmd)[1] &= ~0x80000000;

PDMDevHlpPhysWrite(pDevIns, addr+7, (uint8_t*)tmd + 7, 1);

}

else

{

uint32_t xda[4];

xda[0] = ((uint32_t *)tmd)[2];

xda[1] = ((uint32_t *)tmd)[1];

xda[2] = ((uint32_t *)tmd)[0];

xda[3] = ((uint32_t *)tmd)[3];

xda[1] |= 0x80000000;

PDMDevHlpPhysWrite(pDevIns, addr, (void*)&xda[0], sizeof(xda));

xda[1] &= ~0x80000000;

PDMDevHlpPhysWrite(pDevIns, addr+7, (uint8_t*)xda + 7, 1);

}

STAM_PROFILE_ADV_STOP(&pThis->CTXSUFF(StatTmdStore), a);

}

DECLINLINE(int) pcnetRmdLoad(PCNetState *pThis, RMD *rmd, RTGCPHYS32 addr, bool fRetIfNotOwn)

{

PPDMDEVINS pDevIns = PCNETSTATE_2_DEVINS(pThis);

uint8_t ownbyte;

if (pThis->fPrivIfEnabled)

{

/* RX/TX descriptors shared between host and guest => direct copy */

uint8_t *pb = (uint8_t*)pThis->CTX_SUFF(pSharedMMIO)

+ (addr - pThis->GCRDRA)

+ pThis->CTX_SUFF(pSharedMMIO)->V.V1.offRxDescriptors;

if (!(pb[7] & 0x80) && fRetIfNotOwn)

return false;

memcpy(rmd, pb, 16);

return true;

}

else if (RT_UNLIKELY(BCR_SWSTYLE(pThis) == 0))

{

uint16_t rda[4];

PDMDevHlpPhysRead(pDevIns, addr+3, &ownbyte, 1);

if (!(ownbyte & 0x80) && fRetIfNotOwn)

return false;

PDMDevHlpPhysRead(pDevIns, addr, (void*)&rda[0], sizeof(rda));

((uint32_t *)rmd)[0] = (uint32_t)rda[0] | ((rda[1] & 0x00ff) << 16);

((uint32_t *)rmd)[1] = (uint32_t)rda[2] | ((rda[1] & 0xff00) << 16);

((uint32_t *)rmd)[2] = (uint32_t)rda[3];

((uint32_t *)rmd)[3] = 0;

}

else if (RT_LIKELY(BCR_SWSTYLE(pThis) != 3))

{

PDMDevHlpPhysRead(pDevIns, addr+7, &ownbyte, 1);

if (!(ownbyte & 0x80) && fRetIfNotOwn)

return false;

PDMDevHlpPhysRead(pDevIns, addr, (void*)rmd, 16);

}

else

{

uint32_t rda[4];

PDMDevHlpPhysRead(pDevIns, addr+7, &ownbyte, 1);

if (!(ownbyte & 0x80) && fRetIfNotOwn)

return false;

PDMDevHlpPhysRead(pDevIns, addr, (void*)&rda[0], sizeof(rda));

((uint32_t *)rmd)[0] = rda[2];

((uint32_t *)rmd)[1] = rda[1];

((uint32_t *)rmd)[2] = rda[0];

((uint32_t *)rmd)[3] = rda[3];

}

/* Double check the own bit; guest drivers might be buggy and lock prefixes in the recompiler are ignored by other threads. */

#ifdef DEBUG

if (rmd->rmd1.own == 1 && !(ownbyte & 0x80))

Log(("pcnetRmdLoad: own bit flipped while reading!!\n"));

#endif

if (!(ownbyte & 0x80))

rmd->rmd1.own = 0;

return !!rmd->rmd1.own;

}

#ifdef IN_RING3

DECLINLINE(void) pcnetRmdStorePassHost(PCNetState *pThis, RMD *rmd, RTGCPHYS32 addr)

{

PPDMDEVINS pDevIns = PCNETSTATE_2_DEVINS(pThis);

if (pThis->fPrivIfEnabled)

{

/* RX/TX descriptors shared between host and guest => direct copy */

uint8_t *pv = (uint8_t*)pThis->CTX_SUFF(pSharedMMIO)

+ (addr - pThis->GCRDRA)

+ pThis->CTX_SUFF(pSharedMMIO)->V.V1.offRxDescriptors;

memcpy(pv, rmd, 16);

pv[7] &= ~0x80;

}

else if (RT_UNLIKELY(BCR_SWSTYLE(pThis) == 0))

{

uint16_t rda[4];

rda[0] = ((uint32_t *)rmd)[0] & 0xffff;

rda[1] = ((((uint32_t *)rmd)[0]>>16) & 0xff) | ((((uint32_t *)rmd)[1]>>16) & 0xff00);

rda[2] = ((uint32_t *)rmd)[1] & 0xffff;

rda[3] = ((uint32_t *)rmd)[2] & 0xffff;

rda[1] |= 0x8000;

PDMDevHlpPhysWrite(pDevIns, addr, (void*)&rda[0], sizeof(rda));

rda[1] &= ~0x8000;

PDMDevHlpPhysWrite(pDevIns, addr+3, (uint8_t*)rda + 3, 1);

}

else if (RT_LIKELY(BCR_SWSTYLE(pThis) != 3))

{

((uint32_t*)rmd)[1] |= 0x80000000;

PDMDevHlpPhysWrite(pDevIns, addr, (void*)rmd, 16);

((uint32_t*)rmd)[1] &= ~0x80000000;

PDMDevHlpPhysWrite(pDevIns, addr+7, (uint8_t*)rmd + 7, 1);

}

else

{

uint32_t rda[4];

rda[0] = ((uint32_t *)rmd)[2];

rda[1] = ((uint32_t *)rmd)[1];

rda[2] = ((uint32_t *)rmd)[0];

rda[3] = ((uint32_t *)rmd)[3];

rda[1] |= 0x80000000;

PDMDevHlpPhysWrite(pDevIns, addr, (void*)&rda[0], sizeof(rda));

rda[1] &= ~0x80000000;

PDMDevHlpPhysWrite(pDevIns, addr+7, (uint8_t*)rda + 7, 1);

}

}

static void pcnetDescTouch(PCNetState *pThis, RTGCPHYS32 addr)

{

PPDMDEVINS pDevIns = PCNETSTATE_2_DEVINS(pThis);

if (!pThis->fPrivIfEnabled)

{

uint8_t aBuf[16];

size_t cbDesc;

if (RT_UNLIKELY(BCR_SWSTYLE(pThis) == 0))

cbDesc = 8;

else

cbDesc = 16;

PDMDevHlpPhysRead(pDevIns, addr, aBuf, cbDesc);

PDMDevHlpPhysWrite(pDevIns, addr, aBuf, cbDesc);

}

}

#endif /* IN_RING3 */

#define IS_RMD_BAD(rmd) ((rmd).rmd1.ones != 15 || (rmd).rmd2.zeros != 0)

#define CARD_IS_OWNER(desc) (((desc) & 0x8000))

#define HOST_IS_OWNER(desc) (!((desc) & 0x8000))

#ifndef ETHER_IS_MULTICAST /* Net/Open BSD macro it seems */

#define ETHER_IS_MULTICAST(a) ((*(uint8_t *)(a)) & 1)

#endif

#define ETHER_ADDR_LEN ETH_ALEN

#define ETH_ALEN 6

#pragma pack(1)

struct ether_header /** @todo Use RTNETETHERHDR */

{

uint8_t ether_dhost[ETH_ALEN]; /**< destination ethernet address */

uint8_t ether_shost[ETH_ALEN]; /**< source ethernet address */

uint16_t ether_type; /**< packet type ID field */

};

#pragma pack()

#define PRINT_PKTHDR(BUF) do { \

struct ether_header *hdr = (struct ether_header *)(BUF); \

Log(("#%d packet dhost=%02x:%02x:%02x:%02x:%02x:%02x, " \

"shost=%02x:%02x:%02x:%02x:%02x:%02x, " \

"type=%#06x (bcast=%d)\n", PCNET_INST_NR, \

hdr->ether_dhost[0],hdr->ether_dhost[1],hdr->ether_dhost[2], \

hdr->ether_dhost[3],hdr->ether_dhost[4],hdr->ether_dhost[5], \

hdr->ether_shost[0],hdr->ether_shost[1],hdr->ether_shost[2], \

hdr->ether_shost[3],hdr->ether_shost[4],hdr->ether_shost[5], \

htons(hdr->ether_type), \

!!ETHER_IS_MULTICAST(hdr->ether_dhost))); \

} while (0)

#ifdef IN_RING3

static void pcnetInitSharedMemory(PCNetState *pThis)

{

/* Clear the entire block for pcnetReset usage. */

memset(pThis->pSharedMMIOR3, 0, PCNET_GUEST_SHARED_MEMORY_SIZE);

pThis->pSharedMMIOR3->u32Version = PCNET_GUEST_INTERFACE_VERSION;

uint32_t off = 2048; /* Leave some space for more fields within the header */

/*

pThis->pSharedMMIOR3->V.V1.offTxDescriptors = off;

off = RT_ALIGN(off + PCNET_GUEST_TX_DESCRIPTOR_SIZE * PCNET_GUEST_MAX_TX_DESCRIPTORS, 32);

pThis->pSharedMMIOR3->V.V1.offRxDescriptors = off;

off = RT_ALIGN(off + PCNET_GUEST_RX_DESCRIPTOR_SIZE * PCNET_GUEST_MAX_RX_DESCRIPTORS, 32);

/* Make sure all the descriptors are mapped into HMA space (and later ring-0). The 8192

AssertRelease(off <= 8192);

/*

#if 0

/* Don't allocate TX buffers since Windows guests cannot use it */

pThis->pSharedMMIOR3->V.V1.offTxBuffers = off;

off = RT_ALIGN(off + PCNET_GUEST_NIC_BUFFER_SIZE * PCNET_GUEST_MAX_TX_DESCRIPTORS, 32);

#endif

pThis->pSharedMMIOR3->V.V1.offRxBuffers = off;

pThis->pSharedMMIOR3->fFlags = PCNET_GUEST_FLAGS_ADMIT_HOST;

off = RT_ALIGN(off + PCNET_GUEST_NIC_BUFFER_SIZE * PCNET_GUEST_MAX_RX_DESCRIPTORS, 32);

AssertRelease(off <= PCNET_GUEST_SHARED_MEMORY_SIZE);

/* Update the header with the final size. */

pThis->pSharedMMIOR3->cbUsed = off;

}

#define MULTICAST_FILTER_LEN 8

DECLINLINE(uint32_t) lnc_mchash(const uint8_t *ether_addr)

{

#define LNC_POLYNOMIAL 0xEDB88320UL

uint32_t crc = 0xFFFFFFFF;

int idx, bit;

uint8_t data;

for (idx = 0; idx < ETHER_ADDR_LEN; idx++)

{

for (data = *ether_addr++, bit = 0; bit < MULTICAST_FILTER_LEN; bit++)

{

crc = (crc >> 1) ^ (((crc ^ data) & 1) ? LNC_POLYNOMIAL : 0);

data >>= 1;

}

}

return crc;

#undef LNC_POLYNOMIAL

}

#define CRC(crc, ch) (crc = (crc >> 8) ^ crctab[(crc ^ (ch)) & 0xff])

static const uint32_t crctab[256] =

{

0x00000000, 0x77073096, 0xee0e612c, 0x990951ba,

0x076dc419, 0x706af48f, 0xe963a535, 0x9e6495a3,

0x0edb8832, 0x79dcb8a4, 0xe0d5e91e, 0x97d2d988,

0x09b64c2b, 0x7eb17cbd, 0xe7b82d07, 0x90bf1d91,

0x1db71064, 0x6ab020f2, 0xf3b97148, 0x84be41de,

0x1adad47d, 0x6ddde4eb, 0xf4d4b551, 0x83d385c7,

0x136c9856, 0x646ba8c0, 0xfd62f97a, 0x8a65c9ec,

0x14015c4f, 0x63066cd9, 0xfa0f3d63, 0x8d080df5,

0x3b6e20c8, 0x4c69105e, 0xd56041e4, 0xa2677172,

0x3c03e4d1, 0x4b04d447, 0xd20d85fd, 0xa50ab56b,

0x35b5a8fa, 0x42b2986c, 0xdbbbc9d6, 0xacbcf940,

0x32d86ce3, 0x45df5c75, 0xdcd60dcf, 0xabd13d59,

0x26d930ac, 0x51de003a, 0xc8d75180, 0xbfd06116,

0x21b4f4b5, 0x56b3c423, 0xcfba9599, 0xb8bda50f,

0x2802b89e, 0x5f058808, 0xc60cd9b2, 0xb10be924,

0x2f6f7c87, 0x58684c11, 0xc1611dab, 0xb6662d3d,

0x76dc4190, 0x01db7106, 0x98d220bc, 0xefd5102a,

0x71b18589, 0x06b6b51f, 0x9fbfe4a5, 0xe8b8d433,

0x7807c9a2, 0x0f00f934, 0x9609a88e, 0xe10e9818,

0x7f6a0dbb, 0x086d3d2d, 0x91646c97, 0xe6635c01,

0x6b6b51f4, 0x1c6c6162, 0x856530d8, 0xf262004e,

0x6c0695ed, 0x1b01a57b, 0x8208f4c1, 0xf50fc457,

0x65b0d9c6, 0x12b7e950, 0x8bbeb8ea, 0xfcb9887c,

0x62dd1ddf, 0x15da2d49, 0x8cd37cf3, 0xfbd44c65,

0x4db26158, 0x3ab551ce, 0xa3bc0074, 0xd4bb30e2,

0x4adfa541, 0x3dd895d7, 0xa4d1c46d, 0xd3d6f4fb,

0x4369e96a, 0x346ed9fc, 0xad678846, 0xda60b8d0,

0x44042d73, 0x33031de5, 0xaa0a4c5f, 0xdd0d7cc9,

0x5005713c, 0x270241aa, 0xbe0b1010, 0xc90c2086,

0x5768b525, 0x206f85b3, 0xb966d409, 0xce61e49f,

0x5edef90e, 0x29d9c998, 0xb0d09822, 0xc7d7a8b4,

0x59b33d17, 0x2eb40d81, 0xb7bd5c3b, 0xc0ba6cad,

0xedb88320, 0x9abfb3b6, 0x03b6e20c, 0x74b1d29a,

0xead54739, 0x9dd277af, 0x04db2615, 0x73dc1683,

0xe3630b12, 0x94643b84, 0x0d6d6a3e, 0x7a6a5aa8,

0xe40ecf0b, 0x9309ff9d, 0x0a00ae27, 0x7d079eb1,

0xf00f9344, 0x8708a3d2, 0x1e01f268, 0x6906c2fe,

0xf762575d, 0x806567cb, 0x196c3671, 0x6e6b06e7,

0xfed41b76, 0x89d32be0, 0x10da7a5a, 0x67dd4acc,

0xf9b9df6f, 0x8ebeeff9, 0x17b7be43, 0x60b08ed5,

0xd6d6a3e8, 0xa1d1937e, 0x38d8c2c4, 0x4fdff252,

0xd1bb67f1, 0xa6bc5767, 0x3fb506dd, 0x48b2364b,

0xd80d2bda, 0xaf0a1b4c, 0x36034af6, 0x41047a60,

0xdf60efc3, 0xa867df55, 0x316e8eef, 0x4669be79,

0xcb61b38c, 0xbc66831a, 0x256fd2a0, 0x5268e236,

0xcc0c7795, 0xbb0b4703, 0x220216b9, 0x5505262f,

0xc5ba3bbe, 0xb2bd0b28, 0x2bb45a92, 0x5cb36a04,

0xc2d7ffa7, 0xb5d0cf31, 0x2cd99e8b, 0x5bdeae1d,

0x9b64c2b0, 0xec63f226, 0x756aa39c, 0x026d930a,

0x9c0906a9, 0xeb0e363f, 0x72076785, 0x05005713,

0x95bf4a82, 0xe2b87a14, 0x7bb12bae, 0x0cb61b38,

0x92d28e9b, 0xe5d5be0d, 0x7cdcefb7, 0x0bdbdf21,

0x86d3d2d4, 0xf1d4e242, 0x68ddb3f8, 0x1fda836e,

0x81be16cd, 0xf6b9265b, 0x6fb077e1, 0x18b74777,

0x88085ae6, 0xff0f6a70, 0x66063bca, 0x11010b5c,

0x8f659eff, 0xf862ae69, 0x616bffd3, 0x166ccf45,

0xa00ae278, 0xd70dd2ee, 0x4e048354, 0x3903b3c2,

0xa7672661, 0xd06016f7, 0x4969474d, 0x3e6e77db,

0xaed16a4a, 0xd9d65adc, 0x40df0b66, 0x37d83bf0,

0xa9bcae53, 0xdebb9ec5, 0x47b2cf7f, 0x30b5ffe9,

0xbdbdf21c, 0xcabac28a, 0x53b39330, 0x24b4a3a6,

0xbad03605, 0xcdd70693, 0x54de5729, 0x23d967bf,

0xb3667a2e, 0xc4614ab8, 0x5d681b02, 0x2a6f2b94,

0xb40bbe37, 0xc30c8ea1, 0x5a05df1b, 0x2d02ef8d,

};

DECLINLINE(int) padr_match(PCNetState *pThis, const uint8_t *buf, size_t size)

{

struct ether_header *hdr = (struct ether_header *)buf;

int result;

#if (defined(RT_ARCH_X86) || defined(RT_ARCH_AMD64)) && !defined(PCNET_DEBUG_MATCH)

result = !CSR_DRCVPA(pThis) && !memcmp(hdr->ether_dhost, pThis->aCSR + 12, 6);

#else

uint8_t padr[6];

padr[0] = pThis->aCSR[12] & 0xff;

padr[1] = pThis->aCSR[12] >> 8;

padr[2] = pThis->aCSR[13] & 0xff;

padr[3] = pThis->aCSR[13] >> 8;

padr[4] = pThis->aCSR[14] & 0xff;

padr[5] = pThis->aCSR[14] >> 8;

result = !CSR_DRCVPA(pThis) && !memcmp(hdr->ether_dhost, padr, 6);

#endif

#ifdef PCNET_DEBUG_MATCH

Log(("#%d packet dhost=%02x:%02x:%02x:%02x:%02x:%02x, "

"padr=%02x:%02x:%02x:%02x:%02x:%02x => %d\n", PCNET_INST_NR,

hdr->ether_dhost[0],hdr->ether_dhost[1],hdr->ether_dhost[2],

hdr->ether_dhost[3],hdr->ether_dhost[4],hdr->ether_dhost[5],

padr[0],padr[1],padr[2],padr[3],padr[4],padr[5], result));

#endif

return result;

}

DECLINLINE(int) padr_bcast(PCNetState *pThis, const uint8_t *buf, size_t size)

{

static uint8_t aBCAST[6] = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff };

struct ether_header *hdr = (struct ether_header *)buf;

int result = !CSR_DRCVBC(pThis) && !memcmp(hdr->ether_dhost, aBCAST, 6);

#ifdef PCNET_DEBUG_MATCH

Log(("#%d padr_bcast result=%d\n", PCNET_INST_NR, result));

#endif

return result;

}

static int ladr_match(PCNetState *pThis, const uint8_t *buf, size_t size)

{

struct ether_header *hdr = (struct ether_header *)buf;

if (RT_UNLIKELY(hdr->ether_dhost[0] & 0x01) && ((uint64_t *)&pThis->aCSR[8])[0] != 0LL)

{

int index;

#if defined(RT_ARCH_X86) || defined(RT_ARCH_AMD64)

index = lnc_mchash(hdr->ether_dhost) >> 26;

return ((uint8_t*)(pThis->aCSR + 8))[index >> 3] & (1 << (index & 7));

#else

uint8_t ladr[8];

ladr[0] = pThis->aCSR[8] & 0xff;

ladr[1] = pThis->aCSR[8] >> 8;

ladr[2] = pThis->aCSR[9] & 0xff;

ladr[3] = pThis->aCSR[9] >> 8;

ladr[4] = pThis->aCSR[10] & 0xff;

ladr[5] = pThis->aCSR[10] >> 8;

ladr[6] = pThis->aCSR[11] & 0xff;

ladr[7] = pThis->aCSR[11] >> 8;

index = lnc_mchash(hdr->ether_dhost) >> 26;

return (ladr[index >> 3] & (1 << (index & 7)));

#endif

}

return 0;

}

#endif /* IN_RING3 */

DECLINLINE(RTGCPHYS32) pcnetRdraAddr(PCNetState *pThis, int idx)

{

return pThis->GCRDRA + ((CSR_RCVRL(pThis) - idx) << pThis->iLog2DescSize);

}

DECLINLINE(RTGCPHYS32) pcnetTdraAddr(PCNetState *pThis, int idx)

{

return pThis->GCTDRA + ((CSR_XMTRL(pThis) - idx) << pThis->iLog2DescSize);

}

PDMBOTHCBDECL(int) pcnetIOPortRead(PPDMDEVINS pDevIns, void *pvUser,

RTIOPORT Port, uint32_t *pu32, unsigned cb);

PDMBOTHCBDECL(int) pcnetIOPortWrite(PPDMDEVINS pDevIns, void *pvUser,

RTIOPORT Port, uint32_t u32, unsigned cb);

PDMBOTHCBDECL(int) pcnetIOPortAPromWrite(PPDMDEVINS pDevIns, void *pvUser,

RTIOPORT Port, uint32_t u32, unsigned cb);

PDMBOTHCBDECL(int) pcnetIOPortAPromRead(PPDMDEVINS pDevIns, void *pvUser,

RTIOPORT Port, uint32_t *pu32, unsigned cb);

PDMBOTHCBDECL(int) pcnetMMIORead(PPDMDEVINS pDevIns, void *pvUser,

RTGCPHYS GCPhysAddr, void *pv, unsigned cb);

PDMBOTHCBDECL(int) pcnetMMIOWrite(PPDMDEVINS pDevIns, void *pvUser,

RTGCPHYS GCPhysAddr, void *pv, unsigned cb);

#ifndef IN_RING3

DECLEXPORT(int) pcnetHandleRingWrite(PVM pVM, RTGCUINT uErrorCode, PCPUMCTXCORE pRegFrame,

RTGCPTR pvFault, RTGCPHYS GCPhysFault, void *pvUser);

#endif

#undef htonl

#define htonl(x) ASMByteSwapU32(x)

#undef htons

#define htons(x) ( (((x) & 0xff00) >> 8) | (((x) & 0x00ff) << 8) )

static void pcnetPollRxTx(PCNetState *pThis);

static void pcnetPollTimer(PCNetState *pThis);

static void pcnetUpdateIrq(PCNetState *pThis);

static uint32_t pcnetBCRReadU16(PCNetState *pThis, uint32_t u32RAP);

static int pcnetBCRWriteU16(PCNetState *pThis, uint32_t u32RAP, uint32_t val);

#ifdef PCNET_NO_POLLING

# ifndef IN_RING3

DECLEXPORT(int) pcnetHandleRingWrite(PVM pVM, RTGCUINT uErrorCode, PCPUMCTXCORE pRegFrame,

RTGCPTR pvFault, RTGCPHYS GCPhysFault, void *pvUser)

{

PCNetState *pThis = (PCNetState *)pvUser;

Log(("#%d pcnetHandleRingWriteGC: write to %#010x\n", PCNET_INST_NR, GCPhysFault));

uint32_t cb;

int rc = CTXALLSUFF(pThis->pfnEMInterpretInstruction)(pVM, pRegFrame, pvFault, &cb);

if (RT_SUCCESS(rc) && cb)

{

if ( (GCPhysFault >= pThis->GCTDRA && GCPhysFault + cb < pcnetTdraAddr(pThis, 0))

#ifdef PCNET_MONITOR_RECEIVE_RING

|| (GCPhysFault >= pThis->GCRDRA && GCPhysFault + cb < pcnetRdraAddr(pThis, 0))

#endif

)

{

uint32_t offsetTDRA = (GCPhysFault - pThis->GCTDRA);

int rc = PDMCritSectEnter(&pThis->CritSect, VERR_SEM_BUSY);

if (RT_SUCCESS(rc))

{

STAM_COUNTER_INC(&CTXALLSUFF(pThis->StatRingWrite)); ;

/* Check if we can do something now */

pcnetPollRxTx(pThis);

pcnetUpdateIrq(pThis);

PDMCritSectLeave(&pThis->CritSect);

return VINF_SUCCESS;

}

}

else

{

STAM_COUNTER_INC(&CTXALLSUFF(pThis->StatRingWriteOutside)); ;

return VINF_SUCCESS; /* outside of the ring range */

}

}

STAM_COUNTER_INC(&CTXALLSUFF(pThis->StatRingWriteFailed)); ;

return VINF_IOM_HC_MMIO_WRITE; /* handle in ring3 */

}

# else /* IN_RING3 */

static DECLCALLBACK(int) pcnetHandleRingWrite(PVM pVM, RTGCPHYS GCPhys, void *pvPhys, void *pvBuf,

size_t cbBuf, PGMACCESSTYPE enmAccessType, void *pvUser)

{

PPDMDEVINS pDevIns = (PPDMDEVINS)pvUser;

PCNetState *pThis = PDMINS_2_DATA(pDevIns, PCNetState *);

Log(("#%d pcnetHandleRingWrite: write to %#010x\n", PCNET_INST_NR, GCPhys));

#ifdef VBOX_WITH_STATISTICS

STAM_COUNTER_INC(&CTXSUFF(pThis->StatRingWrite));

if (GCPhys >= pThis->GCRDRA && GCPhys < pcnetRdraAddr(pThis, 0))

STAM_COUNTER_INC(&pThis->StatRCVRingWrite);

else if (GCPhys >= pThis->GCTDRA && GCPhys < pcnetTdraAddr(pThis, 0))

STAM_COUNTER_INC(&pThis->StatTXRingWrite);

#endif

/* Perform the actual write */

memcpy((char *)pvPhys, pvBuf, cbBuf);

/* Writes done by our code don't require polling of course */

if (PDMCritSectIsOwner(&pThis->CritSect) == false)

{

if ( (GCPhys >= pThis->GCTDRA && GCPhys + cbBuf < pcnetTdraAddr(pThis, 0))

#ifdef PCNET_MONITOR_RECEIVE_RING

|| (GCPhys >= pThis->GCRDRA && GCPhys + cbBuf < pcnetRdraAddr(pThis, 0))

#endif

)

{

int rc = PDMCritSectEnter(&pThis->CritSect, VERR_SEM_BUSY);

AssertReleaseRC(rc);

/* Check if we can do something now */

pcnetPollRxTx(pThis);

pcnetUpdateIrq(pThis);

PDMCritSectLeave(&pThis->CritSect);

}

}

return VINF_SUCCESS;

}

# endif /* !IN_RING3 */

#endif /* PCNET_NO_POLLING */

static void pcnetSoftReset(PCNetState *pThis)

{

Log(("#%d pcnetSoftReset:\n", PCNET_INST_NR));

pThis->u32Lnkst = 0x40;

pThis->GCRDRA = 0;

pThis->GCTDRA = 0;

pThis->u32RAP = 0;

pThis->aCSR[0] = 0x0004;

pThis->aCSR[3] = 0x0000;

pThis->aCSR[4] = 0x0115;

pThis->aCSR[5] = 0x0000;

pThis->aCSR[6] = 0x0000;

pThis->aCSR[8] = 0;

pThis->aCSR[9] = 0;

pThis->aCSR[10] = 0;

pThis->aCSR[11] = 0;

pThis->aCSR[12] = RT_LE2H_U16(((uint16_t *)&pThis->aPROM[0])[0]);

pThis->aCSR[13] = RT_LE2H_U16(((uint16_t *)&pThis->aPROM[0])[1]);

pThis->aCSR[14] = RT_LE2H_U16(((uint16_t *)&pThis->aPROM[0])[2]);

pThis->aCSR[15] &= 0x21c4;

CSR_RCVRC(pThis) = 1;

CSR_XMTRC(pThis) = 1;

CSR_RCVRL(pThis) = 1;

CSR_XMTRL(pThis) = 1;

pThis->aCSR[80] = 0x1410;

pThis->aCSR[88] = pThis->fAm79C973 ? CSR_VERSION_LOW_79C973 : CSR_VERSION_LOW_79C970A;

pThis->aCSR[89] = CSR_VERSION_HIGH;

pThis->aCSR[94] = 0x0000;

pThis->aCSR[100] = 0x0200;

pThis->aCSR[103] = 0x0105;

pThis->aCSR[103] = 0x0105;

CSR_MISSC(pThis) = 0;

pThis->aCSR[114] = 0x0000;

pThis->aCSR[122] = 0x0000;

pThis->aCSR[124] = 0x0000;

}

static void pcnetUpdateIrq(PCNetState *pThis)

{

register int iISR = 0;

register uint16_t csr0 = pThis->aCSR[0];

csr0 &= ~0x0080; /* clear INTR */

STAM_PROFILE_ADV_START(&pThis->StatInterrupt, a);

/* Linux guests set csr4=0x0915

#if 1

if ( ( (csr0 & ~pThis->aCSR[3]) & 0x5f00)

|| (((pThis->aCSR[4]>>1) & ~pThis->aCSR[4]) & 0x0115)

|| (((pThis->aCSR[5]>>1) & pThis->aCSR[5]) & 0x0048))

#else

if ( ( !(pThis->aCSR[3] & 0x4000) && !!(csr0 & 0x4000)) /* BABL */

||( !(pThis->aCSR[3] & 0x1000) && !!(csr0 & 0x1000)) /* MISS */

||( !(pThis->aCSR[3] & 0x0100) && !!(csr0 & 0x0100)) /* IDON */

||( !(pThis->aCSR[3] & 0x0200) && !!(csr0 & 0x0200)) /* TINT */

||( !(pThis->aCSR[3] & 0x0400) && !!(csr0 & 0x0400)) /* RINT */

||( !(pThis->aCSR[3] & 0x0800) && !!(csr0 & 0x0800)) /* MERR */

||( !(pThis->aCSR[4] & 0x0001) && !!(pThis->aCSR[4] & 0x0002)) /* JAB */

||( !(pThis->aCSR[4] & 0x0004) && !!(pThis->aCSR[4] & 0x0008)) /* TXSTRT */

||( !(pThis->aCSR[4] & 0x0010) && !!(pThis->aCSR[4] & 0x0020)) /* RCVO */

||( !(pThis->aCSR[4] & 0x0100) && !!(pThis->aCSR[4] & 0x0200)) /* MFCO */

||(!!(pThis->aCSR[5] & 0x0040) && !!(pThis->aCSR[5] & 0x0080)) /* EXDINT */

||(!!(pThis->aCSR[5] & 0x0008) && !!(pThis->aCSR[5] & 0x0010)) /* MPINT */)

#endif

{

iISR = !!(csr0 & 0x0040); /* CSR_INEA */

csr0 |= 0x0080; /* set INTR */

}

#ifdef VBOX

if (pThis->aCSR[4] & 0x0080) /* UINTCMD */

{

pThis->aCSR[4] &= ~0x0080; /* clear UINTCMD */

pThis->aCSR[4] |= 0x0040; /* set UINT */

Log(("#%d user int\n", PCNET_INST_NR));

}

if (pThis->aCSR[4] & csr0 & 0x0040 /* CSR_INEA */)

{

csr0 |= 0x0080; /* set INTR */

iISR = 1;

}

#else /* !VBOX */

if (!!(pThis->aCSR[4] & 0x0080) && CSR_INEA(pThis)) /* UINTCMD */

{

pThis->aCSR[4] &= ~0x0080;

pThis->aCSR[4] |= 0x0040; /* set UINT */

csr0 |= 0x0080; /* set INTR */

iISR = 1;

Log(("#%d user int\n", PCNET_INST_NR));

}

#endif /* !VBOX */

#if 1

if (((pThis->aCSR[5]>>1) & pThis->aCSR[5]) & 0x0500)

#else

if ( (!!(pThis->aCSR[5] & 0x0400) && !!(pThis->aCSR[5] & 0x0800)) /* SINT */

||(!!(pThis->aCSR[5] & 0x0100) && !!(pThis->aCSR[5] & 0x0200)) /* SLPINT */)

#endif

{

iISR = 1;

csr0 |= 0x0080; /* INTR */

}

if ((pThis->aCSR[7] & 0x0C00) == 0x0C00) /* STINT + STINTE */

iISR = 1;

pThis->aCSR[0] = csr0;

Log2(("#%d set irq iISR=%d\n", PCNET_INST_NR, iISR));

/* normal path is to _not_ change the IRQ status */

if (RT_UNLIKELY(iISR != pThis->iISR))

{

Log(("#%d INTA=%d\n", PCNET_INST_NR, iISR));

PDMDevHlpPCISetIrqNoWait(PCNETSTATE_2_DEVINS(pThis), 0, iISR);

pThis->iISR = iISR;

}

STAM_PROFILE_ADV_STOP(&pThis->StatInterrupt, a);

}

static void pcnetEnablePrivateIf(PCNetState *pThis)

{

bool fPrivIfEnabled = pThis->pSharedMMIOR3

&& !!(pThis->CTX_SUFF(pSharedMMIO)->fFlags & PCNET_GUEST_FLAGS_ADMIT_GUEST);

if (fPrivIfEnabled != pThis->fPrivIfEnabled)

{

pThis->fPrivIfEnabled = fPrivIfEnabled;

LogRel(("PCNet#%d: %s private interface\n", PCNET_INST_NR, fPrivIfEnabled ? "Enabling" : "Disabling"));

}

}

#ifdef IN_RING3

#ifdef PCNET_NO_POLLING

static void pcnetUpdateRingHandlers(PCNetState *pThis)

{

PPDMDEVINS pDevIns = PCNETSTATE_2_DEVINS(pThis);

int rc;

Log(("pcnetUpdateRingHandlers TD %RX32 size %#x -> %RX32 ?size? %#x\n", pThis->TDRAPhysOld, pThis->cbTDRAOld, pThis->GCTDRA, pcnetTdraAddr(pThis, 0)));

Log(("pcnetUpdateRingHandlers RX %RX32 size %#x -> %RX32 ?size? %#x\n", pThis->RDRAPhysOld, pThis->cbRDRAOld, pThis->GCRDRA, pcnetRdraAddr(pThis, 0)));

/** @todo unregister order not correct! */

#ifdef PCNET_MONITOR_RECEIVE_RING

if (pThis->GCRDRA != pThis->RDRAPhysOld || CSR_RCVRL(pThis) != pThis->cbRDRAOld)

{

if (pThis->RDRAPhysOld != 0)

PGMHandlerPhysicalDeregister(PDMDevHlpGetVM(pDevIns),

pThis->RDRAPhysOld & ~PAGE_OFFSET_MASK);

rc = PGMR3HandlerPhysicalRegister(PDMDevHlpGetVM(pDevIns),

PGMPHYSHANDLERTYPE_PHYSICAL_WRITE,

pThis->GCRDRA & ~PAGE_OFFSET_MASK,

RT_ALIGN(pcnetRdraAddr(pThis, 0), PAGE_SIZE) - 1,

pcnetHandleRingWrite, pDevIns,

g_DevicePCNet.szR0Mod, "pcnetHandleRingWrite",

pThis->pDevInsHC->pvInstanceDataHC,

g_DevicePCNet.szRCMod, "pcnetHandleRingWrite",

pThis->pDevInsHC->pvInstanceDataRC,

"PCNet receive ring write access handler");

AssertRC(rc);

pThis->RDRAPhysOld = pThis->GCRDRA;

pThis->cbRDRAOld = pcnetRdraAddr(pThis, 0);

}

#endif /* PCNET_MONITOR_RECEIVE_RING */

#ifdef PCNET_MONITOR_RECEIVE_RING

/* 3 possibilities:

RTGCPHYS32 RDRAPageStart = pThis->GCRDRA & ~PAGE_OFFSET_MASK;

RTGCPHYS32 RDRAPageEnd = (pcnetRdraAddr(pThis, 0) - 1) & ~PAGE_OFFSET_MASK;

RTGCPHYS32 TDRAPageStart = pThis->GCTDRA & ~PAGE_OFFSET_MASK;

RTGCPHYS32 TDRAPageEnd = (pcnetTdraAddr(pThis, 0) - 1) & ~PAGE_OFFSET_MASK;

if ( RDRAPageStart > TDRAPageEnd

|| TDRAPageStart > RDRAPageEnd)

{

#endif /* PCNET_MONITOR_RECEIVE_RING */

/* 1) */

if (pThis->GCTDRA != pThis->TDRAPhysOld || CSR_XMTRL(pThis) != pThis->cbTDRAOld)

{

if (pThis->TDRAPhysOld != 0)

PGMHandlerPhysicalDeregister(PDMDevHlpGetVM(pDevIns),

pThis->TDRAPhysOld & ~PAGE_OFFSET_MASK);

rc = PGMR3HandlerPhysicalRegister(PDMDevHlpGetVM(pDevIns),

PGMPHYSHANDLERTYPE_PHYSICAL_WRITE,

pThis->GCTDRA & ~PAGE_OFFSET_MASK,

RT_ALIGN(pcnetTdraAddr(pThis, 0), PAGE_SIZE) - 1,

pcnetHandleRingWrite, pDevIns,

g_DevicePCNet.szR0Mod, "pcnetHandleRingWrite",

pThis->pDevInsHC->pvInstanceDataHC,

g_DevicePCNet.szRCMod, "pcnetHandleRingWrite",

pThis->pDevInsHC->pvInstanceDataRC,

"PCNet transmit ring write access handler");

AssertRC(rc);

pThis->TDRAPhysOld = pThis->GCTDRA;

pThis->cbTDRAOld = pcnetTdraAddr(pThis, 0);

}

#ifdef PCNET_MONITOR_RECEIVE_RING

}

else

if ( RDRAPageStart != TDRAPageStart

&& ( TDRAPageStart == RDRAPageEnd

|| TDRAPageEnd == RDRAPageStart

)

)

{

/* 3) */

AssertFailed();

}

/* else 2) */

#endif

}

#endif /* PCNET_NO_POLLING */

static void pcnetInit(PCNetState *pThis)

{

PPDMDEVINS pDevIns = PCNETSTATE_2_DEVINS(pThis);

Log(("#%d pcnetInit: init_addr=%#010x\n", PCNET_INST_NR, PHYSADDR(pThis, CSR_IADR(pThis))));

/** @todo Documentation says that RCVRL and XMTRL are stored as two's complement!

#define PCNET_INIT() do { \

PDMDevHlpPhysRead(pDevIns, PHYSADDR(pThis, CSR_IADR(pThis)), \

(uint8_t *)&initblk, sizeof(initblk)); \

pThis->aCSR[15] = RT_LE2H_U16(initblk.mode); \

CSR_RCVRL(pThis) = (initblk.rlen < 9) ? (1 << initblk.rlen) : 512; \

CSR_XMTRL(pThis) = (initblk.tlen < 9) ? (1 << initblk.tlen) : 512; \

pThis->aCSR[ 6] = (initblk.tlen << 12) | (initblk.rlen << 8); \

pThis->aCSR[ 8] = RT_LE2H_U16(initblk.ladrf1); \

pThis->aCSR[ 9] = RT_LE2H_U16(initblk.ladrf2); \

pThis->aCSR[10] = RT_LE2H_U16(initblk.ladrf3); \

pThis->aCSR[11] = RT_LE2H_U16(initblk.ladrf4); \

pThis->aCSR[12] = RT_LE2H_U16(initblk.padr1); \

pThis->aCSR[13] = RT_LE2H_U16(initblk.padr2); \

pThis->aCSR[14] = RT_LE2H_U16(initblk.padr3); \

pThis->GCRDRA = PHYSADDR(pThis, initblk.rdra); \

pThis->GCTDRA = PHYSADDR(pThis, initblk.tdra); \

} while (0)

pcnetEnablePrivateIf(pThis);

if (BCR_SSIZE32(pThis))

{

struct INITBLK32 initblk;

pThis->GCUpperPhys = 0;

PCNET_INIT();

Log(("#%d initblk.rlen=%#04x, initblk.tlen=%#04x\n",

PCNET_INST_NR, initblk.rlen, initblk.tlen));

}

else

{

struct INITBLK16 initblk;

pThis->GCUpperPhys = (0xff00 & (uint32_t)pThis->aCSR[2]) << 16;

PCNET_INIT();

Log(("#%d initblk.rlen=%#04x, initblk.tlen=%#04x\n",

PCNET_INST_NR, initblk.rlen, initblk.tlen));

}

#undef PCNET_INIT

size_t cbRxBuffers = 0;

for (int i = CSR_RCVRL(pThis); i >= 1; i--)

{

RMD rmd;

RTGCPHYS32 rdaddr = PHYSADDR(pThis, pcnetRdraAddr(pThis, i));

pcnetDescTouch(pThis, rdaddr);

/* At this time it is not guaranteed that the buffers are already initialized. */

if (pcnetRmdLoad(pThis, &rmd, rdaddr, false))

{

uint32_t cbBuf = 4096U-rmd.rmd1.bcnt;

cbRxBuffers += cbBuf;

}

}

for (int i = CSR_XMTRL(pThis); i >= 1; i--)

{

RTGCPHYS32 tdaddr = PHYSADDR(pThis, pcnetTdraAddr(pThis, i));

pcnetDescTouch(pThis, tdaddr);

}

/*

pThis->fSignalRxMiss = (cbRxBuffers == 0 || cbRxBuffers >= 32*_1K);

if (pThis->pDrv)

pThis->pDrv->pfnSetPromiscuousMode(pThis->pDrv, CSR_PROM(pThis));

CSR_RCVRC(pThis) = CSR_RCVRL(pThis);

CSR_XMTRC(pThis) = CSR_XMTRL(pThis);

#ifdef PCNET_NO_POLLING

pcnetUpdateRingHandlers(pThis);

#endif

/* Reset cached RX and TX states */

CSR_CRST(pThis) = CSR_CRBC(pThis) = CSR_NRST(pThis) = CSR_NRBC(pThis) = 0;

CSR_CXST(pThis) = CSR_CXBC(pThis) = CSR_NXST(pThis) = CSR_NXBC(pThis) = 0;

LogRel(("PCNet#%d: Init: ss32=%d GCRDRA=%#010x[%d] GCTDRA=%#010x[%d]%s\n",

PCNET_INST_NR, BCR_SSIZE32(pThis),

pThis->GCRDRA, CSR_RCVRL(pThis), pThis->GCTDRA, CSR_XMTRL(pThis),

!pThis->fSignalRxMiss ? " (CSR0_MISS disabled)" : ""));

pThis->aCSR[0] |= 0x0101; /* Initialization done */

pThis->aCSR[0] &= ~0x0004; /* clear STOP bit */

}

#endif /* IN_RING3 */

static void pcnetStart(PCNetState *pThis)

{

Log(("#%d pcnetStart:\n", PCNET_INST_NR));

if (!CSR_DTX(pThis))

pThis->aCSR[0] |= 0x0010; /* set TXON */

if (!CSR_DRX(pThis))

pThis->aCSR[0] |= 0x0020; /* set RXON */

pcnetEnablePrivateIf(pThis);

pThis->aCSR[0] &= ~0x0004; /* clear STOP bit */

pThis->aCSR[0] |= 0x0002; /* STRT */

pcnetPollTimerStart(pThis); /* start timer if it was stopped */

}

static void pcnetStop(PCNetState *pThis)

{

Log(("#%d pcnetStop:\n", PCNET_INST_NR));

pThis->aCSR[0] &= ~0x7feb;

pThis->aCSR[0] |= 0x0014;

pThis->aCSR[4] &= ~0x02c2;

pThis->aCSR[5] &= ~0x0011;

pcnetEnablePrivateIf(pThis);

pcnetPollTimer(pThis);

}

#ifdef IN_RING3

static DECLCALLBACK(void) pcnetWakeupReceive(PPDMDEVINS pDevIns)

{

PCNetState *pThis = PDMINS_2_DATA(pDevIns, PCNetState *);

STAM_COUNTER_INC(&pThis->StatRxOverflowWakeup);

if (pThis->hEventOutOfRxSpace != NIL_RTSEMEVENT)

RTSemEventSignal(pThis->hEventOutOfRxSpace);

}

static DECLCALLBACK(bool) pcnetCanRxQueueConsumer(PPDMDEVINS pDevIns, PPDMQUEUEITEMCORE pItem)

{

pcnetWakeupReceive(pDevIns);

return true;

}

#endif /* IN_RING3 */

static void pcnetRdtePoll(PCNetState *pThis, bool fSkipCurrent=false)

{

STAM_PROFILE_ADV_START(&pThis->CTXSUFF(StatRdtePoll), a);

/* assume lack of a next receive descriptor */

CSR_NRST(pThis) = 0;

if (RT_LIKELY(pThis->GCRDRA))

{

/*

RMD rmd;

int i = CSR_RCVRC(pThis);

RTGCPHYS32 addr;

if (i < 1)

i = CSR_RCVRL(pThis);

if (!fSkipCurrent)

{

addr = pcnetRdraAddr(pThis, i);

CSR_CRDA(pThis) = CSR_CRBA(pThis) = 0;

CSR_CRBC(pThis) = CSR_CRST(pThis) = 0;

if (!pcnetRmdLoad(pThis, &rmd, PHYSADDR(pThis, addr), true))

{

STAM_PROFILE_ADV_STOP(&pThis->CTXSUFF(StatRdtePoll), a);

return;

}

if (RT_LIKELY(!IS_RMD_BAD(rmd)))

{

CSR_CRDA(pThis) = addr; /* Receive Descriptor Address */

CSR_CRBA(pThis) = rmd.rmd0.rbadr; /* Receive Buffer Address */

CSR_CRBC(pThis) = rmd.rmd1.bcnt; /* Receive Byte Count */

CSR_CRST(pThis) = ((uint32_t *)&rmd)[1] >> 16; /* Receive Status */

if (pThis->fMaybeOutOfSpace)

{

#ifdef IN_RING3

pcnetWakeupReceive(PCNETSTATE_2_DEVINS(pThis));

#else

PPDMQUEUEITEMCORE pItem = PDMQueueAlloc(pThis->CTX_SUFF(pCanRxQueue));

if (pItem)

PDMQueueInsert(pThis->CTX_SUFF(pCanRxQueue), pItem);

#endif

}

}

else

{

STAM_PROFILE_ADV_STOP(&pThis->CTXSUFF(StatRdtePoll), a);

/* This is not problematic since we don't own the descriptor

if (++pThis->uCntBadRMD < 50)

LogRel(("PCNet#%d: BAD RMD ENTRIES AT %#010x (i=%d)\n",

PCNET_INST_NR, addr, i));

return;

}

}

/*

if (--i < 1)

i = CSR_RCVRL(pThis);

addr = pcnetRdraAddr(pThis, i);

CSR_NRDA(pThis) = CSR_NRBA(pThis) = 0;

CSR_NRBC(pThis) = 0;

if (!pcnetRmdLoad(pThis, &rmd, PHYSADDR(pThis, addr), true))

{

STAM_PROFILE_ADV_STOP(&pThis->CTXSUFF(StatRdtePoll), a);

return;

}

if (RT_LIKELY(!IS_RMD_BAD(rmd)))

{

CSR_NRDA(pThis) = addr; /* Receive Descriptor Address */

CSR_NRBA(pThis) = rmd.rmd0.rbadr; /* Receive Buffer Address */

CSR_NRBC(pThis) = rmd.rmd1.bcnt; /* Receive Byte Count */

CSR_NRST(pThis) = ((uint32_t *)&rmd)[1] >> 16; /* Receive Status */

}

else

{

STAM_PROFILE_ADV_STOP(&pThis->CTXSUFF(StatRdtePoll), a);

/* This is not problematic since we don't own the descriptor

if (++pThis->uCntBadRMD < 50)

LogRel(("PCNet#%d: BAD RMD ENTRIES + AT %#010x (i=%d)\n",

PCNET_INST_NR, addr, i));

return;

}

/**

}

else

{

CSR_CRDA(pThis) = CSR_CRBA(pThis) = CSR_NRDA(pThis) = CSR_NRBA(pThis) = 0;

CSR_CRBC(pThis) = CSR_NRBC(pThis) = CSR_CRST(pThis) = 0;

}

STAM_PROFILE_ADV_STOP(&pThis->CTXSUFF(StatRdtePoll), a);

}

static int pcnetTdtePoll(PCNetState *pThis, TMD *tmd)

{

STAM_PROFILE_ADV_START(&pThis->CTXSUFF(StatTdtePoll), a);

if (RT_LIKELY(pThis->GCTDRA))

{

RTGCPHYS32 cxda = pcnetTdraAddr(pThis, CSR_XMTRC(pThis));

if (!pcnetTmdLoad(pThis, tmd, PHYSADDR(pThis, cxda), true))

{

STAM_PROFILE_ADV_STOP(&pThis->CTXSUFF(StatTdtePoll), a);

return 0;

}

if (RT_UNLIKELY(tmd->tmd1.ones != 15))

{

STAM_PROFILE_ADV_STOP(&pThis->CTXSUFF(StatTdtePoll), a);

LogRel(("PCNet#%d: BAD TMD XDA=%#010x\n",

PCNET_INST_NR, PHYSADDR(pThis, cxda)));

return 0;

}

/* previous xmit descriptor */

CSR_PXDA(pThis) = CSR_CXDA(pThis);

CSR_PXBC(pThis) = CSR_CXBC(pThis);

CSR_PXST(pThis) = CSR_CXST(pThis);

/* set current trasmit decriptor. */

CSR_CXDA(pThis) = cxda;

CSR_CXBC(pThis) = tmd->tmd1.bcnt;

CSR_CXST(pThis) = ((uint32_t *)tmd)[1] >> 16;

STAM_PROFILE_ADV_STOP(&pThis->CTXSUFF(StatTdtePoll), a);

return CARD_IS_OWNER(CSR_CXST(pThis));

}

else

{

/** @todo consistency with previous receive descriptor */

CSR_CXDA(pThis) = 0;

CSR_CXBC(pThis) = CSR_CXST(pThis) = 0;

STAM_PROFILE_ADV_STOP(&pThis->CTXSUFF(StatTdtePoll), a);

return 0;

}

}

#ifdef IN_RING3

static void pcnetReceiveNoSync(PCNetState *pThis, const uint8_t *buf, size_t cbToRecv)

{

PPDMDEVINS pDevIns = PCNETSTATE_2_DEVINS(pThis);

int is_padr = 0, is_bcast = 0, is_ladr = 0;

unsigned iRxDesc;

int cbPacket;

if (RT_UNLIKELY(CSR_DRX(pThis) || CSR_STOP(pThis) || CSR_SPND(pThis) || !cbToRecv))

return;

/*

VMSTATE enmVMState = PDMDevHlpVMState(pDevIns);

if ( enmVMState != VMSTATE_RUNNING

&& enmVMState != VMSTATE_RUNNING_LS)

return;

Log(("#%d pcnetReceiveNoSync: size=%d\n", PCNET_INST_NR, cbToRecv));

/*

if ( CSR_PROM(pThis)

|| (is_padr = padr_match(pThis, buf, cbToRecv))

|| (is_bcast = padr_bcast(pThis, buf, cbToRecv))

|| (is_ladr = ladr_match(pThis, buf, cbToRecv)))

{

if (HOST_IS_OWNER(CSR_CRST(pThis)))

pcnetRdtePoll(pThis);

if (RT_UNLIKELY(HOST_IS_OWNER(CSR_CRST(pThis))))

{

/* Not owned by controller. This should not be possible as

LogRel(("PCNet#%d: no buffer: RCVRC=%d\n",

PCNET_INST_NR, CSR_RCVRC(pThis)));

/* Dump the status of all RX descriptors */

const unsigned cb = 1 << pThis->iLog2DescSize;

RTGCPHYS32 GCPhys = pThis->GCRDRA;

iRxDesc = CSR_RCVRL(pThis);

while (iRxDesc-- > 0)

{

RMD rmd;

pcnetRmdLoad(pThis, &rmd, PHYSADDR(pThis, GCPhys), false);

LogRel((" %#010x\n", rmd.rmd1));

GCPhys += cb;

}

pThis->aCSR[0] |= 0x1000; /* Set MISS flag */

CSR_MISSC(pThis)++;

}

else

{

uint8_t *src = &pThis->abRecvBuf[8];

RTGCPHYS32 crda = CSR_CRDA(pThis);

RTGCPHYS32 next_crda;

RMD rmd, next_rmd;

memcpy(src, buf, cbToRecv);

if (!CSR_ASTRP_RCV(pThis))

{

uint32_t fcs = ~0;

uint8_t *p = src;

while (cbToRecv < 60)

src[cbToRecv++] = 0;

while (p != &src[cbToRecv])

CRC(fcs, *p++);

((uint32_t *)&src[cbToRecv])[0] = htonl(fcs);

/* FCS at end of packet */

}

cbToRecv += 4;

cbPacket = (int)cbToRecv; Assert((size_t)cbPacket == cbToRecv);

#ifdef PCNET_DEBUG_MATCH

PRINT_PKTHDR(buf);

#endif

pcnetRmdLoad(pThis, &rmd, PHYSADDR(pThis, crda), false);

/*if (!CSR_LAPPEN(pThis))*/

rmd.rmd1.stp = 1;

size_t cbBuf = RT_MIN(4096 - (size_t)rmd.rmd1.bcnt, cbToRecv);

RTGCPHYS32 rbadr = PHYSADDR(pThis, rmd.rmd0.rbadr);

/* save the old value to check if it was changed as long as we didn't

iRxDesc = CSR_RCVRC(pThis);

/* We have to leave the critical section here or we risk deadlocking

PDMCritSectLeave(&pThis->CritSect);

PDMDevHlpPhysWrite(pDevIns, rbadr, src, cbBuf);

int rc = PDMCritSectEnter(&pThis->CritSect, VERR_SEM_BUSY);

AssertReleaseRC(rc);

/* RX disabled in the meantime? If so, abort RX. */

if (RT_UNLIKELY(CSR_DRX(pThis) || CSR_STOP(pThis) || CSR_SPND(pThis)))

return;

/* Was the register modified in the meantime? If so, don't touch the

if (RT_LIKELY(iRxDesc == CSR_RCVRC(pThis)))

{

if (iRxDesc-- < 2)

iRxDesc = CSR_RCVRL(pThis);

CSR_RCVRC(pThis) = iRxDesc;

}

else

iRxDesc = CSR_RCVRC(pThis);

src += cbBuf;

cbToRecv -= cbBuf;

while (cbToRecv > 0)

{

/* Read the entire next descriptor as we're likely to need it. */

next_crda = pcnetRdraAddr(pThis, iRxDesc);

/* Check next descriptor's own bit. If we don't own it, we have

if (!pcnetRmdLoad(pThis, &next_rmd, PHYSADDR(pThis, next_crda), true))

break;

/* Write back current descriptor, clear the own bit. */

pcnetRmdStorePassHost(pThis, &rmd, PHYSADDR(pThis, crda));

/* Switch to the next descriptor */

crda = next_crda;

rmd = next_rmd;

cbBuf = RT_MIN(4096 - (size_t)rmd.rmd1.bcnt, cbToRecv);

RTGCPHYS32 rbadr = PHYSADDR(pThis, rmd.rmd0.rbadr);

/* We have to leave the critical section here or we risk deadlocking

PDMCritSectLeave(&pThis->CritSect);

PDMDevHlpPhysWrite(pDevIns, rbadr, src, cbBuf);

rc = PDMCritSectEnter(&pThis->CritSect, VERR_SEM_BUSY);

AssertReleaseRC(rc);

/* RX disabled in the meantime? If so, abort RX. */

if (RT_UNLIKELY(CSR_DRX(pThis) || CSR_STOP(pThis) || CSR_SPND(pThis)))

return;

/* Was the register modified in the meantime? If so, don't touch the

if (RT_LIKELY(iRxDesc == CSR_RCVRC(pThis)))

{

if (iRxDesc-- < 2)

iRxDesc = CSR_RCVRL(pThis);

CSR_RCVRC(pThis) = iRxDesc;

}

else

iRxDesc = CSR_RCVRC(pThis);

src += cbBuf;

cbToRecv -= cbBuf;

}

if (RT_LIKELY(cbToRecv == 0))

{

rmd.rmd1.enp = 1;

rmd.rmd1.pam = !CSR_PROM(pThis) && is_padr;

rmd.rmd1.lafm = !CSR_PROM(pThis) && is_ladr;

rmd.rmd1.bam = !CSR_PROM(pThis) && is_bcast;

rmd.rmd2.mcnt = cbPacket;

STAM_REL_COUNTER_ADD(&pThis->StatReceiveBytes, cbPacket);

}

else

{

Log(("#%d: Overflow by %ubytes\n", PCNET_INST_NR, cbToRecv));

rmd.rmd1.oflo = 1;

rmd.rmd1.buff = 1;

rmd.rmd1.err = 1;

}

/* write back, clear the own bit */

pcnetRmdStorePassHost(pThis, &rmd, PHYSADDR(pThis, crda));

pThis->aCSR[0] |= 0x0400;

Log(("#%d RCVRC=%d CRDA=%#010x\n", PCNET_INST_NR,

CSR_RCVRC(pThis), PHYSADDR(pThis, CSR_CRDA(pThis))));

#ifdef PCNET_DEBUG_RMD

PRINT_RMD(&rmd);

#endif

/* guest driver is owner: force repoll of current and next RDTEs */

CSR_CRST(pThis) = 0;

}

}

/* see description of TXDPOLL:

pcnetPollRxTx(pThis);

pcnetUpdateIrq(pThis);

}

DECLINLINE(bool) pcnetIsLinkUp(PCNetState *pThis)

{

return pThis->pDrv && !pThis->fLinkTempDown && pThis->fLinkUp;

}

static DECLCALLBACK(bool) pcnetXmitQueueConsumer(PPDMDEVINS pDevIns, PPDMQUEUEITEMCORE pItem)

{

PCNetState *pThis = PDMINS_2_DATA(pDevIns, PCNetState *);

NOREF(pItem);

/* Clear counter .*/

ASMAtomicAndU32(&pThis->cPendingSends, 0);

#ifdef PCNET_QUEUE_SEND_PACKETS

int rc = PDMCritSectEnter(&pThis->CritSect, VERR_SEM_BUSY);

AssertReleaseRC(rc);

pcnetSyncTransmit(pThis);

PDMCritSectLeave(&pThis->CritSect);

#else

int rc = RTSemEventSignal(pThis->hSendEventSem);

AssertRC(rc);

#endif

return true;

}

DECLINLINE(void) pcnetXmitScrapFrame(PCNetState *pThis)

{

pThis->pvSendFrame = NULL;

pThis->cbSendFrame = 0;

}

DECLINLINE(void) pcnetXmitRead1st(PCNetState *pThis, RTGCPHYS32 GCPhysFrame, const unsigned cbFrame)

{

Assert(PDMCritSectIsOwner(&pThis->CritSect));

Assert(cbFrame < sizeof(pThis->abSendBuf));

#ifdef PCNET_QUEUE_SEND_PACKETS

AssertRelease(pThis->cXmitRingBufPending < PCNET_MAX_XMIT_SLOTS-1);

pThis->pvSendFrame = pThis->apXmitRingBuffer[pThis->iXmitRingBufProd];

#else

pThis->pvSendFrame = pThis->abSendBuf;

#endif

PDMDevHlpPhysRead(pThis->CTX_SUFF(pDevIns), GCPhysFrame, pThis->pvSendFrame, cbFrame);

pThis->cbSendFrame = cbFrame;

}

DECLINLINE(void) pcnetXmitReadMore(PCNetState *pThis, RTGCPHYS32 GCPhysFrame, const unsigned cbFrame)

{

Assert(pThis->cbSendFrame + cbFrame <= MAX_FRAME);

PDMDevHlpPhysRead(pThis->CTX_SUFF(pDevIns), GCPhysFrame, pThis->pvSendFrame + pThis->cbSendFrame, cbFrame);

pThis->cbSendFrame += cbFrame;

}

DECLINLINE(int) pcnetXmitCompleteFrame(PCNetState *pThis)

{

#ifdef PCNET_QUEUE_SEND_PACKETS

Assert(PDMCritSectIsOwner(&pThis->CritSect));

AssertRelease(pThis->cXmitRingBufPending < PCNET_MAX_XMIT_SLOTS-1);

Assert(!pThis->cbXmitRingBuffer[pThis->iXmitRingBufProd]);

pThis->cbXmitRingBuffer[pThis->iXmitRingBufProd] = (uint16_t)pThis->cbSendFrame;

pThis->iXmitRingBufProd = (pThis->iXmitRingBufProd+1) & PCNET_MAX_XMIT_SLOTS_MASK;

ASMAtomicIncS32(&pThis->cXmitRingBufPending);

int rc = RTSemEventSignal(pThis->hSendEventSem);

AssertRC(rc);

return VINF_SUCCESS;

#else

/* Don't hold the critical section while transmitting data. */

/** @note also avoids deadlocks with NAT as it can call us right back. */

PDMCritSectLeave(&pThis->CritSect);

STAM_PROFILE_ADV_START(&pThis->StatTransmitSend, a);

if (pThis->cbSendFrame > 70) /* unqualified guess */

pThis->Led.Asserted.s.fWriting = pThis->Led.Actual.s.fWriting = 1;

pThis->pDrv->pfnSend(pThis->pDrv, pThis->pvSendFrame, pThis->cbSendFrame);

STAM_REL_COUNTER_ADD(&pThis->StatTransmitBytes, pThis->cbSendFrame);

pThis->Led.Actual.s.fWriting = 0;

STAM_PROFILE_ADV_STOP(&pThis->StatTransmitSend, a);

return PDMCritSectEnter(&pThis->CritSect, VERR_SEM_BUSY);

#endif

}

static void pcnetXmitFailTMDLinkDown(PCNetState *pThis, TMD *pTmd)

{

/* make carrier error - hope this is correct. */

pThis->cLinkDownReported++;

pTmd->tmd2.lcar = pTmd->tmd1.err = 1;

pThis->aCSR[0] |= RT_BIT(15) | RT_BIT(13); /* ERR | CERR */

pThis->Led.Asserted.s.fError = pThis->Led.Actual.s.fError = 1;

Log(("#%d pcnetTransmit: Signaling send error. swstyle=%#x\n",

PCNET_INST_NR, pThis->aBCR[BCR_SWS]));

}

static void pcnetXmitFailTMDGeneric(PCNetState *pThis, TMD *pTmd)

{

/* make carrier error - hope this is correct. */

pTmd->tmd2.lcar = pTmd->tmd1.err = 1;

pThis->aCSR[0] |= RT_BIT(15) | RT_BIT(13); /* ERR | CERR */

pThis->Led.Asserted.s.fError = pThis->Led.Actual.s.fError = 1;

Log(("#%d pcnetTransmit: Signaling send error. swstyle=%#x\n",

PCNET_INST_NR, pThis->aBCR[BCR_SWS]));

}

DECLINLINE(void) pcnetXmitLoopbackFrame(PCNetState *pThis)

{

pThis->Led.Asserted.s.fReading = pThis->Led.Actual.s.fReading = 1;

if (HOST_IS_OWNER(CSR_CRST(pThis)))

pcnetRdtePoll(pThis);

Assert(pThis->pvSendFrame);

pcnetReceiveNoSync(pThis, (const uint8_t *)pThis->pvSendFrame, pThis->cbSendFrame);