Devices/Network/DevE1000Phy.h

	DevE1000Phy.h revision aaf6eb788dab09bc8c3c8576c60fabc60037a483
45e9809aff7304721fddb95654901b32195c9c7avboxsync/** $Id$ */
45e9809aff7304721fddb95654901b32195c9c7avboxsync/** @file
45e9809aff7304721fddb95654901b32195c9c7avboxsync * DevE1000Phy - Intel 82540EM Ethernet Controller Internal PHY Emulation, Header.
45e9809aff7304721fddb95654901b32195c9c7avboxsync */
45e9809aff7304721fddb95654901b32195c9c7avboxsync
45e9809aff7304721fddb95654901b32195c9c7avboxsync/*
45e9809aff7304721fddb95654901b32195c9c7avboxsync * Copyright (C) 2007 Sun Microsystems, Inc.
45e9809aff7304721fddb95654901b32195c9c7avboxsync *
45e9809aff7304721fddb95654901b32195c9c7avboxsync * Sun Microsystems, Inc. confidential
45e9809aff7304721fddb95654901b32195c9c7avboxsync * All rights reserved
45e9809aff7304721fddb95654901b32195c9c7avboxsync */
45e9809aff7304721fddb95654901b32195c9c7avboxsync
45e9809aff7304721fddb95654901b32195c9c7avboxsync#include <VBox/types.h>
45e9809aff7304721fddb95654901b32195c9c7avboxsync
45e9809aff7304721fddb95654901b32195c9c7avboxsync#define PHY_EPID_M881000 0xC50
45e9809aff7304721fddb95654901b32195c9c7avboxsync#define PHY_EPID_M881011 0xC24
45e9809aff7304721fddb95654901b32195c9c7avboxsync
45e9809aff7304721fddb95654901b32195c9c7avboxsync#define PCTRL_SPDSELM 0x0040
45e9809aff7304721fddb95654901b32195c9c7avboxsync#define PCTRL_DUPMOD  0x0100
45e9809aff7304721fddb95654901b32195c9c7avboxsync#define PCTRL_ANEG    0x1000
45e9809aff7304721fddb95654901b32195c9c7avboxsync#define PCTRL_SPDSELL 0x2000
45e9809aff7304721fddb95654901b32195c9c7avboxsync#define PCTRL_RESET   0x8000
45e9809aff7304721fddb95654901b32195c9c7avboxsync
45e9809aff7304721fddb95654901b32195c9c7avboxsync#define PSTATUS_LNKSTAT 0x0004
45e9809aff7304721fddb95654901b32195c9c7avboxsync
45e9809aff7304721fddb95654901b32195c9c7avboxsync#define PSSTAT_LINK     0x0400
45e9809aff7304721fddb95654901b32195c9c7avboxsync
45e9809aff7304721fddb95654901b32195c9c7avboxsyncnamespace Phy
45e9809aff7304721fddb95654901b32195c9c7avboxsync{
45e9809aff7304721fddb95654901b32195c9c7avboxsync    /**
45e9809aff7304721fddb95654901b32195c9c7avboxsync     * Indices of memory-mapped registers in register table
45e9809aff7304721fddb95654901b32195c9c7avboxsync     */
45e9809aff7304721fddb95654901b32195c9c7avboxsync    enum enmRegIdx
45e9809aff7304721fddb95654901b32195c9c7avboxsync    {
45e9809aff7304721fddb95654901b32195c9c7avboxsync        PCTRL_IDX,
45e9809aff7304721fddb95654901b32195c9c7avboxsync        PSTATUS_IDX,
45e9809aff7304721fddb95654901b32195c9c7avboxsync        PID_IDX,
45e9809aff7304721fddb95654901b32195c9c7avboxsync        EPID_IDX,
45e9809aff7304721fddb95654901b32195c9c7avboxsync        ANA_IDX,
45e9809aff7304721fddb95654901b32195c9c7avboxsync        LPA_IDX,
45e9809aff7304721fddb95654901b32195c9c7avboxsync        ANE_IDX,
45e9809aff7304721fddb95654901b32195c9c7avboxsync        NPT_IDX,
45e9809aff7304721fddb95654901b32195c9c7avboxsync        LPN_IDX,
45e9809aff7304721fddb95654901b32195c9c7avboxsync        GCON_IDX,
45e9809aff7304721fddb95654901b32195c9c7avboxsync        GSTATUS_IDX,
        EPSTATUS_IDX,
        PSCON_IDX,
        PSSTAT_IDX,
        PINTE_IDX,
        PINTS_IDX,
        EPSCON1_IDX,
        PREC_IDX,
        EPSCON2_IDX,
        R30PS_IDX,
        R30AW_IDX,
        NUM_OF_PHY_REGS
    };
    /**
     * Emulation state of PHY.
     */
    struct Phy_st
    {
        /** Network controller instance this PHY is attached to. */
        int      iInstance;
        /** Register storage. */
        uint16_t au16Regs[NUM_OF_PHY_REGS];
        /** Current state of serial MDIO interface. */
        uint16_t u16State;
        /** Current state of serial MDIO interface. */
        uint16_t u16Acc;
        /** Number of bits remaining to be shifted into/out of accumulator. */
        uint16_t u16Cnt;
        /** PHY register offset selected for MDIO operation. */
        uint16_t u16RegAdr;
    };
}

#define MDIO_IDLE   0
#define MDIO_ST     1
#define MDIO_OP_ADR 2
#define MDIO_TA_RD  3
#define MDIO_TA_WR  4
#define MDIO_READ   5
#define MDIO_WRITE  6

#define MDIO_READ_OP  2
#define MDIO_WRITE_OP 1

typedef struct Phy::Phy_st PHY;
typedef PHY *PPHY;

/* Interface *****************************************************************/
namespace Phy {
    /** Initialize PHY. */
    void     init(PPHY pPhy, int iNICInstance, uint16_t u16EPid);
    /** Read PHY register at specified address. */
    uint16_t readRegister(PPHY pPhy, uint32_t u32Address);
    /** Write to PHY register at specified address. */
    void     writeRegister(PPHY pPhy, uint32_t u32Address, uint16_t u16Value);
    /** Read the value on MDIO pin. */
    bool     readMDIO(PPHY pPhy);
    /** Set the value of MDIO pin. */
    void     writeMDIO(PPHY pPhy, bool fPin);
    /** Hardware reset. */
    void     hardReset(PPHY pPhy);
    /** Query link status. */
    bool     isLinkUp(PPHY pPhy);
    /** Set link status. */
    void     setLinkStatus(PPHY pPhy, bool fLinkIsUp);
    /** Save PHY state. */
    int      saveState(PSSMHANDLE pSSMHandle, PPHY pPhy);
    /** Restore previously saved PHY state. */
    int      loadState(PSSMHANDLE pSSMHandle, PPHY pPhy);
}