DevE1000.cpp revision 6dea6d87ed79bc0994d314fed1c90431091e8820
/* $Id$ */
/** @file
* DevE1000 - Intel 82540EM Ethernet Controller Emulation.
*
* Implemented in accordance with the specification:
*
*
* 317453-002 Revision 3.5
*
* @todo IPv6 checksum offloading support
* @todo VLAN checksum offloading support
* @todo Flexible Filter / Wakeup (optional?)
*/
/*
* Copyright (C) 2007 Sun Microsystems, Inc.
*
* This file is part of VirtualBox Open Source Edition (OSE), as
* available from http://www.virtualbox.org. This file is free software;
* General Public License (GPL) as published by the Free Software
* Foundation, in version 2 as it comes in the "COPYING" file of the
* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
*
* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
* Clara, CA 95054 USA or visit http://www.sun.com if you need
* additional information or have any questions.
*/
#define LOG_GROUP LOG_GROUP_DEV_E1000
//#define E1kLogRel(a) LogRel(a)
#define E1kLogRel(a)
/* Options */
#define E1K_ITR_ENABLED
//#define E1K_GLOBAL_MUTEX
//#define E1K_USE_TX_TIMERS
//#define E1K_NO_TAD
//#define E1K_REL_DEBUG
//#define E1K_INT_STATS
//#define E1K_REL_STATS
#include <iprt/semaphore.h>
#include "../Builtins.h"
#include "DevEEPROM.h"
#include "DevE1000Phy.h"
/* Little helpers ************************************************************/
#define htonl(x) ASMByteSwapU32(x)
#ifndef DEBUG
# ifdef E1K_REL_STATS
# define STAM_COUNTER_INC STAM_REL_COUNTER_INC
# endif
# ifdef E1K_REL_DEBUG
# define DEBUG
//# define E1kLog3(a)
# else
# define E1kLog(a)
# define E1kLog2(a)
# define E1kLog3(a)
# endif
#else
//# define E1kLog(a)
//# define E1kLog2(a)
//# define E1kLog3(a)
#endif
//#undef DEBUG
#define IFACE_TO_STATE(pIface, ifaceName) ((E1KSTATE *)((char*)pIface - RT_OFFSETOF(E1KSTATE, ifaceName)))
#define E1K_RELOCATE(p, o) *(RTHCUINTPTR *)&p += o
#define E1K_INC_CNT32(cnt) \
do { \
if (cnt < UINT32_MAX) \
cnt++; \
} while (0)
do { \
u64Cnt = UINT64_MAX; \
} while (0)
#ifdef E1K_INT_STATS
#else /* E1K_INT_STATS */
# define E1K_INC_ISTAT_CNT(cnt)
#endif /* E1K_INT_STATS */
/*****************************************************************************/
#define E1K_CHIP_82540EM 0
#define E1K_CHIP_82543GC 1
#define E1K_CHIP_82545EM 2
struct E1kChips
{
const char *pcszName;
} g_Chips[] =
{
/* Vendor Device SSVendor SubSys Name */
{ 0x8086, 0x100E, 0x8086, 0x001E, "82540EM" }, /* Intel 82540EM-A in Intel PRO/1000 MT Desktop */
{ 0x8086, 0x1004, 0x8086, 0x1004, "82543GC" }, /* Intel 82543GC in Intel PRO/1000 T Server */
{ 0x8086, 0x100F, 0x15AD, 0x0750, "82545EM" } /* Intel 82545EM-A in VMWare Network Adapter */
};
/* The size of register area mapped to I/O space */
#define E1K_IOPORT_SIZE 0x8
/* The size of memory-mapped register area */
#define E1K_MM_SIZE 0x20000
#define E1K_MAX_TX_PKT_SIZE 16288
#define E1K_MAX_RX_PKT_SIZE 16384
/*****************************************************************************/
#define SET_BITS(reg, bits, bitval) do { reg = (reg & ~reg##_##bits##_MASK) | (bitval << reg##_##bits##_SHIFT); } while (0)
#define SET_BITS_V(val, reg, bits, bitval) do { val = (val & ~reg##_##bits##_MASK) | (bitval << reg##_##bits##_SHIFT); } while (0)
#define CTRL_SLU 0x00000040
#define CTRL_MDIO 0x00100000
#define CTRL_MDC 0x00200000
#define CTRL_MDIO_DIR 0x01000000
#define CTRL_MDC_DIR 0x02000000
#define CTRL_RESET 0x04000000
#define CTRL_VME 0x40000000
#define STATUS_LU 0x00000002
#define EECD_EE_WIRES 0x0F
#define EECD_EE_REQ 0x40
#define EECD_EE_GNT 0x80
#define MDIC_DATA_MASK 0x0000FFFF
#define MDIC_DATA_SHIFT 0
#define MDIC_REG_MASK 0x001F0000
#define MDIC_REG_SHIFT 16
#define MDIC_PHY_MASK 0x03E00000
#define MDIC_PHY_SHIFT 21
#define MDIC_OP_WRITE 0x04000000
#define MDIC_OP_READ 0x08000000
#define MDIC_READY 0x10000000
#define MDIC_INT_EN 0x20000000
#define MDIC_ERROR 0x40000000
#define TCTL_EN 0x00000002
#define TCTL_PSP 0x00000008
#define RCTL_EN 0x00000002
#define RCTL_UPE 0x00000008
#define RCTL_MPE 0x00000010
#define RCTL_LPE 0x00000020
#define RCTL_LBM_MASK 0x000000C0
#define RCTL_LBM_SHIFT 6
#define RCTL_RDMTS_MASK 0x00000300
#define RCTL_RDMTS_SHIFT 8
#define RCTL_LBM_TCVR 3
#define RCTL_MO_MASK 0x00003000
#define RCTL_MO_SHIFT 12
#define RCTL_BAM 0x00008000
#define RCTL_BSIZE_MASK 0x00030000
#define RCTL_BSIZE_SHIFT 16
#define RCTL_VFE 0x00040000
#define RCTL_BSEX 0x02000000
#define RCTL_SECRC 0x04000000
#define ICR_TXDW 0x00000001
#define ICR_TXQE 0x00000002
#define ICR_LSC 0x00000004
#define ICR_RXDMT0 0x00000010
#define ICR_RXT0 0x00000080
#define ICR_TXD_LOW 0x00008000
#define RDTR_FPD 0x80000000
typedef struct
{
unsigned rxa : 7;
unsigned rxa_r : 9;
unsigned txa : 16;
} PBAST;
#define TXDCTL_WTHRESH_MASK 0x003F0000
#define TXDCTL_WTHRESH_SHIFT 16
#define TXDCTL_LWTHRESH_MASK 0xFE000000
#define TXDCTL_LWTHRESH_SHIFT 25
#define RXCSUM_PCSS_MASK 0x000000FF
#define RXCSUM_PCSS_SHIFT 0
/* Register access macros ****************************************************/
/**
* Indices of memory-mapped registers in register table
*/
typedef enum
{
} E1kRegIndex;
#define E1K_NUM_OF_32BIT_REGS MTA_IDX
/**
* Define E1000-specific EEPROM layout.
*/
class E1kEEPROM
{
public:
#ifdef IN_RING3
/**
* Initialize EEPROM content.
*
* @param macAddr MAC address of E1000.
*/
{
/*
* bit 3 - full support for power management
* bit 10 - full duplex
*/
};
/**
* Compute the checksum as required by E1000 and store it
* in the last word.
*/
void updateChecksum()
{
uint16_t u16Checksum = 0;
};
/**
* First 6 bytes of EEPROM contain MAC address.
*
* @returns MAC address of E1000.
*/
{
};
{
}
{
}
#endif /* IN_RING3 */
};
struct E1kRxDStatus
{
/* Descriptor Status field */
unsigned fDD : 1;
unsigned fEOP : 1;
unsigned fIXSM : 1;
unsigned fVP : 1;
unsigned : 1;
unsigned fTCPCS : 1;
unsigned fIPCS : 1;
unsigned fPIF : 1;
/* Descriptor Errors field */
unsigned fCE : 1;
unsigned : 4;
unsigned fTCPE : 1;
unsigned fIPE : 1;
unsigned fRXE : 1;
/* Descriptor Special field */
unsigned u12VLAN : 12;
unsigned fCFI : 1;
unsigned u3PRI : 3;
};
typedef struct E1kRxDStatus E1KRXDST;
struct E1kRxDesc_st
{
};
typedef struct E1kRxDesc_st E1KRXDESC;
#define E1K_DTYP_LEGACY -1
#define E1K_DTYP_CONTEXT 0
#define E1K_DTYP_DATA 1
struct E1kTDLegacy
{
struct TDLCmd_st
{
unsigned u16Length : 16;
unsigned u8CSO : 8;
/* CMD field : 8 */
unsigned fEOP : 1;
unsigned fIFCS : 1;
unsigned fIC : 1;
unsigned fRS : 1;
unsigned fRSV : 1;
unsigned fDEXT : 1;
unsigned fVLE : 1;
unsigned fIDE : 1;
} cmd;
struct TDLDw3_st
{
/* STA field */
unsigned fDD : 1;
unsigned fEC : 1;
unsigned fLC : 1;
unsigned fTURSV : 1;
/* RSV field */
unsigned u4RSV : 4;
/* CSS field */
unsigned u8CSS : 8;
/* Special field*/
unsigned u12VLAN : 12;
unsigned fCFI : 1;
unsigned u3PRI : 3;
} dw3;
};
struct E1kTDContext
{
struct CheckSum_st
{
unsigned u8CSS : 8;
unsigned u8CSO : 8;
unsigned u16CSE : 16;
} ip;
struct CheckSum_st tu;
struct TDCDw2_st
{
unsigned u20PAYLEN : 20;
unsigned u4DTYP : 4;
/* CMD field : 8 */
unsigned fTCP : 1;
unsigned fIP : 1;
unsigned fTSE : 1;
unsigned fRS : 1;
unsigned fRSV1 : 1;
unsigned fDEXT : 1;
unsigned fRSV2 : 1;
unsigned fIDE : 1;
} dw2;
struct TDCDw3_st
{
unsigned fDD : 1;
unsigned u7RSV : 7;
unsigned u8HDRLEN : 8;
unsigned u16MSS : 16;
} dw3;
};
typedef struct E1kTDContext E1KTXCTX;
struct E1kTDData
{
struct TDDCmd_st
{
unsigned u20DTALEN : 20;
unsigned u4DTYP : 4;
/* DCMD field : 8 */
unsigned fEOP : 1;
unsigned fIFCS : 1;
unsigned fTSE : 1;
unsigned fRS : 1;
unsigned fRSV : 1;
unsigned fDEXT : 1;
unsigned fVLE : 1;
unsigned fIDE : 1;
} cmd;
struct TDDDw3_st
{
/* STA field */
unsigned fDD : 1;
unsigned fEC : 1;
unsigned fLC : 1;
unsigned fTURSV : 1;
/* RSV field */
unsigned u4RSV : 4;
/* POPTS field */
unsigned fIXSM : 1;
unsigned fTXSM : 1;
unsigned u6RSV : 6;
/* Special field*/
unsigned u12VLAN : 12;
unsigned fCFI : 1;
unsigned u3PRI : 3;
} dw3;
};
union E1kTxDesc
{
struct E1kTDLegacy legacy;
struct E1kTDContext context;
};
#define RA_CTL_AS 0x0003
#define RA_CTL_AV 0x8000
union E1kRecAddr
{
struct RAArray
{
} array[16];
};
typedef union E1kRecAddr E1KRA;
/** @todo use+extend RTNETIPV4 */
struct E1kIpHeader
{
/* type of service / version / header length */
/* total length */
/* identification */
uint16_t ident;
/* fragment offset field */
/* time to live / protocol*/
/* checksum */
/* source IP address */
/* destination IP address */
};
#define E1K_TCP_FIN 0x01U
#define E1K_TCP_SYN 0x02U
#define E1K_TCP_RST 0x04U
#define E1K_TCP_PSH 0x08U
#define E1K_TCP_ACK 0x10U
#define E1K_TCP_URG 0x20U
#define E1K_TCP_ECE 0x40U
#define E1K_TCP_CWR 0x80U
#define E1K_TCP_FLAGS 0x3fU
/** @todo use+extend RTNETTCP */
struct E1kTcpHeader
{
};
#define E1K_SAVEDSTATE_VERSION 1
/**
* Device state structure. Holds the current state of device.
*/
struct E1kState_st
{
#ifndef E1K_GLOBAL_MUTEX
// PDMCRITSECT csTx; /**< TX Critical section. */
#endif
/** Transmit thread blocker. */
/** Base address of memory-mapped registers. */
/** MAC address obtained from the configuration. */
/** Base port of I/O space region. */
/** EMT: */
/** EMT: Last time the interrupt was acknowledged. */
/** All: Used for eliminating spurious interrupts. */
bool fIntRaised;
/** EMT: */
bool fCableConnected;
/** EMT: */
bool fR0Enabled;
/** EMT: */
bool fGCEnabled;
/* All: Device register storage. */
/** EMT: Offset of the register to be read via IO. */
/** EMT: Multicast Table Array. */
/** EMT: Receive Address registers. */
/** EMT: VLAN filter table array. */
/** EMT: Receive buffer size. */
/** EMT: Locked state -- no state alteration possible. */
bool fLocked;
/** EMT: */
bool fDelayInts;
/** All: */
bool fIntMaskUsed;
/** N/A: */
bool volatile fMaybeOutOfSpace;
/** EMT: Gets signalled when more RX descriptors become available. */
/** TX: Context used for TCP segmentation packets. */
/** TX: Context used for ordinary packets. */
/** TX: Transmit packet buffer. */
/** TX: Number of bytes assembled in TX packet buffer. */
/** TX: IP checksum has to be inserted if true. */
bool fIPcsum;
bool fTCPcsum;
/** TX: Number of payload bytes remaining in TSE context. */
/** TX: Number of header bytes remaining in TSE context. */
/** TX: Flags from template header. */
/** TX: Partial checksum from template header. */
/** ?: Emulated controller type. */
/** EMT: EEPROM emulation */
/** EMT: Physical interface emulation. */
#if defined(VBOX_WITH_STATISTICS) || defined(E1K_REL_STATS)
#endif /* VBOX_WITH_STATISTICS || E1K_REL_STATS */
#ifdef E1K_INT_STATS
/* Internal stats */
#endif /* E1K_INT_STATS */
};
typedef struct E1kState_st E1KSTATE;
#ifndef VBOX_DEVICE_STRUCT_TESTCASE
/* Forward declarations ******************************************************/
PDMBOTHCBDECL(int) e1kMMIORead (PPDMDEVINS pDevIns, void *pvUser, RTGCPHYS GCPhysAddr, void *pv, unsigned cb);
PDMBOTHCBDECL(int) e1kMMIOWrite(PPDMDEVINS pDevIns, void *pvUser, RTGCPHYS GCPhysAddr, void *pv, unsigned cb);
PDMBOTHCBDECL(int) e1kIOPortIn (PPDMDEVINS pDevIns, void *pvUser, RTIOPORT port, uint32_t *pu32, unsigned cb);
PDMBOTHCBDECL(int) e1kIOPortOut(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT port, uint32_t u32, unsigned cb);
static int e1kRegReadUnimplemented (E1KSTATE* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value);
static int e1kRegWriteUnimplemented(E1KSTATE* pState, uint32_t offset, uint32_t index, uint32_t u32Value);
static int e1kRegReadAutoClear (E1KSTATE* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value);
static int e1kRegReadDefault (E1KSTATE* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value);
static int e1kRegWriteDefault (E1KSTATE* pState, uint32_t offset, uint32_t index, uint32_t u32Value);
#if 0 /* unused */
#endif
/**
* Register map table.
*
* Override fn_read and fn_write to get register-specific behavior.
*/
const static struct E1kRegMap_st
{
/** Register offset in the register space. */
/** Size in bytes. Registers of size > 4 are in fact tables. */
/** Readable bits. */
/** Writable bits. */
/** Read callback. */
/** Write callback. */
/** Abbreviated name. */
const char *abbrev;
/** Full name. */
const char *name;
{
/* offset size read mask write mask read callback write callback abbrev full name */
/*------- ------- ---------- ---------- ----------------------- ------------------------ ---------- ------------------------------*/
{ 0x00000, 0x00004, 0xDBF31BE9, 0xDBF31BE9, e1kRegReadDefault , e1kRegWriteCTRL , "CTRL" , "Device Control" },
{ 0x00008, 0x00004, 0x0000FDFF, 0x00000000, e1kRegReadDefault , e1kRegWriteUnimplemented, "STATUS" , "Device Status" },
{ 0x00010, 0x00004, 0x000027F0, 0x00000070, e1kRegReadEECD , e1kRegWriteEECD , "EECD" , "EEPROM/Flash Control/Data" },
{ 0x00014, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "EERD" , "EEPROM Read" },
{ 0x00018, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "CTRL_EXT", "Extended Device Control" },
{ 0x0001c, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "FLA" , "Flash Access (N/A)" },
{ 0x00020, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadDefault , e1kRegWriteMDIC , "MDIC" , "MDI Control" },
{ 0x00028, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "FCAL" , "Flow Control Address Low" },
{ 0x0002c, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "FCAH" , "Flow Control Address High" },
{ 0x00030, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "FCT" , "Flow Control Type" },
{ 0x00038, 0x00004, 0x0000FFFF, 0x0000FFFF, e1kRegReadDefault , e1kRegWriteDefault , "VET" , "VLAN EtherType" },
{ 0x000c0, 0x00004, 0x0001F6DF, 0x0001F6DF, e1kRegReadICR , e1kRegWriteICR , "ICR" , "Interrupt Cause Read" },
{ 0x000c4, 0x00004, 0x0000FFFF, 0x0000FFFF, e1kRegReadDefault , e1kRegWriteDefault , "ITR" , "Interrupt Throttling" },
{ 0x000c8, 0x00004, 0x00000000, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteICS , "ICS" , "Interrupt Cause Set" },
{ 0x000d0, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadDefault , e1kRegWriteIMS , "IMS" , "Interrupt Mask Set/Read" },
{ 0x000d8, 0x00004, 0x00000000, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteIMC , "IMC" , "Interrupt Mask Clear" },
{ 0x00100, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadDefault , e1kRegWriteRCTL , "RCTL" , "Receive Control" },
{ 0x00170, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "FCTTV" , "Flow Control Transmit Timer Value" },
{ 0x00178, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "TXCW" , "Transmit Configuration Word (N/A)" },
{ 0x00180, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "RXCW" , "Receive Configuration Word (N/A)" },
{ 0x00400, 0x00004, 0x017FFFFA, 0x017FFFFA, e1kRegReadDefault , e1kRegWriteDefault , "TCTL" , "Transmit Control" },
{ 0x00410, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "TIPG" , "Transmit IPG" },
{ 0x00458, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "AIFS" , "Adaptive IFS Throttle - AIT" },
{ 0x00e00, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "LEDCTL" , "LED Control" },
{ 0x01000, 0x00004, 0xFFFF007F, 0x0000007F, e1kRegReadDefault , e1kRegWritePBA , "PBA" , "Packet Buffer Allocation" },
{ 0x02160, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "FCRTL" , "Flow Control Receive Threshold Low" },
{ 0x02168, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "FCRTH" , "Flow Control Receive Threshold High" },
{ 0x02410, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "RDFH" , "Receive Data FIFO Head" },
{ 0x02418, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "RDFT" , "Receive Data FIFO Tail" },
{ 0x02420, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "RDFHS" , "Receive Data FIFO Head Saved Register" },
{ 0x02428, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "RDFTS" , "Receive Data FIFO Tail Saved Register" },
{ 0x02430, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "RDFPC" , "Receive Data FIFO Packet Count" },
{ 0x02800, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadDefault , e1kRegWriteDefault , "RDBAL" , "Receive Descriptor Base Low" },
{ 0x02804, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadDefault , e1kRegWriteDefault , "RDBAH" , "Receive Descriptor Base High" },
{ 0x02808, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadDefault , e1kRegWriteDefault , "RDLEN" , "Receive Descriptor Length" },
{ 0x02810, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadDefault , e1kRegWriteDefault , "RDH" , "Receive Descriptor Head" },
{ 0x02818, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadDefault , e1kRegWriteRDT , "RDT" , "Receive Descriptor Tail" },
{ 0x02820, 0x00004, 0x0000FFFF, 0x0000FFFF, e1kRegReadDefault , e1kRegWriteRDTR , "RDTR" , "Receive Delay Timer" },
{ 0x02828, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "RXDCTL" , "Receive Descriptor Control" },
{ 0x0282c, 0x00004, 0x0000FFFF, 0x0000FFFF, e1kRegReadDefault , e1kRegWriteDefault , "RADV" , "Receive Interrupt Absolute Delay Timer" },
{ 0x02c00, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "RSRPD" , "Receive Small Packet Detect Interrupt" },
{ 0x03000, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "TXDMAC" , "TX DMA Control (N/A)" },
{ 0x03410, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "TDFH" , "Transmit Data FIFO Head" },
{ 0x03418, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "TDFT" , "Transmit Data FIFO Tail" },
{ 0x03420, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "TDFHS" , "Transmit Data FIFO Head Saved Register" },
{ 0x03428, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "TDFTS" , "Transmit Data FIFO Tail Saved Register" },
{ 0x03430, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "TDFPC" , "Transmit Data FIFO Packet Count" },
{ 0x03800, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadDefault , e1kRegWriteDefault , "TDBAL" , "Transmit Descriptor Base Low" },
{ 0x03804, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadDefault , e1kRegWriteDefault , "TDBAH" , "Transmit Descriptor Base High" },
{ 0x03808, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadDefault , e1kRegWriteDefault , "TDLEN" , "Transmit Descriptor Length" },
{ 0x03810, 0x00004, 0x0000FFFF, 0x0000FFFF, e1kRegReadDefault , e1kRegWriteDefault , "TDH" , "Transmit Descriptor Head" },
{ 0x03818, 0x00004, 0x0000FFFF, 0x0000FFFF, e1kRegReadDefault , e1kRegWriteTDT , "TDT" , "Transmit Descriptor Tail" },
{ 0x03820, 0x00004, 0x0000FFFF, 0x0000FFFF, e1kRegReadDefault , e1kRegWriteDefault , "TIDV" , "Transmit Interrupt Delay Value" },
{ 0x03828, 0x00004, 0xFF3F3F3F, 0xFF3F3F3F, e1kRegReadDefault , e1kRegWriteDefault , "TXDCTL" , "Transmit Descriptor Control" },
{ 0x0382c, 0x00004, 0x0000FFFF, 0x0000FFFF, e1kRegReadDefault , e1kRegWriteDefault , "TADV" , "Transmit Absolute Interrupt Delay Timer" },
{ 0x03830, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "TSPMT" , "TCP Segmentation Pad and Threshold" },
{ 0x04000, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "CRCERRS" , "CRC Error Count" },
{ 0x04004, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "ALGNERRC", "Alignment Error Count" },
{ 0x04008, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "SYMERRS" , "Symbol Error Count" },
{ 0x0400c, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "RXERRC" , "RX Error Count" },
{ 0x04010, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "MPC" , "Missed Packets Count" },
{ 0x04014, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "SCC" , "Single Collision Count" },
{ 0x04018, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "ECOL" , "Excessive Collisions Count" },
{ 0x0401c, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "MCC" , "Multiple Collision Count" },
{ 0x04020, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "LATECOL" , "Late Collisions Count" },
{ 0x04028, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "COLC" , "Collision Count" },
{ 0x04030, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "DC" , "Defer Count" },
{ 0x04034, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "TNCRS" , "Transmit - No CRS" },
{ 0x04038, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "SEC" , "Sequence Error Count" },
{ 0x0403c, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "CEXTERR" , "Carrier Extension Error Count" },
{ 0x04040, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "RLEC" , "Receive Length Error Count" },
{ 0x04048, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "XONRXC" , "XON Received Count" },
{ 0x0404c, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "XONTXC" , "XON Transmitted Count" },
{ 0x04050, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "XOFFRXC" , "XOFF Received Count" },
{ 0x04054, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "XOFFTXC" , "XOFF Transmitted Count" },
{ 0x04058, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "FCRUC" , "FC Received Unsupported Count" },
{ 0x0405c, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "PRC64" , "Packets Received (64 Bytes) Count" },
{ 0x04060, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "PRC127" , "Packets Received (65-127 Bytes) Count" },
{ 0x04064, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "PRC255" , "Packets Received (128-255 Bytes) Count" },
{ 0x04068, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "PRC511" , "Packets Received (256-511 Bytes) Count" },
{ 0x0406c, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "PRC1023" , "Packets Received (512-1023 Bytes) Count" },
{ 0x04070, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "PRC1522" , "Packets Received (1024-Max Bytes)" },
{ 0x04074, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "GPRC" , "Good Packets Received Count" },
{ 0x04078, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "BPRC" , "Broadcast Packets Received Count" },
{ 0x0407c, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "MPRC" , "Multicast Packets Received Count" },
{ 0x04080, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "GPTC" , "Good Packets Transmitted Count" },
{ 0x04088, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "GORCL" , "Good Octets Received Count (Low)" },
{ 0x0408c, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "GORCH" , "Good Octets Received Count (Hi)" },
{ 0x04090, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "GOTCL" , "Good Octets Transmitted Count (Low)" },
{ 0x04094, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "GOTCH" , "Good Octets Transmitted Count (Hi)" },
{ 0x040a0, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "RNBC" , "Receive No Buffers Count" },
{ 0x040a4, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "RUC" , "Receive Undersize Count" },
{ 0x040a8, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "RFC" , "Receive Fragment Count" },
{ 0x040ac, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "ROC" , "Receive Oversize Count" },
{ 0x040b0, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "RJC" , "Receive Jabber Count" },
{ 0x040b4, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "MGTPRC" , "Management Packets Received Count" },
{ 0x040b8, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "MGTPDC" , "Management Packets Dropped Count" },
{ 0x040bc, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "MGTPTC" , "Management Pkts Transmitted Count" },
{ 0x040c0, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "TORL" , "Total Octets Received (Lo)" },
{ 0x040c4, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "TORH" , "Total Octets Received (Hi)" },
{ 0x040c8, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "TOTL" , "Total Octets Transmitted (Lo)" },
{ 0x040cc, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "TOTH" , "Total Octets Transmitted (Hi)" },
{ 0x040d0, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "TPR" , "Total Packets Received" },
{ 0x040d4, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "TPT" , "Total Packets Transmitted" },
{ 0x040d8, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "PTC64" , "Packets Transmitted (64 Bytes) Count" },
{ 0x040dc, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "PTC127" , "Packets Transmitted (65-127 Bytes) Count" },
{ 0x040e0, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "PTC255" , "Packets Transmitted (128-255 Bytes) Count" },
{ 0x040e4, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "PTC511" , "Packets Transmitted (256-511 Bytes) Count" },
{ 0x040e8, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "PTC1023" , "Packets Transmitted (512-1023 Bytes) Count" },
{ 0x040ec, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "PTC1522" , "Packets Transmitted (1024 Bytes or Greater) Count" },
{ 0x040f0, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "MPTC" , "Multicast Packets Transmitted Count" },
{ 0x040f4, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "BPTC" , "Broadcast Packets Transmitted Count" },
{ 0x040f8, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadAutoClear , e1kRegWriteUnimplemented, "TSCTC" , "TCP Segmentation Context Transmitted Count" },
{ 0x040fc, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "TSCTFC" , "TCP Segmentation Context Tx Fail Count" },
{ 0x05000, 0x00004, 0x000007FF, 0x000007FF, e1kRegReadDefault , e1kRegWriteDefault , "RXCSUM" , "Receive Checksum Control" },
{ 0x05800, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "WUC" , "Wakeup Control" },
{ 0x05808, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "WUFC" , "Wakeup Filter Control" },
{ 0x05810, 0x00004, 0xFFFFFFFF, 0x00000000, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "WUS" , "Wakeup Status" },
{ 0x05820, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadDefault , e1kRegWriteDefault , "MANC" , "Management Control" },
{ 0x05838, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "IPAV" , "IP Address Valid" },
{ 0x05900, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "WUPL" , "Wakeup Packet Length" },
{ 0x05200, 0x00200, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadMTA , e1kRegWriteMTA , "MTA" , "Multicast Table Array (n)" },
{ 0x05400, 0x00080, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadRA , e1kRegWriteRA , "RA" , "Receive Address (64-bit) (n)" },
{ 0x05600, 0x00200, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadVFTA , e1kRegWriteVFTA , "VFTA" , "VLAN Filter Table Array (n)" },
{ 0x05840, 0x0001c, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "IP4AT" , "IPv4 Address Table" },
{ 0x05880, 0x00010, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "IP6AT" , "IPv6 Address Table" },
{ 0x05a00, 0x00080, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "WUPM" , "Wakeup Packet Memory" },
{ 0x05f00, 0x0001c, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "FFLT" , "Flexible Filter Length Table" },
{ 0x09000, 0x003fc, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "FFMT" , "Flexible Filter Mask Table" },
{ 0x09800, 0x003fc, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "FFVT" , "Flexible Filter Value Table" },
{ 0x10000, 0x10000, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadUnimplemented, e1kRegWriteUnimplemented, "PBM" , "Packet Buffer Memory (n)" },
{ 0x00040, 0x00080, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadRA , e1kRegWriteRA , "RA" , "Receive Address (64-bit) (n) (82542)" },
{ 0x00200, 0x00200, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadMTA , e1kRegWriteMTA , "MTA" , "Multicast Table Array (n) (82542)" },
{ 0x00600, 0x00200, 0xFFFFFFFF, 0xFFFFFFFF, e1kRegReadVFTA , e1kRegWriteVFTA , "VFTA" , "VLAN Filter Table Array (n) (82542)" }
};
#ifdef DEBUG
/**
* Convert U32 value to hex string. Masked bytes are replaced with dots.
*
* @remarks The mask has byte (not bit) granularity (e.g. 000000FF).
*
* @returns The buffer.
*
* @param u32 The word to convert into string.
* @param mask Selects which bytes to convert.
* @param buf Where to put the result.
*/
{
{
if (mask & 0xF)
else
*ptr = '.';
}
buf[8] = 0;
return buf;
}
/**
* Returns timer name for debug purposes.
*
* @returns The timer name.
*
* @param pState The device state structure.
* @param pTimer The timer to get the name for.
*/
{
return "TID";
return "TAD";
return "RID";
return "RAD";
return "Int";
return "unknown";
}
#endif /* DEBUG */
/**
* Arm a timer.
*
* @param pState Pointer to the device state structure.
* @param pTimer Pointer to the timer.
* @param uExpireIn Expiration interval in microseconds.
*/
{
return;
E1kLog2(("%s Arming %s timer to fire in %d usec...\n",
TMTimerGet(pTimer));
}
/**
* Cancel a timer.
*
* @param pState Pointer to the device state structure.
* @param pTimer Pointer to the timer.
*/
{
E1kLog2(("%s Stopping %s timer...\n",
if (RT_FAILURE(rc))
{
E1kLog2(("%s e1kCancelTimer: TMTimerStop() failed with %Rrc\n",
}
}
#ifdef E1K_GLOBAL_MUTEX
{
return VINF_SUCCESS;
}
{
}
#define e1kCsRxLeave(ps)
#define e1kCsTxLeave(ps)
{
{
E1kLog2(("%s ==> FAILED to enter critical section at %s:%d:%s with rc=\n",
"%s Failed to enter critical section, rc=%Rrc\n",
}
else
{
//E1kLog2(("%s ==> Mutex acquired at %s:%d:%s\n", INSTANCE(pState), RT_SRC_POS_ARGS));
}
return rc;
}
{
//E1kLog2(("%s <== Releasing mutex...\n", INSTANCE(pState)));
}
#else /* !E1K_GLOBAL_MUTEX */
#define e1kCsTxLeave(ps)
//#define e1kCsTxEnter(ps, rc) PDMCritSectEnter(&ps->csTx, rc)
//#define e1kCsTxLeave(ps) PDMCritSectLeave(&ps->csTx)
#if 0
{
if (RT_FAILURE(rc))
{
E1kLog2(("%s ==> FAILED to enter critical section at %s:%d:%s with rc=%Rrc\n",
"%s Failed to enter critical section, rc=%Rrc\n",
}
else
{
//E1kLog2(("%s ==> Entered critical section at %s:%d:%s\n", INSTANCE(pState), RT_SRC_POS_ARGS));
}
return RT_SUCCESS(rc);
}
{
//E1kLog2(("%s <== Leaving critical section\n", INSTANCE(pState)));
}
#endif
{
return VINF_SUCCESS;
}
{
}
#endif /* !E1K_GLOBAL_MUTEX */
#ifdef IN_RING3
/**
* Wakeup the RX thread.
*/
{
if ( pState->fMaybeOutOfSpace
{
}
}
/**
* Compute Internet checksum.
*
* @remarks Refer to http://www.netfor2.com/checksum.html for short intro.
*
* @param pState The device state structure.
* @param cpPacket The packet.
* @param cb The size of the packet.
* @param cszText A string denoting direction of packet transfer.
*
* @return The 1's complement of the 1's complement sum.
*
* @thread E1000_TX
*/
{
while (cb > 1)
{
cb -= 2;
}
if (cb)
while (csum >> 16)
return ~csum;
}
/**
* Dump a packet to debug log.
*
* @param pState The device state structure.
* @param cpPacket The packet.
* @param cb The size of the packet.
* @param cszText A string denoting direction of packet transfer.
* @thread E1000_TX
*/
DECLINLINE(void) e1kPacketDump(E1KSTATE* pState, const uint8_t *cpPacket, size_t cb, const char *cszText)
{
#ifdef DEBUG
{
E1kLog(("%s --- %s packet #%d: ---\n",
}
#else
{
E1kLogRel(("E1000: %s packet #%d, seq=%x ack=%x\n", cszText, pState->u32PktNo++, ntohl(*(uint32_t*)(cpPacket+0x26)), ntohl(*(uint32_t*)(cpPacket+0x2A))));
}
#endif
}
/**
* Determine the type of transmit descriptor.
*
* @returns Descriptor type. See E1K_DTYPE_XXX defines.
*
* @param pDesc Pointer to descriptor union.
* @thread E1000_TX
*/
{
return E1K_DTYP_LEGACY;
}
/**
* Dump receive descriptor to debug log.
*
* @param pState The device state structure.
* @param pDesc Pointer to the descriptor.
* @thread E1000_RX
*/
{
E1kLog2((" Address=%16LX Length=%04X Csum=%04X\n",
E1kLog2((" STA: %s %s %s %s %s %s %s ERR: %s %s %s %s SPECIAL: %s VLAN=%03x PRI=%x\n",
}
/**
* Dump transmit descriptor to debug log.
*
* @param pState The device state structure.
* @param pDesc Pointer to descriptor union.
* @param cszDir A string denoting direction of descriptor transfer
* @thread E1000_TX
*/
{
switch (e1kGetDescType(pDesc))
{
case E1K_DTYP_CONTEXT:
E1kLog2(("%s %s Context Transmit Descriptor %s\n",
E1kLog2((" IPCSS=%02X IPCSO=%02X IPCSE=%04X TUCSS=%02X TUCSO=%02X TUCSE=%04X\n",
E1kLog2((" TUCMD:%s%s%s %s %s PAYLEN=%04x HDRLEN=%04x MSS=%04x STA: %s\n",
break;
case E1K_DTYP_DATA:
E1kLog2(("%s %s Data Transmit Descriptor (%d bytes) %s\n",
E1kLog2((" Address=%16LX DTALEN=%05X\n",
E1kLog2((" DCMD:%s%s%s%s%s%s STA:%s%s%s POPTS:%s%s SPECIAL:%s VLAN=%03x PRI=%x\n",
break;
case E1K_DTYP_LEGACY:
E1kLog2(("%s %s Legacy Transmit Descriptor (%d bytes) %s\n",
E1kLog2((" Address=%16LX DTALEN=%05X\n",
E1kLog2((" CMD:%s%s%s%s%s%s STA:%s%s%s CSO=%02x CSS=%02x SPECIAL:%s VLAN=%03x PRI=%x\n",
break;
default:
E1kLog(("%s %s Invalid Transmit Descriptor %s\n",
break;
}
}
#endif /* IN_RING3 */
/**
* Hardware reset. Revert all registers to initial values.
*
* @param pState The device state structure.
*/
{
}
/**
* Raise interrupt if not masked.
*
* @param pState The device state structure.
*/
{
return rc;
ICR |= u32IntCause;
{
#if 0
if (pState->fDelayInts)
{
E1kLog2(("%s e1kRaiseInterrupt: Delayed. ICR=%08x\n",
#define E1K_LOST_IRQ_THRSLD 20
//#define E1K_LOST_IRQ_THRSLD 200000000
{
E1kLog2(("%s WARNING! Disabling delayed interrupt logic: delayed=%d, delivered=%d\n",
pState->fIntMaskUsed = false;
pState->uStatDisDly++;
}
}
else
#endif
if (pState->fIntRaised)
{
E1kLog2(("%s e1kRaiseInterrupt: Already raised, skipped. ICR&IMS=%08x\n",
}
else
{
#ifdef E1K_ITR_ENABLED
/* interrupts/sec = 1 / (256 * 10E-9 * ITR) */
E1kLog2(("%s e1kRaiseInterrupt: tstamp - pState->u64AckedAt = %d, ITR * 256 = %d\n",
{
E1kLog2(("%s e1kRaiseInterrupt: Too early to raise again: %d ns < %d ns.\n",
}
else
#endif
{
/* Since we are delivering the interrupt now
* there is no need to do it later -- stop the timer.
*/
/* Got at least one unmasked interrupt cause */
pState->fIntRaised = true;
/* Raise(1) INTA(0) */
//PDMDevHlpPCISetIrqNoWait(pState->CTXSUFF(pInst), 0, 1);
//e1kMutexRelease(pState);
//e1kMutexAcquire(pState, RT_SRC_POS);
E1kLog(("%s e1kRaiseInterrupt: Raised. ICR&IMS=%08x\n",
}
}
}
else
{
E1kLog2(("%s e1kRaiseInterrupt: Not raising, ICR=%08x, IMS=%08x\n",
}
return VINF_SUCCESS;
}
#ifdef IN_RING3
/**
* Compute the physical address of the descriptor.
*
* @returns the physical address of the descriptor.
*
* @param baseHigh High-order 32 bits of descriptor table address.
* @param baseLow Low-order 32 bits of descriptor table address.
* @param idxDesc The descriptor index in the table.
*/
{
}
/**
* Advance the head pointer of the receive descriptor queue.
*
* @remarks RDH always points to the next available RX descriptor.
*
* @param pState The device state structure.
*/
{
//e1kCsEnter(pState, RT_SRC_POS);
RDH = 0;
/*
* Compute current recieve queue length and fire RXDMT0 interrupt
* if we are low on recieve buffers
*/
/*
* The minimum threshold is controlled by RDMTS bits of RCTL:
* 00 = 1/2 of RDLEN
* 01 = 1/4 of RDLEN
* 10 = 1/8 of RDLEN
* 11 = reserved
*/
if (uRQueueLen <= uMinRQThreshold)
{
E1kLogRel(("E1000: low on RX descriptors, RDH=%x RDT=%x len=%x threshold=%x\n", RDH, RDT, uRQueueLen, uMinRQThreshold));
E1kLog2(("%s Low on RX descriptors, RDH=%x RDT=%x len=%x threshold=%x, raise an interrupt\n",
}
//e1kCsLeave(pState);
}
/**
* Store a fragment of received packet that fits into the next available RX
* buffer.
*
* @remarks Trigger the RXT0 interrupt if it is the last fragment of the packet.
*
* @param pState The device state structure.
* @param pDesc The next available RX descriptor.
* @param pvBuf The fragment.
* @param cb The size of the fragment.
*/
static DECLCALLBACK(void) e1kStoreRxFragment(E1KSTATE *pState, E1KRXDESC *pDesc, const void *pvBuf, size_t cb)
{
E1kLog2(("%s e1kStoreRxFragment: store fragment of %04X at %016LX, EOP=%d\n", pState->szInstance, cb, pDesc->u64BufAddr, pDesc->status.fEOP));
/* Write back the descriptor */
PDMDevHlpPhysWrite(pState->CTX_SUFF(pDevIns), e1kDescAddr(RDBAH, RDBAL, RDH), pDesc, sizeof(E1KRXDESC));
/* Advance head */
//E1kLog2(("%s e1kStoreRxFragment: EOP=%d RDTR=%08X RADV=%08X\n", INSTANCE(pState), pDesc->fEOP, RDTR, RADV));
{
/* Complete packet has been stored -- it is time to let the guest know. */
#ifdef E1K_USE_RX_TIMERS
if (RDTR)
{
/* Arm the timer to fire in RDTR usec (discard .024) */
/* If absolute timer delay is enabled and the timer is not running yet, arm it. */
}
else
{
#endif
/* 0 delay means immediate interrupt */
#ifdef E1K_USE_RX_TIMERS
}
#endif
}
}
/**
* Returns true if it is a broadcast packet.
*
* @returns true if destination address indicates broadcast.
* @param pvBuf The ethernet packet.
*/
{
}
/**
* Returns true if it is a multicast packet.
*
* @remarks returns true for broadcast packets as well.
* @returns true if destination address indicates multicast.
* @param pvBuf The ethernet packet.
*/
{
return (*(char*)pvBuf) & 1;
}
/**
* Pad and store received packet.
*
* @remarks Make sure that the packet appears to upper layer as one coming
* from real Ethernet: pad it and insert FCS.
*
* @returns VBox status code.
* @param pState The device state structure.
* @param pvBuf The available data.
* @param cb Number of bytes available in the buffer.
* @param status Bit fields containing status info.
*/
{
#ifndef E1K_GLOBAL_MUTEX
return rc;
#endif
#ifdef E1K_LEDS_WITH_MUTEX
{
#endif /* E1K_LEDS_WITH_MUTEX */
#ifdef E1K_LEDS_WITH_MUTEX
}
#endif /* E1K_LEDS_WITH_MUTEX */
/* Pad short packets */
if (cb < 60)
cb = 60;
if (!(RCTL & RCTL_SECRC))
{
/* Add FCS if CRC stripping is not enabled */
}
/* Compute checksum of complete packet */
/* Update stats */
if (e1kIsBroadcast(pvBuf))
else if (e1kIsMulticast(pvBuf))
/* Update octet receive counter */
if (cb == 64)
else if (cb < 128)
else if (cb < 256)
else if (cb < 512)
else if (cb < 1024)
else
{
E1kLog(("%s Out of recieve buffers, dropping the packet",
}
/* Store the packet to receive buffers */
{
/* Load the desciptor pointed by head */
if (desc.u64BufAddr)
{
/* Update descriptor */
//desc.fIXSM = true;
//desc.status.fIPE = false;
//desc.status.fTCPE = false;
/*
* We need to leave Rx critical section here or we risk deadlocking
* with EMT in e1kRegWriteRDT when the write is to an unallocated
* page or has an access handler associated with it.
* Note that it is safe to leave the critical section here since e1kRegWriteRDT()
* modifies RDT only.
*/
{
return rc;
}
else
{
#ifdef E1K_LEDS_WITH_MUTEX
{
#endif /* E1K_LEDS_WITH_MUTEX */
#ifdef E1K_LEDS_WITH_MUTEX
}
#endif /* E1K_LEDS_WITH_MUTEX */
return VINF_SUCCESS;
}
/* Note: RDH is advanced by e1kStoreRxFragment! */
}
else
{
}
}
#ifdef E1K_LEDS_WITH_MUTEX
{
#endif /* E1K_LEDS_WITH_MUTEX */
#ifdef E1K_LEDS_WITH_MUTEX
}
#endif /* E1K_LEDS_WITH_MUTEX */
return VINF_SUCCESS;
}
#endif /* IN_RING3 */
#if 0 /* unused */
/**
* Read handler for Device Status register.
*
* Get the link status from PHY.
*
* @returns VBox status code.
*
* @param pState The device state structure.
* @param offset Register offset in memory-mapped frame.
* @param index Register index in register array.
* @param mask Used to implement partial reads (8 and 16-bit).
*/
{
E1kLog(("%s e1kRegReadCTRL: mdio dir=%s mdc dir=%s mdc=%d\n",
{
/* MDC is high and MDIO pin is used for input, read MDIO pin from PHY */
else
E1kLog(("%s e1kRegReadCTRL: Phy::readMDIO(%d)\n",
}
else
{
/* MDIO pin is used for output, ignore it */
}
return VINF_SUCCESS;
}
#endif /* unused */
/**
* Write handler for Device Control register.
*
* Handles reset.
*
* @param pState The device state structure.
* @param offset Register offset in memory-mapped frame.
* @param index Register index in register array.
* @param value The value to store.
* @param mask Used to implement partial writes (8 and 16-bit).
* @thread EMT
*/
{
int rc = VINF_SUCCESS;
if (value & CTRL_RESET)
{ /* RST */
}
else
{
{
/* The driver indicates that we should bring up the link */
}
{
}
E1kLog(("%s e1kRegWriteCTRL: mdio dir=%s mdc dir=%s mdc=%s mdio=%d\n",
{
if (value & CTRL_MDIO_DIR)
{
/* MDIO direction pin is set to output and MDC is high, write MDIO pin value to PHY */
}
else
{
else
E1kLog(("%s e1kRegWriteCTRL: Phy::readMDIO(%d)\n",
}
}
}
return rc;
}
/**
*
* Handles EEPROM access requests; forwards writes to EEPROM device if access has been granted.
*
* @param pState The device state structure.
* @param offset Register offset in memory-mapped frame.
* @param index Register index in register array.
* @param value The value to store.
* @param mask Used to implement partial writes (8 and 16-bit).
* @thread EMT
*/
{
#ifdef IN_RING3
/* So far we are conserned with lower byte only */
{
/* Access to EEPROM granted -- forward 4-wire bits to EEPROM device */
/* Note: 82543GC does not need to request EEPROM access */
}
if (value & EECD_EE_REQ)
else
EECD &= ~EECD_EE_GNT;
//e1kRegWriteDefault(pState, offset, index, value );
return VINF_SUCCESS;
#else /* !IN_RING3 */
return VINF_IOM_HC_MMIO_WRITE;
#endif /* !IN_RING3 */
}
/**
*
* Lower 4 bits come from EEPROM device if EEPROM access has been granted.
*
* @returns VBox status code.
*
* @param pState The device state structure.
* @param offset Register offset in memory-mapped frame.
* @param index Register index in register array.
* @param mask Used to implement partial reads (8 and 16-bit).
* @thread EMT
*/
{
#ifdef IN_RING3
if (RT_SUCCESS(rc))
{
{
/* Note: 82543GC does not need to request EEPROM access */
/* Access to EEPROM granted -- get 4-wire bits to EEPROM device */
}
}
return rc;
#else /* !IN_RING3 */
return VINF_IOM_HC_MMIO_READ;
#endif /* !IN_RING3 */
}
/**
* Write handler for MDI Control register.
*
*
* @param pState The device state structure.
* @param offset Register offset in memory-mapped frame.
* @param index Register index in register array.
* @param value The value to store.
* @param mask Used to implement partial writes (8 and 16-bit).
* @thread EMT
*/
{
if (value & MDIC_INT_EN)
{
E1kLog(("%s ERROR! Interrupt at the end of an MDI cycle is not supported yet.\n",
}
else if (value & MDIC_READY)
{
E1kLog(("%s ERROR! Ready bit is not reset by software during write operation.\n",
}
{
E1kLog(("%s ERROR! Access to invalid PHY detected, phy=%d.\n",
}
else
{
/* Store the value */
/* Forward op to PHY */
if (value & MDIC_OP_READ)
else
/* Let software know that we are done */
MDIC |= MDIC_READY;
}
return VINF_SUCCESS;
}
/**
* Write handler for Interrupt Cause Read register.
*
* Bits corresponding to 1s in 'value' will be cleared in ICR register.
*
* @param pState The device state structure.
* @param offset Register offset in memory-mapped frame.
* @param index Register index in register array.
* @param value The value to store.
* @param mask Used to implement partial writes (8 and 16-bit).
* @thread EMT
*/
{
return VINF_SUCCESS;
}
/**
* Read handler for Interrupt Cause Read register.
*
* Reading this register acknowledges all interrupts.
*
* @returns VBox status code.
*
* @param pState The device state structure.
* @param offset Register offset in memory-mapped frame.
* @param index Register index in register array.
* @param mask Not used.
* @thread EMT
*/
{
return rc;
if (RT_SUCCESS(rc))
{
if (value)
{
if (IMS)
{
/*
* Interrupts were enabled -- we are supposedly at the very
* beginning of interrupt handler
*/
/* Clear all pending interrupts */
ICR = 0;
pState->fIntRaised = false;
/* Lower(0) INTA(0) */
//PDMDevHlpPCISetIrqNoWait(pState->CTX_SUFF(pDevIns), 0, 0);
//e1kMutexRelease(pState);
//e1kMutexAcquire(pState, RT_SRC_POS);
if (pState->fIntMaskUsed)
pState->fDelayInts = true;
}
else
{
/*
* Interrupts are disabled -- in windows guests ICR read is done
* just before re-enabling interrupts
*/
E1kLog(("%s e1kRegReadICR: Suppressing auto-clear due to disabled interrupts (%08x)\n", INSTANCE(pState), ICR));
}
}
}
return rc;
}
/**
* Write handler for Interrupt Cause Set register.
*
* Bits corresponding to 1s in 'value' will be set in ICR register.
*
* @param pState The device state structure.
* @param offset Register offset in memory-mapped frame.
* @param index Register index in register array.
* @param value The value to store.
* @param mask Used to implement partial writes (8 and 16-bit).
* @thread EMT
*/
{
}
/**
* Write handler for Interrupt Mask Set register.
*
* Will trigger pending interrupts.
*
* @param pState The device state structure.
* @param offset Register offset in memory-mapped frame.
* @param index Register index in register array.
* @param value The value to store.
* @param mask Used to implement partial writes (8 and 16-bit).
* @thread EMT
*/
{
/* Mask changes, we need to raise pending interrupts. */
{
E1kLog2(("%s e1kRegWriteIMS: IRQ pending (%08x), arming late int timer...\n",
//TMTimerSet(pState->CTX_SUFF(pIntTimer), TMTimerFromNano(pState->CTX_SUFF(pIntTimer), ITR * 256) +
// TMTimerGet(pState->CTX_SUFF(pIntTimer)));
}
return VINF_SUCCESS;
}
/**
* Write handler for Interrupt Mask Clear register.
*
* Bits corresponding to 1s in 'value' will be cleared in IMS register.
*
* @param pState The device state structure.
* @param offset Register offset in memory-mapped frame.
* @param index Register index in register array.
* @param value The value to store.
* @param mask Used to implement partial writes (8 and 16-bit).
* @thread EMT
*/
{
return rc;
if (pState->fIntRaised)
{
/*
* Technically we should reset fIntRaised in ICR read handler, but it will cause
* Windows to freeze since it may receive an interrupt while still in the very beginning
* of interrupt handler.
*/
/* Lower(0) INTA(0) */
pState->fIntRaised = false;
}
return VINF_SUCCESS;
}
/**
* Write handler for Receive Control register.
*
* @param pState The device state structure.
* @param offset Register offset in memory-mapped frame.
* @param index Register index in register array.
* @param value The value to store.
* @param mask Used to implement partial writes (8 and 16-bit).
* @thread EMT
*/
{
E1kLog2(("%s e1kRegWriteRCTL: Setting receive buffer size to %d\n",
return VINF_SUCCESS;
}
/**
* Write handler for Packet Buffer Allocation register.
*
* TXA = 64 - RXA.
*
* @param pState The device state structure.
* @param offset Register offset in memory-mapped frame.
* @param index Register index in register array.
* @param value The value to store.
* @param mask Used to implement partial writes (8 and 16-bit).
* @thread EMT
*/
{
return VINF_SUCCESS;
}
/**
* Write handler for Receive Descriptor Tail register.
*
* @remarks Write into RDT forces switch to HC and signal to
* e1kWaitReceiveAvail().
*
* @returns VBox status code.
*
* @param pState The device state structure.
* @param offset Register offset in memory-mapped frame.
* @param index Register index in register array.
* @param value The value to store.
* @param mask Used to implement partial writes (8 and 16-bit).
* @thread EMT
*/
{
#ifndef IN_RING3
/* XXX */
// return VINF_IOM_HC_MMIO_WRITE;
#endif
{
if (RT_SUCCESS(rc))
{
#ifdef IN_RING3
/* Signal that we have more receive descriptors avalable. */
#else
if (pItem)
#endif
}
}
return rc;
}
/**
* Write handler for Receive Delay Timer register.
*
* @param pState The device state structure.
* @param offset Register offset in memory-mapped frame.
* @param index Register index in register array.
* @param value The value to store.
* @param mask Used to implement partial writes (8 and 16-bit).
* @thread EMT
*/
{
{
/* Flush requested, cancel both timers and raise interrupt */
#ifdef E1K_USE_RX_TIMERS
#endif
}
return VINF_SUCCESS;
}
{
/**
* Make sure TDT won't change during computation. EMT may modify TDT at
* any moment.
*/
}
#ifdef IN_RING3
#ifdef E1K_USE_TX_TIMERS
/**
* Transmit Interrupt Delay Timer handler.
*
* @remarks We only get here when the timer expires.
*
* @param pDevIns Pointer to device instance structure.
* @param pTimer Pointer to the timer.
* @param pvUser NULL.
* @thread EMT
*/
{
{
/* Cancel absolute delay timer as we have already got attention */
#ifndef E1K_NO_TAD
#endif /* E1K_NO_TAD */
}
}
/**
* Transmit Absolute Delay Timer handler.
*
* @remarks We only get here when the timer expires.
*
* @param pDevIns Pointer to device instance structure.
* @param pTimer Pointer to the timer.
* @param pvUser NULL.
* @thread EMT
*/
{
{
/* Cancel interrupt delay timer as we have already got attention */
}
}
#endif /* E1K_USE_TX_TIMERS */
#ifdef E1K_USE_RX_TIMERS
/**
* Receive Interrupt Delay Timer handler.
*
* @remarks We only get here when the timer expires.
*
* @param pDevIns Pointer to device instance structure.
* @param pTimer Pointer to the timer.
* @param pvUser NULL.
* @thread EMT
*/
{
{
/* Cancel absolute delay timer as we have already got attention */
}
}
/**
* Receive Absolute Delay Timer handler.
*
* @remarks We only get here when the timer expires.
*
* @param pDevIns Pointer to device instance structure.
* @param pTimer Pointer to the timer.
* @param pvUser NULL.
* @thread EMT
*/
{
{
/* Cancel interrupt delay timer as we have already got attention */
}
}
#endif /* E1K_USE_RX_TIMERS */
/**
* Late Interrupt Timer handler.
*
* @param pDevIns Pointer to device instance structure.
* @param pTimer Pointer to the timer.
* @param pvUser NULL.
* @thread EMT
*/
{
{
#if 0
pState->iStatIntLost--;
#endif
}
}
/**
* Link Up Timer handler.
*
* @param pDevIns Pointer to device instance structure.
* @param pTimer Pointer to the timer.
* @param pvUser NULL.
* @thread EMT
*/
{
{
}
}
/**
* Load transmit descriptor from guest memory.
*
* @param pState The device state structure.
* @param pDesc Pointer to descriptor union.
* @param addr Physical address in guest context.
* @thread E1000_TX
*/
{
}
/**
* Write back transmit descriptor to guest memory.
*
* @param pState The device state structure.
* @param pDesc Pointer to descriptor union.
* @param addr Physical address in guest context.
* @thread E1000_TX
*/
{
/* Only the last half of the descriptor has to be written back. */
}
/**
* Transmit complete frame.
*
* @remarks Since we do not have real Ethernet medium between us and NAT (or
* another connector) there is no need for padding and FCS.
*
* @param pState The device state structure.
* @param pFrame Pointer to the frame buffer.
* @param u16FrameLen Length of the frame.
* @thread E1000_TX
*/
{
/* E1kLog2(("%s <<< Outgoing packet. Dump follows: >>>\n"
"%.*Rhxd\n"
"%s <<<<<<<<<<<<< End of dump >>>>>>>>>>>>\n",
INSTANCE(pState), u16FrameLen, pFrame, INSTANCE(pState)));*/
#ifdef E1K_LEDS_WITH_MUTEX
{
#endif /* E1K_LEDS_WITH_MUTEX */
#ifdef E1K_LEDS_WITH_MUTEX
}
#endif /* E1K_LEDS_WITH_MUTEX */
/* Update the stats */
if (e1kIsBroadcast(pFrame))
else if (e1kIsMulticast(pFrame))
/* Update octet transmit counter */
{
}
if (u16FrameLen == 64)
else if (u16FrameLen < 128)
else if (u16FrameLen < 256)
else if (u16FrameLen < 512)
else if (u16FrameLen < 1024)
else
{
/* Loopback mode */
}
{
/* Release critical section to avoid deadlock in CanReceive */
//e1kCsLeave(pState);
if (rc != VINF_SUCCESS)
{
}
//e1kCsEnter(pState, RT_SRC_POS);
}
#ifdef E1K_LEDS_WITH_MUTEX
{
#endif /* E1K_LEDS_WITH_MUTEX */
#ifdef E1K_LEDS_WITH_MUTEX
}
#endif /* E1K_LEDS_WITH_MUTEX */
}
/**
* Compute and write checksum at the specified offset.
*
* @param pState The device state structure.
* @param pPkt Pointer to the packet.
* @param u16PktLen Total length of the packet.
* @param cso Offset in packet to write checksum at.
* @param css Offset in packet to start computing
* checksum from.
* @param cse Offset in packet to stop computing
* checksum at.
* @thread E1000_TX
*/
static void e1kInsertChecksum(E1KSTATE* pState, uint8_t *pPkt, uint16_t u16PktLen, uint8_t cso, uint8_t css, uint16_t cse)
{
{
E1kLog2(("%s cso(%X) is greater than packet length(%X), checksum is not inserted\n",
return;
}
if (cse == 0)
}
/**
* Add a part of descriptor's buffer to transmit frame.
*
* @remarks data.u64BufAddr is used uncoditionally for both data
* and legacy descriptors since it is identical to
* legacy.u64BufAddr.
*
* @param pState The device state structure.
* @param pDesc Pointer to the descriptor to transmit.
* @param u16Len Length of buffer to the end of segment.
* @param fSend Force packet sending.
* @thread E1000_TX
*/
{
/* TCP header being transmitted */
/* IP header being transmitted */
E1kLog3(("%s e1kAddSegment: Length=%x, remaining payload=%x, header=%x, send=%s\n",
E1kLog3(("%s Dump of the segment:\n"
"%.*Rhxd\n"
"%s --- End of dump ---\n",
E1kLog3(("%s e1kAddSegment: pState->u16TxPktLen=%x\n",
if (pState->u16HdrRemain > 0)
{
/* The header was not complete, check if it is now */
{
/* The rest is payload */
pState->u16HdrRemain = 0;
/* Save partial checksum and flags */
/* Clear FIN and PSH flags now and set them only in the last segment */
}
else
{
/* Still not */
E1kLog3(("%s e1kAddSegment: Header is still incomplete, 0x%x bytes remain.\n",
return;
}
}
if (fSend)
{
/* Leave ethernet header intact */
/* IP Total Length = payload + headers - ethernet header */
E1kLog3(("%s e1kAddSegment: End of packet, pIpHdr->total_len=%x\n",
/* Update IP Checksum */
/* Update TCP flags */
/* Restore original FIN and PSH flags for the last segment */
if (pState->u32PayRemain == 0)
{
}
/* Add TCP length to partial pseudo header sum */
while (csum >> 16)
/* Compute final checksum */
/* Update Sequence Number */
/* Increment IP identification */
}
}
/**
* Add descriptor's buffer to transmit frame.
*
* @remarks data.u64BufAddr is used uncoditionally for both data
* and legacy descriptors since it is identical to
* legacy.u64BufAddr.
*
* @param pState The device state structure.
* @param pDesc Pointer to the descriptor to transmit.
* @param u16PartLen Length of descriptor's buffer.
* @thread E1000_TX
*/
{
{
Assert(u16MaxPktLen != 0);
do {
/* Calculate how many bytes have left in this TCP segment */
if (uLen > u32PartLen)
{
/* This descriptor fits completely into current segment */
uLen = u32PartLen;
}
else
{
/*
* Rewind the packet tail pointer to the beginning of payload,
* so we continue writing right beyond the header.
*/
}
u32PartLen -= uLen;
} while (u32PartLen > 0);
{
/* End of packet, next segment will contain header. */
pState->u16TxPktLen = 0;
}
return false;
}
else
{
{
E1kLog(("%s Transmit packet is too large: %d > %d(max)\n",
return false;
}
else
{
PDMDevHlpPhysRead(pState->CTX_SUFF(pDevIns), pDesc->data.u64BufAddr, pState->aTxPacket + pState->u16TxPktLen, u32PartLen);
}
}
return true;
}
/**
* Write the descriptor back to guest memory and notify the guest.
*
* @param pState The device state structure.
* @param pDesc Pointer to the descriptor have been transmited.
* @param addr Physical address of the descriptor in guest memory.
* @thread E1000_TX
*/
{
/*
* We fake descriptor write-back bursting. Descriptors are written back as they are
* processed.
*/
/* Let's pretend we process descriptors. Write back with DD set. */
{
{
#ifdef E1K_USE_TX_TIMERS
{
//if (pState->fIntRaised)
//{
// /* Interrupt is already pending, no need for timers */
// ICR |= ICR_TXDW;
//}
//else {
/* Arm the timer to fire in TIVD usec (discard .024) */
#ifndef E1K_NO_TAD
/* If absolute timer delay is enabled and the timer is not running yet, arm it. */
E1kLog2(("%s Checking if TAD timer is running\n",
#endif /* E1K_NO_TAD */
}
else
{
E1kLog2(("%s No IDE set, cancel TAD timer and raise interrupt\n",
#ifndef E1K_NO_TAD
/* Cancel both timers if armed and fire immediately. */
#endif /* E1K_NO_TAD */
#endif /* E1K_USE_TX_TIMERS */
#ifdef E1K_USE_TX_TIMERS
}
#endif /* E1K_USE_TX_TIMERS */
}
}
else
{
}
}
/**
* Process Transmit Descriptor.
*
* E1000 supports three types of transmit descriptors:
* - legacy data descriptors of older format (context-less).
* - data the same as legacy but providing new offloading capabilities.
* - context sets up the context for following data descriptors.
*
* @param pState The device state structure.
* @param pDesc Pointer to descriptor union.
* @param addr Physical address of descriptor in guest memory.
* @thread E1000_TX
*/
{
#ifdef E1K_USE_TX_TIMERS
#endif /* E1K_USE_TX_TIMERS */
switch (e1kGetDescType(pDesc))
{
case E1K_DTYP_CONTEXT:
{
}
else
E1kLog2(("%s %s context updated: IP CSS=%02X, IP CSO=%02X, IP CSE=%04X"
break;
case E1K_DTYP_DATA:
{
break;
}
&pState->StatTxDescData);
/* IXSM and TXSM options are valid in the first fragment only */
if (pState->u16TxPktLen == 0)
{
}
{
{
/*
* We only insert checksums here if this packet was not segmented,
* otherwise it has already been taken care of by e1kAddSegment().
*/
}
/* Reset transmit packet storage. */
pState->u16TxPktLen = 0;
}
break;
case E1K_DTYP_LEGACY:
{
break;
}
{
/** @todo Offload processing goes here. */
{
/* Reset transmit packet storage. */
pState->u16TxPktLen = 0;
}
}
break;
default:
E1kLog(("%s ERROR Unsupported transmit descriptor type: 0x%04x\n",
break;
}
}
/**
* Wake up callback for transmission thread.
*
* @returns VBox status code. Returning failure will naturally terminate the thread.
* @param pDevIns The pcnet device instance.
* @param pThread The thread.
*/
{
return VINF_SUCCESS;
}
/**
* I/O thread for packet transmission.
*
* @returns VBox status code. Returning failure will naturally terminate the thread.
* @param pDevIns Pointer to device instance structure.
* @param pThread The thread.
* @thread E1000_TX
*/
{
{
break;
{
/* Do not process descriptors in locked state */
{
E1kLog3(("%s About to process new TX descriptor at %08x%08x, TDLEN=%08x, TDH=%08x, TDT=%08x\n",
//if (!e1kCsEnter(pState, RT_SRC_POS))
// return VERR_PERMISSION_DENIED;
TDH = 0;
{
E1kLog2(("%s Low on transmit descriptors, raise ICR.TXD_LOW, len=%x thresh=%x\n",
}
//e1kCsLeave(pState);
}
/// @todo: uncomment: pState->uStatIntTXQE++;
/// @todo: uncomment: e1kRaiseInterrupt(pState, ICR_TXQE);
}
}
return VINF_SUCCESS;
}
/**
* Callback for consuming from transmit queue. It gets called in R3 whenever
*
* @returns true
* @param pDevIns Pointer to device instance structure.
* @param pItem Pointer to the element being dequeued (not used).
* @thread ???
*/
{
return true;
}
/**
* Handler for the wakeup signaller queue.
*/
{
return true;
}
#endif /* IN_RING3 */
/**
* Write handler for Transmit Descriptor Tail register.
*
* @param pState The device state structure.
* @param offset Register offset in memory-mapped frame.
* @param index Register index in register array.
* @param value The value to store.
* @param mask Used to implement partial writes (8 and 16-bit).
* @thread EMT
*/
{
#ifndef IN_RING3
// return VINF_IOM_HC_MMIO_WRITE;
#endif
return rc;
/* All descriptors starting with head and not including tail belong to us. */
/* Process them. */
E1kLog2(("%s e1kRegWriteTDT: TDBAL=%08x, TDBAH=%08x, TDLEN=%08x, TDH=%08x, TDT=%08x\n",
/* Ignore TDT writes when the link is down. */
{
E1kLog(("%s e1kRegWriteTDT: %d descriptors to process, waking up E1000_TX thread\n",
#ifdef IN_RING3
#else
if (RT_UNLIKELY(pItem))
#endif /* !IN_RING3 */
}
return rc;
}
/**
* Write handler for Multicast Table Array registers.
*
* @param pState The device state structure.
* @param offset Register offset in memory-mapped frame.
* @param index Register index in register array.
* @param value The value to store.
* @thread EMT
*/
{
return VINF_SUCCESS;
}
/**
* Read handler for Multicast Table Array registers.
*
* @returns VBox status code.
*
* @param pState The device state structure.
* @param offset Register offset in memory-mapped frame.
* @param index Register index in register array.
* @thread EMT
*/
{
return VINF_SUCCESS;
}
/**
* Write handler for Receive Address registers.
*
* @param pState The device state structure.
* @param offset Register offset in memory-mapped frame.
* @param index Register index in register array.
* @param value The value to store.
* @thread EMT
*/
{
AssertReturn(offset - s_e1kRegMap[index].offset < sizeof(pState->aRecAddr.au32), VERR_DEV_IO_ERROR);
pState->aRecAddr.au32[(offset - s_e1kRegMap[index].offset)/sizeof(pState->aRecAddr.au32[0])] = value;
return VINF_SUCCESS;
}
/**
* Read handler for Receive Address registers.
*
* @returns VBox status code.
*
* @param pState The device state structure.
* @param offset Register offset in memory-mapped frame.
* @param index Register index in register array.
* @thread EMT
*/
{
*pu32Value = pState->aRecAddr.au32[(offset - s_e1kRegMap[index].offset)/sizeof(pState->aRecAddr.au32[0])];
return VINF_SUCCESS;
}
/**
* Write handler for VLAN Filter Table Array registers.
*
* @param pState The device state structure.
* @param offset Register offset in memory-mapped frame.
* @param index Register index in register array.
* @param value The value to store.
* @thread EMT
*/
{
return VINF_SUCCESS;
}
/**
* Read handler for VLAN Filter Table Array registers.
*
* @returns VBox status code.
*
* @param pState The device state structure.
* @param offset Register offset in memory-mapped frame.
* @param index Register index in register array.
* @thread EMT
*/
{
return VINF_SUCCESS;
}
/**
* Read handler for unimplemented registers.
*
* Merely reports reads from unimplemented registers.
*
* @returns VBox status code.
*
* @param pState The device state structure.
* @param offset Register offset in memory-mapped frame.
* @param index Register index in register array.
* @thread EMT
*/
static int e1kRegReadUnimplemented(E1KSTATE* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value)
{
E1kLog(("%s At %08X read (00000000) attempt from unimplemented register %s (%s)\n",
*pu32Value = 0;
return VINF_SUCCESS;
}
/**
* Default register read handler with automatic clear operation.
*
* Retrieves the value of register from register array in device state structure.
* Then resets all bits.
*
* @remarks The 'mask' parameter is simply ignored as masking and shifting is
* done in the caller.
*
* @returns VBox status code.
*
* @param pState The device state structure.
* @param offset Register offset in memory-mapped frame.
* @param index Register index in register array.
* @thread EMT
*/
static int e1kRegReadAutoClear(E1KSTATE* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value)
{
return rc;
}
/**
* Default register read handler.
*
* Retrieves the value of register from register array in device state structure.
* Bits corresponding to 0s in 'readable' mask will always read as 0s.
*
* @remarks The 'mask' parameter is simply ignored as masking and shifting is
* done in the caller.
*
* @returns VBox status code.
*
* @param pState The device state structure.
* @param offset Register offset in memory-mapped frame.
* @param index Register index in register array.
* @thread EMT
*/
static int e1kRegReadDefault(E1KSTATE* pState, uint32_t offset, uint32_t index, uint32_t *pu32Value)
{
return VINF_SUCCESS;
}
/**
* Write handler for unimplemented registers.
*
* Merely reports writes to unimplemented registers.
*
* @param pState The device state structure.
* @param offset Register offset in memory-mapped frame.
* @param index Register index in register array.
* @param value The value to store.
* @thread EMT
*/
static int e1kRegWriteUnimplemented(E1KSTATE* pState, uint32_t offset, uint32_t index, uint32_t value)
{
E1kLog(("%s At %08X write attempt (%08X) to unimplemented register %s (%s)\n",
return VINF_SUCCESS;
}
/**
* Default register write handler.
*
* Stores the value to the register array in device state structure. Only bits
* corresponding to 1s both in 'writable' and 'mask' will be stored.
*
* @returns VBox status code.
*
* @param pState The device state structure.
* @param offset Register offset in memory-mapped frame.
* @param index Register index in register array.
* @param value The value to store.
* @param mask Used to implement partial writes (8 and 16-bit).
* @thread EMT
*/
{
return VINF_SUCCESS;
}
/**
* Search register table for matching register.
*
* @returns Index in the register table or -1 if not found.
*
* @param pState The device state structure.
* @param uOffset Register offset in memory-mapped region.
* @thread EMT
*/
{
int index;
{
if (s_e1kRegMap[index].offset <= uOffset && uOffset < s_e1kRegMap[index].offset + s_e1kRegMap[index].size)
{
return index;
}
}
return -1;
}
/**
* Handle register read operation.
*
* Looks up and calls appropriate handler.
*
* @returns VBox status code.
*
* @param pState The device state structure.
* @param uOffset Register offset in memory-mapped frame.
* @param pv Where to store the result.
* @param cb Number of bytes to read.
* @thread EMT
*/
{
int rc = VINF_SUCCESS;
#ifdef DEBUG
char buf[9];
#endif
/*
* From the spec:
* For registers that should be accessed as 32-bit double words, partial writes (less than a 32-bit
* double word) is ignored. Partial reads return all 32 bits of data regardless of the byte enables.
*/
/*
* To be able to write bytes and short word we convert them
* to properly shifted 32-bit words and masks. The idea is
* to keep register-specific handlers simple. Most accesses
* will be 32-bit anyway.
*/
switch (cb)
{
default:
"%s e1kRegRead: unsupported op size: offset=%#10x cb=%#10x\n",
}
if (index != -1)
{
{
/* Make the mask correspond to the bits we are about to read. */
if (!mask)
"%s e1kRegRead: Zero mask: offset=%#10x cb=%#10x\n",
/*
* Read it. Pass the mask so the handler knows what has to be read.
* Mask out irrelevant bits.
*/
#ifdef E1K_GLOBAL_MUTEX
#else
//rc = e1kCsEnter(pState, VERR_SEM_BUSY, RT_SRC_POS);
#endif
return rc;
//pState->fDelayInts = false;
//pState->iStatIntLost += pState->iStatIntLostOne;
//pState->iStatIntLostOne = 0;
//e1kCsLeave(pState);
E1kLog2(("%s At %08X read %s from %s (%s)\n",
/* Shift back the result. */
}
else
{
E1kLog(("%s At %08X read (%s) attempt from write-only register %s (%s)\n",
}
}
else
{
E1kLog(("%s At %08X read (%s) attempt from non-existing register\n",
}
return rc;
}
/**
* Handle register write operation.
*
* Looks up and calls appropriate handler.
*
* @returns VBox status code.
*
* @param pState The device state structure.
* @param uOffset Register offset in memory-mapped frame.
* @param pv Where to fetch the value.
* @param cb Number of bytes to write.
* @thread EMT
*/
{
int rc = VINF_SUCCESS;
/*
* From the spec:
* For registers that should be accessed as 32-bit double words, partial writes (less than a 32-bit
* double word) is ignored. Partial reads return all 32 bits of data regardless of the byte enables.
*/
if (cb != 4)
{
E1kLog(("%s e1kRegWrite: Spec violation: unsupported op size: offset=%#10x cb=%#10x, ignored.\n",
return VINF_SUCCESS;
}
if (uOffset & 3)
{
E1kLog(("%s e1kRegWrite: Spec violation: misaligned offset: %#10x cb=%#10x, ignored.\n",
return VINF_SUCCESS;
}
if (index != -1)
{
{
/*
* Write it. Pass the mask so the handler knows what has to be written.
* Mask out irrelevant bits.
*/
E1kLog2(("%s At %08X write %08X to %s (%s)\n",
#ifdef E1K_GLOBAL_MUTEX
#else
//rc = e1kCsEnter(pState, VERR_SEM_BUSY, RT_SRC_POS);
#endif
return rc;
//pState->fDelayInts = false;
//pState->iStatIntLost += pState->iStatIntLostOne;
//pState->iStatIntLostOne = 0;
//e1kCsLeave(pState);
}
else
{
E1kLog(("%s At %08X write attempt (%08X) to read-only register %s (%s)\n",
}
}
else
{
E1kLog(("%s At %08X write attempt (%08X) to non-existing register\n",
}
return rc;
}
/**
* I/O handler for memory-mapped read operations.
*
* @returns VBox status code.
*
* @param pDevIns The device instance.
* @param pvUser User argument.
* @param GCPhysAddr Physical address (in GC) where the read starts.
* @param pv Where to store the result.
* @param cb Number of bytes read.
* @thread EMT
*/
{
return rc;
}
/**
* Memory mapped I/O Handler for write operations.
*
* @returns VBox status code.
*
* @param pDevIns The device instance.
* @param pvUser User argument.
* @param GCPhysAddr Physical address (in GC) where the read starts.
* @param pv Where to fetch the value.
* @param cb Number of bytes to write.
* @thread EMT
*/
{
int rc;
if (cb != 4)
{
rc = PDMDeviceDBGFStop(pDevIns, RT_SRC_POS, "e1kMMIOWrite: invalid op size: offset=%#10x cb=%#10x\n", uOffset, cb);
}
else
return rc;
}
/**
* Port I/O Handler for IN operations.
*
* @returns VBox status code.
*
* @param pDevIns The device instance.
* @param pvUser Pointer to the device state structure.
* @param port Port number used for the IN operation.
* @param pu32 Where to store the result.
* @param cb Number of bytes read.
* @thread EMT
*/
{
int rc = VINF_SUCCESS;
if (cb != 4)
{
rc = PDMDeviceDBGFStop(pDevIns, RT_SRC_POS, "%s e1kIOPortIn: invalid op size: port=%RTiop cb=%08x\n", szInst, port, cb);
}
else
switch (port)
{
case 0x00: /* IOADDR */
E1kLog2(("%s e1kIOPortIn: IOADDR(0), selecting register %#010x, val=%#010x\n", szInst, pState->uSelectedReg, *pu32));
break;
case 0x04: /* IODATA */
/* @todo wrong return code triggers assertions in the debug build; fix please */
if (rc == VINF_IOM_HC_MMIO_READ)
E1kLog2(("%s e1kIOPortIn: IODATA(4), reading from selected register %#010x, val=%#010x\n", szInst, pState->uSelectedReg, *pu32));
break;
default:
//*pRC = VERR_IOM_IOPORT_UNUSED;
}
return rc;
}
/**
* Port I/O Handler for OUT operations.
*
* @returns VBox status code.
*
* @param pDevIns The device instance.
* @param pvUser User argument.
* @param Port Port number used for the IN operation.
* @param u32 The value to output.
* @param cb The value size in bytes.
* @thread EMT
*/
{
int rc = VINF_SUCCESS;
if (cb != 4)
{
rc = PDMDeviceDBGFStop(pDevIns, RT_SRC_POS, "%s e1kIOPortOut: invalid op size: port=%RTiop cb=%08x\n", szInst, port, cb);
}
else
{
switch (port)
{
case 0x00: /* IOADDR */
break;
case 0x04: /* IODATA */
E1kLog2(("%s e1kIOPortOut: IODATA(4), writing to selected register %#010x, value=%#010x\n", szInst, pState->uSelectedReg, u32));
/* @todo wrong return code triggers assertions in the debug build; fix please */
if (rc == VINF_IOM_HC_MMIO_WRITE)
break;
default:
/** @todo Do we need to return an error here?
* bird: VINF_SUCCESS is fine for unhandled cases of an OUT handler. (If you're curious
* about the guest code and a bit adventuresome, try rc = PDMDeviceDBGFStop(...);) */
}
}
return rc;
}
#ifdef IN_RING3
/**
* Dump complete device state to log.
*
* @param pState Pointer to device state.
*/
{
for (int i = 0; i<E1K_NUM_OF_32BIT_REGS; ++i)
{
}
#ifdef E1K_INT_STATS
#endif /* E1K_INT_STATS */
}
/**
* Map PCI I/O region.
*
* @return VBox status code.
* @param pPciDev Pointer to PCI device. Use pPciDev->pDevIns to get the device instance.
* @param iRegion The region number.
* @param GCPhysAddress Physical address of the region. If iType is PCI_ADDRESS_SPACE_IO, this is an
* I/O port, else it's a physical address.
* This address is *NOT* relative to pci_mem_base like earlier!
* @param cb Region size.
* @param enmType One of the PCI_ADDRESS_SPACE_* values.
* @thread EMT
*/
{
int rc;
switch (enmType)
{
case PCI_ADDRESS_SPACE_IO:
if (RT_FAILURE(rc))
break;
if (pState->fR0Enabled)
{
if (RT_FAILURE(rc))
break;
}
if (pState->fGCEnabled)
{
}
break;
case PCI_ADDRESS_SPACE_MEM:
if (pState->fR0Enabled)
{
if (RT_FAILURE(rc))
break;
}
if (pState->fGCEnabled)
{
}
break;
default:
/* We should never get here */
AssertMsgFailed(("Invalid PCI address space param in map callback"));
break;
}
return rc;
}
/**
* Check if the device can receive data now.
* This must be called before the pfnRecieve() method is called.
*
* @returns Number of bytes the device can receive.
* @param pInterface Pointer to the interface structure containing the called function pointer.
* @thread EMT
*/
{
return VERR_NET_NO_BUFFER_SPACE;
return VERR_NET_NO_BUFFER_SPACE;
else
{
cb = 0;
E1kLogRel(("E1000: OUT of RX descriptors!\n"));
}
}
{
if (RT_SUCCESS(rc))
return VINF_SUCCESS;
if (RT_UNLIKELY(cMillies == 0))
return VERR_NET_NO_BUFFER_SPACE;
{
if (RT_SUCCESS(rc2))
{
rc = VINF_SUCCESS;
break;
}
E1kLogRel(("E1000 e1kWaitReceiveAvail: waiting cMillies=%u...\n",
cMillies));
E1kLog(("%s e1kWaitReceiveAvail: waiting cMillies=%u...\n",
}
return rc;
}
/**
* Matches the packet addresses against Receive Address table. Looks for
* exact matches only.
*
* @returns true if address matches.
* @param pState Pointer to the state structure.
* @param pvBuf The ethernet packet.
* @param cb Number of bytes available in the packet.
* @thread EMT
*/
{
{
/* Valid address? */
{
//unsigned char *pAddr = (unsigned char*)pvBuf + sizeof(ra->addr)*(ra->ctl & RA_CTL_AS);
//E1kLog3(("%s Matching %02x:%02x:%02x:%02x:%02x:%02x against %02x:%02x:%02x:%02x:%02x:%02x...\n",
// INSTANCE(pState), pAddr[0], pAddr[1], pAddr[2], pAddr[3], pAddr[4], pAddr[5],
// ra->addr[0], ra->addr[1], ra->addr[2], ra->addr[3], ra->addr[4], ra->addr[5]));
/*
* Address Select:
* 00b = Destination address
* 01b = Source address
* 10b = Reserved
* 11b = Reserved
* Since ethernet header is (DA, SA, len) we can use address
* select as index.
*/
return true;
}
}
return false;
}
/**
* Matches the packet addresses against Multicast Table Array.
*
* @remarks This is imperfect match since it matches not exact address but
* a subset of addresses.
*
* @returns true if address matches.
* @param pState Pointer to the state structure.
* @param pvBuf The ethernet packet.
* @param cb Number of bytes available in the packet.
* @thread EMT
*/
{
/* Get bits 32..47 of destination address */
/*
* offset means:
* 00b = bits 36..47
* 01b = bits 35..46
* 10b = bits 34..45
* 11b = bits 32..43
*/
if (offset < 3)
}
/**
* Determines if the packet is to be delivered to upper layer. The following
* filters supported:
* - Multicast
* - VLAN
*
* @returns true if packet is intended for this node.
* @param pState Pointer to the state structure.
* @param pvBuf The ethernet packet.
* @param cb Number of bytes available in the packet.
* @param pStatus Bit field to store status bits.
* @thread EMT
*/
{
/* Assume that we fail to pass exact filter. */
/* Discard oversized packets */
if (cb > E1K_MAX_RX_PKT_SIZE)
{
E1kLog(("%s ERROR: Incoming packet is too big, cb=%d > max=%d\n",
return false;
}
{
/* When long packet reception is disabled packets over 1522 are discarded */
E1kLog(("%s Discarding incoming packet (LPE=0), cb=%d\n",
return false;
}
/* Broadcast filtering */
return true;
if (e1kIsMulticast(pvBuf))
{
/* Is multicast promiscuous enabled? */
return true;
/* Try perfect matches first */
{
return true;
}
return true;
}
else {
/* Is unicast promiscuous enabled? */
return true;
{
return true;
}
}
/* Is VLAN filtering enabled? */
{
/* Compare TPID with VLAN Ether Type */
{
/* It is 802.1q packet indeed, let's filter by VID */
return true;
}
}
return false;
}
/**
* Receive data from the network.
*
* @returns VBox status code.
* @param pInterface Pointer to the interface structure containing the called function pointer.
* @param pvBuf The available data.
* @param cb Number of bytes available in the buffer.
* @thread ???
*/
{
int rc = VINF_SUCCESS;
/* Discard incoming packets in locked state */
{
return VINF_SUCCESS;
}
{
//if (!e1kCsEnter(pState, RT_SRC_POS))
// return VERR_PERMISSION_DENIED;
/* Update stats */
{
}
if (fPassed)
{
}
//e1kCsLeave(pState);
}
return rc;
}
/**
* Gets the pointer to the status LED of a unit.
*
* @returns VBox status code.
* @param pInterface Pointer to the interface structure.
* @param iLUN The unit which status LED we desire.
* @param ppLed Where to store the LED pointer.
* @thread EMT
*/
{
int rc = VERR_PDM_LUN_NOT_FOUND;
if (iLUN == 0)
{
rc = VINF_SUCCESS;
}
return rc;
}
/**
* Gets the current Media Access Control (MAC) address.
*
* @returns VBox status code.
* @param pInterface Pointer to the interface structure containing the called function pointer.
* @param pMac Where to store the MAC address.
* @thread EMT
*/
{
return VINF_SUCCESS;
}
/**
* Gets the new link state.
*
* @returns The current link state.
* @param pInterface Pointer to the interface structure containing the called function pointer.
* @thread EMT
*/
{
return PDMNETWORKLINKSTATE_UP;
return PDMNETWORKLINKSTATE_DOWN;
}
/**
* Sets the new link state.
*
* @returns VBox status code.
* @param pInterface Pointer to the interface structure containing the called function pointer.
* @param enmState The new link state
* @thread EMT
*/
static DECLCALLBACK(int) e1kSetLinkState(PPDMINETWORKCONFIG pInterface, PDMNETWORKLINKSTATE enmState)
{
{
if (fNewUp)
{
/* Restore the link back in 5 second. */
}
else
{
}
}
return VINF_SUCCESS;
}
/**
* Provides interfaces to the driver.
*
* @returns Pointer to interface. NULL if the interface is not supported.
* @param pInterface Pointer to this interface structure.
* @param enmInterface The requested interface identification.
* @thread EMT
*/
static DECLCALLBACK(void *) e1kQueryInterface(struct PDMIBASE *pInterface, PDMINTERFACE enmInterface)
{
switch (enmInterface)
{
case PDMINTERFACE_BASE:
return &pState->INetworkPort;
return &pState->INetworkConfig;
case PDMINTERFACE_LED_PORTS:
default:
return NULL;
}
}
/**
* Prepares for state saving.
*
* @returns VBox status code.
* @param pDevIns The device instance.
* @param pSSMHandle The handle to save the state to.
*/
{
return rc;
return VINF_SUCCESS;
#if 0
return rc;
/* 1) Prevent all threads from modifying the state and memory */
//pState->fLocked = true;
/* 2) Cancel all timers */
#ifdef E1K_USE_TX_TIMERS
#ifndef E1K_NO_TAD
#endif /* E1K_NO_TAD */
#endif /* E1K_USE_TX_TIMERS */
#ifdef E1K_USE_RX_TIMERS
#endif /* E1K_USE_RX_TIMERS */
/* 3) Did I forget anything? */
return VINF_SUCCESS;
#endif
}
/**
* Saves the state of device.
*
* @returns VBox status code.
* @param pDevIns The device instance.
* @param pSSMHandle The handle to save the state to.
*/
{
//SSMR3PutBool(pSSMHandle, pState->fDelayInts);
//SSMR3PutBool(pSSMHandle, pState->fIntMaskUsed);
return VINF_SUCCESS;
}
#if 0
/**
* Cleanup after saving.
*
* @returns VBox status code.
* @param pDevIns The device instance.
* @param pSSMHandle The handle to save the state to.
*/
{
return rc;
/* If VM is being powered off unlocking will result in assertions in PGM */
else
return VINF_SUCCESS;
}
#endif
/**
* Sync with .
*
* @returns VBox status code.
* @param pDevIns The device instance.
* @param pSSMHandle The handle to the saved state.
*/
{
return rc;
return VINF_SUCCESS;
}
/**
* Restore previously saved state of device.
*
* @returns VBox status code.
* @param pDevIns The device instance.
* @param pSSMHandle The handle to the saved state.
* @param uVersion The data unit version number.
* @param uPass The data pass.
*/
static DECLCALLBACK(int) e1kLoadExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSMHandle, uint32_t uVersion, uint32_t uPass)
{
if (uVersion != E1K_SAVEDSTATE_VERSION)
/** @todo: PHY could be made a separate device with its own versioning */
//SSMR3GetBool(pSSMHandle, pState->fDelayInts);
//SSMR3GetBool(pSSMHandle, pState->fIntMaskUsed);
return VINF_SUCCESS;
}
/**
* Link status adjustments after loading.
*
* @returns VBox status code.
* @param pDevIns The device instance.
* @param pSSMHandle The handle to the saved state.
*/
{
return rc;
/*
* Force the link down here, since PDMNETWORKLINKSTATE_DOWN_RESUME is never
* passed to us. We go through all this stuff if the link was up only.
*/
{
/* Restore the link back in five seconds. */
}
return VINF_SUCCESS;
}
/**
* Sets 8-bit register in PCI configuration space.
* @param refPciDev The PCI device.
* @param uOffset The register offset.
* @param u16Value The value to store in the register.
* @thread EMT
*/
{
}
/**
* Sets 16-bit register in PCI configuration space.
* @param refPciDev The PCI device.
* @param uOffset The register offset.
* @param u16Value The value to store in the register.
* @thread EMT
*/
{
}
/**
* Sets 32-bit register in PCI configuration space.
* @param refPciDev The PCI device.
* @param uOffset The register offset.
* @param u32Value The value to store in the register.
* @thread EMT
*/
{
}
/**
* Set PCI configuration space registers.
*
* @param pci Reference to PCI device structure.
* @thread EMT
*/
{
/* Configure PCI Device, assume 32-bit mode ******************************/
/* DEVSEL Timing (medium device), 66 MHz Capable, New capabilities */
/* Stepping A2 */
/* Ethernet adapter */
/* normal single function Ethernet controller */
/* Memory Register Base Address */
/* Memory Flash Base Address */
/* IO Register Base Address */
/* Expansion ROM Base Address */
/* Capabilities Pointer */
/* Interrupt Pin: INTA# */
/* PCI Power Management Registers ****************************************/
/* Capability ID: PCI Power Management Registers */
/* Next Item Pointer: PCI-X */
/* Power Management Capabilities: PM disabled, DSI */
/* Power Management Control / Status Register: PM disabled */
/* PMCSR_BSE Bridge Support Extensions: Not supported */
/* Data Register: PM disabled, always 0 */
/* PCI-X Configuration Registers *****************************************/
/* Capability ID: PCI-X Configuration Registers */
/* Next Item Pointer: None (Message Signalled Interrupts are disabled) */
/* PCI-X Command: Enable Relaxed Ordering */
/* PCI-X Status: 32-bit, 66MHz*/
}
/**
* Construct a device instance for a VM.
*
* @returns VBox status.
* @param pDevIns The device instance data.
* If the registration structure is needed, pDevIns->pDevReg points to it.
* @param iInstance Instance number. Use this to figure out which registers and such to use.
* The device number is also found in pDevIns->iInstance, but since it's
* likely to be freqently used PDM passes it as parameter.
* @param pCfgHandle Configuration node handle for the device. Use this to obtain the configuration
* of the device instance. It's also found in pDevIns->pCfgHandle, but like
* iInstance it's expected to be used a bit in this function.
* @thread EMT
*/
{
int rc;
/* Init handles and log related stuff. */
E1kLog(("%s Constructing new instance sizeof(E1KRXDESC)=%d\n", INSTANCE(pState), sizeof(E1KRXDESC)));
/*
* Validate configuration.
*/
N_("Invalid configuraton for E1000 device"));
/** @todo: LineSpeed unused! */
/* Get config params */
if (RT_FAILURE(rc))
N_("Configuration error: Failed to get MAC address"));
if (RT_FAILURE(rc))
N_("Configuration error: Failed to get the value of 'CableConnected'"));
if (RT_FAILURE(rc))
N_("Configuration error: Failed to get the value of 'AdapterType'"));
/* Initialize state structure */
pState->fR0Enabled = true;
pState->fGCEnabled = true;
pState->u16TxPktLen = 0;
pState->fIntMaskUsed = false;
pState->fDelayInts = false;
pState->u64AckedAt = 0;
#ifdef E1K_INT_STATS
pState->uStatIntTry = 0;
pState->uStatIntLower = 0;
pState->uStatIntDly = 0;
pState->uStatDisDly = 0;
pState->iStatIntLost = 0;
pState->iStatIntLostOne = 0;
pState->uStatIntLate = 0;
pState->uStatIntMasked = 0;
pState->uStatIntEarly = 0;
pState->uStatIntRx = 0;
pState->uStatIntTx = 0;
pState->uStatIntICS = 0;
pState->uStatIntRDTR = 0;
pState->uStatIntRXDMT0 = 0;
pState->uStatIntTXQE = 0;
pState->uStatTxNoRS = 0;
pState->uStatTxIDE = 0;
pState->uStatRxFrm = 0;
pState->uStatTxFrm = 0;
pState->uStatDescCtx = 0;
pState->uStatDescDat = 0;
pState->uStatDescLeg = 0;
#endif /* E1K_INT_STATS */
/* Interfaces */
/* Initialize the EEPROM */
/* Initialize internal PHY */
if (RT_FAILURE(rc))
return rc;
/* Initialize critical section */
if (RT_FAILURE(rc))
return rc;
#ifndef E1K_GLOBAL_MUTEX
if (RT_FAILURE(rc))
return rc;
#endif
/* Set PCI config registers */
/* Register PCI device */
if (RT_FAILURE(rc))
return rc;
/* Map our registers to memory space (region 0, see e1kConfigurePCI)*/
if (RT_FAILURE(rc))
return rc;
/* Map our registers to IO space (region 2, see e1kConfigurePCI) */
if (RT_FAILURE(rc))
return rc;
/* Create transmit queue */
if (RT_FAILURE(rc))
return rc;
/* Create the RX notifier signaller. */
if (RT_FAILURE(rc))
return rc;
#ifdef E1K_USE_TX_TIMERS
/* Create Transmit Interrupt Delay Timer */
TMTIMER_FLAGS_DEFAULT_CRIT_SECT, /** @todo check locking here. */
if (RT_FAILURE(rc))
return rc;
# ifndef E1K_NO_TAD
/* Create Transmit Absolute Delay Timer */
TMTIMER_FLAGS_DEFAULT_CRIT_SECT, /** @todo check locking here. */
if (RT_FAILURE(rc))
return rc;
# endif /* E1K_NO_TAD */
#endif /* E1K_USE_TX_TIMERS */
#ifdef E1K_USE_RX_TIMERS
/* Create Receive Interrupt Delay Timer */
TMTIMER_FLAGS_DEFAULT_CRIT_SECT, /** @todo check locking here. */
if (RT_FAILURE(rc))
return rc;
/* Create Receive Absolute Delay Timer */
TMTIMER_FLAGS_DEFAULT_CRIT_SECT, /** @todo check locking here. */
if (RT_FAILURE(rc))
return rc;
#endif /* E1K_USE_RX_TIMERS */
/* Create Late Interrupt Timer */
TMTIMER_FLAGS_DEFAULT_CRIT_SECT, /** @todo check locking here. */
if (RT_FAILURE(rc))
return rc;
/* Create Link Up Timer */
TMTIMER_FLAGS_DEFAULT_CRIT_SECT, /** @todo check locking here. */
if (RT_FAILURE(rc))
return rc;
/* Status driver */
if (RT_FAILURE(rc))
pState->pLedsConnector = (PPDMILEDCONNECTORS)pBase->pfnQueryInterface(pBase, PDMINTERFACE_LED_CONNECTORS);
if (RT_SUCCESS(rc))
{
if (rc == VINF_NAT_DNS)
{
N_("A Domain Name Server (DNS) for NAT networking could not be determined. Ensure that your host is correctly connected to an ISP. If you ignore this warning the guest will not be able to perform nameserver lookups and it will probably observe delays if trying so"));
}
{
AssertMsgFailed(("%s Failed to obtain the PDMINTERFACE_NETWORK_CONNECTOR interface!\n"));
return VERR_PDM_MISSING_INTERFACE_BELOW;
}
}
else if (rc == VERR_PDM_NO_ATTACHED_DRIVER)
{
}
else
if (RT_FAILURE(rc))
return rc;
if (RT_FAILURE(rc))
return rc;
rc = PDMDevHlpPDMThreadCreate(pDevIns, &pState->pTxThread, pState, e1kTxThread, e1kTxThreadWakeUp, 0, RTTHREADTYPE_IO, "E1000_TX");
if (RT_FAILURE(rc))
return rc;
#if defined(VBOX_WITH_STATISTICS) || defined(E1K_REL_STATS)
PDMDevHlpSTAMRegisterF(pDevIns, &pState->StatMMIOReadGC, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_CALL, "Profiling MMIO reads in GC", "/Devices/E1k%d/MMIO/ReadGC", iInstance);
PDMDevHlpSTAMRegisterF(pDevIns, &pState->StatMMIOReadHC, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_CALL, "Profiling MMIO reads in HC", "/Devices/E1k%d/MMIO/ReadHC", iInstance);
PDMDevHlpSTAMRegisterF(pDevIns, &pState->StatMMIOWriteGC, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_CALL, "Profiling MMIO writes in GC", "/Devices/E1k%d/MMIO/WriteGC", iInstance);
PDMDevHlpSTAMRegisterF(pDevIns, &pState->StatMMIOWriteHC, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_CALL, "Profiling MMIO writes in HC", "/Devices/E1k%d/MMIO/WriteHC", iInstance);
PDMDevHlpSTAMRegisterF(pDevIns, &pState->StatEEPROMRead, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_CALL, "Profiling EEPROM reads", "/Devices/E1k%d/EEPROM/Read", iInstance);
PDMDevHlpSTAMRegisterF(pDevIns, &pState->StatEEPROMWrite, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_CALL, "Profiling EEPROM writes", "/Devices/E1k%d/EEPROM/Write", iInstance);
PDMDevHlpSTAMRegisterF(pDevIns, &pState->StatIOReadGC, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_CALL, "Profiling IO reads in GC", "/Devices/E1k%d/IO/ReadGC", iInstance);
PDMDevHlpSTAMRegisterF(pDevIns, &pState->StatIOReadHC, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_CALL, "Profiling IO reads in HC", "/Devices/E1k%d/IO/ReadHC", iInstance);
PDMDevHlpSTAMRegisterF(pDevIns, &pState->StatIOWriteGC, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_CALL, "Profiling IO writes in GC", "/Devices/E1k%d/IO/WriteGC", iInstance);
PDMDevHlpSTAMRegisterF(pDevIns, &pState->StatIOWriteHC, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_CALL, "Profiling IO writes in HC", "/Devices/E1k%d/IO/WriteHC", iInstance);
PDMDevHlpSTAMRegisterF(pDevIns, &pState->StatLateIntTimer, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_CALL, "Profiling late int timer", "/Devices/E1k%d/LateInt/Timer", iInstance);
PDMDevHlpSTAMRegisterF(pDevIns, &pState->StatLateInts, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, "Number of late interrupts", "/Devices/E1k%d/LateInt/Occured", iInstance);
PDMDevHlpSTAMRegisterF(pDevIns, &pState->StatIntsRaised, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, "Number of raised interrupts", "/Devices/E1k%d/Interrupts/Raised", iInstance);
PDMDevHlpSTAMRegisterF(pDevIns, &pState->StatIntsPrevented, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, "Number of prevented interrupts", "/Devices/E1k%d/Interrupts/Prevented", iInstance);
PDMDevHlpSTAMRegisterF(pDevIns, &pState->StatReceive, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_CALL, "Profiling receive", "/Devices/E1k%d/Receive/Total", iInstance);
PDMDevHlpSTAMRegisterF(pDevIns, &pState->StatReceiveFilter, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_CALL, "Profiling receive filtering", "/Devices/E1k%d/Receive/Filter", iInstance);
PDMDevHlpSTAMRegisterF(pDevIns, &pState->StatReceiveStore, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_CALL, "Profiling receive storing", "/Devices/E1k%d/Receive/Store", iInstance);
PDMDevHlpSTAMRegisterF(pDevIns, &pState->StatRxOverflow, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_OCCURENCE, "Profiling RX overflows", "/Devices/E1k%d/RxOverflow", iInstance);
PDMDevHlpSTAMRegisterF(pDevIns, &pState->StatRxOverflowWakeup, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, "Nr of RX overflow wakeups", "/Devices/E1k%d/RxOverflowWakeup", iInstance);
#endif /* VBOX_WITH_STATISTICS || E1K_REL_STATS */
PDMDevHlpSTAMRegisterF(pDevIns, &pState->StatReceiveBytes, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_BYTES, "Amount of data received", "/Devices/E1k%d/ReceiveBytes", iInstance);
#if defined(VBOX_WITH_STATISTICS) || defined(E1K_REL_STATS)
PDMDevHlpSTAMRegisterF(pDevIns, &pState->StatTransmit, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_CALL, "Profiling transmits in HC", "/Devices/E1k%d/Transmit/Total", iInstance);
#endif /* VBOX_WITH_STATISTICS || E1K_REL_STATS */
PDMDevHlpSTAMRegisterF(pDevIns, &pState->StatTransmitBytes, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_BYTES, "Amount of data transmitted", "/Devices/E1k%d/TransmitBytes", iInstance);
#if defined(VBOX_WITH_STATISTICS) || defined(E1K_REL_STATS)
PDMDevHlpSTAMRegisterF(pDevIns, &pState->StatTransmitSend, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_CALL, "Profiling send transmit in HC", "/Devices/E1k%d/Transmit/Send", iInstance);
PDMDevHlpSTAMRegisterF(pDevIns, &pState->StatTxDescLegacy, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, "Number of TX legacy descriptors", "/Devices/E1k%d/TxDesc/Legacy", iInstance);
PDMDevHlpSTAMRegisterF(pDevIns, &pState->StatTxDescData, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, "Number of TX data descriptors", "/Devices/E1k%d/TxDesc/Data", iInstance);
PDMDevHlpSTAMRegisterF(pDevIns, &pState->StatTxDescTSEData, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, "Number of TX TSE data descriptors", "/Devices/E1k%d/TxDesc/TSEData", iInstance);
PDMDevHlpSTAMRegisterF(pDevIns, &pState->StatPHYAccesses, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, "Number of PHY accesses", "/Devices/E1k%d/PHYAccesses", iInstance);
#endif /* VBOX_WITH_STATISTICS || E1K_REL_STATS */
return VINF_SUCCESS;
}
/**
* Destruct a device instance.
*
* We need to free non-VM resources only.
*
* @returns VBox status.
* @param pDevIns The device instance data.
* @thread EMT
*/
{
{
{
}
{
}
#ifndef E1K_GLOBAL_MUTEX
//PDMR3CritSectDelete(&pState->csTx);
#endif
}
return VINF_SUCCESS;
}
/**
* Device relocation callback.
*
* When this callback is called the device instance data, and if the
* have been changed. The device must use the chance to perform the
* necessary pointer relocations and data updates.
*
* Before the GC code is executed the first time, this function will be
* called with a 0 delta so GC pointer calculations can be one in one place.
*
* @param pDevIns Pointer to the device instance.
* @param offDelta The relocation delta relative to the old location.
*
* @remark A relocation CANNOT fail.
*/
{
#ifdef E1K_USE_RX_TIMERS
#endif /* E1K_USE_RX_TIMERS */
#ifdef E1K_USE_TX_TIMERS
# ifndef E1K_NO_TAD
# endif /* E1K_NO_TAD */
#endif /* E1K_USE_TX_TIMERS */
}
/**
* @copydoc FNPDMDEVSUSPEND
*/
{
/* Poke thread waiting for buffer space. */
}
#ifdef VBOX_DYNAMIC_NET_ATTACH
/**
* Detach notification.
*
* One port on the network card has been disconnected from the network.
*
* @param pDevIns The device instance.
* @param iLUN The logical unit which is being detached.
* @param fFlags Flags, combination of the PDMDEVATT_FLAGS_* \#defines.
*/
{
AssertLogRelReturnVoid(iLUN == 0);
/** @todo: r=pritesh still need to check if i missed
* to clean something in this function
*/
/*
* Zero some important members.
*/
}
/**
* Attach the Network attachment.
*
* One port on the network card has been connected to a network.
*
* @returns VBox status code.
* @param pDevIns The device instance.
* @param iLUN The logical unit which is being attached.
* @param fFlags Flags, combination of the PDMDEVATT_FLAGS_* \#defines.
*
* @remarks This code path is not used during construction.
*/
{
/*
* Attach the driver.
*/
if (RT_SUCCESS(rc))
{
if (rc == VINF_NAT_DNS)
{
#ifdef RT_OS_LINUX
N_("A Domain Name Server (DNS) for NAT networking could not be determined. Please check your /etc/resolv.conf for <tt>nameserver</tt> entries. Either add one manually (<i>man resolv.conf</i>) or ensure that your host is correctly connected to an ISP. If you ignore this warning the guest will not be able to perform nameserver lookups and it will probably observe delays if trying so"));
#else
N_("A Domain Name Server (DNS) for NAT networking could not be determined. Ensure that your host is correctly connected to an ISP. If you ignore this warning the guest will not be able to perform nameserver lookups and it will probably observe delays if trying so"));
#endif
}
pState->pDrv = (PPDMINETWORKCONNECTOR)pState->pDrvBase->pfnQueryInterface(pState->pDrvBase, PDMINTERFACE_NETWORK_CONNECTOR);
{
AssertMsgFailed(("Failed to obtain the PDMINTERFACE_NETWORK_CONNECTOR interface!\n"));
}
}
else if (rc == VERR_PDM_NO_ATTACHED_DRIVER)
/*
* Temporary set the link down if it was up so that the guest
* will know that we have change the configuration of the
* network card
*/
{
/* Restore the link back in 5 second. */
}
return rc;
}
#endif /* VBOX_DYNAMIC_NET_ATTACH */
/**
* @copydoc FNPDMDEVPOWEROFF
*/
{
/* Poke thread waiting for buffer space. */
}
/**
* The device registration structure.
*/
const PDMDEVREG g_DeviceE1000 =
{
/* Structure version. PDM_DEVREG_VERSION defines the current version. */
/* Device name. */
"e1000",
/* Name of guest context module (no path).
* Only evalutated if PDM_DEVREG_FLAGS_RC is set. */
"VBoxDDGC.gc",
/* Name of ring-0 module (no path).
* Only evalutated if PDM_DEVREG_FLAGS_RC is set. */
"VBoxDDR0.r0",
/* The description of the device. The UTF-8 string pointed to shall, like this structure,
* remain unchanged from registration till VM destruction. */
"Intel PRO/1000 MT Desktop Ethernet.\n",
/* Flags, combination of the PDM_DEVREG_FLAGS_* \#defines. */
/* Device class(es), combination of the PDM_DEVREG_CLASS_* \#defines. */
/* Maximum number of instances (per VM). */
8,
/* Size of the instance data. */
sizeof(E1KSTATE),
/* Construct instance - required. */
/* Destruct instance - optional. */
/* Relocation command - optional. */
/* I/O Control interface - optional. */
NULL,
/* Power on notification - optional. */
NULL,
/* Reset notification - optional. */
NULL,
/* Suspend notification - optional. */
/* Resume notification - optional. */
NULL,
#ifdef VBOX_DYNAMIC_NET_ATTACH
/* Attach command - optional. */
/* Detach notification - optional. */
#else /* !VBOX_DYNAMIC_NET_ATTACH */
/* Attach command - optional. */
NULL,
/* Detach notification - optional. */
NULL,
#endif /* !VBOX_DYNAMIC_NET_ATTACH */
/* Query a LUN base interface - optional. */
NULL,
/* Init complete notification - optional. */
NULL,
/* Power off notification - optional. */
/* pfnSoftReset */
NULL,
/* u32VersionEnd */
};
#endif /* IN_RING3 */
#endif /* !VBOX_DEVICE_STRUCT_TESTCASE */