svga_reg.h revision ae94ad7e769e467419ab99cab5403bdb39bc544f
/*
* VMware SVGA II hardware definitions
*/
#ifndef _SVGA_REG_H_
#define _SVGA_REG_H_
#define PCI_VENDOR_ID_VMWARE 0x15AD
#define PCI_DEVICE_ID_VMWARE_SVGA2 0x0405
#define SVGA_IRQFLAG_ANY_FENCE 0x1
#define SVGA_IRQFLAG_FIFO_PROGRESS 0x2
#define SVGA_IRQFLAG_FENCE_GOAL 0x4
#define SVGA_MAX_PSEUDOCOLOR_DEPTH 8
#define SVGA_MAGIC 0x900000UL
#define SVGA_VERSION_2 2
#define SVGA_VERSION_1 1
#define SVGA_VERSION_0 0
#define SVGA_ID_INVALID 0xFFFFFFFF
#define SVGA_INDEX_PORT 0x0
#define SVGA_VALUE_PORT 0x1
#define SVGA_BIOS_PORT 0x2
#define SVGA_IRQSTATUS_PORT 0x8
#define SVGA_IRQFLAG_ANY_FENCE 0x1
#define SVGA_IRQFLAG_FIFO_PROGRESS 0x2
#define SVGA_IRQFLAG_FENCE_GOAL 0x4
enum
{
SVGA_REG_ID = 0,
SVGA_REG_ENABLE = 1,
SVGA_REG_WIDTH = 2,
SVGA_REG_HEIGHT = 3,
SVGA_REG_MAX_WIDTH = 4,
SVGA_REG_MAX_HEIGHT = 5,
SVGA_REG_DEPTH = 6,
SVGA_REG_PSEUDOCOLOR = 8,
SVGA_REG_RED_MASK = 9,
SVGA_REG_GREEN_MASK = 10,
SVGA_REG_BLUE_MASK = 11,
SVGA_REG_BYTES_PER_LINE = 12,
SVGA_REG_FB_START = 13,
SVGA_REG_FB_OFFSET = 14,
SVGA_REG_VRAM_SIZE = 15,
SVGA_REG_FB_SIZE = 16,
SVGA_REG_CAPABILITIES = 17,
SVGA_REG_MEM_START = 18,
SVGA_REG_MEM_SIZE = 19,
SVGA_REG_CONFIG_DONE = 20,
SVGA_REG_SYNC = 21,
SVGA_REG_BUSY = 22,
SVGA_REG_GUEST_ID = 23,
SVGA_REG_CURSOR_ID = 24,
SVGA_REG_CURSOR_X = 25,
SVGA_REG_CURSOR_Y = 26,
SVGA_REG_CURSOR_ON = 27,
SVGA_REG_SCRATCH_SIZE = 29,
SVGA_REG_MEM_REGS = 30,
SVGA_REG_NUM_DISPLAYS = 31,
SVGA_REG_PITCHLOCK = 32,
SVGA_REG_IRQMASK = 33,
SVGA_REG_DISPLAY_ID = 35,
SVGA_REG_DISPLAY_WIDTH = 39,
SVGA_REG_DISPLAY_HEIGHT = 40,
SVGA_REG_GMR_ID = 41,
SVGA_REG_GMR_DESCRIPTOR = 42,
SVGA_REG_GMR_MAX_IDS = 43,
SVGA_REG_TRACES = 45,
SVGA_REG_GMRS_MAX_PAGES = 46,
SVGA_REG_MEMORY_SIZE = 47,
SVGA_REG_TOP = 48,
SVGA_PALETTE_BASE = 1024,
};
enum
{
SVGA_FIFO_MIN = 0,
SVGA_FIFO_3D_CAPS = 32,
};
typedef enum
{
SVGA_CMD_INVALID_CMD = 0,
SVGA_CMD_UPDATE = 1,
SVGA_CMD_RECT_COPY = 3,
SVGA_CMD_DEFINE_CURSOR = 19,
SVGA_CMD_UPDATE_VERBOSE = 25,
SVGA_CMD_FRONT_ROP_FILL = 29,
SVGA_CMD_FENCE = 30,
SVGA_CMD_ESCAPE = 33,
SVGA_CMD_DEFINE_SCREEN = 34,
SVGA_CMD_DESTROY_SCREEN = 35,
SVGA_CMD_DEFINE_GMRFB = 36,
SVGA_CMD_ANNOTATION_FILL = 39,
SVGA_CMD_ANNOTATION_COPY = 40,
SVGA_CMD_DEFINE_GMR2 = 41,
SVGA_CMD_REMAP_GMR2 = 42,
typedef struct SVGAColorBGRX
{
union
{
struct
{
uint32_t b : 8;
uint32_t g : 8;
uint32_t r : 8;
uint32_t x : 8;
} s;
};
typedef struct SVGASignedPoint
{
int32_t x;
int32_t y;
#define SVGA_CAP_NONE 0x00000000
#define SVGA_CAP_RECT_COPY 0x00000002
#define SVGA_CAP_CURSOR 0x00000020
#define SVGA_CAP_CURSOR_BYPASS 0x00000040
#define SVGA_CAP_CURSOR_BYPASS_2 0x00000080
#define SVGA_CAP_8BIT_EMULATION 0x00000100
#define SVGA_CAP_ALPHA_CURSOR 0x00000200
#define SVGA_CAP_3D 0x00004000
#define SVGA_CAP_EXTENDED_FIFO 0x00008000
#define SVGA_CAP_MULTIMON 0x00010000
#define SVGA_CAP_PITCHLOCK 0x00020000
#define SVGA_CAP_IRQMASK 0x00040000
#define SVGA_CAP_DISPLAY_TOPOLOGY 0x00080000
#define SVGA_CAP_GMR 0x00100000
#define SVGA_CAP_TRACES 0x00200000
#define SVGA_CAP_GMR2 0x00400000
#define SVGA_CAP_SCREEN_OBJECT_2 0x00800000
typedef struct SVGAGuestPtr
{
} SVGAGuestPtr;
typedef struct SVGAGMRImageFormat
{
union
{
struct
{
} s;
};
typedef struct SVGAGuestImage
{
#define SVGA_SCREEN_MUST_BE_SET (1 << 0)
typedef struct SVGAScreenObject
{
struct
{
} size;
struct
{
int32_t x;
int32_t y;
} root;
typedef struct
{
typedef struct
{
uint32_t x;
uint32_t y;
typedef struct
{
typedef struct
{
typedef struct
{
typedef struct
{
typedef struct
{
typedef struct
{
typedef struct
{
#define SVGA_FIFO_CAP_NONE 0
#define SVGA_FIFO_CAP_FENCE (1<<0)
#endif /* _SVGA_REG_H_ */