svga_reg.h revision ae94ad7e769e467419ab99cab5403bdb39bc544f
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync * VMware SVGA II hardware definitions
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync#define SVGA_MAX_PSEUDOCOLORS (1 << SVGA_MAX_PSEUDOCOLOR_DEPTH)
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync#define SVGA_NUM_PALETTE_REGS (3 * SVGA_MAX_PSEUDOCOLORS)
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync SVGA_SCRATCH_BASE = SVGA_PALETTE_BASE + SVGA_NUM_PALETTE_REGS
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsynctypedef enum
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsynctypedef struct SVGAGuestPtr
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync#define SVGA_SCREEN_HAS_ROOT SVGA_SCREEN_MUST_BE_SET
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsynctypedef struct
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsynctypedef struct
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsynctypedef struct
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsynctypedef struct
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsynctypedef struct
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsynctypedef struct
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsynctypedef struct
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsynctypedef struct
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsynctypedef struct
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync#define SVGA_FIFO_CAP_3D_HWVERSION_REVISED SVGA_FIFO_CAP_GMR2
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync#endif /* _SVGA_REG_H_ */