svga_reg.h revision 332aaa1da374e694e37fdfe0a00bbe040e670453
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync/**********************************************************
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * Copyright 1998-2009 VMware, Inc. All rights reserved.
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * Permission is hereby granted, free of charge, to any person
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * obtaining a copy of this software and associated documentation
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * files (the "Software"), to deal in the Software without
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * restriction, including without limitation the rights to use, copy,
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * modify, merge, publish, distribute, sublicense, and/or sell copies
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * of the Software, and to permit persons to whom the Software is
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * furnished to do so, subject to the following conditions:
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * The above copyright notice and this permission notice shall be
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * included in all copies or substantial portions of the Software.
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * SOFTWARE.
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync **********************************************************/
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * Virtual hardware definitions for the VMware SVGA II device.
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * PCI device IDs.
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * SVGA_REG_ENABLE bit definitions.
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync#define SVGA_REG_ENABLE_ENABLE_HIDE (SVGA_REG_ENABLE_ENABLE |\
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * Legal values for the SVGA_REG_CURSOR_ON register in old-fashioned
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * cursor bypass mode. This is still supported, but no new guest
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * drivers should use it.
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync#define SVGA_CURSOR_ON_HIDE 0x0 /* Must be 0 to maintain backward compatibility */
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync#define SVGA_CURSOR_ON_SHOW 0x1 /* Must be 1 to maintain backward compatibility */
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync#define SVGA_CURSOR_ON_REMOVE_FROM_FB 0x2 /* Remove the cursor from the framebuffer because we need to see what's under it */
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync#define SVGA_CURSOR_ON_RESTORE_TO_FB 0x3 /* Put the cursor back in the framebuffer so the user can see it */
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * The maximum framebuffer size that can traced for e.g. guests in VESA mode.
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * The changeMap in the monitor is proportional to this number. Therefore, we'd
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * like to keep it as small as possible to reduce monitor overhead (using
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * SVGA_VRAM_MAX_SIZE for this increases the size of the shared area by over
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * NB: For compatibility reasons, this value must be greater than 0xff0000.
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * See bug 335072.
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync#define SVGA_MAX_PSEUDOCOLORS (1 << SVGA_MAX_PSEUDOCOLOR_DEPTH)
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync#define SVGA_NUM_PALETTE_REGS (3 * SVGA_MAX_PSEUDOCOLORS)
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync/* Version 2 let the address of the frame buffer be unsigned on Win32 */
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync/* Version 1 has new registers starting with SVGA_REG_CAPABILITIES so
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync PALETTE_BASE has moved */
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync/* Version 0 is the initial version */
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync/* "Invalid" value for all SVGA IDs. (Version ID, screen object ID, surface ID...) */
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync/* Port offsets, relative to BAR0 */
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * Interrupt source flags for IRQSTATUS_PORT and IRQMASK.
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * Interrupts are only supported when the
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * SVGA_CAP_IRQMASK capability is present.
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync#define SVGA_IRQFLAG_ANY_FENCE 0x1 /* Any fence was passed */
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync#define SVGA_IRQFLAG_FIFO_PROGRESS 0x2 /* Made forward progress in the FIFO */
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync#define SVGA_IRQFLAG_FENCE_GOAL 0x4 /* SVGA_FIFO_FENCE_GOAL reached */
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * Registers
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync SVGA_REG_BITS_PER_PIXEL = 7, /* Current bpp in the guest */
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync /* ID 0 implementation only had the above registers, then the palette */
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync SVGA_REG_CONFIG_DONE = 20, /* Set when memory area configured */
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync SVGA_REG_SYNC = 21, /* See "FIFO Synchronization Registers" */
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync SVGA_REG_BUSY = 22, /* See "FIFO Synchronization Registers" */
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync SVGA_REG_GUEST_ID = 23, /* Set guest OS identifier */
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync SVGA_REG_HOST_BITS_PER_PIXEL = 28, /* (Deprecated) */
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync SVGA_REG_SCRATCH_SIZE = 29, /* Number of scratch registers */
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync SVGA_REG_MEM_REGS = 30, /* Number of FIFO registers */
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync SVGA_REG_PITCHLOCK = 32, /* Fixed pitch for all modes */
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync /* Legacy multi-monitor support */
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync SVGA_REG_NUM_GUEST_DISPLAYS = 34,/* Number of guest displays in X/Y direction */
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync SVGA_REG_DISPLAY_ID = 35, /* Display ID for the following display attributes */
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync SVGA_REG_DISPLAY_IS_PRIMARY = 36,/* Whether this is a primary display */
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync SVGA_REG_DISPLAY_POSITION_X = 37,/* The display position x */
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync SVGA_REG_DISPLAY_POSITION_Y = 38,/* The display position y */
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync SVGA_REG_DISPLAY_WIDTH = 39, /* The display's width */
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync SVGA_REG_DISPLAY_HEIGHT = 40, /* The display's height */
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync /* See "Guest memory regions" below. */
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync SVGA_REG_TRACES = 45, /* Enable trace-based updates even when FIFO is on */
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync SVGA_REG_GMRS_MAX_PAGES = 46, /* Maximum number of 4KB pages for all GMRs */
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync SVGA_REG_MEMORY_SIZE = 47, /* Total dedicated device memory excluding FIFO */
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync SVGA_REG_TOP = 48, /* Must be 1 more than the last register */
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync SVGA_PALETTE_BASE = 1024, /* Base of SVGA color map */
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync /* Next 768 (== 256*3) registers exist for colormap */
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync SVGA_SCRATCH_BASE = SVGA_PALETTE_BASE + SVGA_NUM_PALETTE_REGS
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync /* Base of scratch registers */
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync /* Next reg[SVGA_REG_SCRATCH_SIZE] registers exist for scratch usage:
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync First 4 are reserved for VESA BIOS Extension; any remaining are for
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync the use of the current SVGA driver. */
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * Guest memory regions (GMRs):
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * This is a new memory mapping feature available in SVGA devices
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * which have the SVGA_CAP_GMR bit set. Previously, there were two
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * fixed memory regions available with which to share data between the
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * device and the driver: the FIFO ('MEM') and the framebuffer. GMRs
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * are our name for an extensible way of providing arbitrary DMA
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * buffers for use between the driver and the SVGA device. They are a
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * new alternative to framebuffer memory, usable for both 2D and 3D
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * graphics operations.
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * Since GMR mapping must be done synchronously with guest CPU
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * execution, we use a new pair of SVGA registers:
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * SVGA_REG_GMR_ID --
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * This register holds the 32-bit ID (a small positive integer)
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * of a GMR to create, delete, or redefine. Writing this register
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * has no side-effects.
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * SVGA_REG_GMR_DESCRIPTOR --
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * Write-only.
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * Writing this register will create, delete, or redefine the GMR
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * specified by the above ID register. If this register is zero,
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * the GMR is deleted. Any pointers into this GMR (including those
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * currently being processed by FIFO commands) will be
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * synchronously invalidated.
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * If this register is nonzero, it must be the physical page
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * number (PPN) of a data structure which describes the physical
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * layout of the memory region this GMR should describe. The
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * descriptor structure will be read synchronously by the SVGA
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * device when this register is written. The descriptor need not
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * remain allocated for the lifetime of the GMR.
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * The guest driver should write SVGA_REG_GMR_ID first, then
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * SVGA_REG_GMR_DESCRIPTOR.
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * SVGA_REG_GMR_MAX_IDS --
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * Read-only.
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * The SVGA device may choose to support a maximum number of
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * user-defined GMR IDs. This register holds the number of supported
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * IDs. (The maximum supported ID plus 1)
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * SVGA_REG_GMR_MAX_DESCRIPTOR_LENGTH --
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * Read-only.
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * The SVGA device may choose to put a limit on the total number
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * of SVGAGuestMemDescriptor structures it will read when defining
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * a single GMR.
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * The descriptor structure is an array of SVGAGuestMemDescriptor
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * structures. Each structure may do one of three things:
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * - Terminate the GMR descriptor list.
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * (ppn==0, numPages==0)
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * - Add a PPN or range of PPNs to the GMR's virtual address space.
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * (ppn != 0, numPages != 0)
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * - Provide the PPN of the next SVGAGuestMemDescriptor, in order to
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * support multi-page GMR descriptor tables without forcing the
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * driver to allocate physically contiguous memory.
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * (ppn != 0, numPages == 0)
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * Note that each physical page of SVGAGuestMemDescriptor structures
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * can describe at least 2MB of guest memory. If the driver needs to
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * use more than one page of descriptor structures, it must use one of
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * its SVGAGuestMemDescriptors to point to an additional page. The
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * device will never automatically cross a page boundary.
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * Once the driver has described a GMR, it is immediately available
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * for use via any FIFO command that uses an SVGAGuestPtr structure.
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * These pointers include a GMR identifier plus an offset into that
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * The driver must check the SVGA_CAP_GMR bit before using the GMR
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * registers.
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * Special GMR IDs, allowing SVGAGuestPtrs to point to framebuffer
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * memory as well. In the future, these IDs could even be used to
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * allow legacy memory regions to be redefined by the guest as GMRs.
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * Using the guest framebuffer (GFB) at BAR1 for general purpose DMA
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * is being phased out. Please try to use user-defined GMRs whenever
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * possible.
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync#define SVGA_GMR_FRAMEBUFFER ((uint32_t) -2) // Guest Framebuffer (GFB)
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * SVGAGMRImageFormat --
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * This is a packed representation of the source 2D image format
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * for a GMR-to-screen blit. Currently it is defined as an encoding
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * of the screen's color depth and bits-per-pixel, however, 16 bits
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * are reserved for future use to identify other encodings (such as
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * RGBA or higher-precision images).
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * Currently supported formats:
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * bpp depth Format Name
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * --- ----- -----------
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * 32 24 32-bit BGRX
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * 24 24 24-bit BGR
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * 16 16 RGB 5-6-5
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * 16 15 RGB 5-5-5
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * A note on interpretation of pitch: This value of pitch is the
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * number of bytes between vertically adjacent image
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * blocks. Normally this is the number of bytes between the first
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * pixel of two adjacent scanlines. With compressed textures,
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * however, this may represent the number of bytes between
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * compression blocks rather than between rows of pixels.
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * XXX: Compressed textures currently must be tightly packed in guest memory.
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * If the image is 1-dimensional, pitch is ignored.
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * If 'pitch' is zero, the SVGA3D device calculates a pitch value
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * assuming each row of blocks is tightly packed.
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * SVGAColorBGRX --
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * A 24-bit color format (BGRX), which does not depend on the
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * format of the legacy guest framebuffer (GFB) or the current
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * GMRFB state.
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * SVGASignedRect --
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * SVGASignedPoint --
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * Signed rectangle and point primitives. These are used by the new
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * 2D primitives for drawing to Screen Objects, which can occupy a
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * signed virtual coordinate space.
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * SVGASignedRect specifies a half-open interval: the (left, top)
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * pixel is part of the rectangle, but the (right, bottom) pixel is
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * Capabilities
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * Note the holes in the bitfield. Missing bits have been deprecated,
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * and must not be reused. Those capabilities will never be reported
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * by new versions of the SVGA device.
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * SVGA_CAP_GMR2 --
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * Provides asynchronous commands to define and remap guest memory
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * regions. Adds device registers SVGA_REG_GMRS_MAX_PAGES and
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * SVGA_REG_MEMORY_SIZE.
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * SVGA_CAP_SCREEN_OBJECT_2 --
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * Allow screen object support, and require backing stores from the
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * guest for each screen object.
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync#define SVGA_CAP_CURSOR_BYPASS 0x00000040 // Legacy (Use Cursor Bypass 3 instead)
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync#define SVGA_CAP_CURSOR_BYPASS_2 0x00000080 // Legacy (Use Cursor Bypass 3 instead)
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync#define SVGA_CAP_MULTIMON 0x00010000 // Legacy multi-monitor support
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync#define SVGA_CAP_DISPLAY_TOPOLOGY 0x00080000 // Legacy multi-monitor support
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * FIFO register indices.
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * The FIFO is a chunk of device memory mapped into guest physmem. It
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * is always treated as 32-bit words.
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * The guest driver gets to decide how to partition it between
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * - FIFO registers (there are always at least 4, specifying where the
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * following data area is and how much data it contains; there may be
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * more registers following these, depending on the FIFO protocol
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * version in use)
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * - FIFO data, written by the guest and slurped out by the VMX.
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * These indices are 32-bit word offsets into the FIFO.
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * Block 1 (basic registers): The originally defined FIFO registers.
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * These exist and are valid for all versions of the FIFO protocol.
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync SVGA_FIFO_MAX, /* The distance from MIN to MAX must be at least 10K */
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * Block 2 (extended registers): Mandatory registers for the extended
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * FIFO. These exist if the SVGA caps register includes
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * SVGA_CAP_EXTENDED_FIFO; some of them are valid only if their
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * associated capability bit is enabled.
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * Note that when originally defined, SVGA_CAP_EXTENDED_FIFO implied
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * support only for (FIFO registers) CAPABILITIES, FLAGS, and FENCE.
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * This means that the guest has to test individually (in most cases
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * using FIFO caps) for the presence of registers after this; the VMX
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * can define "extended FIFO" to mean whatever it wants, and currently
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * won't enable it unless there's room for that set and much more.
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync // Valid with SVGA_FIFO_CAP_FENCE:
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * Block 3a (optional extended registers): Additional registers for the
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * extended FIFO, whose presence isn't actually implied by
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * SVGA_CAP_EXTENDED_FIFO; these exist if SVGA_FIFO_MIN is high enough to
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * leave room for them.
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * These in block 3a, the VMX currently considers mandatory for the
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * extended FIFO.
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync // Valid if exists (i.e. if extended FIFO enabled):
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync SVGA_FIFO_3D_HWVERSION, /* See SVGA3dHardwareVersion in svga3d_reg.h */
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync // Valid with SVGA_FIFO_CAP_PITCHLOCK:
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync // Valid with SVGA_FIFO_CAP_CURSOR_BYPASS_3:
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync SVGA_FIFO_CURSOR_ON, /* Cursor bypass 3 show/hide register */
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync SVGA_FIFO_CURSOR_X, /* Cursor bypass 3 x register */
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync SVGA_FIFO_CURSOR_Y, /* Cursor bypass 3 y register */
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync SVGA_FIFO_CURSOR_COUNT, /* Incremented when any of the other 3 change */
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync SVGA_FIFO_CURSOR_LAST_UPDATED,/* Last time the host updated the cursor */
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync // Valid with SVGA_FIFO_CAP_RESERVE:
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync SVGA_FIFO_RESERVED, /* Bytes past NEXT_CMD with real contents */
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * Valid with SVGA_FIFO_CAP_SCREEN_OBJECT or SVGA_FIFO_CAP_SCREEN_OBJECT_2:
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * By default this is SVGA_ID_INVALID, to indicate that the cursor
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * coordinates are specified relative to the virtual root. If this
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * is set to a specific screen ID, cursor position is reinterpreted
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * as a signed offset relative to that screen's origin.
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * Valid with SVGA_FIFO_CAP_DEAD
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * An arbitrary value written by the host, drivers should not use it.
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * Valid with SVGA_FIFO_CAP_3D_HWVERSION_REVISED:
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * Contains 3D HWVERSION (see SVGA3dHardwareVersion in svga3d_reg.h)
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * on platforms that can enforce graphics resource limits.
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * XXX: The gap here, up until SVGA_FIFO_3D_CAPS, can be used for new
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * registers, but this must be done carefully and with judicious use of
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * capability bits, since comparisons based on SVGA_FIFO_MIN aren't
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * enough to tell you whether the register exists: we've shipped drivers
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * and products that used SVGA_FIFO_3D_CAPS but didn't know about some of
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * the earlier ones. The actual order of introduction was:
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * - PITCHLOCK
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * - 3D_CAPS
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * - CURSOR_* (cursor bypass 3)
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * - RESERVED
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * So, code that wants to know whether it can use any of the
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * aforementioned registers, or anything else added after PITCHLOCK and
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * before 3D_CAPS, needs to reason about something other than
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * SVGA_FIFO_MIN.
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * 3D caps block space; valid with 3D hardware version >=
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * SVGA3D_HWVERSION_WS6_B1.
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * End of VMX's current definition of "extended-FIFO registers".
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * Registers before here are always enabled/disabled as a block; either
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * the extended FIFO is enabled and includes all preceding registers, or
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * it's disabled entirely.
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * Block 3b (truly optional extended registers): Additional registers for
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * the extended FIFO, which the VMX already knows how to enable and
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * disable with correct granularity.
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * Registers after here exist if and only if the guest SVGA driver
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * sets SVGA_FIFO_MIN high enough to leave room for them.
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync // Valid if register exists:
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync SVGA_FIFO_GUEST_3D_HWVERSION, /* Guest driver's 3D version */
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync SVGA_FIFO_FENCE_GOAL, /* Matching target for SVGA_IRQFLAG_FENCE_GOAL */
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync SVGA_FIFO_BUSY, /* See "FIFO Synchronization Registers" */
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * Always keep this last. This defines the maximum number of
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * registers we know about. At power-on, this value is placed in
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * the SVGA_REG_MEM_REGS register, and we expect the guest driver
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * to allocate this much space in FIFO memory for registers.
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * Definition of registers included in extended FIFO support.
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * The guest SVGA driver gets to allocate the FIFO between registers
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * and data. It must always allocate at least 4 registers, but old
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * drivers stopped there.
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * The VMX will enable extended FIFO support if and only if the guest
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * left enough room for all registers defined as part of the mandatory
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * set for the extended FIFO.
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * Note that the guest drivers typically allocate the FIFO only at
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * initialization time, not at mode switches, so it's likely that the
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * number of FIFO registers won't change without a reboot.
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * All registers less than this value are guaranteed to be present if
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * svgaUser->fifo.extended is set. Any later registers must be tested
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * individually for compatibility at each use (in the VMX).
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * This value is used only by the VMX, so it can change without
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * affecting driver compatibility; keep it that way?
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync#define SVGA_FIFO_EXTENDED_MANDATORY_REGS (SVGA_FIFO_3D_CAPS_LAST + 1)
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * FIFO Synchronization Registers
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * This explains the relationship between the various FIFO
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * sync-related registers in IOSpace and in FIFO space.
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * SVGA_REG_SYNC --
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * The SYNC register can be used in two different ways by the guest:
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * 1. If the guest wishes to fully sync (drain) the FIFO,
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * it will write once to SYNC then poll on the BUSY
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * register. The FIFO is sync'ed once BUSY is zero.
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * 2. If the guest wants to asynchronously wake up the host,
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * it will write once to SYNC without polling on BUSY.
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * Ideally it will do this after some new commands have
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * been placed in the FIFO, and after reading a zero
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * from SVGA_FIFO_BUSY.
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * (1) is the original behaviour that SYNC was designed to
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * support. Originally, a write to SYNC would implicitly
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * trigger a read from BUSY. This causes us to synchronously
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * process the FIFO.
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * This behaviour has since been changed so that writing SYNC
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * will *not* implicitly cause a read from BUSY. Instead, it
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * makes a channel call which asynchronously wakes up the MKS
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * New guests can use this new behaviour to implement (2)
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * efficiently. This lets guests get the host's attention
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * without waiting for the MKS to poll, which gives us much
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * better CPU utilization on SMP hosts and on UP hosts while
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * we're blocked on the host GPU.
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * Old guests shouldn't notice the behaviour change. SYNC was
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * never guaranteed to process the entire FIFO, since it was
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * bounded to a particular number of CPU cycles. Old guests will
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * still loop on the BUSY register until the FIFO is empty.
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * Writing to SYNC currently has the following side-effects:
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * - Sets SVGA_REG_BUSY to TRUE (in the monitor)
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * - Asynchronously wakes up the MKS thread for FIFO processing
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * - The value written to SYNC is recorded as a "reason", for
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * stats purposes.
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * If SVGA_FIFO_BUSY is available, drivers are advised to only
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * write to SYNC if SVGA_FIFO_BUSY is FALSE. Drivers should set
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * SVGA_FIFO_BUSY to TRUE after writing to SYNC. The MKS will
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * eventually set SVGA_FIFO_BUSY on its own, but this approach
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * lets the driver avoid sending multiple asynchronous wakeup
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * messages to the MKS thread.
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * SVGA_REG_BUSY --
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * This register is set to TRUE when SVGA_REG_SYNC is written,
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * and it reads as FALSE when the FIFO has been completely
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * Every read from this register causes us to synchronously
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * process FIFO commands. There is no guarantee as to how many
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * commands each read will process.
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * CPU time spent processing FIFO commands will be billed to
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * the guest.
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * New drivers should avoid using this register unless they
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * need to guarantee that the FIFO is completely drained. It
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * is overkill for performing a sync-to-fence. Older drivers
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * will use this register for any type of synchronization.
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * SVGA_FIFO_BUSY --
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * This register is a fast way for the guest driver to check
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * whether the FIFO is already being processed. It reads and
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * writes at normal RAM speeds, with no monitor intervention.
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * If this register reads as TRUE, the host is guaranteeing that
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * any new commands written into the FIFO will be noticed before
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * the MKS goes back to sleep.
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * If this register reads as FALSE, no such guarantee can be
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * The guest should use this register to quickly determine
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * whether or not it needs to wake up the host. If the guest
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * just wrote a command or group of commands that it would like
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * the host to begin processing, it should:
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * 1. Read SVGA_FIFO_BUSY. If it reads as TRUE, no further
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * action is necessary.
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * 2. Write TRUE to SVGA_FIFO_BUSY. This informs future guest
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * code that we've already sent a SYNC to the host and we
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * don't need to send a duplicate.
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * 3. Write a reason to SVGA_REG_SYNC. This will send an
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * asynchronous wakeup to the MKS thread.
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * FIFO Capabilities
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * Fence -- Fence register and command are supported
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * Accel Front -- Front buffer only commands are supported
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * Pitch Lock -- Pitch lock register is supported
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * Video -- SVGA Video overlay units are supported
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * Escape -- Escape command is supported
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * XXX: Add longer descriptions for each capability, including a list
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * of the new features that each capability provides.
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * SVGA_FIFO_CAP_SCREEN_OBJECT --
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * Provides dynamic multi-screen rendering, for improved Unity and
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * multi-monitor modes. With Screen Object, the guest can
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * dynamically create and destroy 'screens', which can represent
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * Unity windows or virtual monitors. Screen Object also provides
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * strong guarantees that DMA operations happen only when
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * guest-initiated. Screen Object deprecates the BAR1 guest
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * framebuffer (GFB) and all commands that work only with the GFB.
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * New registers:
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * FIFO_CURSOR_SCREEN_ID, VIDEO_DATA_GMRID, VIDEO_DST_SCREEN_ID
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * New 2D commands:
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * DEFINE_SCREEN, DESTROY_SCREEN, DEFINE_GMRFB, BLIT_GMRFB_TO_SCREEN,
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * BLIT_SCREEN_TO_GMRFB, ANNOTATION_FILL, ANNOTATION_COPY
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * New 3D commands:
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * BLIT_SURFACE_TO_SCREEN
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * New guarantees:
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * - The host will not read or write guest memory, including the GFB,
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * except when explicitly initiated by a DMA command.
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * - All DMA, including legacy DMA like UPDATE and PRESENT_READBACK,
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * is guaranteed to complete before any subsequent FENCEs.
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * - All legacy commands which affect a Screen (UPDATE, PRESENT,
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * PRESENT_READBACK) as well as new Screen blit commands will
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * all behave consistently as blits, and memory will be read
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * or written in FIFO order.
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * For example, if you PRESENT from one SVGA3D surface to multiple
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * places on the screen, the data copied will always be from the
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * SVGA3D surface at the time the PRESENT was issued in the FIFO.
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * This was not necessarily true on devices without Screen Object.
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * This means that on devices that support Screen Object, the
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * PRESENT_READBACK command should not be necessary unless you
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * actually want to read back the results of 3D rendering into
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * system memory. (And for that, the BLIT_SCREEN_TO_GMRFB
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * command provides a strict superset of functionality.)
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * - When a screen is resized, either using Screen Object commands or
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * legacy multimon registers, its contents are preserved.
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * SVGA_FIFO_CAP_GMR2 --
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * Provides new commands to define and remap guest memory regions (GMR).
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * New 2D commands:
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * DEFINE_GMR2, REMAP_GMR2.
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * SVGA_FIFO_CAP_3D_HWVERSION_REVISED --
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * Indicates new register SVGA_FIFO_3D_HWVERSION_REVISED exists.
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * This register may replace SVGA_FIFO_3D_HWVERSION on platforms
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * that enforce graphics resource limits. This allows the platform
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * to clear SVGA_FIFO_3D_HWVERSION and disable 3D in legacy guest
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * drivers that do not limit their resources.
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * Note this is an alias to SVGA_FIFO_CAP_GMR2 because these indicators
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * are codependent (and thus we use a single capability bit).
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * SVGA_FIFO_CAP_SCREEN_OBJECT_2 --
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * Modifies the DEFINE_SCREEN command to include a guest provided
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * backing store in GMR memory and the bytesPerLine for the backing
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * store. This capability requires the use of a backing store when
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * creating screen objects. However if SVGA_FIFO_CAP_SCREEN_OBJECT
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * is present then backing stores are optional.
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * SVGA_FIFO_CAP_DEAD --
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * Drivers should not use this cap bit. This cap bit can not be
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * reused since some hosts already expose it.
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync#define SVGA_FIFO_CAP_3D_HWVERSION_REVISED SVGA_FIFO_CAP_GMR2
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * FIFO Flags
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * Accel Front -- Driver should use front buffer only commands
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync#define SVGA_FIFO_FLAG_RESERVED (1<<31) // Internal use only
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * FIFO reservation sentinel value
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * Video overlay support
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * Video capabilities that the guest is currently using
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * Offsets for the video overlay registers
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync SVGA_VIDEO_DATA_GMRID, // Optional, defaults to SVGA_GMR_FRAMEBUFFER
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync SVGA_VIDEO_DST_SCREEN_ID, // Optional, defaults to virtual coords (SVGA_ID_INVALID)
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * SVGA Overlay Units
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * width and height relate to the entire source video frame.
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * srcX, srcY, srcWidth and srcHeight represent subset of the source
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * video frame to be displayed.
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsynctypedef struct SVGAOverlayUnit {
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * SVGAScreenObject --
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * This is a new way to represent a guest's multi-monitor screen or
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * Unity window. Screen objects are only supported if the
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * SVGA_FIFO_CAP_SCREEN_OBJECT capability bit is set.
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * If Screen Objects are supported, they can be used to fully
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * replace the functionality provided by the framebuffer registers
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * (SVGA_REG_WIDTH, HEIGHT, etc.) and by SVGA_CAP_DISPLAY_TOPOLOGY.
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * The screen object is a struct with guaranteed binary
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * compatibility. New flags can be added, and the struct may grow,
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * but existing fields must retain their meaning.
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * Added with SVGA_FIFO_CAP_SCREEN_OBJECT_2 are required fields of
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * a SVGAGuestPtr that is used to back the screen contents. This
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * memory must come from the GFB. The guest is not allowed to
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * access the memory and doing so will have undefined results. The
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * backing store is required to be page aligned and the size is
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * padded to the next page boundry. The number of pages is:
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * (bytesPerLine * size.width * 4 + PAGE_SIZE - 1) / PAGE_SIZE
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * The pitch in the backingStore is required to be at least large
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * enough to hold a 32bbp scanline. It is recommended that the
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * driver pad bytesPerLine for a potential performance win.
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * The cloneCount field is treated as a hint from the guest that
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * the user wants this display to be cloned, countCount times. A
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * value of zero means no cloning should happen.
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync#define SVGA_SCREEN_MUST_BE_SET (1 << 0) // Must be set or results undefined
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync#define SVGA_SCREEN_HAS_ROOT SVGA_SCREEN_MUST_BE_SET // Deprecated
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync#define SVGA_SCREEN_IS_PRIMARY (1 << 1) // Guest considers this screen to be 'primary'
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync#define SVGA_SCREEN_FULLSCREEN_HINT (1 << 2) // Guest is running a fullscreen app here
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * Added with SVGA_FIFO_CAP_SCREEN_OBJECT_2. When the screen is
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * deactivated the base layer is defined to lose all contents and
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * become black. When a screen is deactivated the backing store is
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * optional. When set backingPtr and bytesPerLine will be ignored.
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * Added with SVGA_FIFO_CAP_SCREEN_OBJECT_2. When this flag is set
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * the screen contents will be outputted as all black to the user
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * though the base layer contents is preserved. The screen base layer
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * can still be read and written to like normal though the no visible
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * effect will be seen by the user. When the flag is changed the
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * screen will be blanked or redrawn to the current contents as needed
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * without any extra commands from the driver. This flag only has an
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * effect when the screen is not deactivated.
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * Added and required by SVGA_FIFO_CAP_SCREEN_OBJECT_2, optional
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * with SVGA_FIFO_CAP_SCREEN_OBJECT.
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * Commands in the command FIFO:
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * Command IDs defined below are used for the traditional 2D FIFO
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * communication (not all commands are available for all versions of the
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * SVGA FIFO protocol).
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * Note the holes in the command ID numbers: These commands have been
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * deprecated, and the old IDs must not be reused.
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * Command IDs from 1000 to 1999 are reserved for use by the SVGA3D
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * protocol.
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * Each command's parameters are described by the comments and
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * structs below.
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsynctypedef enum {
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * SVGA_CMD_UPDATE --
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * This is a DMA transfer which copies from the Guest Framebuffer
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * (GFB) at BAR1 + SVGA_REG_FB_OFFSET to any screens which
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * intersect with the provided virtual rectangle.
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * This command does not support using arbitrary guest memory as a
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * data source- it only works with the pre-defined GFB memory.
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * This command also does not support signed virtual coordinates.
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * If you have defined screens (using SVGA_CMD_DEFINE_SCREEN) with
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * negative root x/y coordinates, the negative portion of those
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * screens will not be reachable by this command.
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * This command is not necessary when using framebuffer
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * traces. Traces are automatically enabled if the SVGA FIFO is
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * disabled, and you may explicitly enable/disable traces using
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * SVGA_REG_TRACES. With traces enabled, any write to the GFB will
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * automatically act as if a subsequent SVGA_CMD_UPDATE was issued.
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * Traces and SVGA_CMD_UPDATE are the only supported ways to render
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * pseudocolor screen updates. The newer Screen Object commands
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * only support true color formats.
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * Availability:
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * Always available.
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * SVGA_CMD_RECT_COPY --
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * Perform a rectangular DMA transfer from one area of the GFB to
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * another, and copy the result to any screens which intersect it.
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * Availability:
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * SVGA_CAP_RECT_COPY
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * SVGA_CMD_DEFINE_CURSOR --
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * Provide a new cursor image, as an AND/XOR mask.
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * The recommended way to position the cursor overlay is by using
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * the SVGA_FIFO_CURSOR_* registers, supported by the
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * SVGA_FIFO_CAP_CURSOR_BYPASS_3 capability.
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * Availability:
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * SVGA_CAP_CURSOR
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync uint32_t andMaskDepth; // Value must be 1 or equal to BITS_PER_PIXEL
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync uint32_t xorMaskDepth; // Value must be 1 or equal to BITS_PER_PIXEL
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * Followed by scanline data for AND mask, then XOR mask.
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * Each scanline is padded to a 32-bit boundary.
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * SVGA_CMD_DEFINE_ALPHA_CURSOR --
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * Provide a new cursor image, in 32-bit BGRA format.
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * The recommended way to position the cursor overlay is by using
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * the SVGA_FIFO_CURSOR_* registers, supported by the
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * SVGA_FIFO_CAP_CURSOR_BYPASS_3 capability.
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * Availability:
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * SVGA_CAP_ALPHA_CURSOR
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync /* Followed by scanline data */
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * SVGA_CMD_UPDATE_VERBOSE --
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * Just like SVGA_CMD_UPDATE, but also provide a per-rectangle
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * 'reason' value, an opaque cookie which is used by internal
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * debugging tools. Third party drivers should not use this
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * Availability:
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * SVGA_CAP_EXTENDED_FIFO
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * SVGA_CMD_FRONT_ROP_FILL --
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * This is a hint which tells the SVGA device that the driver has
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * just filled a rectangular region of the GFB with a solid
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * color. Instead of reading these pixels from the GFB, the device
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * can assume that they all equal 'color'. This is primarily used
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * for remote desktop protocols.
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * Availability:
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * SVGA_FIFO_CAP_ACCELFRONT
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * SVGA_CMD_FENCE --
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * Insert a synchronization fence. When the SVGA device reaches
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * this command, it will copy the 'fence' value into the
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * SVGA_FIFO_FENCE register. It will also compare the fence against
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * SVGA_FIFO_FENCE_GOAL. If the fence matches the goal and the
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * SVGA_IRQFLAG_FENCE_GOAL interrupt is enabled, the device will
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * raise this interrupt.
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * Availability:
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * SVGA_FIFO_FENCE for this command,
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * SVGA_CAP_IRQMASK for SVGA_FIFO_FENCE_GOAL.
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * SVGA_CMD_ESCAPE --
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * Send an extended or vendor-specific variable length command.
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * This is used for video overlay, third party plugins, and
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * internal debugging tools. See svga_escape.h
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * Availability:
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * SVGA_FIFO_CAP_ESCAPE
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync /* followed by 'size' bytes of data */
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * SVGA_CMD_DEFINE_SCREEN --
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * Define or redefine an SVGAScreenObject. See the description of
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * SVGAScreenObject above. The video driver is responsible for
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * generating new screen IDs. They should be small positive
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * integers. The virtual device will have an implementation
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * specific upper limit on the number of screen IDs
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * supported. Drivers are responsible for recycling IDs. The first
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * valid ID is zero.
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * - Interaction with other registers:
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * For backwards compatibility, when the GFB mode registers (WIDTH,
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * HEIGHT, PITCHLOCK, BITS_PER_PIXEL) are modified, the SVGA device
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * deletes all screens other than screen #0, and redefines screen
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * #0 according to the specified mode. Drivers that use
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * SVGA_CMD_DEFINE_SCREEN should destroy or redefine screen #0.
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * If you use screen objects, do not use the legacy multi-mon
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * registers (SVGA_REG_NUM_GUEST_DISPLAYS, SVGA_REG_DISPLAY_*).
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * Availability:
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * SVGA_FIFO_CAP_SCREEN_OBJECT or SVGA_FIFO_CAP_SCREEN_OBJECT_2
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync SVGAScreenObject screen; // Variable-length according to version
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * SVGA_CMD_DESTROY_SCREEN --
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * Destroy an SVGAScreenObject. Its ID is immediately available for
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * Availability:
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * SVGA_FIFO_CAP_SCREEN_OBJECT or SVGA_FIFO_CAP_SCREEN_OBJECT_2
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * SVGA_CMD_DEFINE_GMRFB --
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * This command sets a piece of SVGA device state called the
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * Guest Memory Region Framebuffer, or GMRFB. The GMRFB is a
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * piece of light-weight state which identifies the location and
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * format of an image in guest memory or in BAR1. The GMRFB has
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * an arbitrary size, and it doesn't need to match the geometry
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * of the GFB or any screen object.
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * The GMRFB can be redefined as often as you like. You could
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * always use the same GMRFB, you could redefine it before
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * rendering from a different guest screen, or you could even
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * redefine it before every blit.
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * There are multiple ways to use this command. The simplest way is
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * to use it to move the framebuffer either to elsewhere in the GFB
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * (BAR1) memory region, or to a user-defined GMR. This lets a
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * driver use a framebuffer allocated entirely out of normal system
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * memory, which we encourage.
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * Another way to use this command is to set up a ring buffer of
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * updates in GFB memory. If a driver wants to ensure that no
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * frames are skipped by the SVGA device, it is important that the
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * driver not modify the source data for a blit until the device is
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * done processing the command. One efficient way to accomplish
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * this is to use a ring of small DMA buffers. Each buffer is used
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * for one blit, then we move on to the next buffer in the
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * ring. The FENCE mechanism is used to protect each buffer from
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * re-use until the device is finished with that buffer's
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * corresponding blit.
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * This command does not affect the meaning of SVGA_CMD_UPDATE.
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * UPDATEs always occur from the legacy GFB memory area. This
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * command has no support for pseudocolor GMRFBs. Currently only
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * true-color 15, 16, and 24-bit depths are supported. Future
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * devices may expose capabilities for additional framebuffer
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * The default GMRFB value is undefined. Drivers must always send
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * this command at least once before performing any blit from the
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * Availability:
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * SVGA_FIFO_CAP_SCREEN_OBJECT or SVGA_FIFO_CAP_SCREEN_OBJECT_2
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * SVGA_CMD_BLIT_GMRFB_TO_SCREEN --
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * This is a guest-to-host blit. It performs a DMA operation to
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * copy a rectangular region of pixels from the current GMRFB to
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * one or more Screen Objects.
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * The destination coordinate may be specified relative to a
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * screen's origin (if a screen ID is specified) or relative to the
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * virtual coordinate system's origin (if the screen ID is
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * SVGA_ID_INVALID). The actual destination may span zero or more
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * screens, in the case of a virtual destination rect or a rect
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * which extends off the edge of the specified screen.
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * This command writes to the screen's "base layer": the underlying
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * framebuffer which exists below any cursor or video overlays. No
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * action is necessary to explicitly hide or update any overlays
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * which exist on top of the updated region.
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * The SVGA device is guaranteed to finish reading from the GMRFB
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * by the time any subsequent FENCE commands are reached.
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * This command consumes an annotation. See the
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * SVGA_CMD_ANNOTATION_* commands for details.
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * Availability:
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * SVGA_FIFO_CAP_SCREEN_OBJECT or SVGA_FIFO_CAP_SCREEN_OBJECT_2
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * SVGA_CMD_BLIT_SCREEN_TO_GMRFB --
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * This is a host-to-guest blit. It performs a DMA operation to
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * copy a rectangular region of pixels from a single Screen Object
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * back to the current GMRFB.
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * Usage note: This command should be used rarely. It will
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * typically be inefficient, but it is necessary for some types of
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * synchronization between 3D (GPU) and 2D (CPU) rendering into
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * overlapping areas of a screen.
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * The source coordinate is specified relative to a screen's
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * origin. The provided screen ID must be valid. If any parameters
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * are invalid, the resulting pixel values are undefined.
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * This command reads the screen's "base layer". Overlays like
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * video and cursor are not included, but any data which was sent
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * using a blit-to-screen primitive will be available, no matter
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * whether the data's original source was the GMRFB or the 3D
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * acceleration hardware.
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * Note that our guest-to-host blits and host-to-guest blits aren't
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * symmetric in their current implementation. While the parameters
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * are identical, host-to-guest blits are a lot less featureful.
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * They do not support clipping: If the source parameters don't
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * fully fit within a screen, the blit fails. They must originate
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * from exactly one screen. Virtual coordinates are not directly
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * supported.
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * Host-to-guest blits do support the same set of GMRFB formats
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * offered by guest-to-host blits.
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * The SVGA device is guaranteed to finish writing to the GMRFB by
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * the time any subsequent FENCE commands are reached.
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * Availability:
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * SVGA_FIFO_CAP_SCREEN_OBJECT or SVGA_FIFO_CAP_SCREEN_OBJECT_2
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * SVGA_CMD_ANNOTATION_FILL --
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * This is a blit annotation. This command stores a small piece of
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * device state which is consumed by the next blit-to-screen
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * command. The state is only cleared by commands which are
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * specifically documented as consuming an annotation. Other
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * commands (such as ESCAPEs for debugging) may intervene between
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * the annotation and its associated blit.
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * This annotation is a promise about the contents of the next
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * blit: The video driver is guaranteeing that all pixels in that
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * blit will have the same value, specified here as a color in
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * SVGAColorBGRX format.
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * The SVGA device can still render the blit correctly even if it
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * ignores this annotation, but the annotation may allow it to
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * perform the blit more efficiently, for example by ignoring the
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * source data and performing a fill in hardware.
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * This annotation is most important for performance when the
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * user's display is being remoted over a network connection.
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * Availability:
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * SVGA_FIFO_CAP_SCREEN_OBJECT or SVGA_FIFO_CAP_SCREEN_OBJECT_2
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * SVGA_CMD_ANNOTATION_COPY --
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * This is a blit annotation. See SVGA_CMD_ANNOTATION_FILL for more
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * information about annotations.
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * This annotation is a promise about the contents of the next
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * blit: The video driver is guaranteeing that all pixels in that
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * blit will have the same value as those which already exist at an
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * identically-sized region on the same or a different screen.
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * Note that the source pixels for the COPY in this annotation are
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * sampled before applying the anqnotation's associated blit. They
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * are allowed to overlap with the blit's destination pixels.
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * The copy source rectangle is specified the same way as the blit
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * destination: it can be a rectangle which spans zero or more
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * screens, specified relative to either a screen or to the virtual
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * coordinate system's origin. If the source rectangle includes
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * pixels which are not from exactly one screen, the results are
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * undefined.
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * Availability:
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * SVGA_FIFO_CAP_SCREEN_OBJECT or SVGA_FIFO_CAP_SCREEN_OBJECT_2
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * SVGA_CMD_DEFINE_GMR2 --
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * Define guest memory region v2. See the description of GMRs above.
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * Availability:
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * SVGA_CAP_GMR2
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * SVGA_CMD_REMAP_GMR2 --
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * Remap guest memory region v2. See the description of GMRs above.
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * This command allows guest to modify a portion of an existing GMR by
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * invalidating it or reassigning it to different guest physical pages.
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * The pages are identified by physical page number (PPN). The pages
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * are assumed to be pinned and valid for DMA operations.
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * Description of command flags:
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * SVGA_REMAP_GMR2_VIA_GMR: If enabled, references a PPN list in a GMR.
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * The PPN list must not overlap with the remap region (this can be
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * handled trivially by referencing a separate GMR). If flag is
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * disabled, PPN list is appended to SVGARemapGMR command.
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * SVGA_REMAP_GMR2_PPN64: If set, PPN list is in PPN64 format, otherwise
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * it is in PPN32 format.
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * SVGA_REMAP_GMR2_SINGLE_PPN: If set, PPN list contains a single entry.
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * A single PPN can be used to invalidate a portion of a GMR or
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * map it to to a single guest scratch page.
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * Availability:
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * SVGA_CAP_GMR2
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsynctypedef enum {
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync uint32_t offsetPages; // offset in pages to begin remap
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * Followed by additional data depending on SVGARemapGMR2Flags.
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * If flag SVGA_REMAP_GMR2_VIA_GMR is set, single SVGAGuestPtr follows.
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * Otherwise an array of page descriptors in PPN32 or PPN64 format
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * (according to flag SVGA_REMAP_GMR2_PPN64) follows. If flag
332aaa1da374e694e37fdfe0a00bbe040e670453vboxsync * SVGA_REMAP_GMR2_SINGLE_PPN is set, array contains a single entry.