DevVGA.h revision e60946156fb485f563a11846fd0836396e4bad92
43af8389304c77c3d4db525de8907cb74207c380vboxsync/* $Id$ */
43af8389304c77c3d4db525de8907cb74207c380vboxsync/** @file
43af8389304c77c3d4db525de8907cb74207c380vboxsync * DevVGA - VBox VGA/VESA device, internal header.
43af8389304c77c3d4db525de8907cb74207c380vboxsync */
43af8389304c77c3d4db525de8907cb74207c380vboxsync
43af8389304c77c3d4db525de8907cb74207c380vboxsync/*
c7814cf6e1240a519cbec0441e033d0e2470ed00vboxsync * Copyright (C) 2006-2007 Oracle Corporation
43af8389304c77c3d4db525de8907cb74207c380vboxsync *
43af8389304c77c3d4db525de8907cb74207c380vboxsync * This file is part of VirtualBox Open Source Edition (OSE), as
43af8389304c77c3d4db525de8907cb74207c380vboxsync * available from http://www.virtualbox.org. This file is free software;
43af8389304c77c3d4db525de8907cb74207c380vboxsync * you can redistribute it and/or modify it under the terms of the GNU
43af8389304c77c3d4db525de8907cb74207c380vboxsync * General Public License (GPL) as published by the Free Software
43af8389304c77c3d4db525de8907cb74207c380vboxsync * Foundation, in version 2 as it comes in the "COPYING" file of the
43af8389304c77c3d4db525de8907cb74207c380vboxsync * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
43af8389304c77c3d4db525de8907cb74207c380vboxsync * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
43af8389304c77c3d4db525de8907cb74207c380vboxsync * --------------------------------------------------------------------
43af8389304c77c3d4db525de8907cb74207c380vboxsync *
43af8389304c77c3d4db525de8907cb74207c380vboxsync * This code is based on:
43af8389304c77c3d4db525de8907cb74207c380vboxsync *
43af8389304c77c3d4db525de8907cb74207c380vboxsync * QEMU internal VGA defines.
43af8389304c77c3d4db525de8907cb74207c380vboxsync *
43af8389304c77c3d4db525de8907cb74207c380vboxsync * Copyright (c) 2003-2004 Fabrice Bellard
43af8389304c77c3d4db525de8907cb74207c380vboxsync *
43af8389304c77c3d4db525de8907cb74207c380vboxsync * Permission is hereby granted, free of charge, to any person obtaining a copy
43af8389304c77c3d4db525de8907cb74207c380vboxsync * of this software and associated documentation files (the "Software"), to deal
43af8389304c77c3d4db525de8907cb74207c380vboxsync * in the Software without restriction, including without limitation the rights
43af8389304c77c3d4db525de8907cb74207c380vboxsync * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
43af8389304c77c3d4db525de8907cb74207c380vboxsync * copies of the Software, and to permit persons to whom the Software is
43af8389304c77c3d4db525de8907cb74207c380vboxsync * furnished to do so, subject to the following conditions:
43af8389304c77c3d4db525de8907cb74207c380vboxsync *
43af8389304c77c3d4db525de8907cb74207c380vboxsync * The above copyright notice and this permission notice shall be included in
43af8389304c77c3d4db525de8907cb74207c380vboxsync * all copies or substantial portions of the Software.
43af8389304c77c3d4db525de8907cb74207c380vboxsync *
1e7030f54deae0a8aa27817ab26c5d6d6c246541vboxsync * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
43af8389304c77c3d4db525de8907cb74207c380vboxsync * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
1a62088b18e24a01c1dc85e13d60468e78bd649dvboxsync * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
43af8389304c77c3d4db525de8907cb74207c380vboxsync * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
43af8389304c77c3d4db525de8907cb74207c380vboxsync * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
4152e1d3f89dc5e2319a53c242e8e7cfcdf3726evboxsync * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
43af8389304c77c3d4db525de8907cb74207c380vboxsync * THE SOFTWARE.
43af8389304c77c3d4db525de8907cb74207c380vboxsync */
43af8389304c77c3d4db525de8907cb74207c380vboxsync
43af8389304c77c3d4db525de8907cb74207c380vboxsync/** Use VBE bytewise I/O. Only needed for Windows Longhorn/Vista betas and backwards compatibility. */
43af8389304c77c3d4db525de8907cb74207c380vboxsync#define VBE_BYTEWISE_IO
43af8389304c77c3d4db525de8907cb74207c380vboxsync
43af8389304c77c3d4db525de8907cb74207c380vboxsync/** Use VBE new dynamic mode list.
43af8389304c77c3d4db525de8907cb74207c380vboxsync * If this is not defined, no checks are carried out to see if the modes all
43af8389304c77c3d4db525de8907cb74207c380vboxsync * fit into the framebuffer! See the VRAM_SIZE_FIX define. */
43af8389304c77c3d4db525de8907cb74207c380vboxsync#define VBE_NEW_DYN_LIST
1a62088b18e24a01c1dc85e13d60468e78bd649dvboxsync
1a62088b18e24a01c1dc85e13d60468e78bd649dvboxsync#ifdef VBOX
1a62088b18e24a01c1dc85e13d60468e78bd649dvboxsync/** The default amount of VRAM. */
1a62088b18e24a01c1dc85e13d60468e78bd649dvboxsync# define VGA_VRAM_DEFAULT (_4M)
1a62088b18e24a01c1dc85e13d60468e78bd649dvboxsync/** The maximum amount of VRAM. Limited by VBOX_MAX_ALLOC_PAGE_COUNT. */
1a62088b18e24a01c1dc85e13d60468e78bd649dvboxsync# define VGA_VRAM_MAX (256 * _1M)
1a62088b18e24a01c1dc85e13d60468e78bd649dvboxsync/** The minimum amount of VRAM. */
1a62088b18e24a01c1dc85e13d60468e78bd649dvboxsync# define VGA_VRAM_MIN (_1M)
1a62088b18e24a01c1dc85e13d60468e78bd649dvboxsync#endif
1a62088b18e24a01c1dc85e13d60468e78bd649dvboxsync
1a62088b18e24a01c1dc85e13d60468e78bd649dvboxsync#include <VBox/Hardware/VBoxVideoVBE.h>
1a62088b18e24a01c1dc85e13d60468e78bd649dvboxsync
1a62088b18e24a01c1dc85e13d60468e78bd649dvboxsync#ifdef VBOX_WITH_HGSMI
1a62088b18e24a01c1dc85e13d60468e78bd649dvboxsync# include "HGSMI/HGSMIHost.h"
1a62088b18e24a01c1dc85e13d60468e78bd649dvboxsync#endif /* VBOX_WITH_HGSMI */
1a62088b18e24a01c1dc85e13d60468e78bd649dvboxsync#include "DevVGASavedState.h"
1a62088b18e24a01c1dc85e13d60468e78bd649dvboxsync
1a62088b18e24a01c1dc85e13d60468e78bd649dvboxsync#define MSR_COLOR_EMULATION 0x01
1a62088b18e24a01c1dc85e13d60468e78bd649dvboxsync#define MSR_PAGE_SELECT 0x20
1a62088b18e24a01c1dc85e13d60468e78bd649dvboxsync
1a62088b18e24a01c1dc85e13d60468e78bd649dvboxsync#define ST01_V_RETRACE 0x08
1a62088b18e24a01c1dc85e13d60468e78bd649dvboxsync#define ST01_DISP_ENABLE 0x01
1a62088b18e24a01c1dc85e13d60468e78bd649dvboxsync
1a62088b18e24a01c1dc85e13d60468e78bd649dvboxsync/* bochs VBE support */
1a62088b18e24a01c1dc85e13d60468e78bd649dvboxsync#define CONFIG_BOCHS_VBE
1a62088b18e24a01c1dc85e13d60468e78bd649dvboxsync
1a62088b18e24a01c1dc85e13d60468e78bd649dvboxsync#ifdef CONFIG_BOCHS_VBE
1a62088b18e24a01c1dc85e13d60468e78bd649dvboxsync
1a62088b18e24a01c1dc85e13d60468e78bd649dvboxsync/* Cross reference with <VBox/Hardware/VBoxVideoVBE.h> */
1a62088b18e24a01c1dc85e13d60468e78bd649dvboxsync#define VBE_DISPI_INDEX_NB_SAVED 0xb /* Number of saved registers (vbe_regs array) */
1a62088b18e24a01c1dc85e13d60468e78bd649dvboxsync#define VBE_DISPI_INDEX_NB 0xc /* Total number of VBE registers */
1a62088b18e24a01c1dc85e13d60468e78bd649dvboxsync
1a62088b18e24a01c1dc85e13d60468e78bd649dvboxsync#define VGA_STATE_COMMON_BOCHS_VBE \
1a62088b18e24a01c1dc85e13d60468e78bd649dvboxsync uint16_t vbe_index; \
1a62088b18e24a01c1dc85e13d60468e78bd649dvboxsync uint16_t vbe_regs[VBE_DISPI_INDEX_NB]; \
1a62088b18e24a01c1dc85e13d60468e78bd649dvboxsync uint16_t alignment[3]; /* pad to 64 bits */ \
1a62088b18e24a01c1dc85e13d60468e78bd649dvboxsync uint32_t vbe_start_addr; \
1a62088b18e24a01c1dc85e13d60468e78bd649dvboxsync uint32_t vbe_line_offset; \
1a62088b18e24a01c1dc85e13d60468e78bd649dvboxsync uint32_t vbe_bank_max;
1a62088b18e24a01c1dc85e13d60468e78bd649dvboxsync
1a62088b18e24a01c1dc85e13d60468e78bd649dvboxsync#else
1a62088b18e24a01c1dc85e13d60468e78bd649dvboxsync
1a62088b18e24a01c1dc85e13d60468e78bd649dvboxsync#define VGA_STATE_COMMON_BOCHS_VBE
1a62088b18e24a01c1dc85e13d60468e78bd649dvboxsync
1a62088b18e24a01c1dc85e13d60468e78bd649dvboxsync#endif /* !CONFIG_BOCHS_VBE */
1a62088b18e24a01c1dc85e13d60468e78bd649dvboxsync
1a62088b18e24a01c1dc85e13d60468e78bd649dvboxsync#define CH_ATTR_SIZE (160 * 100)
1a62088b18e24a01c1dc85e13d60468e78bd649dvboxsync#define VGA_MAX_HEIGHT VBE_DISPI_MAX_YRES
1a62088b18e24a01c1dc85e13d60468e78bd649dvboxsync
43af8389304c77c3d4db525de8907cb74207c380vboxsynctypedef struct vga_retrace_s {
43af8389304c77c3d4db525de8907cb74207c380vboxsync unsigned frame_cclks; /* Character clocks per frame. */
43af8389304c77c3d4db525de8907cb74207c380vboxsync unsigned frame_ns; /* Frame duration in ns. */
43af8389304c77c3d4db525de8907cb74207c380vboxsync unsigned cclk_ns; /* Character clock duration in ns. */
43af8389304c77c3d4db525de8907cb74207c380vboxsync unsigned vb_start; /* Vertical blanking start (scanline). */
43af8389304c77c3d4db525de8907cb74207c380vboxsync unsigned vb_end; /* Vertical blanking end (scanline). */
1a62088b18e24a01c1dc85e13d60468e78bd649dvboxsync unsigned vb_end_ns; /* Vertical blanking end time (length) in ns. */
1a62088b18e24a01c1dc85e13d60468e78bd649dvboxsync unsigned vs_start; /* Vertical sync start (scanline). */
1a62088b18e24a01c1dc85e13d60468e78bd649dvboxsync unsigned vs_end; /* Vertical sync end (scanline). */
1a62088b18e24a01c1dc85e13d60468e78bd649dvboxsync unsigned vs_start_ns; /* Vertical sync start time in ns. */
1a62088b18e24a01c1dc85e13d60468e78bd649dvboxsync unsigned vs_end_ns; /* Vertical sync end time in ns. */
43af8389304c77c3d4db525de8907cb74207c380vboxsync unsigned h_total; /* Horizontal total (cclks per scanline). */
1a62088b18e24a01c1dc85e13d60468e78bd649dvboxsync unsigned h_total_ns; /* Scanline duration in ns. */
43af8389304c77c3d4db525de8907cb74207c380vboxsync unsigned hb_start; /* Horizontal blanking start (cclk). */
1a62088b18e24a01c1dc85e13d60468e78bd649dvboxsync unsigned hb_end; /* Horizontal blanking end (cclk). */
43af8389304c77c3d4db525de8907cb74207c380vboxsync unsigned hb_end_ns; /* Horizontal blanking end time (length) in ns. */
43af8389304c77c3d4db525de8907cb74207c380vboxsync unsigned v_freq_hz; /* Vertical refresh rate to emulate. */
43af8389304c77c3d4db525de8907cb74207c380vboxsync} vga_retrace_s;
43af8389304c77c3d4db525de8907cb74207c380vboxsync
43af8389304c77c3d4db525de8907cb74207c380vboxsync#ifndef VBOX
43af8389304c77c3d4db525de8907cb74207c380vboxsync#define VGA_STATE_COMMON \
43af8389304c77c3d4db525de8907cb74207c380vboxsync uint8_t *vram_ptr; \
43af8389304c77c3d4db525de8907cb74207c380vboxsync unsigned long vram_offset; \
1a62088b18e24a01c1dc85e13d60468e78bd649dvboxsync unsigned int vram_size; \
1a62088b18e24a01c1dc85e13d60468e78bd649dvboxsync uint32_t latch; \
43af8389304c77c3d4db525de8907cb74207c380vboxsync uint8_t sr_index; \
1a62088b18e24a01c1dc85e13d60468e78bd649dvboxsync uint8_t sr[256]; \
43af8389304c77c3d4db525de8907cb74207c380vboxsync uint8_t gr_index; \
1a62088b18e24a01c1dc85e13d60468e78bd649dvboxsync uint8_t gr[256]; \
3904c2d16fea12be79d817b255d59d480658b799vboxsync uint8_t ar_index; \
3904c2d16fea12be79d817b255d59d480658b799vboxsync uint8_t ar[21]; \
43af8389304c77c3d4db525de8907cb74207c380vboxsync int ar_flip_flop; \
1a62088b18e24a01c1dc85e13d60468e78bd649dvboxsync uint8_t cr_index; \
43af8389304c77c3d4db525de8907cb74207c380vboxsync uint8_t cr[256]; /* CRT registers */ \
1a62088b18e24a01c1dc85e13d60468e78bd649dvboxsync uint8_t msr; /* Misc Output Register */ \
43af8389304c77c3d4db525de8907cb74207c380vboxsync uint8_t fcr; /* Feature Control Register */ \
1a62088b18e24a01c1dc85e13d60468e78bd649dvboxsync uint8_t st00; /* status 0 */ \
43af8389304c77c3d4db525de8907cb74207c380vboxsync uint8_t st01; /* status 1 */ \
1a62088b18e24a01c1dc85e13d60468e78bd649dvboxsync uint8_t dac_state; \
43af8389304c77c3d4db525de8907cb74207c380vboxsync uint8_t dac_sub_index; \
43af8389304c77c3d4db525de8907cb74207c380vboxsync uint8_t dac_read_index; \
43af8389304c77c3d4db525de8907cb74207c380vboxsync uint8_t dac_write_index; \
43af8389304c77c3d4db525de8907cb74207c380vboxsync uint8_t dac_cache[3]; /* used when writing */ \
43af8389304c77c3d4db525de8907cb74207c380vboxsync uint8_t palette[768]; \
43af8389304c77c3d4db525de8907cb74207c380vboxsync int32_t bank_offset; \
43af8389304c77c3d4db525de8907cb74207c380vboxsync int (*get_bpp)(struct VGAState *s); \
43af8389304c77c3d4db525de8907cb74207c380vboxsync void (*get_offsets)(struct VGAState *s, \
43af8389304c77c3d4db525de8907cb74207c380vboxsync uint32_t *pline_offset, \
1a62088b18e24a01c1dc85e13d60468e78bd649dvboxsync uint32_t *pstart_addr, \
43af8389304c77c3d4db525de8907cb74207c380vboxsync uint32_t *pline_compare); \
43af8389304c77c3d4db525de8907cb74207c380vboxsync void (*get_resolution)(struct VGAState *s, \
1a62088b18e24a01c1dc85e13d60468e78bd649dvboxsync int *pwidth, \
43af8389304c77c3d4db525de8907cb74207c380vboxsync int *pheight); \
1a62088b18e24a01c1dc85e13d60468e78bd649dvboxsync VGA_STATE_COMMON_BOCHS_VBE \
43af8389304c77c3d4db525de8907cb74207c380vboxsync /* display refresh support */ \
43af8389304c77c3d4db525de8907cb74207c380vboxsync DisplayState *ds; \
1a62088b18e24a01c1dc85e13d60468e78bd649dvboxsync uint32_t font_offsets[2]; \
43af8389304c77c3d4db525de8907cb74207c380vboxsync int graphic_mode; \
1a62088b18e24a01c1dc85e13d60468e78bd649dvboxsync uint8_t shift_control; \
43af8389304c77c3d4db525de8907cb74207c380vboxsync uint8_t double_scan; \
43af8389304c77c3d4db525de8907cb74207c380vboxsync uint32_t line_offset; \
1a62088b18e24a01c1dc85e13d60468e78bd649dvboxsync uint32_t line_compare; \
43af8389304c77c3d4db525de8907cb74207c380vboxsync uint32_t start_addr; \
1a62088b18e24a01c1dc85e13d60468e78bd649dvboxsync uint32_t plane_updated; \
1a62088b18e24a01c1dc85e13d60468e78bd649dvboxsync uint8_t last_cw, last_ch; \
1a62088b18e24a01c1dc85e13d60468e78bd649dvboxsync uint32_t last_width, last_height; /* in chars or pixels */ \
1a62088b18e24a01c1dc85e13d60468e78bd649dvboxsync uint32_t last_scr_width, last_scr_height; /* in pixels */ \
43af8389304c77c3d4db525de8907cb74207c380vboxsync uint8_t cursor_start, cursor_end; \
1a62088b18e24a01c1dc85e13d60468e78bd649dvboxsync uint32_t cursor_offset; \
43af8389304c77c3d4db525de8907cb74207c380vboxsync unsigned int (*rgb_to_pixel)(unsigned int r, \
43af8389304c77c3d4db525de8907cb74207c380vboxsync unsigned int g, unsigned b); \
43af8389304c77c3d4db525de8907cb74207c380vboxsync /* hardware mouse cursor support */ \
4152e1d3f89dc5e2319a53c242e8e7cfcdf3726evboxsync uint32_t invalidated_y_table[VGA_MAX_HEIGHT / 32]; \
1e7030f54deae0a8aa27817ab26c5d6d6c246541vboxsync void (*cursor_invalidate)(struct VGAState *s); \
1e7030f54deae0a8aa27817ab26c5d6d6c246541vboxsync void (*cursor_draw_line)(struct VGAState *s, uint8_t *d, int y); \
1e7030f54deae0a8aa27817ab26c5d6d6c246541vboxsync /* tell for each page if it has been updated since the last time */ \
1e7030f54deae0a8aa27817ab26c5d6d6c246541vboxsync uint32_t last_palette[256]; \
1e7030f54deae0a8aa27817ab26c5d6d6c246541vboxsync uint32_t last_ch_attr[CH_ATTR_SIZE]; /* XXX: make it dynamic */
1e7030f54deae0a8aa27817ab26c5d6d6c246541vboxsync
1e7030f54deae0a8aa27817ab26c5d6d6c246541vboxsync#else /* VBOX */
1e7030f54deae0a8aa27817ab26c5d6d6c246541vboxsync
1e7030f54deae0a8aa27817ab26c5d6d6c246541vboxsyncstruct VGAState;
1e7030f54deae0a8aa27817ab26c5d6d6c246541vboxsynctypedef int FNGETBPP(struct VGAState *s);
1e7030f54deae0a8aa27817ab26c5d6d6c246541vboxsynctypedef void FNGETOFFSETS(struct VGAState *s, uint32_t *pline_offset, uint32_t *pstart_addr, uint32_t *pline_compare);
1e7030f54deae0a8aa27817ab26c5d6d6c246541vboxsynctypedef void FNGETRESOLUTION(struct VGAState *s, int *pwidth, int *pheight);
6efcec753717bae68ada4b060466934b111739fdvboxsynctypedef unsigned int FNRGBTOPIXEL(unsigned int r, unsigned int g, unsigned b);
6efcec753717bae68ada4b060466934b111739fdvboxsynctypedef void FNCURSORINVALIDATE(struct VGAState *s);
3a1d76f6489a485dfa7e3784c1fa76b4a53c28afvboxsynctypedef void FNCURSORDRAWLINE(struct VGAState *s, uint8_t *d, int y);
6efcec753717bae68ada4b060466934b111739fdvboxsync
3a1d76f6489a485dfa7e3784c1fa76b4a53c28afvboxsync/* bird: vram_offset have been remove, function pointers declared external,
3a1d76f6489a485dfa7e3784c1fa76b4a53c28afvboxsync some type changes, and some padding have been added. */
1a62088b18e24a01c1dc85e13d60468e78bd649dvboxsync#define VGA_STATE_COMMON \
3a1d76f6489a485dfa7e3784c1fa76b4a53c28afvboxsync R3PTRTYPE(uint8_t *) vram_ptrR3; \
6efcec753717bae68ada4b060466934b111739fdvboxsync uint32_t vram_size; \
6efcec753717bae68ada4b060466934b111739fdvboxsync uint32_t latch; \
6efcec753717bae68ada4b060466934b111739fdvboxsync uint8_t sr_index; \
3a1d76f6489a485dfa7e3784c1fa76b4a53c28afvboxsync uint8_t sr[256]; \
3a1d76f6489a485dfa7e3784c1fa76b4a53c28afvboxsync uint8_t gr_index; \
3a1d76f6489a485dfa7e3784c1fa76b4a53c28afvboxsync uint8_t gr[256]; \
3a1d76f6489a485dfa7e3784c1fa76b4a53c28afvboxsync uint8_t ar_index; \
3a1d76f6489a485dfa7e3784c1fa76b4a53c28afvboxsync uint8_t ar[21]; \
3a1d76f6489a485dfa7e3784c1fa76b4a53c28afvboxsync int32_t ar_flip_flop; \
3a1d76f6489a485dfa7e3784c1fa76b4a53c28afvboxsync uint8_t cr_index; \
6efcec753717bae68ada4b060466934b111739fdvboxsync uint8_t cr[256]; /* CRT registers */ \
3a1d76f6489a485dfa7e3784c1fa76b4a53c28afvboxsync uint8_t msr; /* Misc Output Register */ \
3a1d76f6489a485dfa7e3784c1fa76b4a53c28afvboxsync uint8_t fcr; /* Feature Control Register */ \
3a1d76f6489a485dfa7e3784c1fa76b4a53c28afvboxsync uint8_t st00; /* status 0 */ \
3a1d76f6489a485dfa7e3784c1fa76b4a53c28afvboxsync uint8_t st01; /* status 1 */ \
3a1d76f6489a485dfa7e3784c1fa76b4a53c28afvboxsync uint8_t dac_state; \
6efcec753717bae68ada4b060466934b111739fdvboxsync uint8_t dac_sub_index; \
3a1d76f6489a485dfa7e3784c1fa76b4a53c28afvboxsync uint8_t dac_read_index; \
3a1d76f6489a485dfa7e3784c1fa76b4a53c28afvboxsync uint8_t dac_write_index; \
3a1d76f6489a485dfa7e3784c1fa76b4a53c28afvboxsync uint8_t dac_cache[3]; /* used when writing */ \
3a1d76f6489a485dfa7e3784c1fa76b4a53c28afvboxsync uint8_t palette[768]; \
3a1d76f6489a485dfa7e3784c1fa76b4a53c28afvboxsync int32_t bank_offset; \
3a1d76f6489a485dfa7e3784c1fa76b4a53c28afvboxsync int32_t padding0; \
3a1d76f6489a485dfa7e3784c1fa76b4a53c28afvboxsync R3PTRTYPE(FNGETBPP *) get_bpp; \
3a1d76f6489a485dfa7e3784c1fa76b4a53c28afvboxsync R3PTRTYPE(FNGETOFFSETS *) get_offsets; \
3a1d76f6489a485dfa7e3784c1fa76b4a53c28afvboxsync R3PTRTYPE(FNGETRESOLUTION *) get_resolution; \
6efcec753717bae68ada4b060466934b111739fdvboxsync VGA_STATE_COMMON_BOCHS_VBE \
3a1d76f6489a485dfa7e3784c1fa76b4a53c28afvboxsync /* display refresh support */ \
3a1d76f6489a485dfa7e3784c1fa76b4a53c28afvboxsync uint32_t font_offsets[2]; \
3a1d76f6489a485dfa7e3784c1fa76b4a53c28afvboxsync int32_t graphic_mode; \
3a1d76f6489a485dfa7e3784c1fa76b4a53c28afvboxsync uint8_t shift_control; \
3a1d76f6489a485dfa7e3784c1fa76b4a53c28afvboxsync uint8_t double_scan; \
3a1d76f6489a485dfa7e3784c1fa76b4a53c28afvboxsync uint8_t padding1[2]; \
3a1d76f6489a485dfa7e3784c1fa76b4a53c28afvboxsync uint32_t line_offset; \
3a1d76f6489a485dfa7e3784c1fa76b4a53c28afvboxsync uint32_t line_compare; \
3a1d76f6489a485dfa7e3784c1fa76b4a53c28afvboxsync uint32_t start_addr; \
6efcec753717bae68ada4b060466934b111739fdvboxsync uint32_t plane_updated; \
6efcec753717bae68ada4b060466934b111739fdvboxsync uint8_t last_cw, last_ch, padding2[2]; \
6efcec753717bae68ada4b060466934b111739fdvboxsync uint32_t last_width, last_height; /* in chars or pixels */ \
6efcec753717bae68ada4b060466934b111739fdvboxsync uint32_t last_scr_width, last_scr_height; /* in pixels */ \
6efcec753717bae68ada4b060466934b111739fdvboxsync uint32_t last_bpp; \
6efcec753717bae68ada4b060466934b111739fdvboxsync uint8_t cursor_start, cursor_end, padding3[2]; \
6efcec753717bae68ada4b060466934b111739fdvboxsync uint32_t cursor_offset; \
6efcec753717bae68ada4b060466934b111739fdvboxsync uint32_t padding4; \
6efcec753717bae68ada4b060466934b111739fdvboxsync R3PTRTYPE(FNRGBTOPIXEL *) rgb_to_pixel; \
6efcec753717bae68ada4b060466934b111739fdvboxsync /* hardware mouse cursor support */ \
6efcec753717bae68ada4b060466934b111739fdvboxsync uint32_t invalidated_y_table[VGA_MAX_HEIGHT / 32]; \
6efcec753717bae68ada4b060466934b111739fdvboxsync R3PTRTYPE(FNCURSORINVALIDATE *) cursor_invalidate; \
6efcec753717bae68ada4b060466934b111739fdvboxsync R3PTRTYPE(FNCURSORDRAWLINE *) cursor_draw_line; \
6efcec753717bae68ada4b060466934b111739fdvboxsync /* tell for each page if it has been updated since the last time */ \
6efcec753717bae68ada4b060466934b111739fdvboxsync uint32_t last_palette[256]; \
6efcec753717bae68ada4b060466934b111739fdvboxsync uint32_t last_ch_attr[CH_ATTR_SIZE]; /* XXX: make it dynamic */
6efcec753717bae68ada4b060466934b111739fdvboxsync
6efcec753717bae68ada4b060466934b111739fdvboxsync#endif /* VBOX */
6efcec753717bae68ada4b060466934b111739fdvboxsync
6efcec753717bae68ada4b060466934b111739fdvboxsync#ifdef VBOX_WITH_VDMA
6efcec753717bae68ada4b060466934b111739fdvboxsynctypedef struct VBOXVDMAHOST *PVBOXVDMAHOST;
3a1d76f6489a485dfa7e3784c1fa76b4a53c28afvboxsync#endif
3a1d76f6489a485dfa7e3784c1fa76b4a53c28afvboxsync
3a1d76f6489a485dfa7e3784c1fa76b4a53c28afvboxsynctypedef struct VGAState {
3a1d76f6489a485dfa7e3784c1fa76b4a53c28afvboxsync VGA_STATE_COMMON
3a1d76f6489a485dfa7e3784c1fa76b4a53c28afvboxsync#ifdef VBOX
3a1d76f6489a485dfa7e3784c1fa76b4a53c28afvboxsync /** end-of-common-state-marker */
3a1d76f6489a485dfa7e3784c1fa76b4a53c28afvboxsync uint32_t u32Marker;
1a62088b18e24a01c1dc85e13d60468e78bd649dvboxsync#if HC_ARCH_BITS == 64
3a1d76f6489a485dfa7e3784c1fa76b4a53c28afvboxsync uint32_t Padding0;
3a1d76f6489a485dfa7e3784c1fa76b4a53c28afvboxsync#endif
3a1d76f6489a485dfa7e3784c1fa76b4a53c28afvboxsync /** The physical address the VRAM was assigned. */
3a1d76f6489a485dfa7e3784c1fa76b4a53c28afvboxsync RTGCPHYS GCPhysVRAM;
3a1d76f6489a485dfa7e3784c1fa76b4a53c28afvboxsync /** The R0 vram pointer... */
3a1d76f6489a485dfa7e3784c1fa76b4a53c28afvboxsync R0PTRTYPE(uint8_t *) vram_ptrR0;
3a1d76f6489a485dfa7e3784c1fa76b4a53c28afvboxsync /** Pointer to the GC vram mapping. */
3a1d76f6489a485dfa7e3784c1fa76b4a53c28afvboxsync RCPTRTYPE(uint8_t *) vram_ptrRC;
3a1d76f6489a485dfa7e3784c1fa76b4a53c28afvboxsync /** LFB was updated flag. */
3a1d76f6489a485dfa7e3784c1fa76b4a53c28afvboxsync bool fLFBUpdated;
3a1d76f6489a485dfa7e3784c1fa76b4a53c28afvboxsync /** Indicates if the GC extensions are enabled or not. */
3a1d76f6489a485dfa7e3784c1fa76b4a53c28afvboxsync bool fGCEnabled;
3a1d76f6489a485dfa7e3784c1fa76b4a53c28afvboxsync /** Indicates if the R0 extensions are enabled or not. */
3a1d76f6489a485dfa7e3784c1fa76b4a53c28afvboxsync bool fR0Enabled;
3a1d76f6489a485dfa7e3784c1fa76b4a53c28afvboxsync /** Flag indicating that there are dirty bits. This is used to optimize the handler resetting. */
3a1d76f6489a485dfa7e3784c1fa76b4a53c28afvboxsync bool fHasDirtyBits;
3a1d76f6489a485dfa7e3784c1fa76b4a53c28afvboxsync /** Flag indicating that the VGA memory in the 0xa0000-0xbffff region has been remapped to allow direct access. */
3a1d76f6489a485dfa7e3784c1fa76b4a53c28afvboxsync bool fRemappedVGA;
3a1d76f6489a485dfa7e3784c1fa76b4a53c28afvboxsync /** Whether to render the guest VRAM to the framebuffer memory. False only for some LFB modes. */
3a1d76f6489a485dfa7e3784c1fa76b4a53c28afvboxsync bool fRenderVRAM;
3a1d76f6489a485dfa7e3784c1fa76b4a53c28afvboxsync bool Padding1[2];
3a1d76f6489a485dfa7e3784c1fa76b4a53c28afvboxsync
3a1d76f6489a485dfa7e3784c1fa76b4a53c28afvboxsync#if HC_ARCH_BITS == 32
3a1d76f6489a485dfa7e3784c1fa76b4a53c28afvboxsync uint32_t Padding2;
3a1d76f6489a485dfa7e3784c1fa76b4a53c28afvboxsync#endif
3a1d76f6489a485dfa7e3784c1fa76b4a53c28afvboxsync
3a1d76f6489a485dfa7e3784c1fa76b4a53c28afvboxsync#ifdef VBOX_WITH_HGSMI
3a1d76f6489a485dfa7e3784c1fa76b4a53c28afvboxsync R3PTRTYPE(PHGSMIINSTANCE) pHGSMI;
3a1d76f6489a485dfa7e3784c1fa76b4a53c28afvboxsync#endif /* VBOX_WITH_HGSMI */
3a1d76f6489a485dfa7e3784c1fa76b4a53c28afvboxsync#ifdef VBOX_WITH_VDMA
3a1d76f6489a485dfa7e3784c1fa76b4a53c28afvboxsync R3PTRTYPE(PVBOXVDMAHOST) pVdma;
3a1d76f6489a485dfa7e3784c1fa76b4a53c28afvboxsync#endif
3a1d76f6489a485dfa7e3784c1fa76b4a53c28afvboxsync
3a1d76f6489a485dfa7e3784c1fa76b4a53c28afvboxsync#if HC_ARCH_BITS == 32
1a62088b18e24a01c1dc85e13d60468e78bd649dvboxsync# if defined(VBOX_WITH_HGSMI) != defined(VBOX_WITH_VDMA)
1a62088b18e24a01c1dc85e13d60468e78bd649dvboxsync uint32_t Padding3;
3a1d76f6489a485dfa7e3784c1fa76b4a53c28afvboxsync# endif
3a1d76f6489a485dfa7e3784c1fa76b4a53c28afvboxsync#endif
3a1d76f6489a485dfa7e3784c1fa76b4a53c28afvboxsync
3a1d76f6489a485dfa7e3784c1fa76b4a53c28afvboxsync
3a1d76f6489a485dfa7e3784c1fa76b4a53c28afvboxsync uint32_t cMonitors;
3a1d76f6489a485dfa7e3784c1fa76b4a53c28afvboxsync /** Current refresh timer interval. */
1a62088b18e24a01c1dc85e13d60468e78bd649dvboxsync uint32_t cMilliesRefreshInterval;
1a62088b18e24a01c1dc85e13d60468e78bd649dvboxsync /** Refresh timer handle - HC. */
3a1d76f6489a485dfa7e3784c1fa76b4a53c28afvboxsync PTMTIMERR3 RefreshTimer;
3a1d76f6489a485dfa7e3784c1fa76b4a53c28afvboxsync
3a1d76f6489a485dfa7e3784c1fa76b4a53c28afvboxsync /** Bitmap tracking dirty pages. */
3a1d76f6489a485dfa7e3784c1fa76b4a53c28afvboxsync uint32_t au32DirtyBitmap[VGA_VRAM_MAX / PAGE_SIZE / 32];
3a1d76f6489a485dfa7e3784c1fa76b4a53c28afvboxsync /** Pointer to vgaGCLFBAccessHandler(). */
3a1d76f6489a485dfa7e3784c1fa76b4a53c28afvboxsync RTRCPTR RCPtrLFBHandler;
3a1d76f6489a485dfa7e3784c1fa76b4a53c28afvboxsync /** Pointer to the device instance - RC Ptr. */
3a1d76f6489a485dfa7e3784c1fa76b4a53c28afvboxsync PPDMDEVINSRC pDevInsRC;
3a1d76f6489a485dfa7e3784c1fa76b4a53c28afvboxsync /** Pointer to the device instance - R3 Ptr. */
3a1d76f6489a485dfa7e3784c1fa76b4a53c28afvboxsync PPDMDEVINSR3 pDevInsR3;
3a1d76f6489a485dfa7e3784c1fa76b4a53c28afvboxsync /** Pointer to the device instance - R0 Ptr. */
1a62088b18e24a01c1dc85e13d60468e78bd649dvboxsync PPDMDEVINSR0 pDevInsR0;
1a62088b18e24a01c1dc85e13d60468e78bd649dvboxsync
3a1d76f6489a485dfa7e3784c1fa76b4a53c28afvboxsync /** The critical section. */
0bb0c0c0e3f9e5fdb3e745715dde1af951c04998vboxsync PDMCRITSECT lock;
3a1d76f6489a485dfa7e3784c1fa76b4a53c28afvboxsync
0bb0c0c0e3f9e5fdb3e745715dde1af951c04998vboxsync /** LUN\#0: The display port base interface. */
3a1d76f6489a485dfa7e3784c1fa76b4a53c28afvboxsync PDMIBASE IBase;
3a1d76f6489a485dfa7e3784c1fa76b4a53c28afvboxsync /** LUN\#0: The display port interface. */
3a1d76f6489a485dfa7e3784c1fa76b4a53c28afvboxsync PDMIDISPLAYPORT IPort;
3a1d76f6489a485dfa7e3784c1fa76b4a53c28afvboxsync#if defined(VBOX_WITH_HGSMI) && (defined(VBOX_WITH_VIDEOHWACCEL) || defined(VBOX_WITH_CRHGSMI))
3a1d76f6489a485dfa7e3784c1fa76b4a53c28afvboxsync /** LUN\#0: VBVA callbacks interface */
3a1d76f6489a485dfa7e3784c1fa76b4a53c28afvboxsync PDMIDISPLAYVBVACALLBACKS IVBVACallbacks;
3a1d76f6489a485dfa7e3784c1fa76b4a53c28afvboxsync#else
3a1d76f6489a485dfa7e3784c1fa76b4a53c28afvboxsync# if HC_ARCH_BITS == 32
3a1d76f6489a485dfa7e3784c1fa76b4a53c28afvboxsync uint32_t Padding4;
3a1d76f6489a485dfa7e3784c1fa76b4a53c28afvboxsync# endif
3a1d76f6489a485dfa7e3784c1fa76b4a53c28afvboxsync#endif
3a1d76f6489a485dfa7e3784c1fa76b4a53c28afvboxsync /** Pointer to base interface of the driver. */
3a1d76f6489a485dfa7e3784c1fa76b4a53c28afvboxsync R3PTRTYPE(PPDMIBASE) pDrvBase;
1a62088b18e24a01c1dc85e13d60468e78bd649dvboxsync /** Pointer to display connector interface of the driver. */
3a1d76f6489a485dfa7e3784c1fa76b4a53c28afvboxsync R3PTRTYPE(PPDMIDISPLAYCONNECTOR) pDrv;
3a1d76f6489a485dfa7e3784c1fa76b4a53c28afvboxsync
cf9045d402be1e8b7344a439eaefe2ca4c2b53d3vboxsync /** The PCI device. */
0bb0c0c0e3f9e5fdb3e745715dde1af951c04998vboxsync PCIDEVICE Dev;
cf9045d402be1e8b7344a439eaefe2ca4c2b53d3vboxsync
3a1d76f6489a485dfa7e3784c1fa76b4a53c28afvboxsync STAMPROFILE StatRZMemoryRead;
3a1d76f6489a485dfa7e3784c1fa76b4a53c28afvboxsync STAMPROFILE StatR3MemoryRead;
1a62088b18e24a01c1dc85e13d60468e78bd649dvboxsync STAMPROFILE StatRZMemoryWrite;
3a1d76f6489a485dfa7e3784c1fa76b4a53c28afvboxsync STAMPROFILE StatR3MemoryWrite;
0bb0c0c0e3f9e5fdb3e745715dde1af951c04998vboxsync STAMCOUNTER StatMapPage; /**< Counts IOMMMIOMapMMIO2Page calls. */
1a62088b18e24a01c1dc85e13d60468e78bd649dvboxsync STAMCOUNTER StatUpdateDisp; /**< Counts vgaPortUpdateDisplay calls. */
1a62088b18e24a01c1dc85e13d60468e78bd649dvboxsync
1a62088b18e24a01c1dc85e13d60468e78bd649dvboxsync /* Keep track of ring 0 latched accesses to the VGA MMIO memory. */
1a62088b18e24a01c1dc85e13d60468e78bd649dvboxsync uint64_t u64LastLatchedAccess;
1a62088b18e24a01c1dc85e13d60468e78bd649dvboxsync uint32_t cLatchAccesses;
1c434bf12564eb5a885b3f7e230b7638955004cevboxsync uint16_t uMaskLatchAccess;
1a62088b18e24a01c1dc85e13d60468e78bd649dvboxsync uint16_t iMask;
1a62088b18e24a01c1dc85e13d60468e78bd649dvboxsync
1a62088b18e24a01c1dc85e13d60468e78bd649dvboxsync#ifdef VBE_BYTEWISE_IO
1a62088b18e24a01c1dc85e13d60468e78bd649dvboxsync /** VBE read/write data/index flags */
0bb0c0c0e3f9e5fdb3e745715dde1af951c04998vboxsync uint8_t fReadVBEData;
1a62088b18e24a01c1dc85e13d60468e78bd649dvboxsync uint8_t fWriteVBEData;
e4bb2f8312bbd05cdb3c4c01406274f946e7b76cvboxsync uint8_t fReadVBEIndex;
e4bb2f8312bbd05cdb3c4c01406274f946e7b76cvboxsync uint8_t fWriteVBEIndex;
2b114c590cf5a19f8047cd7bde9c7e5ae00aa22bvboxsync /** VBE write data/index one byte buffer */
2b114c590cf5a19f8047cd7bde9c7e5ae00aa22bvboxsync uint8_t cbWriteVBEData;
e4bb2f8312bbd05cdb3c4c01406274f946e7b76cvboxsync uint8_t cbWriteVBEIndex;
e4bb2f8312bbd05cdb3c4c01406274f946e7b76cvboxsync# ifdef VBE_NEW_DYN_LIST
2b114c590cf5a19f8047cd7bde9c7e5ae00aa22bvboxsync /** VBE Extra Data write address one byte buffer */
0bb0c0c0e3f9e5fdb3e745715dde1af951c04998vboxsync uint8_t cbWriteVBEExtraAddress;
0bb0c0c0e3f9e5fdb3e745715dde1af951c04998vboxsync uint8_t Padding5;
1c434bf12564eb5a885b3f7e230b7638955004cevboxsync# else
0bb0c0c0e3f9e5fdb3e745715dde1af951c04998vboxsync uint8_t Padding5[2];
0bb0c0c0e3f9e5fdb3e745715dde1af951c04998vboxsync# endif
0bb0c0c0e3f9e5fdb3e745715dde1af951c04998vboxsync#endif
3a1d76f6489a485dfa7e3784c1fa76b4a53c28afvboxsync
0bb0c0c0e3f9e5fdb3e745715dde1af951c04998vboxsync /** Retrace emulation state */
0bb0c0c0e3f9e5fdb3e745715dde1af951c04998vboxsync bool fRealRetrace;
0bb0c0c0e3f9e5fdb3e745715dde1af951c04998vboxsync bool Padding6[HC_ARCH_BITS == 64 ? 7 : 3];
1a62088b18e24a01c1dc85e13d60468e78bd649dvboxsync vga_retrace_s retrace_state;
1a62088b18e24a01c1dc85e13d60468e78bd649dvboxsync
1a62088b18e24a01c1dc85e13d60468e78bd649dvboxsync#ifdef VBE_NEW_DYN_LIST
1a62088b18e24a01c1dc85e13d60468e78bd649dvboxsync /** The VBE BIOS extra data. */
0b4e62c819b44a33a2ff548c18f11ed9709e1c48vboxsync R3PTRTYPE(uint8_t *) pu8VBEExtraData;
1a62088b18e24a01c1dc85e13d60468e78bd649dvboxsync /** The size of the VBE BIOS extra data. */
1a62088b18e24a01c1dc85e13d60468e78bd649dvboxsync uint16_t cbVBEExtraData;
1a62088b18e24a01c1dc85e13d60468e78bd649dvboxsync /** The VBE BIOS current memory address. */
1a62088b18e24a01c1dc85e13d60468e78bd649dvboxsync uint16_t u16VBEExtraAddress;
1a62088b18e24a01c1dc85e13d60468e78bd649dvboxsync uint16_t Padding7[2];
1a62088b18e24a01c1dc85e13d60468e78bd649dvboxsync#endif
1a62088b18e24a01c1dc85e13d60468e78bd649dvboxsync /** Current logo data offset. */
1a62088b18e24a01c1dc85e13d60468e78bd649dvboxsync uint32_t offLogoData;
1a62088b18e24a01c1dc85e13d60468e78bd649dvboxsync /** The size of the BIOS logo data. */
1a62088b18e24a01c1dc85e13d60468e78bd649dvboxsync uint32_t cbLogo;
1a62088b18e24a01c1dc85e13d60468e78bd649dvboxsync /** The BIOS logo data. */
1a62088b18e24a01c1dc85e13d60468e78bd649dvboxsync R3PTRTYPE(uint8_t *) pu8Logo;
1a62088b18e24a01c1dc85e13d60468e78bd649dvboxsync /** The name of the logo file. */
1a62088b18e24a01c1dc85e13d60468e78bd649dvboxsync R3PTRTYPE(char *) pszLogoFile;
1a62088b18e24a01c1dc85e13d60468e78bd649dvboxsync /** Bitmap image data. */
1a62088b18e24a01c1dc85e13d60468e78bd649dvboxsync R3PTRTYPE(uint8_t *) pu8LogoBitmap;
1a62088b18e24a01c1dc85e13d60468e78bd649dvboxsync /** Current logo command. */
1a62088b18e24a01c1dc85e13d60468e78bd649dvboxsync uint16_t LogoCommand;
1a62088b18e24a01c1dc85e13d60468e78bd649dvboxsync /** Bitmap width. */
1a62088b18e24a01c1dc85e13d60468e78bd649dvboxsync uint16_t cxLogo;
1a62088b18e24a01c1dc85e13d60468e78bd649dvboxsync /** Bitmap height. */
1a62088b18e24a01c1dc85e13d60468e78bd649dvboxsync uint16_t cyLogo;
1a62088b18e24a01c1dc85e13d60468e78bd649dvboxsync /** Bitmap planes. */
1a62088b18e24a01c1dc85e13d60468e78bd649dvboxsync uint16_t cLogoPlanes;
1a62088b18e24a01c1dc85e13d60468e78bd649dvboxsync /** Bitmap depth. */
1a62088b18e24a01c1dc85e13d60468e78bd649dvboxsync uint16_t cLogoBits;
1a62088b18e24a01c1dc85e13d60468e78bd649dvboxsync /** Bitmap compression. */
1a62088b18e24a01c1dc85e13d60468e78bd649dvboxsync uint16_t LogoCompression;
1a62088b18e24a01c1dc85e13d60468e78bd649dvboxsync /** Bitmap colors used. */
1a62088b18e24a01c1dc85e13d60468e78bd649dvboxsync uint16_t cLogoUsedColors;
1a62088b18e24a01c1dc85e13d60468e78bd649dvboxsync /** Palette size. */
1a62088b18e24a01c1dc85e13d60468e78bd649dvboxsync uint16_t cLogoPalEntries;
1a62088b18e24a01c1dc85e13d60468e78bd649dvboxsync /** Clear screen flag. */
1a62088b18e24a01c1dc85e13d60468e78bd649dvboxsync uint8_t fLogoClearScreen;
1a62088b18e24a01c1dc85e13d60468e78bd649dvboxsync uint8_t Padding8[7];
1a62088b18e24a01c1dc85e13d60468e78bd649dvboxsync /** Palette data. */
1a62088b18e24a01c1dc85e13d60468e78bd649dvboxsync uint32_t au32LogoPalette[256];
1a62088b18e24a01c1dc85e13d60468e78bd649dvboxsync /** The VGA BIOS ROM data. */
1a62088b18e24a01c1dc85e13d60468e78bd649dvboxsync R3PTRTYPE(uint8_t *) pu8VgaBios;
1a62088b18e24a01c1dc85e13d60468e78bd649dvboxsync /** The size of the VGA BIOS ROM. */
1a62088b18e24a01c1dc85e13d60468e78bd649dvboxsync uint64_t cbVgaBios;
1a62088b18e24a01c1dc85e13d60468e78bd649dvboxsync /** The name of the VGA BIOS ROM file. */
1a62088b18e24a01c1dc85e13d60468e78bd649dvboxsync R3PTRTYPE(char *) pszVgaBiosFile;
1a62088b18e24a01c1dc85e13d60468e78bd649dvboxsync#endif /* VBOX */
1a62088b18e24a01c1dc85e13d60468e78bd649dvboxsync#ifdef VBOX_WITH_HGSMI
1a62088b18e24a01c1dc85e13d60468e78bd649dvboxsync /** Base port in the assigned PCI I/O space. */
1a62088b18e24a01c1dc85e13d60468e78bd649dvboxsync RTIOPORT IOPortBase;
1a62088b18e24a01c1dc85e13d60468e78bd649dvboxsync#ifdef VBOX_WITH_WDDM
1a62088b18e24a01c1dc85e13d60468e78bd649dvboxsync uint8_t Padding9[2];
1a62088b18e24a01c1dc85e13d60468e78bd649dvboxsync /* specifies guest driver caps, i.e. whether it can handle IRQs from the adapter,
1a62088b18e24a01c1dc85e13d60468e78bd649dvboxsync * the way it can handle async HGSMI command completion, etc. */
1a62088b18e24a01c1dc85e13d60468e78bd649dvboxsync uint32_t fGuestCaps;
1a62088b18e24a01c1dc85e13d60468e78bd649dvboxsync#else
1a62088b18e24a01c1dc85e13d60468e78bd649dvboxsync uint8_t Padding10[6];
1a62088b18e24a01c1dc85e13d60468e78bd649dvboxsync#endif
1a62088b18e24a01c1dc85e13d60468e78bd649dvboxsync#endif /* VBOX_WITH_HGSMI */
1a62088b18e24a01c1dc85e13d60468e78bd649dvboxsync} VGAState;
1a62088b18e24a01c1dc85e13d60468e78bd649dvboxsync#ifdef VBOX
1a62088b18e24a01c1dc85e13d60468e78bd649dvboxsync/** VGA state. */
1a62088b18e24a01c1dc85e13d60468e78bd649dvboxsynctypedef VGAState VGASTATE;
1a62088b18e24a01c1dc85e13d60468e78bd649dvboxsync/** Pointer to the VGA state. */
1a62088b18e24a01c1dc85e13d60468e78bd649dvboxsynctypedef VGASTATE *PVGASTATE;
1a62088b18e24a01c1dc85e13d60468e78bd649dvboxsync#endif
1a62088b18e24a01c1dc85e13d60468e78bd649dvboxsync
1a62088b18e24a01c1dc85e13d60468e78bd649dvboxsync#ifdef VBE_NEW_DYN_LIST
1a62088b18e24a01c1dc85e13d60468e78bd649dvboxsync/**
1a62088b18e24a01c1dc85e13d60468e78bd649dvboxsync * VBE Bios Extra Data structure.
1a62088b18e24a01c1dc85e13d60468e78bd649dvboxsync * @remark duplicated in vbe.h.
1a62088b18e24a01c1dc85e13d60468e78bd649dvboxsync */
1a62088b18e24a01c1dc85e13d60468e78bd649dvboxsynctypedef struct VBEHeader
1a62088b18e24a01c1dc85e13d60468e78bd649dvboxsync{
1a62088b18e24a01c1dc85e13d60468e78bd649dvboxsync /** Signature (VBEHEADER_MAGIC). */
1a62088b18e24a01c1dc85e13d60468e78bd649dvboxsync uint16_t u16Signature;
1a62088b18e24a01c1dc85e13d60468e78bd649dvboxsync /** Data size. */
1a62088b18e24a01c1dc85e13d60468e78bd649dvboxsync uint16_t cbData;
1a62088b18e24a01c1dc85e13d60468e78bd649dvboxsync} VBEHeader;
1a62088b18e24a01c1dc85e13d60468e78bd649dvboxsync
1a62088b18e24a01c1dc85e13d60468e78bd649dvboxsync/** VBE Extra Data. */
1a62088b18e24a01c1dc85e13d60468e78bd649dvboxsynctypedef VBEHeader VBEHEADER;
1a62088b18e24a01c1dc85e13d60468e78bd649dvboxsync/** Pointer to the VBE Extra Data. */
1a62088b18e24a01c1dc85e13d60468e78bd649dvboxsynctypedef VBEHEADER *PVBEHEADER;
1a62088b18e24a01c1dc85e13d60468e78bd649dvboxsync
1a62088b18e24a01c1dc85e13d60468e78bd649dvboxsync/** The value of the VBEHEADER::u16Signature field.
1a62088b18e24a01c1dc85e13d60468e78bd649dvboxsync * @remark duplicated in vbe.h. */
1a62088b18e24a01c1dc85e13d60468e78bd649dvboxsync#define VBEHEADER_MAGIC 0x77CC
1a62088b18e24a01c1dc85e13d60468e78bd649dvboxsync
1a62088b18e24a01c1dc85e13d60468e78bd649dvboxsync/** The extra port which is used to read the mode list.
1a62088b18e24a01c1dc85e13d60468e78bd649dvboxsync * @remark duplicated in vbe.h. */
1a62088b18e24a01c1dc85e13d60468e78bd649dvboxsync#define VBE_EXTRA_PORT 0x3b6
1a62088b18e24a01c1dc85e13d60468e78bd649dvboxsync
1a62088b18e24a01c1dc85e13d60468e78bd649dvboxsync/** The extra port which is used for debug printf.
3a1d76f6489a485dfa7e3784c1fa76b4a53c28afvboxsync * @remark duplicated in vbe.h. */
3a1d76f6489a485dfa7e3784c1fa76b4a53c28afvboxsync#define VBE_PRINTF_PORT 0x3b7
3a1d76f6489a485dfa7e3784c1fa76b4a53c28afvboxsync
3a1d76f6489a485dfa7e3784c1fa76b4a53c28afvboxsync#endif /* VBE_NEW_DYN_LIST */
3a1d76f6489a485dfa7e3784c1fa76b4a53c28afvboxsync
3a1d76f6489a485dfa7e3784c1fa76b4a53c28afvboxsync#if !defined(VBOX) || defined(IN_RING3)
3a1d76f6489a485dfa7e3784c1fa76b4a53c28afvboxsyncstatic inline int c6_to_8(int v)
3a1d76f6489a485dfa7e3784c1fa76b4a53c28afvboxsync{
3a1d76f6489a485dfa7e3784c1fa76b4a53c28afvboxsync int b;
1a62088b18e24a01c1dc85e13d60468e78bd649dvboxsync v &= 0x3f;
1a62088b18e24a01c1dc85e13d60468e78bd649dvboxsync b = v & 1;
1a62088b18e24a01c1dc85e13d60468e78bd649dvboxsync return (v << 2) | (b << 1) | b;
1a62088b18e24a01c1dc85e13d60468e78bd649dvboxsync}
1a62088b18e24a01c1dc85e13d60468e78bd649dvboxsync#endif /* !VBOX || IN_RING3 */
3a1d76f6489a485dfa7e3784c1fa76b4a53c28afvboxsync
1a62088b18e24a01c1dc85e13d60468e78bd649dvboxsync
1a62088b18e24a01c1dc85e13d60468e78bd649dvboxsync#ifdef VBOX_WITH_HGSMI
1a62088b18e24a01c1dc85e13d60468e78bd649dvboxsyncint VBVAInit (PVGASTATE pVGAState);
1a62088b18e24a01c1dc85e13d60468e78bd649dvboxsyncvoid VBVADestroy (PVGASTATE pVGAState);
1a62088b18e24a01c1dc85e13d60468e78bd649dvboxsyncint VBVAUpdateDisplay (PVGASTATE pVGAState);
1a62088b18e24a01c1dc85e13d60468e78bd649dvboxsyncvoid VBVAReset (PVGASTATE pVGAState);
1a62088b18e24a01c1dc85e13d60468e78bd649dvboxsync
1a62088b18e24a01c1dc85e13d60468e78bd649dvboxsyncbool VBVAIsEnabled(PVGASTATE pVGAState);
1a62088b18e24a01c1dc85e13d60468e78bd649dvboxsync
1a62088b18e24a01c1dc85e13d60468e78bd649dvboxsync/* @return host-guest flags that were set on reset
1a62088b18e24a01c1dc85e13d60468e78bd649dvboxsync * this allows the caller to make further cleaning when needed,
1a62088b18e24a01c1dc85e13d60468e78bd649dvboxsync * e.g. reset the IRQ */
1a62088b18e24a01c1dc85e13d60468e78bd649dvboxsyncuint32_t HGSMIReset (PHGSMIINSTANCE pIns);
1a62088b18e24a01c1dc85e13d60468e78bd649dvboxsync
1a62088b18e24a01c1dc85e13d60468e78bd649dvboxsync# ifdef VBOX_WITH_VIDEOHWACCEL
1a62088b18e24a01c1dc85e13d60468e78bd649dvboxsyncint vbvaVHWACommandCompleteAsynch(PPDMIDISPLAYVBVACALLBACKS pInterface, PVBOXVHWACMD pCmd);
1a62088b18e24a01c1dc85e13d60468e78bd649dvboxsyncint vbvaVHWAConstruct (PVGASTATE pVGAState);
1a62088b18e24a01c1dc85e13d60468e78bd649dvboxsyncint vbvaVHWAReset (PVGASTATE pVGAState);
1a62088b18e24a01c1dc85e13d60468e78bd649dvboxsync
1a62088b18e24a01c1dc85e13d60468e78bd649dvboxsyncint vboxVBVASaveStatePrep (PPDMDEVINS pDevIns, PSSMHANDLE pSSM);
1a62088b18e24a01c1dc85e13d60468e78bd649dvboxsyncint vboxVBVASaveStateDone (PPDMDEVINS pDevIns, PSSMHANDLE pSSM);
1a62088b18e24a01c1dc85e13d60468e78bd649dvboxsync# endif
1a62088b18e24a01c1dc85e13d60468e78bd649dvboxsync
1a62088b18e24a01c1dc85e13d60468e78bd649dvboxsync#ifdef VBOX_WITH_HGSMI
1a62088b18e24a01c1dc85e13d60468e78bd649dvboxsync#define PPDMIDISPLAYVBVACALLBACKS_2_PVGASTATE(_pcb) ( (PVGASTATE)((uint8_t *)(_pcb) - RT_OFFSETOF(VGASTATE, IVBVACallbacks)) )
1a62088b18e24a01c1dc85e13d60468e78bd649dvboxsync#endif
1a62088b18e24a01c1dc85e13d60468e78bd649dvboxsync
1a62088b18e24a01c1dc85e13d60468e78bd649dvboxsync# ifdef VBOX_WITH_CRHGSMI
1a62088b18e24a01c1dc85e13d60468e78bd649dvboxsyncint vboxVDMACrHgsmiCommandCompleteAsync(PPDMIDISPLAYVBVACALLBACKS pInterface, PVBOXVDMACMD_CHROMIUM_CMD pCmd, int rc);
3a1d76f6489a485dfa7e3784c1fa76b4a53c28afvboxsyncint vboxVDMACrHgsmiControlCompleteAsync(PPDMIDISPLAYVBVACALLBACKS pInterface, PVBOXVDMACMD_CHROMIUM_CTL pCmd, int rc);
1a62088b18e24a01c1dc85e13d60468e78bd649dvboxsync# endif
1a62088b18e24a01c1dc85e13d60468e78bd649dvboxsync
1a62088b18e24a01c1dc85e13d60468e78bd649dvboxsyncint vboxVBVASaveStateExec (PPDMDEVINS pDevIns, PSSMHANDLE pSSM);
1a62088b18e24a01c1dc85e13d60468e78bd649dvboxsyncint vboxVBVALoadStateExec (PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t u32Version);
1a62088b18e24a01c1dc85e13d60468e78bd649dvboxsyncint vboxVBVALoadStateDone (PPDMDEVINS pDevIns, PSSMHANDLE pSSM);
1a62088b18e24a01c1dc85e13d60468e78bd649dvboxsync
1a62088b18e24a01c1dc85e13d60468e78bd649dvboxsync# ifdef VBOX_WITH_VDMA
1a62088b18e24a01c1dc85e13d60468e78bd649dvboxsynctypedef struct VBOXVDMAHOST *PVBOXVDMAHOST;
1a62088b18e24a01c1dc85e13d60468e78bd649dvboxsyncint vboxVDMAConstruct(PVGASTATE pVGAState, uint32_t cPipeElements);
1a62088b18e24a01c1dc85e13d60468e78bd649dvboxsyncint vboxVDMADestruct(PVBOXVDMAHOST pVdma);
1a62088b18e24a01c1dc85e13d60468e78bd649dvboxsyncvoid vboxVDMAControl(PVBOXVDMAHOST pVdma, PVBOXVDMA_CTL pCmd, uint32_t cbCmd);
1a62088b18e24a01c1dc85e13d60468e78bd649dvboxsyncvoid vboxVDMACommand(PVBOXVDMAHOST pVdma, PVBOXVDMACBUF_DR pCmd, uint32_t cbCmd);
1a62088b18e24a01c1dc85e13d60468e78bd649dvboxsyncint vboxVDMASaveStateExecPrep(struct VBOXVDMAHOST *pVdma, PSSMHANDLE pSSM);
1a62088b18e24a01c1dc85e13d60468e78bd649dvboxsyncint vboxVDMASaveStateExecDone(struct VBOXVDMAHOST *pVdma, PSSMHANDLE pSSM);
1a62088b18e24a01c1dc85e13d60468e78bd649dvboxsync# endif /* VBOX_WITH_VDMA */
1a62088b18e24a01c1dc85e13d60468e78bd649dvboxsync
1a62088b18e24a01c1dc85e13d60468e78bd649dvboxsync#endif /* VBOX_WITH_HGSMI */
1a62088b18e24a01c1dc85e13d60468e78bd649dvboxsync
1a62088b18e24a01c1dc85e13d60468e78bd649dvboxsync#ifndef VBOX
3a1d76f6489a485dfa7e3784c1fa76b4a53c28afvboxsyncvoid vga_common_init(VGAState *s, DisplayState *ds, uint8_t *vga_ram_base,
1a62088b18e24a01c1dc85e13d60468e78bd649dvboxsync unsigned long vga_ram_offset, int vga_ram_size);
3a1d76f6489a485dfa7e3784c1fa76b4a53c28afvboxsyncuint32_t vga_mem_readb(void *opaque, target_phys_addr_t addr);
3a1d76f6489a485dfa7e3784c1fa76b4a53c28afvboxsyncvoid vga_mem_writeb(void *opaque, target_phys_addr_t addr, uint32_t val);
3a1d76f6489a485dfa7e3784c1fa76b4a53c28afvboxsyncvoid vga_invalidate_scanlines(VGAState *s, int y1, int y2);
3a1d76f6489a485dfa7e3784c1fa76b4a53c28afvboxsync
1a62088b18e24a01c1dc85e13d60468e78bd649dvboxsyncvoid vga_draw_cursor_line_8(uint8_t *d1, const uint8_t *src1,
3a1d76f6489a485dfa7e3784c1fa76b4a53c28afvboxsync int poffset, int w,
3a1d76f6489a485dfa7e3784c1fa76b4a53c28afvboxsync unsigned int color0, unsigned int color1,
3a1d76f6489a485dfa7e3784c1fa76b4a53c28afvboxsync unsigned int color_xor);
1a62088b18e24a01c1dc85e13d60468e78bd649dvboxsyncvoid vga_draw_cursor_line_16(uint8_t *d1, const uint8_t *src1,
3a1d76f6489a485dfa7e3784c1fa76b4a53c28afvboxsync int poffset, int w,
3a1d76f6489a485dfa7e3784c1fa76b4a53c28afvboxsync unsigned int color0, unsigned int color1,
1a62088b18e24a01c1dc85e13d60468e78bd649dvboxsync unsigned int color_xor);
1a62088b18e24a01c1dc85e13d60468e78bd649dvboxsyncvoid vga_draw_cursor_line_32(uint8_t *d1, const uint8_t *src1,
1a62088b18e24a01c1dc85e13d60468e78bd649dvboxsync int poffset, int w,
1a62088b18e24a01c1dc85e13d60468e78bd649dvboxsync unsigned int color0, unsigned int color1,
1a62088b18e24a01c1dc85e13d60468e78bd649dvboxsync unsigned int color_xor);
1a62088b18e24a01c1dc85e13d60468e78bd649dvboxsync
1a62088b18e24a01c1dc85e13d60468e78bd649dvboxsyncextern const uint8_t sr_mask[8];
1a62088b18e24a01c1dc85e13d60468e78bd649dvboxsyncextern const uint8_t gr_mask[16];
3a1d76f6489a485dfa7e3784c1fa76b4a53c28afvboxsync#endif /* !VBOX */
1a62088b18e24a01c1dc85e13d60468e78bd649dvboxsync
1a62088b18e24a01c1dc85e13d60468e78bd649dvboxsync