DevVGA-SVGA.cpp revision c598affb4a1578b0e7be124835a70c4f08c5d2bd
84f746c9015f34e9ab096b87e063d0d6ab7fc7aevboxsync * VMWare SVGA device.
84f746c9015f34e9ab096b87e063d0d6ab7fc7aevboxsync * Logging levels guidelines for this and related files:
84f746c9015f34e9ab096b87e063d0d6ab7fc7aevboxsync * - Log() for normal bits.
c58f1213e628a545081c70e26c6b67a841cff880vboxsync * - LogFlow() for more info.
84f746c9015f34e9ab096b87e063d0d6ab7fc7aevboxsync * - Log2 for hex dump of cursor data.
84f746c9015f34e9ab096b87e063d0d6ab7fc7aevboxsync * - Log3 for hex dump of shader code.
84f746c9015f34e9ab096b87e063d0d6ab7fc7aevboxsync * - Log4 for hex dumps of 3D data.
84f746c9015f34e9ab096b87e063d0d6ab7fc7aevboxsync * Copyright (C) 2013-2014 Oracle Corporation
84f746c9015f34e9ab096b87e063d0d6ab7fc7aevboxsync * This file is part of VirtualBox Open Source Edition (OSE), as
84f746c9015f34e9ab096b87e063d0d6ab7fc7aevboxsync * available from http://www.virtualbox.org. This file is free software;
84f746c9015f34e9ab096b87e063d0d6ab7fc7aevboxsync * you can redistribute it and/or modify it under the terms of the GNU
84f746c9015f34e9ab096b87e063d0d6ab7fc7aevboxsync * General Public License (GPL) as published by the Free Software
84f746c9015f34e9ab096b87e063d0d6ab7fc7aevboxsync * Foundation, in version 2 as it comes in the "COPYING" file of the
84f746c9015f34e9ab096b87e063d0d6ab7fc7aevboxsync * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
84f746c9015f34e9ab096b87e063d0d6ab7fc7aevboxsync * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
84f746c9015f34e9ab096b87e063d0d6ab7fc7aevboxsync/*******************************************************************************
84f746c9015f34e9ab096b87e063d0d6ab7fc7aevboxsync* Header Files *
84f746c9015f34e9ab096b87e063d0d6ab7fc7aevboxsync*******************************************************************************/
e2a73964f463b9e91f6f096f9e15974a3edcc416vboxsync/* should go BEFORE any other DevVGA include to make all DevVGA.h config defines be visible */
e2a73964f463b9e91f6f096f9e15974a3edcc416vboxsync/* Enable to log FIFO register accesses. */
e2a73964f463b9e91f6f096f9e15974a3edcc416vboxsync//# define DEBUG_FIFO_ACCESS
e2a73964f463b9e91f6f096f9e15974a3edcc416vboxsync/* Enable to log GMR page accesses. */
e2a73964f463b9e91f6f096f9e15974a3edcc416vboxsync//# define DEBUG_GMR_ACCESS
e2a73964f463b9e91f6f096f9e15974a3edcc416vboxsync/*******************************************************************************
84f746c9015f34e9ab096b87e063d0d6ab7fc7aevboxsync* Structures and Typedefs *
84f746c9015f34e9ab096b87e063d0d6ab7fc7aevboxsync*******************************************************************************/
84f746c9015f34e9ab096b87e063d0d6ab7fc7aevboxsync/* 64-bit GMR descriptor */
84f746c9015f34e9ab096b87e063d0d6ab7fc7aevboxsynctypedef struct
9b456547aefb8a2e8f5600eba9ec377dbc9b4475vboxsync/* GMR slot */
84f746c9015f34e9ab096b87e063d0d6ab7fc7aevboxsynctypedef struct
39c2eccedfdb7455c52225543c355e33a65f0c81vboxsync/* Internal SVGA state. */
39c2eccedfdb7455c52225543c355e33a65f0c81vboxsynctypedef struct
84f746c9015f34e9ab096b87e063d0d6ab7fc7aevboxsync * SSM descriptor table for the VMSVGAGMRDESCRIPTOR structure.
d1c36fd86d36726777e3d6f9d040573e0aaf30devboxsyncstatic SSMFIELD const g_aVMSVGAGMRDESCRIPTORFields[] =
d1c36fd86d36726777e3d6f9d040573e0aaf30devboxsync SSMFIELD_ENTRY_GCPHYS( VMSVGAGMRDESCRIPTOR, GCPhys),
d1c36fd86d36726777e3d6f9d040573e0aaf30devboxsync * SSM descriptor table for the GMR structure.
d1c36fd86d36726777e3d6f9d040573e0aaf30devboxsync * SSM descriptor table for the VMSVGASTATE structure.
d1c36fd86d36726777e3d6f9d040573e0aaf30devboxsync SSMFIELD_ENTRY_IGN_HCPTR( VMSVGASTATE, Cursor.pData),
d1c36fd86d36726777e3d6f9d040573e0aaf30devboxsync SSMFIELD_ENTRY_IGNORE( VMSVGASTATE, StatR3CmdPresent),
84f746c9015f34e9ab096b87e063d0d6ab7fc7aevboxsync SSMFIELD_ENTRY_IGNORE( VMSVGASTATE, StatR3CmdDrawPrimitive),
84f746c9015f34e9ab096b87e063d0d6ab7fc7aevboxsync SSMFIELD_ENTRY_IGNORE( VMSVGASTATE, StatR3CmdSurfaceDMA),
d1c36fd86d36726777e3d6f9d040573e0aaf30devboxsync * SSM descriptor table for the VGAState.svga structure.
84f746c9015f34e9ab096b87e063d0d6ab7fc7aevboxsync SSMFIELD_ENTRY_IGNORE( VMSVGAState, u64HostWindowId),
84f746c9015f34e9ab096b87e063d0d6ab7fc7aevboxsync SSMFIELD_ENTRY_IGN_HCPTR( VMSVGAState, pSVGAState),
d1c36fd86d36726777e3d6f9d040573e0aaf30devboxsync SSMFIELD_ENTRY_IGN_HCPTR( VMSVGAState, pFrameBufferBackup),
d1c36fd86d36726777e3d6f9d040573e0aaf30devboxsync SSMFIELD_ENTRY_IGN_HCPTR( VMSVGAState, pFIFOExtCmdParam),
d1c36fd86d36726777e3d6f9d040573e0aaf30devboxsync SSMFIELD_ENTRY_IGN_GCPHYS( VMSVGAState, GCPhysFIFO),
e2a73964f463b9e91f6f096f9e15974a3edcc416vboxsync SSMFIELD_ENTRY_IGNORE( VMSVGAState, pSupDrvSession),
e2a73964f463b9e91f6f096f9e15974a3edcc416vboxsync SSMFIELD_ENTRY_IGNORE( VMSVGAState, FIFORequestSem),
e2a73964f463b9e91f6f096f9e15974a3edcc416vboxsync SSMFIELD_ENTRY_IGNORE( VMSVGAState, FIFOExtCmdSem),
e2a73964f463b9e91f6f096f9e15974a3edcc416vboxsync SSMFIELD_ENTRY_IGN_HCPTR( VMSVGAState, pFIFOIOThread),
0612e2adbcc146b9eb7748983c720e35e38d0dc9vboxsync SSMFIELD_ENTRY_IGNORE( VMSVGAState, u8FIFOExtCommand),
0612e2adbcc146b9eb7748983c720e35e38d0dc9vboxsyncstatic void vmsvgaSetTraces(PVGASTATE pThis, bool fTraces);
0612e2adbcc146b9eb7748983c720e35e38d0dc9vboxsync#endif /* IN_RING3 */
e2a73964f463b9e91f6f096f9e15974a3edcc416vboxsync * Index register string name lookup
e2a73964f463b9e91f6f096f9e15974a3edcc416vboxsync * @returns Index register string or "UNKNOWN"
e2a73964f463b9e91f6f096f9e15974a3edcc416vboxsync * @param pThis VMSVGA State
e2a73964f463b9e91f6f096f9e15974a3edcc416vboxsyncstatic const char *vmsvgaIndexToString(PVGASTATE pThis)
e2a73964f463b9e91f6f096f9e15974a3edcc416vboxsync return "SVGA_REG_ID";
0612e2adbcc146b9eb7748983c720e35e38d0dc9vboxsync return "SVGA_REG_ENABLE";
0612e2adbcc146b9eb7748983c720e35e38d0dc9vboxsync return "SVGA_REG_WIDTH";
0612e2adbcc146b9eb7748983c720e35e38d0dc9vboxsync return "SVGA_REG_HEIGHT";
0612e2adbcc146b9eb7748983c720e35e38d0dc9vboxsync return "SVGA_REG_MAX_WIDTH";
0612e2adbcc146b9eb7748983c720e35e38d0dc9vboxsync return "SVGA_REG_MAX_HEIGHT";
0612e2adbcc146b9eb7748983c720e35e38d0dc9vboxsync return "SVGA_REG_DEPTH";
39c2eccedfdb7455c52225543c355e33a65f0c81vboxsync case SVGA_REG_BITS_PER_PIXEL: /* Current bpp in the guest */
39c2eccedfdb7455c52225543c355e33a65f0c81vboxsync return "SVGA_REG_BITS_PER_PIXEL";
39c2eccedfdb7455c52225543c355e33a65f0c81vboxsync case SVGA_REG_HOST_BITS_PER_PIXEL: /* (Deprecated) */
b72d3233df38e3122eda39b39a27b35c27209615vboxsync return "SVGA_REG_HOST_BITS_PER_PIXEL";
5981e6935987b08737b730b63a41acc1dd696377vboxsync return "SVGA_REG_PSEUDOCOLOR";
d8dee9a7ef33d4c705d5fd087d5af9c7cb071f85vboxsync return "SVGA_REG_RED_MASK";
39c2eccedfdb7455c52225543c355e33a65f0c81vboxsync return "SVGA_REG_GREEN_MASK";
39c2eccedfdb7455c52225543c355e33a65f0c81vboxsync return "SVGA_REG_BLUE_MASK";
39c2eccedfdb7455c52225543c355e33a65f0c81vboxsync return "SVGA_REG_BYTES_PER_LINE";
39c2eccedfdb7455c52225543c355e33a65f0c81vboxsync return "SVGA_REG_VRAM_SIZE";
39c2eccedfdb7455c52225543c355e33a65f0c81vboxsync case SVGA_REG_FB_START: /* Frame buffer physical address. */
39c2eccedfdb7455c52225543c355e33a65f0c81vboxsync return "SVGA_REG_FB_START";
39c2eccedfdb7455c52225543c355e33a65f0c81vboxsync case SVGA_REG_FB_OFFSET: /* Offset of the frame buffer in VRAM */
39c2eccedfdb7455c52225543c355e33a65f0c81vboxsync return "SVGA_REG_FB_OFFSET";
d8dee9a7ef33d4c705d5fd087d5af9c7cb071f85vboxsync return "SVGA_REG_FB_SIZE";
39c2eccedfdb7455c52225543c355e33a65f0c81vboxsync return "SVGA_REG_CAPABILITIES";
39c2eccedfdb7455c52225543c355e33a65f0c81vboxsync return "SVGA_REG_MEM_START";
d8dee9a7ef33d4c705d5fd087d5af9c7cb071f85vboxsync return "SVGA_REG_MEM_SIZE";
d8dee9a7ef33d4c705d5fd087d5af9c7cb071f85vboxsync case SVGA_REG_CONFIG_DONE: /* Set when memory area configured */
d8dee9a7ef33d4c705d5fd087d5af9c7cb071f85vboxsync return "SVGA_REG_CONFIG_DONE";
d8dee9a7ef33d4c705d5fd087d5af9c7cb071f85vboxsync case SVGA_REG_SYNC: /* See "FIFO Synchronization Registers" */
d8dee9a7ef33d4c705d5fd087d5af9c7cb071f85vboxsync return "SVGA_REG_SYNC";
b35e3948f1287430503b6b432945b8cf4bfd3a23vboxsync case SVGA_REG_BUSY: /* See "FIFO Synchronization Registers" */
d8dee9a7ef33d4c705d5fd087d5af9c7cb071f85vboxsync return "SVGA_REG_BUSY";
d8dee9a7ef33d4c705d5fd087d5af9c7cb071f85vboxsync case SVGA_REG_GUEST_ID: /* Set guest OS identifier */
d8dee9a7ef33d4c705d5fd087d5af9c7cb071f85vboxsync return "SVGA_REG_GUEST_ID";
d8dee9a7ef33d4c705d5fd087d5af9c7cb071f85vboxsync case SVGA_REG_SCRATCH_SIZE: /* Number of scratch registers */
d8dee9a7ef33d4c705d5fd087d5af9c7cb071f85vboxsync return "SVGA_REG_SCRATCH_SIZE";
d8dee9a7ef33d4c705d5fd087d5af9c7cb071f85vboxsync case SVGA_REG_MEM_REGS: /* Number of FIFO registers */
d8dee9a7ef33d4c705d5fd087d5af9c7cb071f85vboxsync return "SVGA_REG_MEM_REGS";
d8dee9a7ef33d4c705d5fd087d5af9c7cb071f85vboxsync case SVGA_REG_PITCHLOCK: /* Fixed pitch for all modes */
d8dee9a7ef33d4c705d5fd087d5af9c7cb071f85vboxsync return "SVGA_REG_PITCHLOCK";
d8dee9a7ef33d4c705d5fd087d5af9c7cb071f85vboxsync return "SVGA_REG_IRQMASK";
d8dee9a7ef33d4c705d5fd087d5af9c7cb071f85vboxsync return "SVGA_REG_GMR_ID";
d8dee9a7ef33d4c705d5fd087d5af9c7cb071f85vboxsync return "SVGA_REG_GMR_DESCRIPTOR";
d8dee9a7ef33d4c705d5fd087d5af9c7cb071f85vboxsync return "SVGA_REG_GMR_MAX_IDS";
d8dee9a7ef33d4c705d5fd087d5af9c7cb071f85vboxsync return "SVGA_REG_GMR_MAX_DESCRIPTOR_LENGTH";
d8dee9a7ef33d4c705d5fd087d5af9c7cb071f85vboxsync case SVGA_REG_TRACES: /* Enable trace-based updates even when FIFO is on */
0612e2adbcc146b9eb7748983c720e35e38d0dc9vboxsync return "SVGA_REG_TRACES";
e2a73964f463b9e91f6f096f9e15974a3edcc416vboxsync case SVGA_REG_GMRS_MAX_PAGES: /* Maximum number of 4KB pages for all GMRs */
683eff3070b1b86fe71b71af7fda82766ea19d17vboxsync return "SVGA_REG_GMRS_MAX_PAGES";
6d41476175401a18893ea8cb8a40d125eefa04f3vboxsync case SVGA_REG_MEMORY_SIZE: /* Total dedicated device memory excluding FIFO */
6d41476175401a18893ea8cb8a40d125eefa04f3vboxsync return "SVGA_REG_MEMORY_SIZE";
683eff3070b1b86fe71b71af7fda82766ea19d17vboxsync case SVGA_REG_TOP: /* Must be 1 more than the last register */
9b456547aefb8a2e8f5600eba9ec377dbc9b4475vboxsync return "SVGA_REG_TOP";
683eff3070b1b86fe71b71af7fda82766ea19d17vboxsync case SVGA_PALETTE_BASE: /* Base of SVGA color map */
9b456547aefb8a2e8f5600eba9ec377dbc9b4475vboxsync return "SVGA_PALETTE_BASE";
9b456547aefb8a2e8f5600eba9ec377dbc9b4475vboxsync return "SVGA_REG_CURSOR_ID";
9b456547aefb8a2e8f5600eba9ec377dbc9b4475vboxsync return "SVGA_REG_CURSOR_X";
9b456547aefb8a2e8f5600eba9ec377dbc9b4475vboxsync return "SVGA_REG_CURSOR_Y";
9b456547aefb8a2e8f5600eba9ec377dbc9b4475vboxsync return "SVGA_REG_CURSOR_ON";
9b456547aefb8a2e8f5600eba9ec377dbc9b4475vboxsync case SVGA_REG_NUM_GUEST_DISPLAYS:/* Number of guest displays in X/Y direction */
9b456547aefb8a2e8f5600eba9ec377dbc9b4475vboxsync return "SVGA_REG_NUM_GUEST_DISPLAYS";
6d41476175401a18893ea8cb8a40d125eefa04f3vboxsync case SVGA_REG_DISPLAY_ID: /* Display ID for the following display attributes */
6d41476175401a18893ea8cb8a40d125eefa04f3vboxsync return "SVGA_REG_DISPLAY_ID";
9b456547aefb8a2e8f5600eba9ec377dbc9b4475vboxsync case SVGA_REG_DISPLAY_IS_PRIMARY:/* Whether this is a primary display */
9b456547aefb8a2e8f5600eba9ec377dbc9b4475vboxsync return "SVGA_REG_DISPLAY_IS_PRIMARY";
9b456547aefb8a2e8f5600eba9ec377dbc9b4475vboxsync case SVGA_REG_DISPLAY_POSITION_X:/* The display position x */
9b456547aefb8a2e8f5600eba9ec377dbc9b4475vboxsync return "SVGA_REG_DISPLAY_POSITION_X";
9b456547aefb8a2e8f5600eba9ec377dbc9b4475vboxsync case SVGA_REG_DISPLAY_POSITION_Y:/* The display position y */
9b456547aefb8a2e8f5600eba9ec377dbc9b4475vboxsync return "SVGA_REG_DISPLAY_POSITION_Y";
6d41476175401a18893ea8cb8a40d125eefa04f3vboxsync case SVGA_REG_DISPLAY_WIDTH: /* The display's width */
6d41476175401a18893ea8cb8a40d125eefa04f3vboxsync return "SVGA_REG_DISPLAY_WIDTH";
6d41476175401a18893ea8cb8a40d125eefa04f3vboxsync case SVGA_REG_DISPLAY_HEIGHT: /* The display's height */
6d41476175401a18893ea8cb8a40d125eefa04f3vboxsync return "SVGA_REG_DISPLAY_HEIGHT";
6d41476175401a18893ea8cb8a40d125eefa04f3vboxsync return "SVGA_REG_NUM_DISPLAYS";
9b456547aefb8a2e8f5600eba9ec377dbc9b4475vboxsync && pThis->svga.u32IndexReg < SVGA_SCRATCH_BASE + pThis->svga.cScratchRegion)
9b456547aefb8a2e8f5600eba9ec377dbc9b4475vboxsync return "SVGA_SCRATCH_BASE reg";
9b456547aefb8a2e8f5600eba9ec377dbc9b4475vboxsync return "UNKNOWN";
9b456547aefb8a2e8f5600eba9ec377dbc9b4475vboxsync * FIFO command name lookup
6d41476175401a18893ea8cb8a40d125eefa04f3vboxsync * @returns FIFO command string or "UNKNOWN"
9b456547aefb8a2e8f5600eba9ec377dbc9b4475vboxsync * @param u32Cmd FIFO command
9b456547aefb8a2e8f5600eba9ec377dbc9b4475vboxsyncstatic const char *vmsvgaFIFOCmdToString(uint32_t u32Cmd)
9b456547aefb8a2e8f5600eba9ec377dbc9b4475vboxsync return "SVGA_CMD_INVALID_CMD";
6d41476175401a18893ea8cb8a40d125eefa04f3vboxsync return "SVGA_CMD_UPDATE";
683eff3070b1b86fe71b71af7fda82766ea19d17vboxsync return "SVGA_CMD_RECT_COPY";
9b456547aefb8a2e8f5600eba9ec377dbc9b4475vboxsync return "SVGA_CMD_DEFINE_CURSOR";
9b456547aefb8a2e8f5600eba9ec377dbc9b4475vboxsync return "SVGA_CMD_DEFINE_ALPHA_CURSOR";
6d41476175401a18893ea8cb8a40d125eefa04f3vboxsync return "SVGA_CMD_UPDATE_VERBOSE";
9b456547aefb8a2e8f5600eba9ec377dbc9b4475vboxsync return "SVGA_CMD_FRONT_ROP_FILL";
9b456547aefb8a2e8f5600eba9ec377dbc9b4475vboxsync return "SVGA_CMD_FENCE";
9b456547aefb8a2e8f5600eba9ec377dbc9b4475vboxsync return "SVGA_CMD_ESCAPE";
6d41476175401a18893ea8cb8a40d125eefa04f3vboxsync return "SVGA_CMD_DEFINE_SCREEN";
9b456547aefb8a2e8f5600eba9ec377dbc9b4475vboxsync return "SVGA_CMD_DESTROY_SCREEN";
9b456547aefb8a2e8f5600eba9ec377dbc9b4475vboxsync return "SVGA_CMD_DEFINE_GMRFB";
9b456547aefb8a2e8f5600eba9ec377dbc9b4475vboxsync return "SVGA_CMD_BLIT_GMRFB_TO_SCREEN";
6d41476175401a18893ea8cb8a40d125eefa04f3vboxsync return "SVGA_CMD_BLIT_SCREEN_TO_GMRFB";
6d41476175401a18893ea8cb8a40d125eefa04f3vboxsync return "SVGA_CMD_ANNOTATION_FILL";
6d41476175401a18893ea8cb8a40d125eefa04f3vboxsync return "SVGA_CMD_ANNOTATION_COPY";
6d41476175401a18893ea8cb8a40d125eefa04f3vboxsync return "SVGA_CMD_DEFINE_GMR2";
6d41476175401a18893ea8cb8a40d125eefa04f3vboxsync return "SVGA_CMD_REMAP_GMR2";
9b456547aefb8a2e8f5600eba9ec377dbc9b4475vboxsync return "SVGA_3D_CMD_SURFACE_DEFINE";
9b456547aefb8a2e8f5600eba9ec377dbc9b4475vboxsync return "SVGA_3D_CMD_SURFACE_DESTROY";
9b456547aefb8a2e8f5600eba9ec377dbc9b4475vboxsync return "SVGA_3D_CMD_SURFACE_COPY";
9b456547aefb8a2e8f5600eba9ec377dbc9b4475vboxsync return "SVGA_3D_CMD_SURFACE_STRETCHBLT";
9b456547aefb8a2e8f5600eba9ec377dbc9b4475vboxsync return "SVGA_3D_CMD_SURFACE_DMA";
6d41476175401a18893ea8cb8a40d125eefa04f3vboxsync return "SVGA_3D_CMD_CONTEXT_DEFINE";
9b456547aefb8a2e8f5600eba9ec377dbc9b4475vboxsync return "SVGA_3D_CMD_CONTEXT_DESTROY";
6d41476175401a18893ea8cb8a40d125eefa04f3vboxsync return "SVGA_3D_CMD_SETTRANSFORM";
9b456547aefb8a2e8f5600eba9ec377dbc9b4475vboxsync return "SVGA_3D_CMD_SETZRANGE";
9b456547aefb8a2e8f5600eba9ec377dbc9b4475vboxsync return "SVGA_3D_CMD_SETRENDERSTATE";
6d41476175401a18893ea8cb8a40d125eefa04f3vboxsync return "SVGA_3D_CMD_SETRENDERTARGET";
683eff3070b1b86fe71b71af7fda82766ea19d17vboxsync return "SVGA_3D_CMD_SETTEXTURESTATE";
b72d3233df38e3122eda39b39a27b35c27209615vboxsync return "SVGA_3D_CMD_SETMATERIAL";
9b456547aefb8a2e8f5600eba9ec377dbc9b4475vboxsync return "SVGA_3D_CMD_SETLIGHTDATA";
9b456547aefb8a2e8f5600eba9ec377dbc9b4475vboxsync return "SVGA_3D_CMD_SETLIGHTENABLED";
9b456547aefb8a2e8f5600eba9ec377dbc9b4475vboxsync return "SVGA_3D_CMD_SETVIEWPORT";
9b456547aefb8a2e8f5600eba9ec377dbc9b4475vboxsync return "SVGA_3D_CMD_SETCLIPPLANE";
9b456547aefb8a2e8f5600eba9ec377dbc9b4475vboxsync return "SVGA_3D_CMD_CLEAR";
6d41476175401a18893ea8cb8a40d125eefa04f3vboxsync return "SVGA_3D_CMD_PRESENT";
9b456547aefb8a2e8f5600eba9ec377dbc9b4475vboxsync return "SVGA_3D_CMD_SHADER_DEFINE";
9b456547aefb8a2e8f5600eba9ec377dbc9b4475vboxsync return "SVGA_3D_CMD_SHADER_DESTROY";
9b456547aefb8a2e8f5600eba9ec377dbc9b4475vboxsync return "SVGA_3D_CMD_SET_SHADER";
6d41476175401a18893ea8cb8a40d125eefa04f3vboxsync return "SVGA_3D_CMD_SET_SHADER_CONST";
9b456547aefb8a2e8f5600eba9ec377dbc9b4475vboxsync return "SVGA_3D_CMD_DRAW_PRIMITIVES";
9b456547aefb8a2e8f5600eba9ec377dbc9b4475vboxsync return "SVGA_3D_CMD_SETSCISSORRECT";
9b456547aefb8a2e8f5600eba9ec377dbc9b4475vboxsync return "SVGA_3D_CMD_BEGIN_QUERY";
6d41476175401a18893ea8cb8a40d125eefa04f3vboxsync return "SVGA_3D_CMD_END_QUERY";
6d41476175401a18893ea8cb8a40d125eefa04f3vboxsync return "SVGA_3D_CMD_WAIT_FOR_QUERY";
6d41476175401a18893ea8cb8a40d125eefa04f3vboxsync return "SVGA_3D_CMD_PRESENT_READBACK";
6d41476175401a18893ea8cb8a40d125eefa04f3vboxsync return "SVGA_3D_CMD_BLIT_SURFACE_TO_SCREEN";
6d41476175401a18893ea8cb8a40d125eefa04f3vboxsync return "SVGA_3D_CMD_SURFACE_DEFINE_V2";
9b456547aefb8a2e8f5600eba9ec377dbc9b4475vboxsync return "SVGA_3D_CMD_GENERATE_MIPMAPS";
9b456547aefb8a2e8f5600eba9ec377dbc9b4475vboxsync return "SVGA_3D_CMD_ACTIVATE_SURFACE";
9b456547aefb8a2e8f5600eba9ec377dbc9b4475vboxsync return "SVGA_3D_CMD_DEACTIVATE_SURFACE";
9b456547aefb8a2e8f5600eba9ec377dbc9b4475vboxsync return "UNKNOWN";
9b456547aefb8a2e8f5600eba9ec377dbc9b4475vboxsync * Inform the VGA device of viewport changes (as a result of e.g. scrolling)
6d41476175401a18893ea8cb8a40d125eefa04f3vboxsync * @param pInterface Pointer to this interface.
9b456547aefb8a2e8f5600eba9ec377dbc9b4475vboxsync * @param uScreenId The screen updates are for.
9b456547aefb8a2e8f5600eba9ec377dbc9b4475vboxsync * @param x The upper left corner x coordinate of the new viewport rectangle
9b456547aefb8a2e8f5600eba9ec377dbc9b4475vboxsync * @param y The upper left corner y coordinate of the new viewport rectangle
9b456547aefb8a2e8f5600eba9ec377dbc9b4475vboxsync * @param cx The width of the new viewport rectangle
6d41476175401a18893ea8cb8a40d125eefa04f3vboxsync * @param cy The height of the new viewport rectangle
9b456547aefb8a2e8f5600eba9ec377dbc9b4475vboxsync * @thread The emulation thread.
9b456547aefb8a2e8f5600eba9ec377dbc9b4475vboxsyncDECLCALLBACK(void) vmsvgaPortSetViewPort(PPDMIDISPLAYPORT pInterface, uint32_t uScreenId, uint32_t x, uint32_t y, uint32_t cx, uint32_t cy)
9b456547aefb8a2e8f5600eba9ec377dbc9b4475vboxsync PVGASTATE pThis = RT_FROM_MEMBER(pInterface, VGASTATE, IPort);
9b456547aefb8a2e8f5600eba9ec377dbc9b4475vboxsync Log(("vmsvgaPortSetViewPort: screen %d (%d,%d)(%d,%d)\n", uScreenId, x, y, cx, cy));
9b456547aefb8a2e8f5600eba9ec377dbc9b4475vboxsync pThis->svga.viewport.cx = RT_MIN(cx, (uint32_t)pThis->svga.uWidth);
9b456547aefb8a2e8f5600eba9ec377dbc9b4475vboxsync pThis->svga.viewport.cy = RT_MIN(cy, (uint32_t)pThis->svga.uHeight);
6d41476175401a18893ea8cb8a40d125eefa04f3vboxsync * Read port register
9b456547aefb8a2e8f5600eba9ec377dbc9b4475vboxsync * @returns VBox status code.
9b456547aefb8a2e8f5600eba9ec377dbc9b4475vboxsync * @param pThis VMSVGA State
9b456547aefb8a2e8f5600eba9ec377dbc9b4475vboxsync * @param pu32 Where to store the read value
9b456547aefb8a2e8f5600eba9ec377dbc9b4475vboxsyncPDMBOTHCBDECL(int) vmsvgaReadPort(PVGASTATE pThis, uint32_t *pu32)
9b456547aefb8a2e8f5600eba9ec377dbc9b4475vboxsync && pThis->svga.uHeight != VMSVGA_VAL_UNINITIALIZED)
6d41476175401a18893ea8cb8a40d125eefa04f3vboxsync /* This returns the color depth of the current mode. */
9b456547aefb8a2e8f5600eba9ec377dbc9b4475vboxsync *pu32 = 24; /* The upper 8 bits are either alpha bits or not used. */
9b456547aefb8a2e8f5600eba9ec377dbc9b4475vboxsync case SVGA_REG_HOST_BITS_PER_PIXEL: /* (Deprecated) */
9b456547aefb8a2e8f5600eba9ec377dbc9b4475vboxsync case SVGA_REG_BITS_PER_PIXEL: /* Current bpp in the guest */
case SVGA_REG_RED_MASK:
case SVGA_REG_GREEN_MASK:
case SVGA_REG_BLUE_MASK:
case SVGA_REG_BYTES_PER_LINE:
#ifndef IN_RING3
*pu32 = 0;
#ifndef IN_RING3
case SVGA_REG_CAPABILITIES:
*pu32 = 0;
#ifndef IN_RING3
case SVGA_REG_GMR_ID:
case SVGA_REG_GMR_DESCRIPTOR:
*pu32 = 0;
case SVGA_REG_GMR_MAX_IDS:
case SVGA_REG_CURSOR_ID:
case SVGA_REG_CURSOR_X:
case SVGA_REG_CURSOR_Y:
case SVGA_REG_CURSOR_ON:
*pu32 = 0;
*pu32 = 1; /* Must return something sensible here otherwise the Linux driver will take a legacy code path without 3d support. */
Log(("vmsvgaReadPort index=%s (%d) val=%#x rc=%x\n", vmsvgaIndexToString(pThis), pThis->svga.u32IndexReg, *pu32, rc));
return rc;
#ifdef IN_RING3
int rc;
Log(("vmsvgaChangeMode: BOGUS sEnable LFB mode and resize to (%d,%d) bpp=%d\n", pThis->svga.uWidth, pThis->svga.uHeight, pThis->svga.uBpp));
return VINF_SUCCESS;
Log(("vmsvgaChangeMode: BOGUS sEnable LFB mode and resize to (%d,%d) bpp=%d\n", pThis->svga.uWidth, pThis->svga.uHeight, pThis->svga.uBpp));
return VINF_SUCCESS;
return VINF_SUCCESS;
Log(("vmsvgaChangeMode: sEnable LFB mode and resize to (%d,%d) bpp=%d\n", pThis->svga.uWidth, pThis->svga.uHeight, pThis->svga.uBpp));
rc = pThis->pDrv->pfnResize(pThis->pDrv, pThis->svga.uBpp, pThis->CTX_SUFF(vram_ptr), pThis->svga.cbScanline, pThis->svga.uWidth, pThis->svga.uHeight);
return VINF_SUCCESS;
Log(("vmsvgaWritePort index=%s (%d) val=%#x\n", vmsvgaIndexToString(pThis), pThis->svga.u32IndexReg, u32));
case SVGA_REG_ID:
case SVGA_REG_ENABLE:
#ifdef IN_RING3
pThis->svga.cbScanline = 0; */
case SVGA_REG_WIDTH:
#ifdef IN_RING3
case SVGA_REG_HEIGHT:
#ifdef IN_RING3
case SVGA_REG_DEPTH:
#ifdef IN_RING3
case SVGA_REG_PSEUDOCOLOR:
#ifdef IN_RING3
case SVGA_REG_CURSOR_ID:
case SVGA_REG_CURSOR_X:
case SVGA_REG_CURSOR_Y:
case SVGA_REG_CURSOR_ON:
#ifdef VBOX_WITH_VMSVGA3D
case SVGA_REG_GMR_ID:
case SVGA_REG_GMR_DESCRIPTOR:
# ifndef IN_RING3
if (GCPhys == 0)
pSVGAState->aGMR[idGMR].paDesc = (PVMSVGAGMRDESCRIPTOR)RTMemAllocZ(cDescriptorsAllocated * sizeof(VMSVGAGMRDESCRIPTOR));
pSVGAState->aGMR[idGMR].paDesc = (PVMSVGAGMRDESCRIPTOR)RTMemRealloc(pSVGAState->aGMR[idGMR].paDesc, cDescriptorsAllocated * sizeof(VMSVGAGMRDESCRIPTOR));
Log(("Defined new gmr %x numDescriptors=%d cbTotal=%x\n", idGMR, iDescriptor, pSVGAState->aGMR[idGMR].cbTotal));
AssertFailed();
#ifdef IN_RING3
case SVGA_REG_FB_START:
case SVGA_REG_MEM_START:
case SVGA_REG_MAX_WIDTH:
case SVGA_REG_MAX_HEIGHT:
case SVGA_REG_VRAM_SIZE:
case SVGA_REG_FB_SIZE:
case SVGA_REG_CAPABILITIES:
case SVGA_REG_MEM_SIZE:
case SVGA_REG_BYTES_PER_LINE:
case SVGA_REG_FB_OFFSET:
case SVGA_REG_RED_MASK:
case SVGA_REG_GREEN_MASK:
case SVGA_REG_BLUE_MASK:
case SVGA_REG_GMR_MAX_IDS:
return rc;
PDMBOTHCBDECL(int) vmsvgaIORead(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t *pu32, unsigned cb)
*pu32 = ~0;
return VINF_SUCCESS;
case SVGA_INDEX_PORT:
case SVGA_VALUE_PORT:
case SVGA_BIOS_PORT:
*pu32 = 0;
case SVGA_IRQSTATUS_PORT:
return rc;
PDMBOTHCBDECL(int) vmsvgaIOWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb)
return VINF_SUCCESS;
case SVGA_INDEX_PORT:
case SVGA_VALUE_PORT:
case SVGA_BIOS_PORT:
case SVGA_IRQSTATUS_PORT:
Log(("vmsvgaIOWrite SVGA_IRQSTATUS_PORT %x: status %x -> %x\n", u32, pThis->svga.u32IrqStatus, pThis->svga.u32IrqStatus & ~u32));
return rc;
#ifdef DEBUG_FIFO_ACCESS
# ifdef IN_RING3
case SVGA_FIFO_MIN:
Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_MIN = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
case SVGA_FIFO_MAX:
Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_MAX = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
case SVGA_FIFO_NEXT_CMD:
Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_NEXT_CMD = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
case SVGA_FIFO_STOP:
Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_STOP = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
case SVGA_FIFO_CAPABILITIES:
Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_CAPABILITIES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
case SVGA_FIFO_FLAGS:
Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_FLAGS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
case SVGA_FIFO_FENCE:
Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_FENCE = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
case SVGA_FIFO_3D_HWVERSION:
Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_HWVERSION = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
case SVGA_FIFO_PITCHLOCK:
Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_PITCHLOCK = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
case SVGA_FIFO_CURSOR_ON:
Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_CURSOR_ON = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
case SVGA_FIFO_CURSOR_X:
Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_CURSOR_X = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
case SVGA_FIFO_CURSOR_Y:
Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_CURSOR_Y = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
case SVGA_FIFO_CURSOR_COUNT:
Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_CURSOR_COUNT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_CURSOR_LAST_UPDATED = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
case SVGA_FIFO_RESERVED:
Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_RESERVED = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_CURSOR_SCREEN_ID = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
case SVGA_FIFO_DEAD:
Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_DEAD = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_HWVERSION_REVISED = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_3D = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_LIGHTS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_TEXTURES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_CLIP_PLANES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_VERTEX_SHADER_VERSION = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_VERTEX_SHADER = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_FRAGMENT_SHADER_VERSION = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_FRAGMENT_SHADER = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_RENDER_TARGETS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_S23E8_TEXTURES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_S10E5_TEXTURES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_FIXED_VERTEXBLEND = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_D16_BUFFER_FORMAT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_D24S8_BUFFER_FORMAT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_D24X8_BUFFER_FORMAT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_QUERY_TYPES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_TEXTURE_GRADIENT_SAMPLING = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_POINT_SIZE = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_SHADER_TEXTURES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_TEXTURE_WIDTH = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_TEXTURE_HEIGHT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_VOLUME_EXTENT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_TEXTURE_REPEAT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_TEXTURE_ASPECT_RATIO = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_TEXTURE_ANISOTROPY = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_PRIMITIVE_COUNT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_VERTEX_INDEX = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_VERTEX_SHADER_INSTRUCTIONS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_FRAGMENT_SHADER_INSTRUCTIONS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_VERTEX_SHADER_TEMPS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_FRAGMENT_SHADER_TEMPS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_TEXTURE_OPS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_X8R8G8B8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_A8R8G8B8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_A2R10G10B10 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_X1R5G5B5 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_A1R5G5B5 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_A4R4G4B4 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_R5G6B5 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE16 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE8_ALPHA8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_ALPHA8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_Z_D16 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_Z_D24S8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_Z_D24X8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_DXT1 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_DXT2 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_DXT3 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_DXT4 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_DXT5 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_BUMPX8L8V8U8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_A2W10V10U10 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_BUMPU8V8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_Q8W8V8U8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_CxV8U8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_R_S10E5 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_R_S23E8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_RG_S10E5 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_RG_S23E8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_ARGB_S10E5 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_ARGB_S23E8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_VERTEX_SHADER_TEXTURES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_SIMULTANEOUS_RENDER_TARGETS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_V16U16 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_G16R16 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_A16B16G16R16 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_UYVY = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_YUY2 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MULTISAMPLE_NONMASKABLESAMPLES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MULTISAMPLE_MASKABLESAMPLES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_ALPHATOCOVERAGE = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SUPERSAMPLE = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_AUTOGENMIPMAPS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_NV12 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_AYUV = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_CONTEXT_IDS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_SURFACE_IDS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_Z_DF16 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_Z_DF24 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_Z_D24S8_INT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_BC4_UNORM = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_BC5_UNORM = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
case SVGA_FIFO_3D_CAPS_LAST:
Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS_LAST = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_GUEST_3D_HWVERSION = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
case SVGA_FIFO_FENCE_GOAL:
Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_FENCE_GOAL = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
case SVGA_FIFO_BUSY:
Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_BUSY = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
Log(("vmsvgaFIFOAccess [0x%x]: %s access at offset %x = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", GCPhysOffset, pFIFO[GCPhysOffset >> 2]));
return VINF_EM_RAW_EMULATE_INSTR;
static DECLCALLBACK(int) vmsvgaR3FIFOAccessHandler(PVM pVM, RTGCPHYS GCPhys, void *pvPhys, void *pvBuf, size_t cbBuf, PGMACCESSTYPE enmAccessType, void *pvUser)
int rc;
return VINF_PGM_HANDLER_DO_DEFAULT;
return rc;
#ifdef DEBUG_GMR_ACCESS
static DECLCALLBACK(int) vmsvgaR3GMRAccessHandler(PVM pVM, RTGCPHYS GCPhys, void *pvPhys, void *pvBuf, size_t cbBuf, PGMACCESSTYPE enmAccessType, void *pvUser)
goto end;
end:
return VINF_PGM_HANDLER_DO_DEFAULT;
# ifdef IN_RING3
int rc;
return VINF_SUCCESS;
return VINF_SUCCESS;
return VINF_SUCCESS;
#ifdef IN_RING3
static void *vmsvgaFIFOGetCmdPayload(PPDMTHREAD pThread, uint32_t cbPayloadReq, uint32_t volatile *pFIFO,
return pbBounceBuf;
AssertMsgReturn(cbPayloadReq <= cbFifoCmd, ("cbPayloadReq=%#x cbFifoCmd=%#x\n", cbPayloadReq, cbFifoCmd), NULL);
cbBefore = 0;
cbBefore = 0;
cbBefore = 0;
return pbBounceBuf;
#define VMSVGA_IS_VALID_FIFO_REG(a_iIndex, a_offFifoMin) ( ((a_iIndex) + 1) * sizeof(uint32_t) <= (a_offFifoMin) )
int rc;
return VINF_SUCCESS;
Log(("vmsvgaFIFOLoop: enabled=%d configured=%d busy=%d\n", pThis->svga.fEnabled, pThis->svga.fConfigured, pThis->svga.pFIFOR3[SVGA_FIFO_BUSY]));
case VMSVGA_FIFO_EXTCMD_RESET:
# ifdef VBOX_WITH_VMSVGA3D
# ifdef VBOX_WITH_VMSVGA3D
# ifdef VBOX_WITH_VMSVGA3D
# ifdef VBOX_WITH_VMSVGA3D
LogRelMax(8, ("vmsvgaFIFOLoop: Bad fifo: min=%#x stop=%#x max=%#x\n", offFifoMin, offCurrentCmd, offFifoMax));
bool fDone = false;
bool fTriggerIrq = false;
# ifdef VBOX_WITH_VMSVGA3D
switch (enmCmdId)
case SVGA_CMD_INVALID_CMD:
case SVGA_CMD_FENCE:
case SVGA_CMD_UPDATE:
case SVGA_CMD_UPDATE_VERBOSE:
Log(("vmsvgaFIFOLoop: UPDATE (%d,%d)(%d,%d)\n", pUpdate->x, pUpdate->y, pUpdate->width, pUpdate->height));
case SVGA_CMD_DEFINE_CURSOR:
Log(("vmsvgaFIFOLoop: ALPHA_CURSOR id=%d size (%d,%d) hotspot (%d,%d)\n", pCursor->id, pCursor->width, pCursor->height, pCursor->hotspotX, pCursor->hotspotY));
/* Check against a reasonable upper limit to prevent integer overflows in the sanity checks below. */
cbCmd = sizeof(SVGAFifoCmdDefineAlphaCursor) + pCursor->width * pCursor->height * sizeof(uint32_t) /* 32-bit BRGA format */;
cbCursorShape = cbAndMask + pCursor->width * sizeof(uint32_t) * pCursor->height; /* + size of the XOR mask (32-bit BRGA format) */
memcpy(pCursorCopy + cbAndMask, (pCursor + 1), pCursor->width * pCursor->height * sizeof(uint32_t));
case SVGA_CMD_ESCAPE:
switch (cmd)
Log(("SVGA_ESCAPE_VMWARE_VIDEO_SET_REGS: reg %x val %x\n", pVideoCmd->items[iReg].registerId, pVideoCmd->items[iReg].value));
# ifdef VBOX_WITH_VMSVGA3D
case SVGA_CMD_DEFINE_GMR2:
case SVGA_CMD_REMAP_GMR2:
Log(("vmsvgaFIFOLoop: SVGA_CMD_REMAP_GMR2 id=%x flags=%x offset=%x npages=%x\n", pCmd->gmrId, pCmd->flags, pCmd->offsetPages, pCmd->numPages));
AssertFailed();
if (paNewPage64)
fGCPhys64 = true;
if (fGCPhys64)
GCPhys = (pPage64[0] << PAGE_SHIFT) & 0x00000FFFFFFFFFFFULL; /* seeing rubbish in the top bits with certain linux guests*/
GCPhys = (pPage64[i] << PAGE_SHIFT) & 0x00000FFFFFFFFFFFULL; /* seeing rubbish in the top bits with certain linux guests*/
iDescriptor++;
if (paNewPage64)
# ifdef DEBUG_GMR_ACCESS
VMR3ReqCallWait(PDMDevHlpGetVM(pThis->pDevInsR3), VMCPUID_ANY, (PFNRT)vmsvgaRegisterGMR, 2, pThis->pDevInsR3, pCmd->gmrId);
case SVGA_CMD_DEFINE_SCREEN:
RT_BZERO(&pCmd->screen.id, sizeof(*pCmd) - RT_OFFSETOF(SVGAFifoCmdDefineScreen, screen.structSize));
VMSVGAFIFO_GET_MORE_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdDefineScreen, RT_MAX(sizeof(pCmd->screen.structSize), pCmd->screen.structSize));
Log(("vmsvgaFIFOLoop: SVGA_CMD_DEFINE_SCREEN id=%x flags=%x size=(%d,%d) root=(%d,%d)\n", pCmd->screen.id, pCmd->screen.flags, pCmd->screen.size.width, pCmd->screen.size.height, pCmd->screen.root.x, pCmd->screen.root.y));
case SVGA_CMD_DESTROY_SCREEN:
# ifdef VBOX_WITH_VMSVGA3D
case SVGA_CMD_DEFINE_GMRFB:
Log(("vmsvgaFIFOLoop: SVGA_CMD_DEFINE_GMRFB gmr=%x offset=%x bytesPerLine=%x bpp=%d color depth=%d\n", pCmd->ptr.gmrId, pCmd->ptr.offset, pCmd->bytesPerLine, pCmd->format.s.bitsPerPixel, pCmd->format.s.colorDepth));
Log(("vmsvgaFIFOLoop: SVGA_CMD_BLIT_GMRFB_TO_SCREEN src=(%d,%d) dest id=%d (%d,%d)(%d,%d)\n", pCmd->srcOrigin.x, pCmd->srcOrigin.y, pCmd->destScreenId, pCmd->destRect.left, pCmd->destRect.top, pCmd->destRect.right, pCmd->destRect.bottom));
/** @todo Support GMRFB.format.s.bitsPerPixel != pThis->svga.uBpp */
if ( width == 0
|| height == 0)
unsigned offsetSource = (pCmd->srcOrigin.x * pSVGAState->GMRFB.format.s.bitsPerPixel) / 8 + pSVGAState->GMRFB.bytesPerLine * pCmd->srcOrigin.y;
unsigned offsetDest = (pCmd->destRect.left * RT_ALIGN(pThis->svga.uBpp, 8)) / 8 + pThis->svga.cbScanline * pCmd->destRect.top;
rc = vmsvgaGMRTransfer(pThis, SVGA3D_WRITE_HOST_VRAM, pThis->CTX_SUFF(vram_ptr) + offsetDest, pThis->svga.cbScanline, pSVGAState->GMRFB.ptr, offsetSource, pSVGAState->GMRFB.bytesPerLine, cbCopyWidth, height);
vgaR3UpdateDisplay(pThis, pCmd->destRect.left, pCmd->destRect.top, pCmd->destRect.right - pCmd->destRect.left, pCmd->destRect.bottom - pCmd->destRect.top);
Log(("vmsvgaFIFOLoop: SVGA_CMD_BLIT_SCREEN_TO_GMRFB dest=(%d,%d) src id=%d (%d,%d)(%d,%d)\n", pCmd->destOrigin.x, pCmd->destOrigin.y, pCmd->srcScreenId, pCmd->srcRect.left, pCmd->srcRect.top, pCmd->srcRect.right, pCmd->srcRect.bottom));
AssertFailed();
case SVGA_CMD_ANNOTATION_FILL:
Log(("vmsvgaFIFOLoop: SVGA_CMD_ANNOTATION_FILL red=%x green=%x blue=%x\n", pCmd->color.s.r, pCmd->color.s.g, pCmd->color.s.b));
case SVGA_CMD_ANNOTATION_COPY:
AssertFailed();
# ifdef VBOX_WITH_VMSVGA3D
switch (enmCmdId)
rc = vmsvga3dSurfaceDefine(pThis, pCmd->sid, (uint32_t)pCmd->surfaceFlags, pCmd->format, pCmd->face, 0, SVGA3D_TEX_FILTER_NONE, cMipLevels, (SVGA3dSize *)(pCmd + 1));
# ifdef DEBUG_GMR_ACCESS
VMR3ReqCallWait(PDMDevHlpGetVM(pThis->pDevInsR3), VMCPUID_ANY, (PFNRT)vmsvgaResetGMRHandlers, 1, pThis);
rc = vmsvga3dSurfaceDefine(pThis, pCmd->sid, pCmd->surfaceFlags, pCmd->format, pCmd->face, pCmd->multisampleCount, pCmd->autogenFilter, cMipLevels, (SVGA3dSize *)(pCmd + 1));
case SVGA_3D_CMD_SURFACE_COPY:
rc = vmsvga3dSurfaceStretchBlt(pThis, pCmd->dest, pCmd->boxDest, pCmd->src, pCmd->boxSrc, pCmd->mode);
case SVGA_3D_CMD_SURFACE_DMA:
rc = vmsvga3dSurfaceDMA(pThis, pCmd->guest, pCmd->host, pCmd->transfer, cCopyBoxes, (SVGA3dCopyBox *)(pCmd + 1));
rc = vmsvga3dSurfaceBlitToScreen(pThis, pCmd->destScreenId, pCmd->destRect, pCmd->srcImage, pCmd->srcRect, cRects, (SVGASignedRect *)(pCmd + 1));
case SVGA_3D_CMD_SETTRANSFORM:
case SVGA_3D_CMD_SETZRANGE:
case SVGA_3D_CMD_SETMATERIAL:
case SVGA_3D_CMD_SETLIGHTDATA:
case SVGA_3D_CMD_SETVIEWPORT:
case SVGA_3D_CMD_SETCLIPPLANE:
case SVGA_3D_CMD_CLEAR:
rc = vmsvga3dCommandClear(pThis, pCmd->cid, pCmd->clearFlag, pCmd->color, pCmd->depth, pCmd->stencil, cRects, (SVGA3dRect *)(pCmd + 1));
case SVGA_3D_CMD_PRESENT:
rc = vmsvga3dShaderDefine(pThis, pCmd->cid, pCmd->shid, pCmd->type, cbData, (uint32_t *)(pCmd + 1));
case SVGA_3D_CMD_SET_SHADER:
rc = vmsvga3dShaderSetConst(pThis, pCmd->cid, pCmd->reg, pCmd->type, pCmd->ctype, cRegisters, pCmd->values);
cVertexDivisor = (pHdr->size - sizeof(*pCmd) - sizeof(SVGA3dVertexDecl) * pCmd->numVertexDecls - sizeof(SVGA3dPrimitiveRange) * pCmd->numRanges);
SVGA3dVertexDivisor *pVertexDivisor = (cVertexDivisor) ? (SVGA3dVertexDivisor *)(&pNumRange[pCmd->numRanges]) : NULL;
rc = vmsvga3dDrawPrimitives(pThis, pCmd->cid, pCmd->numVertexDecls, pVertexDecl, pCmd->numRanges, pNumRange, cVertexDivisor, pVertexDivisor);
case SVGA_3D_CMD_BEGIN_QUERY:
case SVGA_3D_CMD_END_QUERY:
AssertFailed();
if (fDone)
Log(("vmsvgaFIFOLoop: emptied the FIFO next=%x stop=%x\n", pFIFO[SVGA_FIFO_NEXT_CMD], offCurrentCmd));
return VINF_SUCCESS;
# ifdef DEBUG_GMR_ACCESS
VMR3ReqCallWait(PDMDevHlpGetVM(pThis->pDevInsR3), VMCPUID_ANY, (PFNRT)vmsvgaUnregisterGMR, 2, pThis->pDevInsR3, idGMR);
int vmsvgaGMRTransfer(PVGASTATE pThis, const SVGA3dTransferType enmTransferType, uint8_t *pbDst, int32_t cbDestPitch,
int rc;
unsigned offDesc = 0;
Log(("vmsvgaGMRTransfer: gmr=%x offset=%x pitch=%d cbWidth=%d cHeight=%d; src offset=%d src pitch=%d\n",
return VINF_SUCCESS;
pDesc++;
while (cbCurrentWidth)
LogFlow(("vmsvgaGMRTransfer: %s phys=%RGp\n", (enmTransferType == SVGA3D_WRITE_HOST_VRAM) ? "READ" : "WRITE", pDesc->GCPhys + offCurrent - offDesc));
rc = PDMDevHlpPhysRead(pThis->CTX_SUFF(pDevIns), pDesc->GCPhys + offCurrent - offDesc, pCurrentDest, cbToCopy);
rc = PDMDevHlpPhysWrite(pThis->CTX_SUFF(pDevIns), pDesc->GCPhys + offCurrent - offDesc, pCurrentDest, cbToCopy);
if (cbCurrentWidth)
pDesc++;
return VINF_SUCCESS;
&& !fTraces)
Log(("vmsvgaSetTraces: *not* allowed to disable dirty page tracking when the device is in legacy mode.\n"));
Log(("vmsvgaSetTraces: enable frame buffer dirty page tracking. (%x bytes; vram %x)\n", cbFrameBuffer, pThis->vram_size));
DECLCALLBACK(int) vmsvgaR3IORegionMap(PPCIDEVICE pPciDev, int iRegion, RTGCPHYS GCPhysAddress, uint32_t cb, PCIADDRESSSPACE enmType)
int rc;
Log(("vgasvgaR3IORegionMap: iRegion=%d GCPhysAddress=%RGp cb=%#x enmType=%d\n", iRegion, GCPhysAddress, cb, enmType));
return rc;
return rc;
return rc;
# ifdef DEBUG_FIFO_ACCESS
# ifdef DEBUG_FIFO_ACCESS
return VINF_SUCCESS;
int rc;
pGMR->paDesc = (PVMSVGAGMRDESCRIPTOR)RTMemAllocZ((pGMR->cMaxPages) ? pGMR->cMaxPages : (pGMR->cbTotal >> PAGE_SHIFT) * sizeof(VMSVGAGMRDESCRIPTOR));
rc = SSMR3GetStructEx(pSSM, &pGMR->paDesc[j], sizeof(pGMR->paDesc[j]), 0, g_aVMSVGAGMRDESCRIPTORFields, NULL);
# ifdef VBOX_WITH_VMSVGA3D
return VINF_SUCCESS;
int rc;
return VINF_SUCCESS;
int rc;
rc = SSMR3PutStructEx(pSSM, &pSVGAState->aGMR[i], sizeof(pSVGAState->aGMR[i]), 0, g_aGMRFields, NULL);
rc = SSMR3PutStructEx(pSSM, &pSVGAState->aGMR[i].paDesc[j], sizeof(pSVGAState->aGMR[i].paDesc[j]), 0, g_aVMSVGAGMRDESCRIPTORFields, NULL);
# ifdef VBOX_WITH_VMSVGA3D
return VINF_SUCCESS;
if (!pSVGAState)
return VINF_SUCCESS;
pThis->svga.u32RegCaps = SVGA_CAP_GMR | SVGA_CAP_GMR2 | SVGA_CAP_CURSOR | SVGA_CAP_CURSOR_BYPASS_2 | SVGA_CAP_EXTENDED_FIFO | SVGA_CAP_IRQMASK | SVGA_CAP_PITCHLOCK | SVGA_CAP_TRACES | SVGA_CAP_SCREEN_OBJECT_2 | SVGA_CAP_ALPHA_CURSOR;
# ifdef VBOX_WITH_VMSVGA3D
pThis->svga.pFIFOR3[SVGA_FIFO_CAPABILITIES] = SVGA_FIFO_CAP_FENCE | SVGA_FIFO_CAP_CURSOR_BYPASS_3 | SVGA_FIFO_CAP_GMR2 | SVGA_FIFO_CAP_3D_HWVERSION_REVISED | SVGA_FIFO_CAP_SCREEN_OBJECT_2;
return rc;
int rc;
if (pSVGAState)
return VINF_SUCCESS;
int rc;
return rc;
return rc;
pThis->svga.u32RegCaps = SVGA_CAP_GMR | SVGA_CAP_GMR2 | SVGA_CAP_CURSOR | SVGA_CAP_CURSOR_BYPASS_2 | SVGA_CAP_EXTENDED_FIFO | SVGA_CAP_IRQMASK | SVGA_CAP_PITCHLOCK | SVGA_CAP_TRACES | SVGA_CAP_SCREEN_OBJECT_2 | SVGA_CAP_ALPHA_CURSOR;
# ifdef VBOX_WITH_VMSVGA3D
pThis->svga.pFIFOR3[SVGA_FIFO_CAPABILITIES] = SVGA_FIFO_CAP_FENCE | SVGA_FIFO_CAP_CURSOR_BYPASS_3 | SVGA_FIFO_CAP_GMR2 | SVGA_FIFO_CAP_3D_HWVERSION_REVISED | SVGA_FIFO_CAP_SCREEN_OBJECT_2;
pThis->svga.pFIFOR3[SVGA_FIFO_3D_HWVERSION] = pThis->svga.pFIFOR3[SVGA_FIFO_3D_HWVERSION_REVISED] = 0; /* no 3d available. */
# ifdef VBOX_WITH_VMSVGA3D
rc = PDMDevHlpThreadCreate(pDevIns, &pThis->svga.pFIFOIOThread, pThis, vmsvgaFIFOLoop, vmsvgaFIFOLoopWakeUp, 0,
AssertMsgFailed(("%s: Async IO Thread creation for FIFO handling failed rc=%d\n", __FUNCTION__, rc));
return rc;
STAM_REG(pVM, &pSVGAState->StatR3CmdPresent, STAMTYPE_PROFILE, "/Devices/VMSVGA/3d/Cmd/Present", STAMUNIT_TICKS_PER_CALL, "Profiling of Present.");
STAM_REG(pVM, &pSVGAState->StatR3CmdDrawPrimitive, STAMTYPE_PROFILE, "/Devices/VMSVGA/3d/Cmd/DrawPrimitive", STAMUNIT_TICKS_PER_CALL, "Profiling of DrawPrimitive.");
STAM_REG(pVM, &pSVGAState->StatR3CmdSurfaceDMA, STAMTYPE_PROFILE, "/Devices/VMSVGA/3d/Cmd/SurfaceDMA", STAMUNIT_TICKS_PER_CALL, "Profiling of SurfaceDMA.");
return VINF_SUCCESS;
int rc;
# ifdef VBOX_WITH_VMSVGA3D
for (unsigned i = 0; i < SVGA3D_DEVCAP_MAX; i++)
idxCap++;