c6ade8a5a12fad69394e7223b7ea170bd729f0f4vboxsync

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync#define LOG_GROUP LOG_GROUP_DEV_VMSVGA

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync#include <VBox/vmm/pdmdev.h>

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync#include <VBox/version.h>

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync#include <VBox/err.h>

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync#include <VBox/log.h>

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync#include <VBox/vmm/pgm.h>

cb39011e69667689c166f1cdf95247b46fff324dvboxsync#include <VBox/sup.h>

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync#include <iprt/assert.h>

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync#include <iprt/semaphore.h>

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync#include <iprt/uuid.h>

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync#ifdef IN_RING3

0802b726efeabba46f90cb2b285de4dadaac9507vboxsync# include <iprt/mem.h>

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync#endif

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync#include <VBox/VMMDev.h>

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync#include <VBox/VBoxVideo.h>

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync#include <VBox/bioslogo.h>

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync#include "DevVGA.h"

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync#ifdef DEBUG

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync#endif

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync#include "DevVGA-SVGA.h"

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync#include "vmsvga/svga_reg.h"

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync#include "vmsvga/svga_escape.h"

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync#include "vmsvga/svga_overlay.h"

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync#include "vmsvga/svga3d_reg.h"

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync#include "vmsvga/svga3d_caps.h"

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync#ifdef VBOX_WITH_VMSVGA3D

0802b726efeabba46f90cb2b285de4dadaac9507vboxsync# include "DevVGA-SVGA3d.h"

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync#endif

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync

2b114c590cf5a19f8047cd7bde9c7e5ae00aa22bvboxsynctypedef struct

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync{

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync RTGCPHYS GCPhys;

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync uint64_t numPages;

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync} VMSVGAGMRDESCRIPTOR, *PVMSVGAGMRDESCRIPTOR;

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsynctypedef struct

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync{

3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync uint32_t cMaxPages;

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync uint32_t cbTotal;

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync uint32_t numDescriptors;

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync PVMSVGAGMRDESCRIPTOR paDesc;

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync} GMR, *PGMR;

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsynctypedef struct

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync{

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync GMR aGMR[VMSVGA_MAX_GMR_IDS];

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync struct

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync {

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync SVGAGuestPtr ptr;

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync uint32_t bytesPerLine;

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync SVGAGMRImageFormat format;

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync } GMRFB;

2b114c590cf5a19f8047cd7bde9c7e5ae00aa22bvboxsync struct

3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync {

3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync bool fActive;

3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync uint32_t xHotspot;

3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync uint32_t yHotspot;

3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync uint32_t width;

3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync uint32_t height;

3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync uint32_t cbData;

3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync void *pData;

3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync } Cursor;

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync SVGAColorBGRX colorAnnotation;

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync STAMPROFILE StatR3CmdPresent;

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync STAMPROFILE StatR3CmdDrawPrimitive;

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync STAMPROFILE StatR3CmdSurfaceDMA;

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync} VMSVGASTATE, *PVMSVGASTATE;

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync#ifdef IN_RING3

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsyncstatic SSMFIELD const g_aVMSVGAGMRDESCRIPTORFields[] =

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync{

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync SSMFIELD_ENTRY_GCPHYS( VMSVGAGMRDESCRIPTOR, GCPhys),

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync SSMFIELD_ENTRY( VMSVGAGMRDESCRIPTOR, numPages),

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync SSMFIELD_ENTRY_TERM()

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync};

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsyncstatic SSMFIELD const g_aGMRFields[] =

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync{

3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync SSMFIELD_ENTRY( GMR, cMaxPages),

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync SSMFIELD_ENTRY( GMR, cbTotal),

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync SSMFIELD_ENTRY( GMR, numDescriptors),

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync SSMFIELD_ENTRY_IGN_HCPTR( GMR, paDesc),

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync SSMFIELD_ENTRY_TERM()

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync};

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsyncstatic SSMFIELD const g_aVMSVGASTATEFields[] =

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync{

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync SSMFIELD_ENTRY_IGNORE( VMSVGASTATE, aGMR),

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync SSMFIELD_ENTRY( VMSVGASTATE, GMRFB),

3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync SSMFIELD_ENTRY( VMSVGASTATE, Cursor.fActive),

3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync SSMFIELD_ENTRY( VMSVGASTATE, Cursor.xHotspot),

3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync SSMFIELD_ENTRY( VMSVGASTATE, Cursor.yHotspot),

3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync SSMFIELD_ENTRY( VMSVGASTATE, Cursor.width),

3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync SSMFIELD_ENTRY( VMSVGASTATE, Cursor.height),

3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync SSMFIELD_ENTRY( VMSVGASTATE, Cursor.cbData),

3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync SSMFIELD_ENTRY_IGN_HCPTR( VMSVGASTATE, Cursor.pData),

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync SSMFIELD_ENTRY( VMSVGASTATE, colorAnnotation),

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync SSMFIELD_ENTRY_IGNORE( VMSVGASTATE, StatR3CmdPresent),

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync SSMFIELD_ENTRY_IGNORE( VMSVGASTATE, StatR3CmdDrawPrimitive),

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync SSMFIELD_ENTRY_IGNORE( VMSVGASTATE, StatR3CmdSurfaceDMA),

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync SSMFIELD_ENTRY_TERM()

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync};

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsyncstatic SSMFIELD const g_aVGAStateSVGAFields[] =

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync{

3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync SSMFIELD_ENTRY_IGNORE( VMSVGAState, u64HostWindowId),

3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync SSMFIELD_ENTRY_IGN_HCPTR( VMSVGAState, pFIFOR3),

3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync SSMFIELD_ENTRY_IGN_HCPTR( VMSVGAState, pFIFOR0),

3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync SSMFIELD_ENTRY_IGN_HCPTR( VMSVGAState, pSVGAState),

3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync SSMFIELD_ENTRY_IGN_HCPTR( VMSVGAState, p3dState),

3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync SSMFIELD_ENTRY_IGN_HCPTR( VMSVGAState, pFrameBufferBackup),

2b114c590cf5a19f8047cd7bde9c7e5ae00aa22bvboxsync SSMFIELD_ENTRY_IGN_HCPTR( VMSVGAState, pFIFOExtCmdParam),

3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync SSMFIELD_ENTRY_IGN_GCPHYS( VMSVGAState, GCPhysFIFO),

3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync SSMFIELD_ENTRY_IGNORE( VMSVGAState, cbFIFO),

3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync SSMFIELD_ENTRY( VMSVGAState, u32SVGAId),

3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync SSMFIELD_ENTRY( VMSVGAState, fEnabled),

3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync SSMFIELD_ENTRY( VMSVGAState, fConfigured),

3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync SSMFIELD_ENTRY( VMSVGAState, fBusy),

3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync SSMFIELD_ENTRY( VMSVGAState, fTraces),

3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync SSMFIELD_ENTRY( VMSVGAState, u32GuestId),

3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync SSMFIELD_ENTRY( VMSVGAState, cScratchRegion),

3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync SSMFIELD_ENTRY( VMSVGAState, au32ScratchRegion),

3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync SSMFIELD_ENTRY( VMSVGAState, u32IrqStatus),

3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync SSMFIELD_ENTRY( VMSVGAState, u32IrqMask),

3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync SSMFIELD_ENTRY( VMSVGAState, u32PitchLock),

3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync SSMFIELD_ENTRY( VMSVGAState, u32CurrentGMRId),

3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync SSMFIELD_ENTRY( VMSVGAState, u32RegCaps),

3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync SSMFIELD_ENTRY_IGNORE( VMSVGAState, BasePort),

3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync SSMFIELD_ENTRY( VMSVGAState, u32IndexReg),

cb39011e69667689c166f1cdf95247b46fff324dvboxsync SSMFIELD_ENTRY_IGNORE( VMSVGAState, pSupDrvSession),

3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync SSMFIELD_ENTRY_IGNORE( VMSVGAState, FIFORequestSem),

3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync SSMFIELD_ENTRY_IGNORE( VMSVGAState, FIFOExtCmdSem),

3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync SSMFIELD_ENTRY_IGN_HCPTR( VMSVGAState, pFIFOIOThread),

3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync SSMFIELD_ENTRY( VMSVGAState, uWidth),

3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync SSMFIELD_ENTRY( VMSVGAState, uHeight),

3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync SSMFIELD_ENTRY( VMSVGAState, uBpp),

3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync SSMFIELD_ENTRY( VMSVGAState, cbScanline),

3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync SSMFIELD_ENTRY( VMSVGAState, u32MaxWidth),

3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync SSMFIELD_ENTRY( VMSVGAState, u32MaxHeight),

3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync SSMFIELD_ENTRY( VMSVGAState, u32ActionFlags),

3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync SSMFIELD_ENTRY( VMSVGAState, f3DEnabled),

3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync SSMFIELD_ENTRY( VMSVGAState, fVRAMTracking),

3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync SSMFIELD_ENTRY_IGNORE( VMSVGAState, u8FIFOExtCommand),

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync SSMFIELD_ENTRY_TERM()

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync};

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsyncstatic void vmsvgaSetTraces(PVGASTATE pThis, bool fTraces);

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync

0802b726efeabba46f90cb2b285de4dadaac9507vboxsync#endif /* IN_RING3 */

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync#ifdef LOG_ENABLED

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsyncstatic const char *vmsvgaIndexToString(PVGASTATE pThis)

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync{

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync switch (pThis->svga.u32IndexReg)

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync {

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync case SVGA_REG_ID:

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync return "SVGA_REG_ID";

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync case SVGA_REG_ENABLE:

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync return "SVGA_REG_ENABLE";

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync case SVGA_REG_WIDTH:

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync return "SVGA_REG_WIDTH";

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync case SVGA_REG_HEIGHT:

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync return "SVGA_REG_HEIGHT";

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync case SVGA_REG_MAX_WIDTH:

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync return "SVGA_REG_MAX_WIDTH";

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync case SVGA_REG_MAX_HEIGHT:

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync return "SVGA_REG_MAX_HEIGHT";

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync case SVGA_REG_DEPTH:

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync return "SVGA_REG_DEPTH";

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync case SVGA_REG_BITS_PER_PIXEL: /* Current bpp in the guest */

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync return "SVGA_REG_BITS_PER_PIXEL";

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync case SVGA_REG_HOST_BITS_PER_PIXEL: /* (Deprecated) */

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync return "SVGA_REG_HOST_BITS_PER_PIXEL";

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync case SVGA_REG_PSEUDOCOLOR:

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync return "SVGA_REG_PSEUDOCOLOR";

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync case SVGA_REG_RED_MASK:

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync return "SVGA_REG_RED_MASK";

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync case SVGA_REG_GREEN_MASK:

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync return "SVGA_REG_GREEN_MASK";

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync case SVGA_REG_BLUE_MASK:

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync return "SVGA_REG_BLUE_MASK";

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync case SVGA_REG_BYTES_PER_LINE:

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync return "SVGA_REG_BYTES_PER_LINE";

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync case SVGA_REG_VRAM_SIZE: /* VRAM size */

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync return "SVGA_REG_VRAM_SIZE";

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync case SVGA_REG_FB_START: /* Frame buffer physical address. */

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync return "SVGA_REG_FB_START";

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync case SVGA_REG_FB_OFFSET: /* Offset of the frame buffer in VRAM */

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync return "SVGA_REG_FB_OFFSET";

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync case SVGA_REG_FB_SIZE: /* Frame buffer size */

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync return "SVGA_REG_FB_SIZE";

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync case SVGA_REG_CAPABILITIES:

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync return "SVGA_REG_CAPABILITIES";

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync case SVGA_REG_MEM_START: /* FIFO start */

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync return "SVGA_REG_MEM_START";

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync case SVGA_REG_MEM_SIZE: /* FIFO size */

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync return "SVGA_REG_MEM_SIZE";

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync case SVGA_REG_CONFIG_DONE: /* Set when memory area configured */

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync return "SVGA_REG_CONFIG_DONE";

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync case SVGA_REG_SYNC: /* See "FIFO Synchronization Registers" */

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync return "SVGA_REG_SYNC";

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync case SVGA_REG_BUSY: /* See "FIFO Synchronization Registers" */

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync return "SVGA_REG_BUSY";

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync case SVGA_REG_GUEST_ID: /* Set guest OS identifier */

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync return "SVGA_REG_GUEST_ID";

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync case SVGA_REG_SCRATCH_SIZE: /* Number of scratch registers */

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync return "SVGA_REG_SCRATCH_SIZE";

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync case SVGA_REG_MEM_REGS: /* Number of FIFO registers */

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync return "SVGA_REG_MEM_REGS";

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync case SVGA_REG_PITCHLOCK: /* Fixed pitch for all modes */

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync return "SVGA_REG_PITCHLOCK";

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync case SVGA_REG_IRQMASK: /* Interrupt mask */

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync return "SVGA_REG_IRQMASK";

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync case SVGA_REG_GMR_ID:

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync return "SVGA_REG_GMR_ID";

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync case SVGA_REG_GMR_DESCRIPTOR:

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync return "SVGA_REG_GMR_DESCRIPTOR";

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync case SVGA_REG_GMR_MAX_IDS:

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync return "SVGA_REG_GMR_MAX_IDS";

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync case SVGA_REG_GMR_MAX_DESCRIPTOR_LENGTH:

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync return "SVGA_REG_GMR_MAX_DESCRIPTOR_LENGTH";

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync case SVGA_REG_TRACES: /* Enable trace-based updates even when FIFO is on */

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync return "SVGA_REG_TRACES";

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync case SVGA_REG_GMRS_MAX_PAGES: /* Maximum number of 4KB pages for all GMRs */

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync return "SVGA_REG_GMRS_MAX_PAGES";

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync case SVGA_REG_MEMORY_SIZE: /* Total dedicated device memory excluding FIFO */

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync return "SVGA_REG_MEMORY_SIZE";

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync case SVGA_REG_TOP: /* Must be 1 more than the last register */

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync return "SVGA_REG_TOP";

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync case SVGA_PALETTE_BASE: /* Base of SVGA color map */

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync return "SVGA_PALETTE_BASE";

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync case SVGA_REG_CURSOR_ID:

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync return "SVGA_REG_CURSOR_ID";

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync case SVGA_REG_CURSOR_X:

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync return "SVGA_REG_CURSOR_X";

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync case SVGA_REG_CURSOR_Y:

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync return "SVGA_REG_CURSOR_Y";

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync case SVGA_REG_CURSOR_ON:

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync return "SVGA_REG_CURSOR_ON";

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync case SVGA_REG_NUM_GUEST_DISPLAYS:/* Number of guest displays in X/Y direction */

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync return "SVGA_REG_NUM_GUEST_DISPLAYS";

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync case SVGA_REG_DISPLAY_ID: /* Display ID for the following display attributes */

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync return "SVGA_REG_DISPLAY_ID";

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync case SVGA_REG_DISPLAY_IS_PRIMARY:/* Whether this is a primary display */

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync return "SVGA_REG_DISPLAY_IS_PRIMARY";

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync case SVGA_REG_DISPLAY_POSITION_X:/* The display position x */

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync return "SVGA_REG_DISPLAY_POSITION_X";

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync case SVGA_REG_DISPLAY_POSITION_Y:/* The display position y */

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync return "SVGA_REG_DISPLAY_POSITION_Y";

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync case SVGA_REG_DISPLAY_WIDTH: /* The display's width */

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync return "SVGA_REG_DISPLAY_WIDTH";

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync case SVGA_REG_DISPLAY_HEIGHT: /* The display's height */

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync return "SVGA_REG_DISPLAY_HEIGHT";

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync case SVGA_REG_NUM_DISPLAYS: /* (Deprecated) */

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync return "SVGA_REG_NUM_DISPLAYS";

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync default:

de8636fc8bdeb02161ee5b329c407dd0c48b0885vboxsync if (pThis->svga.u32IndexReg - (uint32_t)SVGA_SCRATCH_BASE < pThis->svga.cScratchRegion)

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync return "SVGA_SCRATCH_BASE reg";

de8636fc8bdeb02161ee5b329c407dd0c48b0885vboxsync if (pThis->svga.u32IndexReg - (uint32_t)SVGA_PALETTE_BASE < (uint32_t)SVGA_NUM_PALETTE_REGS)

de8636fc8bdeb02161ee5b329c407dd0c48b0885vboxsync return "SVGA_PALETTE_BASE reg";

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync return "UNKNOWN";

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync }

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync}

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsyncstatic const char *vmsvgaFIFOCmdToString(uint32_t u32Cmd)

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync{

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync switch (u32Cmd)

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync {

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync case SVGA_CMD_INVALID_CMD:

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync return "SVGA_CMD_INVALID_CMD";

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync case SVGA_CMD_UPDATE:

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync return "SVGA_CMD_UPDATE";

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync case SVGA_CMD_RECT_COPY:

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync return "SVGA_CMD_RECT_COPY";

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync case SVGA_CMD_DEFINE_CURSOR:

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync return "SVGA_CMD_DEFINE_CURSOR";

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync case SVGA_CMD_DEFINE_ALPHA_CURSOR:

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync return "SVGA_CMD_DEFINE_ALPHA_CURSOR";

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync case SVGA_CMD_UPDATE_VERBOSE:

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync return "SVGA_CMD_UPDATE_VERBOSE";

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync case SVGA_CMD_FRONT_ROP_FILL:

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync return "SVGA_CMD_FRONT_ROP_FILL";

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync case SVGA_CMD_FENCE:

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync return "SVGA_CMD_FENCE";

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync case SVGA_CMD_ESCAPE:

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync return "SVGA_CMD_ESCAPE";

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync case SVGA_CMD_DEFINE_SCREEN:

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync return "SVGA_CMD_DEFINE_SCREEN";

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync case SVGA_CMD_DESTROY_SCREEN:

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync return "SVGA_CMD_DESTROY_SCREEN";

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync case SVGA_CMD_DEFINE_GMRFB:

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync return "SVGA_CMD_DEFINE_GMRFB";

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync case SVGA_CMD_BLIT_GMRFB_TO_SCREEN:

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync return "SVGA_CMD_BLIT_GMRFB_TO_SCREEN";

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync case SVGA_CMD_BLIT_SCREEN_TO_GMRFB:

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync return "SVGA_CMD_BLIT_SCREEN_TO_GMRFB";

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync case SVGA_CMD_ANNOTATION_FILL:

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync return "SVGA_CMD_ANNOTATION_FILL";

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync case SVGA_CMD_ANNOTATION_COPY:

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync return "SVGA_CMD_ANNOTATION_COPY";

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync case SVGA_CMD_DEFINE_GMR2:

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync return "SVGA_CMD_DEFINE_GMR2";

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync case SVGA_CMD_REMAP_GMR2:

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync return "SVGA_CMD_REMAP_GMR2";

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync case SVGA_3D_CMD_SURFACE_DEFINE:

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync return "SVGA_3D_CMD_SURFACE_DEFINE";

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync case SVGA_3D_CMD_SURFACE_DESTROY:

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync return "SVGA_3D_CMD_SURFACE_DESTROY";

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync case SVGA_3D_CMD_SURFACE_COPY:

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync return "SVGA_3D_CMD_SURFACE_COPY";

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync case SVGA_3D_CMD_SURFACE_STRETCHBLT:

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync return "SVGA_3D_CMD_SURFACE_STRETCHBLT";

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync case SVGA_3D_CMD_SURFACE_DMA:

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync return "SVGA_3D_CMD_SURFACE_DMA";

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync case SVGA_3D_CMD_CONTEXT_DEFINE:

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync return "SVGA_3D_CMD_CONTEXT_DEFINE";

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync case SVGA_3D_CMD_CONTEXT_DESTROY:

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync return "SVGA_3D_CMD_CONTEXT_DESTROY";

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync case SVGA_3D_CMD_SETTRANSFORM:

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync return "SVGA_3D_CMD_SETTRANSFORM";

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync case SVGA_3D_CMD_SETZRANGE:

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync return "SVGA_3D_CMD_SETZRANGE";

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync case SVGA_3D_CMD_SETRENDERSTATE:

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync return "SVGA_3D_CMD_SETRENDERSTATE";

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync case SVGA_3D_CMD_SETRENDERTARGET:

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync return "SVGA_3D_CMD_SETRENDERTARGET";

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync case SVGA_3D_CMD_SETTEXTURESTATE:

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync return "SVGA_3D_CMD_SETTEXTURESTATE";

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync case SVGA_3D_CMD_SETMATERIAL:

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync return "SVGA_3D_CMD_SETMATERIAL";

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync case SVGA_3D_CMD_SETLIGHTDATA:

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync return "SVGA_3D_CMD_SETLIGHTDATA";

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync case SVGA_3D_CMD_SETLIGHTENABLED:

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync return "SVGA_3D_CMD_SETLIGHTENABLED";

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync case SVGA_3D_CMD_SETVIEWPORT:

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync return "SVGA_3D_CMD_SETVIEWPORT";

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync case SVGA_3D_CMD_SETCLIPPLANE:

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync return "SVGA_3D_CMD_SETCLIPPLANE";

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync case SVGA_3D_CMD_CLEAR:

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync return "SVGA_3D_CMD_CLEAR";

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync case SVGA_3D_CMD_PRESENT:

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync return "SVGA_3D_CMD_PRESENT";

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync case SVGA_3D_CMD_SHADER_DEFINE:

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync return "SVGA_3D_CMD_SHADER_DEFINE";

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync case SVGA_3D_CMD_SHADER_DESTROY:

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync return "SVGA_3D_CMD_SHADER_DESTROY";

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync case SVGA_3D_CMD_SET_SHADER:

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync return "SVGA_3D_CMD_SET_SHADER";

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync case SVGA_3D_CMD_SET_SHADER_CONST:

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync return "SVGA_3D_CMD_SET_SHADER_CONST";

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync case SVGA_3D_CMD_DRAW_PRIMITIVES:

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync return "SVGA_3D_CMD_DRAW_PRIMITIVES";

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync case SVGA_3D_CMD_SETSCISSORRECT:

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync return "SVGA_3D_CMD_SETSCISSORRECT";

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync case SVGA_3D_CMD_BEGIN_QUERY:

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync return "SVGA_3D_CMD_BEGIN_QUERY";

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync case SVGA_3D_CMD_END_QUERY:

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync return "SVGA_3D_CMD_END_QUERY";

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync case SVGA_3D_CMD_WAIT_FOR_QUERY:

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync return "SVGA_3D_CMD_WAIT_FOR_QUERY";

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync case SVGA_3D_CMD_PRESENT_READBACK:

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync return "SVGA_3D_CMD_PRESENT_READBACK";

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync case SVGA_3D_CMD_BLIT_SURFACE_TO_SCREEN:

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync return "SVGA_3D_CMD_BLIT_SURFACE_TO_SCREEN";

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync case SVGA_3D_CMD_SURFACE_DEFINE_V2:

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync return "SVGA_3D_CMD_SURFACE_DEFINE_V2";

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync case SVGA_3D_CMD_GENERATE_MIPMAPS:

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync return "SVGA_3D_CMD_GENERATE_MIPMAPS";

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync case SVGA_3D_CMD_ACTIVATE_SURFACE:

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync return "SVGA_3D_CMD_ACTIVATE_SURFACE";

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync case SVGA_3D_CMD_DEACTIVATE_SURFACE:

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync return "SVGA_3D_CMD_DEACTIVATE_SURFACE";

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync default:

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync return "UNKNOWN";

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync }

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync}

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync#endif

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync

3194da424708abdd288b28d96892b3a5f3f7df0bvboxsyncDECLCALLBACK(void) vmsvgaPortSetViewPort(PPDMIDISPLAYPORT pInterface, uint32_t uScreenId, uint32_t x, uint32_t y, uint32_t cx, uint32_t cy)

3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync{

8f8e1c3bab8eabbad1cddcd165f3e30cc2011a33vboxsync PVGASTATE pThis = RT_FROM_MEMBER(pInterface, VGASTATE, IPort);

3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync

3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync Log(("vmsvgaPortSetViewPort: screen %d (%d,%d)(%d,%d)\n", uScreenId, x, y, cx, cy));

3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync

3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync pThis->svga.viewport.x = x;

3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync pThis->svga.viewport.y = y;

3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync pThis->svga.viewport.cx = RT_MIN(cx, (uint32_t)pThis->svga.uWidth);

3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync pThis->svga.viewport.cy = RT_MIN(cy, (uint32_t)pThis->svga.uHeight);

3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync return;

3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync}

3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsyncPDMBOTHCBDECL(int) vmsvgaReadPort(PVGASTATE pThis, uint32_t *pu32)

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync{

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync int rc = VINF_SUCCESS;

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync *pu32 = 0;

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync switch (pThis->svga.u32IndexReg)

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync {

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync case SVGA_REG_ID:

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync *pu32 = pThis->svga.u32SVGAId;

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync break;

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync case SVGA_REG_ENABLE:

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync *pu32 = pThis->svga.fEnabled;

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync break;

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync case SVGA_REG_WIDTH:

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync {

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync if ( pThis->svga.fEnabled

3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync && pThis->svga.uWidth != VMSVGA_VAL_UNINITIALIZED)

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync {

3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync *pu32 = pThis->svga.uWidth;

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync }

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync else

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync {

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync#ifndef IN_RING3

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync rc = VINF_IOM_R3_IOPORT_READ;

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync#else

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync *pu32 = pThis->pDrv->cx;

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync#endif

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync }

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync break;

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync }

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync case SVGA_REG_HEIGHT:

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync {

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync if ( pThis->svga.fEnabled

3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync && pThis->svga.uHeight != VMSVGA_VAL_UNINITIALIZED)

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync {

3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync *pu32 = pThis->svga.uHeight;

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync }

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync else

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync {

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync#ifndef IN_RING3

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync rc = VINF_IOM_R3_IOPORT_READ;

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync#else

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync *pu32 = pThis->pDrv->cy;

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync#endif

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync }

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync break;

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync }

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync case SVGA_REG_MAX_WIDTH:

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync *pu32 = pThis->svga.u32MaxWidth;

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync break;

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync case SVGA_REG_MAX_HEIGHT:

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync *pu32 = pThis->svga.u32MaxHeight;

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync break;

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync case SVGA_REG_DEPTH:

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync /* This returns the color depth of the current mode. */

3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync switch (pThis->svga.uBpp)

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync {

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync case 15:

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync case 16:

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync case 24:

3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync *pu32 = pThis->svga.uBpp;

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync break;

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync default:

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync case 32:

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync *pu32 = 24; /* The upper 8 bits are either alpha bits or not used. */

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync break;

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync }

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync break;

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync case SVGA_REG_HOST_BITS_PER_PIXEL: /* (Deprecated) */

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync if ( pThis->svga.fEnabled

3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync && pThis->svga.uBpp != VMSVGA_VAL_UNINITIALIZED)

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync {

3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync *pu32 = pThis->svga.uBpp;

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync }

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync else

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync {

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync#ifndef IN_RING3

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync rc = VINF_IOM_R3_IOPORT_READ;

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync#else

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync *pu32 = pThis->pDrv->cBits;

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync#endif

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync }

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync break;

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync case SVGA_REG_BITS_PER_PIXEL: /* Current bpp in the guest */

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync if ( pThis->svga.fEnabled

3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync && pThis->svga.uBpp != VMSVGA_VAL_UNINITIALIZED)

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync {

3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync *pu32 = (pThis->svga.uBpp + 7) & ~7;

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync }

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync else

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync {

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync#ifndef IN_RING3

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync rc = VINF_IOM_R3_IOPORT_READ;

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync#else

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync *pu32 = (pThis->pDrv->cBits + 7) & ~7;

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync#endif

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync }

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync break;

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync case SVGA_REG_PSEUDOCOLOR:

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync *pu32 = 0;

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync break;

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync case SVGA_REG_RED_MASK:

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync case SVGA_REG_GREEN_MASK:

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync case SVGA_REG_BLUE_MASK:

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync {

3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync uint32_t uBpp;

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync if ( pThis->svga.fEnabled

3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync && pThis->svga.uBpp != VMSVGA_VAL_UNINITIALIZED)

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync {

3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync uBpp = pThis->svga.uBpp;

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync }

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync else

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync {

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync#ifndef IN_RING3

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync rc = VINF_IOM_R3_IOPORT_READ;

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync break;

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync#else

3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync uBpp = pThis->pDrv->cBits;

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync#endif

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync }

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync uint32_t u32RedMask, u32GreenMask, u32BlueMask;

3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync switch (uBpp)

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync {

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync case 8:

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync u32RedMask = 0x07;

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync u32GreenMask = 0x38;

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync u32BlueMask = 0xc0;

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync break;

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync case 15:

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync u32RedMask = 0x0000001f;

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync u32GreenMask = 0x000003e0;

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync u32BlueMask = 0x00007c00;

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync break;

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync case 16:

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync u32RedMask = 0x0000001f;

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync u32GreenMask = 0x000007e0;

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync u32BlueMask = 0x0000f800;

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync break;

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync case 24:

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync case 32:

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync default:

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync u32RedMask = 0x00ff0000;

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync u32GreenMask = 0x0000ff00;

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync u32BlueMask = 0x000000ff;

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync break;

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync }

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync switch (pThis->svga.u32IndexReg)

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync {

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync case SVGA_REG_RED_MASK:

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync *pu32 = u32RedMask;

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync break;

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync case SVGA_REG_GREEN_MASK:

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync *pu32 = u32GreenMask;

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync break;

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync case SVGA_REG_BLUE_MASK:

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync *pu32 = u32BlueMask;

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync break;

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync }

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync break;

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync }

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync case SVGA_REG_BYTES_PER_LINE:

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync {

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync if ( pThis->svga.fEnabled

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync && pThis->svga.cbScanline)

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync {

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync *pu32 = pThis->svga.cbScanline;

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync }

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync else

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync {

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync#ifndef IN_RING3

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync rc = VINF_IOM_R3_IOPORT_READ;

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync#else

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync *pu32 = pThis->pDrv->cbScanline;

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync#endif

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync }

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync break;

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync }

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync case SVGA_REG_VRAM_SIZE: /* VRAM size */

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync *pu32 = pThis->vram_size;

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync break;

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync case SVGA_REG_FB_START: /* Frame buffer physical address. */

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync Assert(pThis->GCPhysVRAM <= 0xffffffff);

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync *pu32 = pThis->GCPhysVRAM;

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync break;

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync case SVGA_REG_FB_OFFSET: /* Offset of the frame buffer in VRAM */

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync /* Always zero in our case. */

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync *pu32 = 0;

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync break;

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync case SVGA_REG_FB_SIZE: /* Frame buffer size */

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync {

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync#ifndef IN_RING3

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync rc = VINF_IOM_R3_IOPORT_READ;

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync#else

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync /* VMWare testcases want at least 4 MB in case the hardware is disabled. */

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync if ( pThis->svga.fEnabled

3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync && pThis->svga.uHeight != VMSVGA_VAL_UNINITIALIZED)

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync {

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync /* Hardware enabled; return real framebuffer size .*/

3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync *pu32 = (uint32_t)pThis->svga.uHeight * pThis->svga.cbScanline;

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync }

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync else

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync *pu32 = RT_MAX(0x100000, (uint32_t)pThis->pDrv->cy * pThis->pDrv->cbScanline);

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync *pu32 = RT_MIN(pThis->vram_size, *pu32);

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync Log(("h=%d w=%d bpp=%d\n", pThis->pDrv->cy, pThis->pDrv->cx, pThis->pDrv->cBits));

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync#endif

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync break;

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync }

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync case SVGA_REG_CAPABILITIES:

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync *pu32 = pThis->svga.u32RegCaps;

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync break;

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync case SVGA_REG_MEM_START: /* FIFO start */

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync Assert(pThis->svga.GCPhysFIFO <= 0xffffffff);

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync *pu32 = pThis->svga.GCPhysFIFO;

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync break;

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync case SVGA_REG_MEM_SIZE: /* FIFO size */

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync *pu32 = pThis->svga.cbFIFO;

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync break;

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync case SVGA_REG_CONFIG_DONE: /* Set when memory area configured */

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync *pu32 = pThis->svga.fConfigured;

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync break;

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync case SVGA_REG_SYNC: /* See "FIFO Synchronization Registers" */

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync *pu32 = 0;

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync break;

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync case SVGA_REG_BUSY: /* See "FIFO Synchronization Registers" */

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync if (pThis->svga.fBusy)

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync {

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync#ifndef IN_RING3

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync rc = VINF_IOM_R3_IOPORT_READ;

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync break;

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync#else

0802b726efeabba46f90cb2b285de4dadaac9507vboxsync /** @todo bit crude */

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync RTThreadSleep(50);

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync#endif

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync }

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync *pu32 = pThis->svga.fBusy;

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync break;

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync case SVGA_REG_GUEST_ID: /* Set guest OS identifier */

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync *pu32 = pThis->svga.u32GuestId;

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync break;

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync case SVGA_REG_SCRATCH_SIZE: /* Number of scratch registers */

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync *pu32 = pThis->svga.cScratchRegion;

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync break;

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync case SVGA_REG_MEM_REGS: /* Number of FIFO registers */

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync *pu32 = SVGA_FIFO_NUM_REGS;

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync break;

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync case SVGA_REG_PITCHLOCK: /* Fixed pitch for all modes */

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync *pu32 = pThis->svga.u32PitchLock;

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync break;

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync case SVGA_REG_IRQMASK: /* Interrupt mask */

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync *pu32 = pThis->svga.u32IrqMask;

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync break;

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync /* See "Guest memory regions" below. */

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync case SVGA_REG_GMR_ID:

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync *pu32 = pThis->svga.u32CurrentGMRId;

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync break;

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync case SVGA_REG_GMR_DESCRIPTOR:

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync /* Write only */

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync *pu32 = 0;

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync break;

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync case SVGA_REG_GMR_MAX_IDS:

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync *pu32 = VMSVGA_MAX_GMR_IDS;

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync break;

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync case SVGA_REG_GMR_MAX_DESCRIPTOR_LENGTH:

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync *pu32 = VMSVGA_MAX_GMR_PAGES;

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync break;

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync case SVGA_REG_TRACES: /* Enable trace-based updates even when FIFO is on */

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync *pu32 = pThis->svga.fTraces;

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync break;

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync case SVGA_REG_GMRS_MAX_PAGES: /* Maximum number of 4KB pages for all GMRs */

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync *pu32 = VMSVGA_MAX_GMR_PAGES;

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync break;

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync case SVGA_REG_MEMORY_SIZE: /* Total dedicated device memory excluding FIFO */

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync *pu32 = VMSVGA_SURFACE_SIZE;

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync break;

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync case SVGA_REG_TOP: /* Must be 1 more than the last register */

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync break;

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync case SVGA_PALETTE_BASE: /* Base of SVGA color map */

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync break;

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync /* Next 768 (== 256*3) registers exist for colormap */

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync /* Mouse cursor support. */

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync case SVGA_REG_CURSOR_ID:

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync case SVGA_REG_CURSOR_X:

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync case SVGA_REG_CURSOR_Y:

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync case SVGA_REG_CURSOR_ON:

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync break;

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync /* Legacy multi-monitor support */

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync case SVGA_REG_NUM_GUEST_DISPLAYS:/* Number of guest displays in X/Y direction */

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync *pu32 = 1;

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync break;

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync case SVGA_REG_DISPLAY_ID: /* Display ID for the following display attributes */

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync case SVGA_REG_DISPLAY_IS_PRIMARY:/* Whether this is a primary display */

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync case SVGA_REG_DISPLAY_POSITION_X:/* The display position x */

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync case SVGA_REG_DISPLAY_POSITION_Y:/* The display position y */

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync *pu32 = 0;

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync break;

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync case SVGA_REG_DISPLAY_WIDTH: /* The display's width */

3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync *pu32 = pThis->svga.uWidth;

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync break;

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync case SVGA_REG_DISPLAY_HEIGHT: /* The display's height */

3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync *pu32 = pThis->svga.uHeight;

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync break;

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync case SVGA_REG_NUM_DISPLAYS: /* (Deprecated) */

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync *pu32 = 1; /* Must return something sensible here otherwise the Linux driver will take a legacy code path without 3d support. */

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync break;

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync default:

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync if ( pThis->svga.u32IndexReg >= SVGA_SCRATCH_BASE

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync && pThis->svga.u32IndexReg < SVGA_SCRATCH_BASE + pThis->svga.cScratchRegion)

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync {

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync *pu32 = pThis->svga.au32ScratchRegion[pThis->svga.u32IndexReg - SVGA_SCRATCH_BASE];

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync }

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync break;

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync }

0802b726efeabba46f90cb2b285de4dadaac9507vboxsync Log(("vmsvgaReadPort index=%s (%d) val=%#x rc=%x\n", vmsvgaIndexToString(pThis), pThis->svga.u32IndexReg, *pu32, rc));

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync return rc;

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync}

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync#ifdef IN_RING3

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsyncint vmsvgaChangeMode(PVGASTATE pThis)

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync{

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync int rc;

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync

3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync if ( pThis->svga.uWidth == VMSVGA_VAL_UNINITIALIZED

3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync || pThis->svga.uHeight == VMSVGA_VAL_UNINITIALIZED

3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync || pThis->svga.uBpp == VMSVGA_VAL_UNINITIALIZED)

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync {

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync /* Mode change in progress; wait for all values to be set. */

3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync Log(("vmsvgaChangeMode: BOGUS sEnable LFB mode and resize to (%d,%d) bpp=%d\n", pThis->svga.uWidth, pThis->svga.uHeight, pThis->svga.uBpp));

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync return VINF_SUCCESS;

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync }

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync

3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync if ( pThis->svga.uWidth == 0

3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync || pThis->svga.uHeight == 0

3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync || pThis->svga.uBpp == 0)

3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync {

3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync /* Invalid mode change. */

3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync Log(("vmsvgaChangeMode: BOGUS sEnable LFB mode and resize to (%d,%d) bpp=%d\n", pThis->svga.uWidth, pThis->svga.uHeight, pThis->svga.uBpp));

3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync return VINF_SUCCESS;

3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync }

3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync

3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync if ( pThis->last_bpp == (unsigned)pThis->svga.uBpp

3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync && pThis->last_scr_width == (unsigned)pThis->svga.uWidth

3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync && pThis->last_scr_height == (unsigned)pThis->svga.uHeight

3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync && pThis->last_width == (unsigned)pThis->svga.uWidth

3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync && pThis->last_height == (unsigned)pThis->svga.uHeight

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync )

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync {

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync /* Nothing to do. */

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync Log(("vmsvgaChangeMode: nothing changed; ignore\n"));

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync return VINF_SUCCESS;

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync }

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync

3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync Log(("vmsvgaChangeMode: sEnable LFB mode and resize to (%d,%d) bpp=%d\n", pThis->svga.uWidth, pThis->svga.uHeight, pThis->svga.uBpp));

3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync pThis->svga.cbScanline = ((pThis->svga.uWidth * pThis->svga.uBpp + 7) & ~7) / 8;

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync pThis->pDrv->pfnLFBModeChange(pThis->pDrv, true);

3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync rc = pThis->pDrv->pfnResize(pThis->pDrv, pThis->svga.uBpp, pThis->CTX_SUFF(vram_ptr), pThis->svga.cbScanline, pThis->svga.uWidth, pThis->svga.uHeight);

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync AssertRC(rc);

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync AssertReturn(rc == VINF_SUCCESS || rc == VINF_VGA_RESIZE_IN_PROGRESS, rc);

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync /* last stuff */

3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync pThis->last_bpp = pThis->svga.uBpp;

3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync pThis->last_scr_width = pThis->svga.uWidth;

3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync pThis->last_scr_height = pThis->svga.uHeight;

3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync pThis->last_width = pThis->svga.uWidth;

3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync pThis->last_height = pThis->svga.uHeight;

2b114c590cf5a19f8047cd7bde9c7e5ae00aa22bvboxsync

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync ASMAtomicOrU32(&pThis->svga.u32ActionFlags, VMSVGA_ACTION_CHANGEMODE);

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync

3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync /* vmsvgaPortSetViewPort not called after state load; set sensible defaults. */

3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync if ( pThis->svga.viewport.cx == 0

3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync && pThis->svga.viewport.cy == 0)

3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync {

3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync pThis->svga.viewport.cx = pThis->svga.uWidth;

3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync pThis->svga.viewport.cy = pThis->svga.uHeight;

3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync }

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync return VINF_SUCCESS;

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync}

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync#endif /* IN_RING3 */

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsyncPDMBOTHCBDECL(int) vmsvgaWritePort(PVGASTATE pThis, uint32_t u32)

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync{

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync PVMSVGASTATE pSVGAState = (PVMSVGASTATE)pThis->svga.pSVGAState;

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync int rc = VINF_SUCCESS;

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync

0802b726efeabba46f90cb2b285de4dadaac9507vboxsync Log(("vmsvgaWritePort index=%s (%d) val=%#x\n", vmsvgaIndexToString(pThis), pThis->svga.u32IndexReg, u32));

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync switch (pThis->svga.u32IndexReg)

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync {

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync case SVGA_REG_ID:

2b114c590cf5a19f8047cd7bde9c7e5ae00aa22bvboxsync if ( u32 == SVGA_ID_0

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync || u32 == SVGA_ID_1

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync || u32 == SVGA_ID_2)

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync pThis->svga.u32SVGAId = u32;

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync break;

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync case SVGA_REG_ENABLE:

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync if ( pThis->svga.fEnabled == u32

3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync && pThis->last_bpp == (unsigned)pThis->svga.uBpp

3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync && pThis->last_scr_width == (unsigned)pThis->svga.uWidth

3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync && pThis->last_scr_height == (unsigned)pThis->svga.uHeight

3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync && pThis->last_width == (unsigned)pThis->svga.uWidth

3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync && pThis->last_height == (unsigned)pThis->svga.uHeight

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync )

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync /* Nothing to do. */

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync break;

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync#ifdef IN_RING3

2b114c590cf5a19f8047cd7bde9c7e5ae00aa22bvboxsync if ( u32 == 1

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync && pThis->svga.fEnabled == false)

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync {

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync /* Make a backup copy of the first 32k in order to save font data etc. */

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync memcpy(pThis->svga.pFrameBufferBackup, pThis->vram_ptrR3, VMSVGA_FRAMEBUFFER_BACKUP_SIZE);

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync }

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync pThis->svga.fEnabled = u32;

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync if (pThis->svga.fEnabled)

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync {

3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync if ( pThis->svga.uWidth == VMSVGA_VAL_UNINITIALIZED

3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync && pThis->svga.uHeight == VMSVGA_VAL_UNINITIALIZED

3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync && pThis->svga.uBpp == VMSVGA_VAL_UNINITIALIZED)

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync {

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync /* Keep the current mode. */

3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync pThis->svga.uWidth = pThis->pDrv->cx;

3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync pThis->svga.uHeight = pThis->pDrv->cy;

3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync pThis->svga.uBpp = (pThis->pDrv->cBits + 7) & ~7;

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync }

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync

3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync if ( pThis->svga.uWidth != VMSVGA_VAL_UNINITIALIZED

3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync && pThis->svga.uHeight != VMSVGA_VAL_UNINITIALIZED

3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync && pThis->svga.uBpp != VMSVGA_VAL_UNINITIALIZED)

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync {

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync rc = vmsvgaChangeMode(pThis);

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync AssertRCReturn(rc, rc);

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync }

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync Log(("configured=%d busy=%d\n", pThis->svga.fConfigured, pThis->svga.pFIFOR3[SVGA_FIFO_BUSY]));

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync uint32_t *pFIFO = pThis->svga.pFIFOR3;

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync Log(("next %x stop %x\n", pFIFO[SVGA_FIFO_NEXT_CMD], pFIFO[SVGA_FIFO_STOP]));

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync /* Disable or enable dirty page tracking according to the current fTraces value. */

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync vmsvgaSetTraces(pThis, !!pThis->svga.fTraces);

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync }

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync else

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync {

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync /* Restore the text mode backup. */

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync memcpy(pThis->vram_ptrR3, pThis->svga.pFrameBufferBackup, VMSVGA_FRAMEBUFFER_BACKUP_SIZE);

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync pThis->pDrv->pfnLFBModeChange(pThis->pDrv, false);

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync /* Enable dirty page tracking again when going into legacy mode. */

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync vmsvgaSetTraces(pThis, true);

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync }

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync#else

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync rc = VINF_IOM_R3_IOPORT_WRITE;

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync#endif

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync break;

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync case SVGA_REG_WIDTH:

0802b726efeabba46f90cb2b285de4dadaac9507vboxsync if (pThis->svga.uWidth != u32)

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync {

0802b726efeabba46f90cb2b285de4dadaac9507vboxsync if (pThis->svga.fEnabled)

0802b726efeabba46f90cb2b285de4dadaac9507vboxsync {

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync#ifdef IN_RING3

0802b726efeabba46f90cb2b285de4dadaac9507vboxsync pThis->svga.uWidth = u32;

0802b726efeabba46f90cb2b285de4dadaac9507vboxsync rc = vmsvgaChangeMode(pThis);

0802b726efeabba46f90cb2b285de4dadaac9507vboxsync AssertRCReturn(rc, rc);

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync#else

0802b726efeabba46f90cb2b285de4dadaac9507vboxsync rc = VINF_IOM_R3_IOPORT_WRITE;

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync#endif

0802b726efeabba46f90cb2b285de4dadaac9507vboxsync }

0802b726efeabba46f90cb2b285de4dadaac9507vboxsync else

0802b726efeabba46f90cb2b285de4dadaac9507vboxsync pThis->svga.uWidth = u32;

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync }

0802b726efeabba46f90cb2b285de4dadaac9507vboxsync /* else: nop */

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync break;

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync case SVGA_REG_HEIGHT:

0802b726efeabba46f90cb2b285de4dadaac9507vboxsync if (pThis->svga.uHeight != u32)

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync {

0802b726efeabba46f90cb2b285de4dadaac9507vboxsync if (pThis->svga.fEnabled)

0802b726efeabba46f90cb2b285de4dadaac9507vboxsync {

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync#ifdef IN_RING3

0802b726efeabba46f90cb2b285de4dadaac9507vboxsync pThis->svga.uHeight = u32;

0802b726efeabba46f90cb2b285de4dadaac9507vboxsync rc = vmsvgaChangeMode(pThis);

0802b726efeabba46f90cb2b285de4dadaac9507vboxsync AssertRCReturn(rc, rc);

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync#else

0802b726efeabba46f90cb2b285de4dadaac9507vboxsync rc = VINF_IOM_R3_IOPORT_WRITE;

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync#endif

0802b726efeabba46f90cb2b285de4dadaac9507vboxsync }

0802b726efeabba46f90cb2b285de4dadaac9507vboxsync else

0802b726efeabba46f90cb2b285de4dadaac9507vboxsync pThis->svga.uHeight = u32;

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync }

0802b726efeabba46f90cb2b285de4dadaac9507vboxsync /* else: nop */

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync break;

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync case SVGA_REG_DEPTH:

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync /* @todo read-only?? */

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync break;

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync case SVGA_REG_BITS_PER_PIXEL: /* Current bpp in the guest */

0802b726efeabba46f90cb2b285de4dadaac9507vboxsync if (pThis->svga.uBpp != u32)

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync {

0802b726efeabba46f90cb2b285de4dadaac9507vboxsync if (pThis->svga.fEnabled)

0802b726efeabba46f90cb2b285de4dadaac9507vboxsync {

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync#ifdef IN_RING3

0802b726efeabba46f90cb2b285de4dadaac9507vboxsync pThis->svga.uBpp = u32;

0802b726efeabba46f90cb2b285de4dadaac9507vboxsync rc = vmsvgaChangeMode(pThis);

0802b726efeabba46f90cb2b285de4dadaac9507vboxsync AssertRCReturn(rc, rc);

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync#else

0802b726efeabba46f90cb2b285de4dadaac9507vboxsync rc = VINF_IOM_R3_IOPORT_WRITE;

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync#endif

0802b726efeabba46f90cb2b285de4dadaac9507vboxsync }

0802b726efeabba46f90cb2b285de4dadaac9507vboxsync else

0802b726efeabba46f90cb2b285de4dadaac9507vboxsync pThis->svga.uBpp = u32;

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync }

0802b726efeabba46f90cb2b285de4dadaac9507vboxsync /* else: nop */

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync break;

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync case SVGA_REG_PSEUDOCOLOR:

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync break;

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync case SVGA_REG_CONFIG_DONE: /* Set when memory area configured */

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync#ifdef IN_RING3

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync pThis->svga.fConfigured = u32;

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync /* Disabling the FIFO enables tracing (dirty page detection) by default. */

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync if (!pThis->svga.fConfigured)

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync {

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync pThis->svga.fTraces = true;

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync }

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync vmsvgaSetTraces(pThis, !!pThis->svga.fTraces);

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync#else

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync rc = VINF_IOM_R3_IOPORT_WRITE;

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync#endif

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync break;

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync case SVGA_REG_SYNC: /* See "FIFO Synchronization Registers" */

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync if ( pThis->svga.fEnabled

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync && pThis->svga.fConfigured)

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync {

cb39011e69667689c166f1cdf95247b46fff324dvboxsync#if defined(IN_RING3) || defined(IN_RING0)

cb39011e69667689c166f1cdf95247b46fff324dvboxsync Log(("SVGA_REG_SYNC: SVGA_FIFO_BUSY=%d\n", pThis->svga.CTX_SUFF(pFIFO)[SVGA_FIFO_BUSY]));

2b114c590cf5a19f8047cd7bde9c7e5ae00aa22bvboxsync pThis->svga.fBusy = true;

cb39011e69667689c166f1cdf95247b46fff324dvboxsync pThis->svga.CTX_SUFF(pFIFO)[SVGA_FIFO_BUSY] = pThis->svga.fBusy;

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync /* Kick the FIFO thread to start processing commands again. */

cb39011e69667689c166f1cdf95247b46fff324dvboxsync SUPSemEventSignal(pThis->svga.pSupDrvSession, pThis->svga.FIFORequestSem);

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync#else

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync rc = VINF_IOM_R3_IOPORT_WRITE;

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync#endif

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync }

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync /* else nothing to do. */

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync else

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync Log(("Sync ignored enabled=%d configured=%d\n", pThis->svga.fEnabled, pThis->svga.fConfigured));

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync break;

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync case SVGA_REG_BUSY: /* See "FIFO Synchronization Registers" (read-only) */

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync break;

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync case SVGA_REG_GUEST_ID: /* Set guest OS identifier */

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync pThis->svga.u32GuestId = u32;

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync break;

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync case SVGA_REG_PITCHLOCK: /* Fixed pitch for all modes */

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync pThis->svga.u32PitchLock = u32;

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync break;

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync case SVGA_REG_IRQMASK: /* Interrupt mask */

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync pThis->svga.u32IrqMask = u32;

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync /* Irq pending after the above change? */

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync if (pThis->svga.u32IrqMask & pThis->svga.u32IrqStatus)

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync {

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync Log(("SVGA_REG_IRQMASK: Trigger interrupt with status %x\n", pThis->svga.u32IrqStatus));

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync PDMDevHlpPCISetIrqNoWait(pThis->CTX_SUFF(pDevIns), 0, 1);

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync }

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync else

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync PDMDevHlpPCISetIrqNoWait(pThis->CTX_SUFF(pDevIns), 0, 0);

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync break;

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync /* Mouse cursor support */

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync case SVGA_REG_CURSOR_ID:

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync case SVGA_REG_CURSOR_X:

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync case SVGA_REG_CURSOR_Y:

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync case SVGA_REG_CURSOR_ON:

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync break;

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync /* Legacy multi-monitor support */

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync case SVGA_REG_NUM_GUEST_DISPLAYS:/* Number of guest displays in X/Y direction */

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync break;

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync case SVGA_REG_DISPLAY_ID: /* Display ID for the following display attributes */

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync break;

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync case SVGA_REG_DISPLAY_IS_PRIMARY:/* Whether this is a primary display */

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync break;

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync case SVGA_REG_DISPLAY_POSITION_X:/* The display position x */

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync break;

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync case SVGA_REG_DISPLAY_POSITION_Y:/* The display position y */

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync break;

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync case SVGA_REG_DISPLAY_WIDTH: /* The display's width */

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync break;

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync case SVGA_REG_DISPLAY_HEIGHT: /* The display's height */

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync break;

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync#ifdef VBOX_WITH_VMSVGA3D

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync /* See "Guest memory regions" below. */

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync case SVGA_REG_GMR_ID:

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync pThis->svga.u32CurrentGMRId = u32;

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync break;

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync case SVGA_REG_GMR_DESCRIPTOR:

0802b726efeabba46f90cb2b285de4dadaac9507vboxsync# ifndef IN_RING3

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync rc = VINF_IOM_R3_IOPORT_WRITE;

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync break;

0802b726efeabba46f90cb2b285de4dadaac9507vboxsync# else /* IN_RING3 */

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync {

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync SVGAGuestMemDescriptor desc;

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync RTGCPHYS GCPhys = (RTGCPHYS)u32 << PAGE_SHIFT;

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync RTGCPHYS GCPhysBase = GCPhys;

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync uint32_t idGMR = pThis->svga.u32CurrentGMRId;

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync uint32_t cDescriptorsAllocated = 16;

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync uint32_t iDescriptor = 0;

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync /* Validate current GMR id. */

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync AssertBreak(idGMR < VMSVGA_MAX_GMR_IDS);

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync /* Free the old GMR if present. */

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync vmsvgaGMRFree(pThis, idGMR);

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync /* Just undefine the GMR? */

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync if (GCPhys == 0)

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync break;

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync pSVGAState->aGMR[idGMR].paDesc = (PVMSVGAGMRDESCRIPTOR)RTMemAllocZ(cDescriptorsAllocated * sizeof(VMSVGAGMRDESCRIPTOR));

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync AssertReturn(pSVGAState->aGMR[idGMR].paDesc, VERR_NO_MEMORY);

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync /* Never cross a page boundary automatically. */

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync while (PHYS_PAGE_ADDRESS(GCPhys) == PHYS_PAGE_ADDRESS(GCPhysBase))

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync {

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync /* Read descriptor. */

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync rc = PDMDevHlpPhysRead(pThis->CTX_SUFF(pDevIns), GCPhys, &desc, sizeof(desc));

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync AssertRCBreak(rc);

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync if ( desc.ppn == 0

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync && desc.numPages == 0)

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync break; /* terminator */

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync if ( desc.ppn != 0

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync && desc.numPages == 0)

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync {

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync /* Pointer to the next physical page of descriptors. */

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync GCPhys = GCPhysBase = desc.ppn << PAGE_SHIFT;

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync }

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync else

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync {

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync if (iDescriptor == cDescriptorsAllocated)

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync {

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync cDescriptorsAllocated += 16;

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync pSVGAState->aGMR[idGMR].paDesc = (PVMSVGAGMRDESCRIPTOR)RTMemRealloc(pSVGAState->aGMR[idGMR].paDesc, cDescriptorsAllocated * sizeof(VMSVGAGMRDESCRIPTOR));

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync AssertReturn(pSVGAState->aGMR[idGMR].paDesc, VERR_NO_MEMORY);

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync }

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync pSVGAState->aGMR[idGMR].paDesc[iDescriptor].GCPhys = desc.ppn << PAGE_SHIFT;

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync pSVGAState->aGMR[idGMR].paDesc[iDescriptor++].numPages = desc.numPages;

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync pSVGAState->aGMR[idGMR].cbTotal += desc.numPages * PAGE_SIZE;

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync /* Continue with the next descriptor. */

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync GCPhys += sizeof(desc);

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync }

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync }

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync pSVGAState->aGMR[idGMR].numDescriptors = iDescriptor;

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync Log(("Defined new gmr %x numDescriptors=%d cbTotal=%x\n", idGMR, iDescriptor, pSVGAState->aGMR[idGMR].cbTotal));

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync if (!pSVGAState->aGMR[idGMR].numDescriptors)

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync {

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync AssertFailed();

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync RTMemFree(pSVGAState->aGMR[idGMR].paDesc);

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync pSVGAState->aGMR[idGMR].paDesc = NULL;

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync }

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync AssertRC(rc);

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync break;

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync }

0802b726efeabba46f90cb2b285de4dadaac9507vboxsync# endif /* IN_RING3 */

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync#endif // VBOX_WITH_VMSVGA3D

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync case SVGA_REG_TRACES: /* Enable trace-based updates even when FIFO is on */

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync if (pThis->svga.fTraces == u32)

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync break; /* nothing to do */

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync

2b114c590cf5a19f8047cd7bde9c7e5ae00aa22bvboxsync#ifdef IN_RING3

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync vmsvgaSetTraces(pThis, !!u32);

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync#else

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync rc = VINF_IOM_R3_IOPORT_WRITE;

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync#endif

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync break;

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync case SVGA_REG_TOP: /* Must be 1 more than the last register */

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync break;

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync case SVGA_PALETTE_BASE: /* Base of SVGA color map */

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync break;

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync /* Next 768 (== 256*3) registers exist for colormap */

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync case SVGA_REG_NUM_DISPLAYS: /* (Deprecated) */

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync Log(("Write to deprecated register %x - val %x ignored\n", pThis->svga.u32IndexReg, u32));

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync break;

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync case SVGA_REG_FB_START:

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync case SVGA_REG_MEM_START:

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync case SVGA_REG_HOST_BITS_PER_PIXEL:

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync case SVGA_REG_MAX_WIDTH:

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync case SVGA_REG_MAX_HEIGHT:

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync case SVGA_REG_VRAM_SIZE:

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync case SVGA_REG_FB_SIZE:

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync case SVGA_REG_CAPABILITIES:

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync case SVGA_REG_MEM_SIZE:

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync case SVGA_REG_SCRATCH_SIZE: /* Number of scratch registers */

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync case SVGA_REG_MEM_REGS: /* Number of FIFO registers */

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync case SVGA_REG_BYTES_PER_LINE:

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync case SVGA_REG_FB_OFFSET:

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync case SVGA_REG_RED_MASK:

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync case SVGA_REG_GREEN_MASK:

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync case SVGA_REG_BLUE_MASK:

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync case SVGA_REG_GMRS_MAX_PAGES: /* Maximum number of 4KB pages for all GMRs */

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync case SVGA_REG_MEMORY_SIZE: /* Total dedicated device memory excluding FIFO */

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync case SVGA_REG_GMR_MAX_IDS:

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync case SVGA_REG_GMR_MAX_DESCRIPTOR_LENGTH:

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync /* Read only - ignore. */

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync Log(("Write to R/O register %x - val %x ignored\n", pThis->svga.u32IndexReg, u32));

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync break;

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync default:

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync if ( pThis->svga.u32IndexReg >= SVGA_SCRATCH_BASE

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync && pThis->svga.u32IndexReg < SVGA_SCRATCH_BASE + pThis->svga.cScratchRegion)

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync {

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync pThis->svga.au32ScratchRegion[pThis->svga.u32IndexReg - SVGA_SCRATCH_BASE] = u32;

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync }

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync break;

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync }

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync return rc;

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync}

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsyncPDMBOTHCBDECL(int) vmsvgaIORead(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t *pu32, unsigned cb)

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync{

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync PVGASTATE pThis = PDMINS_2_DATA(pDevIns, PVGASTATE);

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync int rc = VINF_SUCCESS;

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync /* Ignore non-dword accesses. */

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync if (cb != 4)

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync {

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync Log(("Ignoring non-dword read at %x cb=%d\n", Port, cb));

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync *pu32 = ~0;

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync return VINF_SUCCESS;

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync }

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync switch (Port - pThis->svga.BasePort)

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync {

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync case SVGA_INDEX_PORT:

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync *pu32 = pThis->svga.u32IndexReg;

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync break;

ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync