c6ade8a5a12fad69394e7223b7ea170bd729f0f4vboxsync * VMWare SVGA device.
c6ade8a5a12fad69394e7223b7ea170bd729f0f4vboxsync * Logging levels guidelines for this and related files:
c6ade8a5a12fad69394e7223b7ea170bd729f0f4vboxsync * - Log() for normal bits.
c6ade8a5a12fad69394e7223b7ea170bd729f0f4vboxsync * - LogFlow() for more info.
c6ade8a5a12fad69394e7223b7ea170bd729f0f4vboxsync * - Log2 for hex dump of cursor data.
c6ade8a5a12fad69394e7223b7ea170bd729f0f4vboxsync * - Log3 for hex dump of shader code.
c6ade8a5a12fad69394e7223b7ea170bd729f0f4vboxsync * - Log4 for hex dumps of 3D data.
c6ade8a5a12fad69394e7223b7ea170bd729f0f4vboxsync * Copyright (C) 2013-2014 Oracle Corporation
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync * This file is part of VirtualBox Open Source Edition (OSE), as
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync * available from http://www.virtualbox.org. This file is free software;
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync * you can redistribute it and/or modify it under the terms of the GNU
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync * General Public License (GPL) as published by the Free Software
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync * Foundation, in version 2 as it comes in the "COPYING" file of the
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync/*******************************************************************************
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync* Header Files *
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync*******************************************************************************/
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync/* should go BEFORE any other DevVGA include to make all DevVGA.h config defines be visible */
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync/* Enable to log FIFO register accesses. */
0802b726efeabba46f90cb2b285de4dadaac9507vboxsync//# define DEBUG_FIFO_ACCESS
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync/* Enable to log GMR page accesses. */
0802b726efeabba46f90cb2b285de4dadaac9507vboxsync//# define DEBUG_GMR_ACCESS
36c3589d6411416bba897f2595f1812b9d9ff4b3vboxsync/*******************************************************************************
36c3589d6411416bba897f2595f1812b9d9ff4b3vboxsync* Defined Constants And Macros *
36c3589d6411416bba897f2595f1812b9d9ff4b3vboxsync*******************************************************************************/
36c3589d6411416bba897f2595f1812b9d9ff4b3vboxsync * Macro for checking if a fixed FIFO register is valid according to the
36c3589d6411416bba897f2595f1812b9d9ff4b3vboxsync * current FIFO configuration.
36c3589d6411416bba897f2595f1812b9d9ff4b3vboxsync * @returns true / false.
36c3589d6411416bba897f2595f1812b9d9ff4b3vboxsync * @param a_iIndex The fifo register index (like SVGA_FIFO_CAPABILITIES).
36c3589d6411416bba897f2595f1812b9d9ff4b3vboxsync * @param a_offFifoMin A valid SVGA_FIFO_MIN value.
36c3589d6411416bba897f2595f1812b9d9ff4b3vboxsync#define VMSVGA_IS_VALID_FIFO_REG(a_iIndex, a_offFifoMin) ( ((a_iIndex) + 1) * sizeof(uint32_t) <= (a_offFifoMin) )
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync/*******************************************************************************
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync* Structures and Typedefs *
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync*******************************************************************************/
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync/* 64-bit GMR descriptor */
2b114c590cf5a19f8047cd7bde9c7e5ae00aa22bvboxsynctypedef struct
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync/* GMR slot */
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsynctypedef struct
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync/* Internal SVGA state. */
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsynctypedef struct
51163b26ef6e81898acf6db392f1ca751335f71bvboxsync /** Number of EMTs in BusyDelayedEmts (quicker than scanning the set). */
51163b26ef6e81898acf6db392f1ca751335f71bvboxsync /** Set of EMTs that are */
36c3589d6411416bba897f2595f1812b9d9ff4b3vboxsync /** Number of EMTs waiting on hBusyDelayedEmts. */
36c3589d6411416bba897f2595f1812b9d9ff4b3vboxsync /** Semaphore that EMTs wait on when reading SVGA_REG_BUSY and the FIFO is
36c3589d6411416bba897f2595f1812b9d9ff4b3vboxsync * busy (ugly). */
36c3589d6411416bba897f2595f1812b9d9ff4b3vboxsync /** Tracks how much time we waste reading SVGA_REG_BUSY with a busy FIFO. */
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync * SSM descriptor table for the VMSVGAGMRDESCRIPTOR structure.
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsyncstatic SSMFIELD const g_aVMSVGAGMRDESCRIPTORFields[] =
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync SSMFIELD_ENTRY_GCPHYS( VMSVGAGMRDESCRIPTOR, GCPhys),
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync * SSM descriptor table for the GMR structure.
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync * SSM descriptor table for the VMSVGASTATE structure.
3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync SSMFIELD_ENTRY_IGN_HCPTR( VMSVGASTATE, Cursor.pData),
36c3589d6411416bba897f2595f1812b9d9ff4b3vboxsync SSMFIELD_ENTRY_IGNORE( VMSVGASTATE, cBusyDelayedEmts),
51163b26ef6e81898acf6db392f1ca751335f71bvboxsync SSMFIELD_ENTRY_IGNORE( VMSVGASTATE, BusyDelayedEmts),
36c3589d6411416bba897f2595f1812b9d9ff4b3vboxsync SSMFIELD_ENTRY_IGNORE( VMSVGASTATE, hBusyDelayedEmts),
36c3589d6411416bba897f2595f1812b9d9ff4b3vboxsync SSMFIELD_ENTRY_IGNORE( VMSVGASTATE, StatBusyDelayEmts),
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync SSMFIELD_ENTRY_IGNORE( VMSVGASTATE, StatR3CmdPresent),
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync SSMFIELD_ENTRY_IGNORE( VMSVGASTATE, StatR3CmdDrawPrimitive),
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync SSMFIELD_ENTRY_IGNORE( VMSVGASTATE, StatR3CmdSurfaceDMA),
36c3589d6411416bba897f2595f1812b9d9ff4b3vboxsync SSMFIELD_ENTRY_IGNORE( VMSVGASTATE, StatFifoCommands),
36c3589d6411416bba897f2595f1812b9d9ff4b3vboxsync SSMFIELD_ENTRY_IGNORE( VMSVGASTATE, StatFifoErrors),
36c3589d6411416bba897f2595f1812b9d9ff4b3vboxsync SSMFIELD_ENTRY_IGNORE( VMSVGASTATE, StatFifoUnkCmds),
36c3589d6411416bba897f2595f1812b9d9ff4b3vboxsync SSMFIELD_ENTRY_IGNORE( VMSVGASTATE, StatFifoTodoTimeout),
36c3589d6411416bba897f2595f1812b9d9ff4b3vboxsync SSMFIELD_ENTRY_IGNORE( VMSVGASTATE, StatFifoTodoWoken),
36c3589d6411416bba897f2595f1812b9d9ff4b3vboxsync SSMFIELD_ENTRY_IGNORE( VMSVGASTATE, StatFifoStalls),
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync * SSM descriptor table for the VGAState.svga structure.
3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync SSMFIELD_ENTRY_IGNORE( VMSVGAState, u64HostWindowId),
3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync SSMFIELD_ENTRY_IGN_HCPTR( VMSVGAState, pSVGAState),
3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync SSMFIELD_ENTRY_IGN_HCPTR( VMSVGAState, pFrameBufferBackup),
2b114c590cf5a19f8047cd7bde9c7e5ae00aa22bvboxsync SSMFIELD_ENTRY_IGN_HCPTR( VMSVGAState, pFIFOExtCmdParam),
3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync SSMFIELD_ENTRY_IGN_GCPHYS( VMSVGAState, GCPhysFIFO),
cb39011e69667689c166f1cdf95247b46fff324dvboxsync SSMFIELD_ENTRY_IGNORE( VMSVGAState, pSupDrvSession),
3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync SSMFIELD_ENTRY_IGNORE( VMSVGAState, FIFORequestSem),
3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync SSMFIELD_ENTRY_IGNORE( VMSVGAState, FIFOExtCmdSem),
3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync SSMFIELD_ENTRY_IGN_HCPTR( VMSVGAState, pFIFOIOThread),
3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync SSMFIELD_ENTRY_IGNORE( VMSVGAState, u8FIFOExtCommand),
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsyncstatic void vmsvgaSetTraces(PVGASTATE pThis, bool fTraces);
0802b726efeabba46f90cb2b285de4dadaac9507vboxsync#endif /* IN_RING3 */
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync * Index register string name lookup
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync * @returns Index register string or "UNKNOWN"
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync * @param pThis VMSVGA State
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsyncstatic const char *vmsvgaIndexToString(PVGASTATE pThis)
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync return "SVGA_REG_ID";
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync return "SVGA_REG_ENABLE";
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync return "SVGA_REG_WIDTH";
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync return "SVGA_REG_HEIGHT";
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync return "SVGA_REG_MAX_WIDTH";
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync return "SVGA_REG_MAX_HEIGHT";
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync return "SVGA_REG_DEPTH";
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync case SVGA_REG_BITS_PER_PIXEL: /* Current bpp in the guest */
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync return "SVGA_REG_BITS_PER_PIXEL";
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync case SVGA_REG_HOST_BITS_PER_PIXEL: /* (Deprecated) */
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync return "SVGA_REG_HOST_BITS_PER_PIXEL";
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync return "SVGA_REG_PSEUDOCOLOR";
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync return "SVGA_REG_RED_MASK";
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync return "SVGA_REG_GREEN_MASK";
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync return "SVGA_REG_BLUE_MASK";
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync return "SVGA_REG_BYTES_PER_LINE";
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync return "SVGA_REG_VRAM_SIZE";
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync case SVGA_REG_FB_START: /* Frame buffer physical address. */
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync return "SVGA_REG_FB_START";
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync case SVGA_REG_FB_OFFSET: /* Offset of the frame buffer in VRAM */
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync return "SVGA_REG_FB_OFFSET";
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync return "SVGA_REG_FB_SIZE";
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync return "SVGA_REG_CAPABILITIES";
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync return "SVGA_REG_MEM_START";
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync return "SVGA_REG_MEM_SIZE";
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync case SVGA_REG_CONFIG_DONE: /* Set when memory area configured */
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync return "SVGA_REG_CONFIG_DONE";
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync case SVGA_REG_SYNC: /* See "FIFO Synchronization Registers" */
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync return "SVGA_REG_SYNC";
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync case SVGA_REG_BUSY: /* See "FIFO Synchronization Registers" */
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync return "SVGA_REG_BUSY";
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync case SVGA_REG_GUEST_ID: /* Set guest OS identifier */
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync return "SVGA_REG_GUEST_ID";
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync case SVGA_REG_SCRATCH_SIZE: /* Number of scratch registers */
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync return "SVGA_REG_SCRATCH_SIZE";
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync case SVGA_REG_MEM_REGS: /* Number of FIFO registers */
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync return "SVGA_REG_MEM_REGS";
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync case SVGA_REG_PITCHLOCK: /* Fixed pitch for all modes */
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync return "SVGA_REG_PITCHLOCK";
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync return "SVGA_REG_IRQMASK";
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync return "SVGA_REG_GMR_ID";
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync return "SVGA_REG_GMR_DESCRIPTOR";
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync return "SVGA_REG_GMR_MAX_IDS";
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync return "SVGA_REG_GMR_MAX_DESCRIPTOR_LENGTH";
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync case SVGA_REG_TRACES: /* Enable trace-based updates even when FIFO is on */
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync return "SVGA_REG_TRACES";
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync case SVGA_REG_GMRS_MAX_PAGES: /* Maximum number of 4KB pages for all GMRs */
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync return "SVGA_REG_GMRS_MAX_PAGES";
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync case SVGA_REG_MEMORY_SIZE: /* Total dedicated device memory excluding FIFO */
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync return "SVGA_REG_MEMORY_SIZE";
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync case SVGA_REG_TOP: /* Must be 1 more than the last register */
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync return "SVGA_REG_TOP";
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync case SVGA_PALETTE_BASE: /* Base of SVGA color map */
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync return "SVGA_PALETTE_BASE";
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync return "SVGA_REG_CURSOR_ID";
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync return "SVGA_REG_CURSOR_X";
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync return "SVGA_REG_CURSOR_Y";
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync return "SVGA_REG_CURSOR_ON";
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync case SVGA_REG_NUM_GUEST_DISPLAYS:/* Number of guest displays in X/Y direction */
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync return "SVGA_REG_NUM_GUEST_DISPLAYS";
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync case SVGA_REG_DISPLAY_ID: /* Display ID for the following display attributes */
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync return "SVGA_REG_DISPLAY_ID";
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync case SVGA_REG_DISPLAY_IS_PRIMARY:/* Whether this is a primary display */
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync return "SVGA_REG_DISPLAY_IS_PRIMARY";
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync case SVGA_REG_DISPLAY_POSITION_X:/* The display position x */
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync return "SVGA_REG_DISPLAY_POSITION_X";
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync case SVGA_REG_DISPLAY_POSITION_Y:/* The display position y */
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync return "SVGA_REG_DISPLAY_POSITION_Y";
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync case SVGA_REG_DISPLAY_WIDTH: /* The display's width */
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync return "SVGA_REG_DISPLAY_WIDTH";
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync case SVGA_REG_DISPLAY_HEIGHT: /* The display's height */
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync return "SVGA_REG_DISPLAY_HEIGHT";
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync return "SVGA_REG_NUM_DISPLAYS";
de8636fc8bdeb02161ee5b329c407dd0c48b0885vboxsync if (pThis->svga.u32IndexReg - (uint32_t)SVGA_SCRATCH_BASE < pThis->svga.cScratchRegion)
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync return "SVGA_SCRATCH_BASE reg";
de8636fc8bdeb02161ee5b329c407dd0c48b0885vboxsync if (pThis->svga.u32IndexReg - (uint32_t)SVGA_PALETTE_BASE < (uint32_t)SVGA_NUM_PALETTE_REGS)
de8636fc8bdeb02161ee5b329c407dd0c48b0885vboxsync return "SVGA_PALETTE_BASE reg";
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync return "UNKNOWN";
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync * FIFO command name lookup
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync * @returns FIFO command string or "UNKNOWN"
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync * @param u32Cmd FIFO command
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsyncstatic const char *vmsvgaFIFOCmdToString(uint32_t u32Cmd)
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync return "SVGA_CMD_INVALID_CMD";
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync return "SVGA_CMD_UPDATE";
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync return "SVGA_CMD_RECT_COPY";
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync return "SVGA_CMD_DEFINE_CURSOR";
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync return "SVGA_CMD_DEFINE_ALPHA_CURSOR";
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync return "SVGA_CMD_UPDATE_VERBOSE";
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync return "SVGA_CMD_FRONT_ROP_FILL";
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync return "SVGA_CMD_FENCE";
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync return "SVGA_CMD_ESCAPE";
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync return "SVGA_CMD_DEFINE_SCREEN";
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync return "SVGA_CMD_DESTROY_SCREEN";
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync return "SVGA_CMD_DEFINE_GMRFB";
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync return "SVGA_CMD_BLIT_GMRFB_TO_SCREEN";
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync return "SVGA_CMD_BLIT_SCREEN_TO_GMRFB";
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync return "SVGA_CMD_ANNOTATION_FILL";
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync return "SVGA_CMD_ANNOTATION_COPY";
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync return "SVGA_CMD_DEFINE_GMR2";
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync return "SVGA_CMD_REMAP_GMR2";
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync return "SVGA_3D_CMD_SURFACE_DEFINE";
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync return "SVGA_3D_CMD_SURFACE_DESTROY";
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync return "SVGA_3D_CMD_SURFACE_COPY";
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync return "SVGA_3D_CMD_SURFACE_STRETCHBLT";
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync return "SVGA_3D_CMD_SURFACE_DMA";
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync return "SVGA_3D_CMD_CONTEXT_DEFINE";
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync return "SVGA_3D_CMD_CONTEXT_DESTROY";
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync return "SVGA_3D_CMD_SETTRANSFORM";
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync return "SVGA_3D_CMD_SETZRANGE";
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync return "SVGA_3D_CMD_SETRENDERSTATE";
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync return "SVGA_3D_CMD_SETRENDERTARGET";
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync return "SVGA_3D_CMD_SETTEXTURESTATE";
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync return "SVGA_3D_CMD_SETMATERIAL";
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync return "SVGA_3D_CMD_SETLIGHTDATA";
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync return "SVGA_3D_CMD_SETLIGHTENABLED";
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync return "SVGA_3D_CMD_SETVIEWPORT";
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync return "SVGA_3D_CMD_SETCLIPPLANE";
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync return "SVGA_3D_CMD_CLEAR";
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync return "SVGA_3D_CMD_PRESENT";
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync return "SVGA_3D_CMD_SHADER_DEFINE";
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync return "SVGA_3D_CMD_SHADER_DESTROY";
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync return "SVGA_3D_CMD_SET_SHADER";
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync return "SVGA_3D_CMD_SET_SHADER_CONST";
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync return "SVGA_3D_CMD_DRAW_PRIMITIVES";
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync return "SVGA_3D_CMD_SETSCISSORRECT";
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync return "SVGA_3D_CMD_BEGIN_QUERY";
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync return "SVGA_3D_CMD_END_QUERY";
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync return "SVGA_3D_CMD_WAIT_FOR_QUERY";
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync return "SVGA_3D_CMD_PRESENT_READBACK";
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync return "SVGA_3D_CMD_BLIT_SURFACE_TO_SCREEN";
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync return "SVGA_3D_CMD_SURFACE_DEFINE_V2";
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync return "SVGA_3D_CMD_GENERATE_MIPMAPS";
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync return "SVGA_3D_CMD_ACTIVATE_SURFACE";
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync return "SVGA_3D_CMD_DEACTIVATE_SURFACE";
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync return "UNKNOWN";
3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync * Inform the VGA device of viewport changes (as a result of e.g. scrolling)
3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync * @param pInterface Pointer to this interface.
3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync * @param uScreenId The screen updates are for.
3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync * @param x The upper left corner x coordinate of the new viewport rectangle
3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync * @param y The upper left corner y coordinate of the new viewport rectangle
3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync * @param cx The width of the new viewport rectangle
3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync * @param cy The height of the new viewport rectangle
3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync * @thread The emulation thread.
3194da424708abdd288b28d96892b3a5f3f7df0bvboxsyncDECLCALLBACK(void) vmsvgaPortSetViewPort(PPDMIDISPLAYPORT pInterface, uint32_t uScreenId, uint32_t x, uint32_t y, uint32_t cx, uint32_t cy)
8f8e1c3bab8eabbad1cddcd165f3e30cc2011a33vboxsync PVGASTATE pThis = RT_FROM_MEMBER(pInterface, VGASTATE, IPort);
3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync Log(("vmsvgaPortSetViewPort: screen %d (%d,%d)(%d,%d)\n", uScreenId, x, y, cx, cy));
3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync pThis->svga.viewport.cx = RT_MIN(cx, (uint32_t)pThis->svga.uWidth);
3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync pThis->svga.viewport.cy = RT_MIN(cy, (uint32_t)pThis->svga.uHeight);
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync * Read port register
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync * @returns VBox status code.
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync * @param pThis VMSVGA State
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync * @param pu32 Where to store the read value
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsyncPDMBOTHCBDECL(int) vmsvgaReadPort(PVGASTATE pThis, uint32_t *pu32)
3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync && pThis->svga.uHeight != VMSVGA_VAL_UNINITIALIZED)
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync /* This returns the color depth of the current mode. */
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync *pu32 = 24; /* The upper 8 bits are either alpha bits or not used. */
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync case SVGA_REG_HOST_BITS_PER_PIXEL: /* (Deprecated) */
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync case SVGA_REG_BITS_PER_PIXEL: /* Current bpp in the guest */
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync case SVGA_REG_FB_START: /* Frame buffer physical address. */
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync case SVGA_REG_FB_OFFSET: /* Offset of the frame buffer in VRAM */
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync /* Always zero in our case. */
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync /* VMWare testcases want at least 4 MB in case the hardware is disabled. */
3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync && pThis->svga.uHeight != VMSVGA_VAL_UNINITIALIZED)
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync /* Hardware enabled; return real framebuffer size .*/
3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync *pu32 = (uint32_t)pThis->svga.uHeight * pThis->svga.cbScanline;
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync *pu32 = RT_MAX(0x100000, (uint32_t)pThis->pDrv->cy * pThis->pDrv->cbScanline);
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync Log(("h=%d w=%d bpp=%d\n", pThis->pDrv->cy, pThis->pDrv->cx, pThis->pDrv->cBits));
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync case SVGA_REG_CONFIG_DONE: /* Set when memory area configured */
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync case SVGA_REG_SYNC: /* See "FIFO Synchronization Registers" */
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync case SVGA_REG_BUSY: /* See "FIFO Synchronization Registers" */
51163b26ef6e81898acf6db392f1ca751335f71bvboxsync /* Go to ring-3 and halt the CPU. */
51163b26ef6e81898acf6db392f1ca751335f71bvboxsync /* The guest is basically doing a HLT via the device here, but with
51163b26ef6e81898acf6db392f1ca751335f71bvboxsync a special wake up condition on FIFO completion. */
51163b26ef6e81898acf6db392f1ca751335f71bvboxsync PVMSVGASTATE pSVGAState = (PVMSVGASTATE)pThis->svga.pSVGAState;
51163b26ef6e81898acf6db392f1ca751335f71bvboxsync STAM_REL_PROFILE_START(&pSVGAState->StatBusyDelayEmts, EmtDelay);
702b9cf91dc7858d23ccc7cd1dae30e4bc1c5d39vboxsync VMCPUID idCpu = PDMDevHlpGetCurrentCpuId(pThis->pDevInsR3);
51163b26ef6e81898acf6db392f1ca751335f71bvboxsync VMCPUSET_ATOMIC_ADD(&pSVGAState->BusyDelayedEmts, idCpu);
51163b26ef6e81898acf6db392f1ca751335f71bvboxsync VMCPUSET_ATOMIC_DEL(&pSVGAState->BusyDelayedEmts, idCpu);
36c3589d6411416bba897f2595f1812b9d9ff4b3vboxsync /* Delay the EMT a bit so the FIFO and others can get some work done.
36c3589d6411416bba897f2595f1812b9d9ff4b3vboxsync This used to be a crude 50 ms sleep. The current code tries to be
36c3589d6411416bba897f2595f1812b9d9ff4b3vboxsync more efficient, but the consept is still very crude. */
36c3589d6411416bba897f2595f1812b9d9ff4b3vboxsync PVMSVGASTATE pSVGAState = (PVMSVGASTATE)pThis->svga.pSVGAState;
36c3589d6411416bba897f2595f1812b9d9ff4b3vboxsync STAM_REL_PROFILE_START(&pSVGAState->StatBusyDelayEmts, EmtDelay);
36c3589d6411416bba897f2595f1812b9d9ff4b3vboxsync uint32_t cRefs = ASMAtomicIncU32(&pSVGAState->cBusyDelayedEmts);
36c3589d6411416bba897f2595f1812b9d9ff4b3vboxsync RTSemEventMultiReset(pSVGAState->hBusyDelayedEmts);
326ffe46af8b56e4a0b9648193c1c0681104f127vboxsync /** @todo If this code is going to stay, we need to call into the halt/wait
326ffe46af8b56e4a0b9648193c1c0681104f127vboxsync * code in VMEmt.cpp here, otherwise all kind of EMT interaction will
326ffe46af8b56e4a0b9648193c1c0681104f127vboxsync * suffer when the guest is polling on a busy FIFO. */
326ffe46af8b56e4a0b9648193c1c0681104f127vboxsync uint64_t cNsMaxWait = TMVirtualSyncGetNsToDeadline(PDMDevHlpGetVM(pThis->pDevInsR3));
326ffe46af8b56e4a0b9648193c1c0681104f127vboxsync RTSemEventMultiWaitEx(pSVGAState->hBusyDelayedEmts,
534b08d8ec6f569f90e80fd5eb49021993da0745vboxsync RTSEMWAIT_FLAGS_NANOSECS | RTSEMWAIT_FLAGS_RELATIVE | RTSEMWAIT_FLAGS_NORESUME,
36c3589d6411416bba897f2595f1812b9d9ff4b3vboxsync STAM_REL_PROFILE_STOP(&pSVGAState->StatBusyDelayEmts, EmtDelay);
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync case SVGA_REG_GUEST_ID: /* Set guest OS identifier */
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync case SVGA_REG_SCRATCH_SIZE: /* Number of scratch registers */
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync case SVGA_REG_MEM_REGS: /* Number of FIFO registers */
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync case SVGA_REG_PITCHLOCK: /* Fixed pitch for all modes */
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync /* See "Guest memory regions" below. */
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync /* Write only */
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync case SVGA_REG_TRACES: /* Enable trace-based updates even when FIFO is on */
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync case SVGA_REG_GMRS_MAX_PAGES: /* Maximum number of 4KB pages for all GMRs */
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync case SVGA_REG_MEMORY_SIZE: /* Total dedicated device memory excluding FIFO */
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync case SVGA_REG_TOP: /* Must be 1 more than the last register */
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync case SVGA_PALETTE_BASE: /* Base of SVGA color map */
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync /* Next 768 (== 256*3) registers exist for colormap */
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync /* Mouse cursor support. */
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync /* Legacy multi-monitor support */
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync case SVGA_REG_NUM_GUEST_DISPLAYS:/* Number of guest displays in X/Y direction */
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync case SVGA_REG_DISPLAY_ID: /* Display ID for the following display attributes */
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync case SVGA_REG_DISPLAY_IS_PRIMARY:/* Whether this is a primary display */
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync case SVGA_REG_DISPLAY_POSITION_X:/* The display position x */
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync case SVGA_REG_DISPLAY_POSITION_Y:/* The display position y */
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync case SVGA_REG_DISPLAY_WIDTH: /* The display's width */
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync case SVGA_REG_DISPLAY_HEIGHT: /* The display's height */
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync *pu32 = 1; /* Must return something sensible here otherwise the Linux driver will take a legacy code path without 3d support. */
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync && pThis->svga.u32IndexReg < SVGA_SCRATCH_BASE + pThis->svga.cScratchRegion)
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync *pu32 = pThis->svga.au32ScratchRegion[pThis->svga.u32IndexReg - SVGA_SCRATCH_BASE];
0802b726efeabba46f90cb2b285de4dadaac9507vboxsync Log(("vmsvgaReadPort index=%s (%d) val=%#x rc=%x\n", vmsvgaIndexToString(pThis), pThis->svga.u32IndexReg, *pu32, rc));
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync * Apply the current resolution settings to change the video mode.
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync * @returns VBox status code.
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync * @param pThis VMSVGA State
3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync if ( pThis->svga.uWidth == VMSVGA_VAL_UNINITIALIZED
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync /* Mode change in progress; wait for all values to be set. */
3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync Log(("vmsvgaChangeMode: BOGUS sEnable LFB mode and resize to (%d,%d) bpp=%d\n", pThis->svga.uWidth, pThis->svga.uHeight, pThis->svga.uBpp));
3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync /* Invalid mode change. */
3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync Log(("vmsvgaChangeMode: BOGUS sEnable LFB mode and resize to (%d,%d) bpp=%d\n", pThis->svga.uWidth, pThis->svga.uHeight, pThis->svga.uBpp));
3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync && pThis->last_scr_width == (unsigned)pThis->svga.uWidth
3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync && pThis->last_scr_height == (unsigned)pThis->svga.uHeight
3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync && pThis->last_width == (unsigned)pThis->svga.uWidth
3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync && pThis->last_height == (unsigned)pThis->svga.uHeight
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync /* Nothing to do. */
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync Log(("vmsvgaChangeMode: nothing changed; ignore\n"));
3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync Log(("vmsvgaChangeMode: sEnable LFB mode and resize to (%d,%d) bpp=%d\n", pThis->svga.uWidth, pThis->svga.uHeight, pThis->svga.uBpp));
3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync pThis->svga.cbScanline = ((pThis->svga.uWidth * pThis->svga.uBpp + 7) & ~7) / 8;
3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync rc = pThis->pDrv->pfnResize(pThis->pDrv, pThis->svga.uBpp, pThis->CTX_SUFF(vram_ptr), pThis->svga.cbScanline, pThis->svga.uWidth, pThis->svga.uHeight);
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync AssertReturn(rc == VINF_SUCCESS || rc == VINF_VGA_RESIZE_IN_PROGRESS, rc);
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync /* last stuff */
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync ASMAtomicOrU32(&pThis->svga.u32ActionFlags, VMSVGA_ACTION_CHANGEMODE);
3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync /* vmsvgaPortSetViewPort not called after state load; set sensible defaults. */
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync#endif /* IN_RING3 */
36c3589d6411416bba897f2595f1812b9d9ff4b3vboxsync * Safely updates the SVGA_FIFO_BUSY register (in shared memory).
36c3589d6411416bba897f2595f1812b9d9ff4b3vboxsync * @param pThis The VMSVGA state.
36c3589d6411416bba897f2595f1812b9d9ff4b3vboxsync * @param fState The busy state.
36c3589d6411416bba897f2595f1812b9d9ff4b3vboxsyncDECLINLINE(void) vmsvgaSafeFifoBusyRegUpdate(PVGASTATE pThis, bool fState)
36c3589d6411416bba897f2595f1812b9d9ff4b3vboxsync ASMAtomicWriteU32(&pThis->svga.CTX_SUFF(pFIFO)[SVGA_FIFO_BUSY], fState);
36c3589d6411416bba897f2595f1812b9d9ff4b3vboxsync if (RT_UNLIKELY(fState != (pThis->svga.fBusy != 0)))
36c3589d6411416bba897f2595f1812b9d9ff4b3vboxsync /* Race / unfortunately scheduling. Highly unlikly. */
36c3589d6411416bba897f2595f1812b9d9ff4b3vboxsync ASMAtomicWriteU32(&pThis->svga.CTX_SUFF(pFIFO)[SVGA_FIFO_BUSY], fState != 0);
36c3589d6411416bba897f2595f1812b9d9ff4b3vboxsync } while (cLoops-- > 0 && fState != (pThis->svga.fBusy != 0));
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync * Write port register
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync * @returns VBox status code.
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync * @param pThis VMSVGA State
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync * @param u32 Value to write
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsyncPDMBOTHCBDECL(int) vmsvgaWritePort(PVGASTATE pThis, uint32_t u32)
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync PVMSVGASTATE pSVGAState = (PVMSVGASTATE)pThis->svga.pSVGAState;
0802b726efeabba46f90cb2b285de4dadaac9507vboxsync Log(("vmsvgaWritePort index=%s (%d) val=%#x\n", vmsvgaIndexToString(pThis), pThis->svga.u32IndexReg, u32));
3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync && pThis->last_scr_width == (unsigned)pThis->svga.uWidth
3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync && pThis->last_scr_height == (unsigned)pThis->svga.uHeight
3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync && pThis->last_width == (unsigned)pThis->svga.uWidth
3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync && pThis->last_height == (unsigned)pThis->svga.uHeight
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync /* Nothing to do. */
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync /* Make a backup copy of the first 32k in order to save font data etc. */
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync memcpy(pThis->svga.pFrameBufferBackup, pThis->vram_ptrR3, VMSVGA_FRAMEBUFFER_BACKUP_SIZE);
3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync if ( pThis->svga.uWidth == VMSVGA_VAL_UNINITIALIZED
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync /* Keep the current mode. */
3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync if ( pThis->svga.uWidth != VMSVGA_VAL_UNINITIALIZED
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync Log(("configured=%d busy=%d\n", pThis->svga.fConfigured, pThis->svga.pFIFOR3[SVGA_FIFO_BUSY]));
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync Log(("next %x stop %x\n", pFIFO[SVGA_FIFO_NEXT_CMD], pFIFO[SVGA_FIFO_STOP]));
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync /* Disable or enable dirty page tracking according to the current fTraces value. */
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync /* Restore the text mode backup. */
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync memcpy(pThis->vram_ptrR3, pThis->svga.pFrameBufferBackup, VMSVGA_FRAMEBUFFER_BACKUP_SIZE);
3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync/* pThis->svga.uHeight = -1;
3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync pThis->svga.uWidth = -1;
3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync pThis->svga.uBpp = -1;
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync pThis->svga.cbScanline = 0; */
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync /* Enable dirty page tracking again when going into legacy mode. */
0802b726efeabba46f90cb2b285de4dadaac9507vboxsync /* else: nop */
0802b726efeabba46f90cb2b285de4dadaac9507vboxsync /* else: nop */
c66e448632d5ef48cf6b896f02e750440f5c6586vboxsync /** @todo read-only?? */
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync case SVGA_REG_BITS_PER_PIXEL: /* Current bpp in the guest */
0802b726efeabba46f90cb2b285de4dadaac9507vboxsync /* else: nop */
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync case SVGA_REG_CONFIG_DONE: /* Set when memory area configured */
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync /* Disabling the FIFO enables tracing (dirty page detection) by default. */
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync case SVGA_REG_SYNC: /* See "FIFO Synchronization Registers" */
cb39011e69667689c166f1cdf95247b46fff324dvboxsync Log(("SVGA_REG_SYNC: SVGA_FIFO_BUSY=%d\n", pThis->svga.CTX_SUFF(pFIFO)[SVGA_FIFO_BUSY]));
36c3589d6411416bba897f2595f1812b9d9ff4b3vboxsync ASMAtomicWriteU32(&pThis->svga.fBusy, VMSVGA_BUSY_F_EMT_FORCE | VMSVGA_BUSY_F_FIFO);
36c3589d6411416bba897f2595f1812b9d9ff4b3vboxsync if (VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_BUSY, pThis->svga.CTX_SUFF(pFIFO)[SVGA_FIFO_MIN]))
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync /* Kick the FIFO thread to start processing commands again. */
cb39011e69667689c166f1cdf95247b46fff324dvboxsync SUPSemEventSignal(pThis->svga.pSupDrvSession, pThis->svga.FIFORequestSem);
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync /* else nothing to do. */
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync Log(("Sync ignored enabled=%d configured=%d\n", pThis->svga.fEnabled, pThis->svga.fConfigured));
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync case SVGA_REG_BUSY: /* See "FIFO Synchronization Registers" (read-only) */
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync case SVGA_REG_GUEST_ID: /* Set guest OS identifier */
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync case SVGA_REG_PITCHLOCK: /* Fixed pitch for all modes */
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync /* Irq pending after the above change? */
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync if (pThis->svga.u32IrqMask & pThis->svga.u32IrqStatus)
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync Log(("SVGA_REG_IRQMASK: Trigger interrupt with status %x\n", pThis->svga.u32IrqStatus));
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync PDMDevHlpPCISetIrqNoWait(pThis->CTX_SUFF(pDevIns), 0, 1);
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync PDMDevHlpPCISetIrqNoWait(pThis->CTX_SUFF(pDevIns), 0, 0);
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync /* Mouse cursor support */
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync /* Legacy multi-monitor support */
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync case SVGA_REG_NUM_GUEST_DISPLAYS:/* Number of guest displays in X/Y direction */
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync case SVGA_REG_DISPLAY_ID: /* Display ID for the following display attributes */
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync case SVGA_REG_DISPLAY_IS_PRIMARY:/* Whether this is a primary display */
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync case SVGA_REG_DISPLAY_POSITION_X:/* The display position x */
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync case SVGA_REG_DISPLAY_POSITION_Y:/* The display position y */
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync case SVGA_REG_DISPLAY_WIDTH: /* The display's width */
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync case SVGA_REG_DISPLAY_HEIGHT: /* The display's height */
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync /* See "Guest memory regions" below. */
0802b726efeabba46f90cb2b285de4dadaac9507vboxsync# else /* IN_RING3 */
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync /* Validate current GMR id. */
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync /* Free the old GMR if present. */
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync /* Just undefine the GMR? */
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync pSVGAState->aGMR[idGMR].paDesc = (PVMSVGAGMRDESCRIPTOR)RTMemAllocZ(cDescriptorsAllocated * sizeof(VMSVGAGMRDESCRIPTOR));
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync AssertReturn(pSVGAState->aGMR[idGMR].paDesc, VERR_NO_MEMORY);
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync /* Never cross a page boundary automatically. */
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync while (PHYS_PAGE_ADDRESS(GCPhys) == PHYS_PAGE_ADDRESS(GCPhysBase))
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync /* Read descriptor. */
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync rc = PDMDevHlpPhysRead(pThis->CTX_SUFF(pDevIns), GCPhys, &desc, sizeof(desc));
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync break; /* terminator */
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync /* Pointer to the next physical page of descriptors. */
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync pSVGAState->aGMR[idGMR].paDesc = (PVMSVGAGMRDESCRIPTOR)RTMemRealloc(pSVGAState->aGMR[idGMR].paDesc, cDescriptorsAllocated * sizeof(VMSVGAGMRDESCRIPTOR));
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync AssertReturn(pSVGAState->aGMR[idGMR].paDesc, VERR_NO_MEMORY);
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync pSVGAState->aGMR[idGMR].paDesc[iDescriptor].GCPhys = desc.ppn << PAGE_SHIFT;
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync pSVGAState->aGMR[idGMR].paDesc[iDescriptor++].numPages = desc.numPages;
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync pSVGAState->aGMR[idGMR].cbTotal += desc.numPages * PAGE_SIZE;
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync /* Continue with the next descriptor. */
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync pSVGAState->aGMR[idGMR].numDescriptors = iDescriptor;
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync Log(("Defined new gmr %x numDescriptors=%d cbTotal=%x\n", idGMR, iDescriptor, pSVGAState->aGMR[idGMR].cbTotal));
0802b726efeabba46f90cb2b285de4dadaac9507vboxsync# endif /* IN_RING3 */
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync#endif // VBOX_WITH_VMSVGA3D
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync case SVGA_REG_TRACES: /* Enable trace-based updates even when FIFO is on */
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync break; /* nothing to do */
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync case SVGA_REG_TOP: /* Must be 1 more than the last register */
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync case SVGA_PALETTE_BASE: /* Base of SVGA color map */
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync /* Next 768 (== 256*3) registers exist for colormap */
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync Log(("Write to deprecated register %x - val %x ignored\n", pThis->svga.u32IndexReg, u32));
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync case SVGA_REG_SCRATCH_SIZE: /* Number of scratch registers */
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync case SVGA_REG_MEM_REGS: /* Number of FIFO registers */
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync case SVGA_REG_GMRS_MAX_PAGES: /* Maximum number of 4KB pages for all GMRs */
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync case SVGA_REG_MEMORY_SIZE: /* Total dedicated device memory excluding FIFO */
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync /* Read only - ignore. */
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync Log(("Write to R/O register %x - val %x ignored\n", pThis->svga.u32IndexReg, u32));
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync && pThis->svga.u32IndexReg < SVGA_SCRATCH_BASE + pThis->svga.cScratchRegion)
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync pThis->svga.au32ScratchRegion[pThis->svga.u32IndexReg - SVGA_SCRATCH_BASE] = u32;
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync * Port I/O Handler for IN operations.
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync * @returns VINF_SUCCESS or VINF_EM_*.
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync * @returns VERR_IOM_IOPORT_UNUSED if the port is really unused and a ~0 value should be returned.
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync * @param pDevIns The device instance.
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync * @param pvUser User argument.
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync * @param uPort Port number used for the IN operation.
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync * @param pu32 Where to store the result. This is always a 32-bit
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync * variable regardless of what @a cb might say.
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync * @param cb Number of bytes read.
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsyncPDMBOTHCBDECL(int) vmsvgaIORead(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t *pu32, unsigned cb)
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync PVGASTATE pThis = PDMINS_2_DATA(pDevIns, PVGASTATE);
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync /* Ignore non-dword accesses. */
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync Log(("Ignoring non-dword read at %x cb=%d\n", Port, cb));
3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync LogFlow(("vmsvgaIORead: SVGA_IRQSTATUS_PORT %x\n", pThis->svga.u32IrqStatus));
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync * Port I/O Handler for OUT operations.
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync * @returns VINF_SUCCESS or VINF_EM_*.
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync * @param pDevIns The device instance.
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync * @param pvUser User argument.
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync * @param uPort Port number used for the OUT operation.
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync * @param u32 The value to output.
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync * @param cb The value size in bytes.
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsyncPDMBOTHCBDECL(int) vmsvgaIOWrite(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb)
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync PVGASTATE pThis = PDMINS_2_DATA(pDevIns, PVGASTATE);
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync /* Ignore non-dword accesses. */
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync Log(("Ignoring non-dword write at %x val=%x cb=%d\n", Port, u32, cb));
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync Log(("vmsvgaIOWrite SVGA_IRQSTATUS_PORT %x: status %x -> %x\n", u32, pThis->svga.u32IrqStatus, pThis->svga.u32IrqStatus & ~u32));
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync /* Clear the irq in case all events have been cleared. */
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync if (!(pThis->svga.u32IrqStatus & pThis->svga.u32IrqMask))
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync * Handle LFB access.
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync * @returns VBox status code.
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync * @param pVM VM handle.
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync * @param pThis VGA device instance data.
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync * @param GCPhys The access physical address.
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync * @param fWriteAccess Read or write access
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsyncstatic int vmsvgaFIFOAccess(PVM pVM, PVGASTATE pThis, RTGCPHYS GCPhys, bool fWriteAccess)
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync RTGCPHYS GCPhysOffset = GCPhys - pThis->svga.GCPhysFIFO;
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_MIN = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_MAX = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_NEXT_CMD = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_STOP = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_CAPABILITIES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_FLAGS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_FENCE = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_HWVERSION = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_PITCHLOCK = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_CURSOR_ON = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_CURSOR_X = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_CURSOR_Y = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_CURSOR_COUNT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_CURSOR_LAST_UPDATED = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_RESERVED = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_CURSOR_SCREEN_ID = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_DEAD = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_HWVERSION_REVISED = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_3D = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_LIGHTS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_TEXTURES:
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_TEXTURES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_CLIP_PLANES:
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_CLIP_PLANES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_VERTEX_SHADER_VERSION:
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_VERTEX_SHADER_VERSION = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_VERTEX_SHADER:
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_VERTEX_SHADER = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_FRAGMENT_SHADER_VERSION:
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_FRAGMENT_SHADER_VERSION = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_FRAGMENT_SHADER:
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_FRAGMENT_SHADER = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_RENDER_TARGETS:
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_RENDER_TARGETS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_S23E8_TEXTURES:
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_S23E8_TEXTURES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_S10E5_TEXTURES:
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_S10E5_TEXTURES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_FIXED_VERTEXBLEND:
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_FIXED_VERTEXBLEND = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_D16_BUFFER_FORMAT:
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_D16_BUFFER_FORMAT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_D24S8_BUFFER_FORMAT:
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_D24S8_BUFFER_FORMAT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_D24X8_BUFFER_FORMAT:
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_D24X8_BUFFER_FORMAT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_QUERY_TYPES:
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_QUERY_TYPES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_TEXTURE_GRADIENT_SAMPLING:
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_TEXTURE_GRADIENT_SAMPLING = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_POINT_SIZE:
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_POINT_SIZE = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_SHADER_TEXTURES:
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_SHADER_TEXTURES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_TEXTURE_WIDTH:
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_TEXTURE_WIDTH = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_TEXTURE_HEIGHT:
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_TEXTURE_HEIGHT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_VOLUME_EXTENT:
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_VOLUME_EXTENT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_TEXTURE_REPEAT:
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_TEXTURE_REPEAT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_TEXTURE_ASPECT_RATIO:
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_TEXTURE_ASPECT_RATIO = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_TEXTURE_ANISOTROPY:
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_TEXTURE_ANISOTROPY = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_PRIMITIVE_COUNT:
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_PRIMITIVE_COUNT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_VERTEX_INDEX:
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_VERTEX_INDEX = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_VERTEX_SHADER_INSTRUCTIONS:
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_VERTEX_SHADER_INSTRUCTIONS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_FRAGMENT_SHADER_INSTRUCTIONS:
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_FRAGMENT_SHADER_INSTRUCTIONS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_VERTEX_SHADER_TEMPS:
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_VERTEX_SHADER_TEMPS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_FRAGMENT_SHADER_TEMPS:
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_FRAGMENT_SHADER_TEMPS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_TEXTURE_OPS:
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_TEXTURE_OPS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_X8R8G8B8:
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_X8R8G8B8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_A8R8G8B8:
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_A8R8G8B8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_A2R10G10B10:
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_A2R10G10B10 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_X1R5G5B5:
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_X1R5G5B5 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_A1R5G5B5:
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_A1R5G5B5 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_A4R4G4B4:
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_A4R4G4B4 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_R5G6B5:
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_R5G6B5 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE16:
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE16 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE8_ALPHA8:
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE8_ALPHA8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_ALPHA8:
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_ALPHA8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE8:
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_Z_D16:
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_Z_D16 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_Z_D24S8:
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_Z_D24S8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_Z_D24X8:
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_Z_D24X8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_DXT1:
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_DXT1 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_DXT2:
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_DXT2 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_DXT3:
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_DXT3 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_DXT4:
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_DXT4 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_DXT5:
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_DXT5 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_BUMPX8L8V8U8:
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_BUMPX8L8V8U8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_A2W10V10U10:
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_A2W10V10U10 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_BUMPU8V8:
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_BUMPU8V8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_Q8W8V8U8:
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_Q8W8V8U8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_CxV8U8:
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_CxV8U8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_R_S10E5:
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_R_S10E5 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_R_S23E8:
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_R_S23E8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_RG_S10E5:
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_RG_S10E5 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_RG_S23E8:
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_RG_S23E8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_ARGB_S10E5:
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_ARGB_S10E5 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_ARGB_S23E8:
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_ARGB_S23E8 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_VERTEX_SHADER_TEXTURES:
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_VERTEX_SHADER_TEXTURES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_SIMULTANEOUS_RENDER_TARGETS:
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_SIMULTANEOUS_RENDER_TARGETS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_V16U16:
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_V16U16 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_G16R16:
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_G16R16 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_A16B16G16R16:
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_A16B16G16R16 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_UYVY:
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_UYVY = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_YUY2:
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_YUY2 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MULTISAMPLE_NONMASKABLESAMPLES:
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MULTISAMPLE_NONMASKABLESAMPLES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MULTISAMPLE_MASKABLESAMPLES:
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MULTISAMPLE_MASKABLESAMPLES = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_ALPHATOCOVERAGE:
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_ALPHATOCOVERAGE = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SUPERSAMPLE:
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SUPERSAMPLE = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_AUTOGENMIPMAPS:
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_AUTOGENMIPMAPS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_NV12:
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_NV12 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_AYUV:
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_AYUV = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_CONTEXT_IDS:
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_CONTEXT_IDS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_MAX_SURFACE_IDS:
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_MAX_SURFACE_IDS = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_Z_DF16:
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_Z_DF16 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_Z_DF24:
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_Z_DF24 = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_Z_D24S8_INT:
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_Z_D24S8_INT = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_BC4_UNORM:
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_BC4_UNORM = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync case SVGA_FIFO_3D_CAPS + SVGA3D_DEVCAP_SURFACEFMT_BC5_UNORM:
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS SVGA3D_DEVCAP_SURFACEFMT_BC5_UNORM = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_3D_CAPS_LAST = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_GUEST_3D_HWVERSION = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_FENCE_GOAL = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync Log(("vmsvgaFIFOAccess [0x%x]: %s SVGA_FIFO_BUSY = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", pFIFO[GCPhysOffset >> 2]));
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync Log(("vmsvgaFIFOAccess [0x%x]: %s access at offset %x = %x\n", GCPhysOffset >> 2, (fWriteAccess) ? "WRITE" : "READ", GCPhysOffset, pFIFO[GCPhysOffset >> 2]));
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync * HC access handler for the FIFO.
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync * @returns VINF_SUCCESS if the handler have carried out the operation.
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync * @returns VINF_PGM_HANDLER_DO_DEFAULT if the caller should carry out the access operation.
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync * @param pVM VM Handle.
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync * @param GCPhys The physical address the guest is writing to.
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync * @param pvPhys The HC mapping of that address.
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync * @param pvBuf What the guest is reading/writing.
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync * @param cbBuf How much it's reading/writing.
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync * @param enmAccessType The access type.
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync * @param pvUser User argument.
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsyncstatic DECLCALLBACK(int) vmsvgaR3FIFOAccessHandler(PVM pVM, RTGCPHYS GCPhys, void *pvPhys, void *pvBuf, size_t cbBuf, PGMACCESSTYPE enmAccessType, void *pvUser)
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync rc = vmsvgaFIFOAccess(pVM, pThis, GCPhys, enmAccessType == PGMACCESSTYPE_WRITE);
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync# endif /* IN_RING3 */
0802b726efeabba46f90cb2b285de4dadaac9507vboxsync#endif /* DEBUG_FIFO_ACCESS */
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync * HC access handler for the FIFO.
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync * @returns VINF_SUCCESS if the handler have carried out the operation.
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync * @returns VINF_PGM_HANDLER_DO_DEFAULT if the caller should carry out the access operation.
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync * @param pVM VM Handle.
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync * @param GCPhys The physical address the guest is writing to.
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync * @param pvPhys The HC mapping of that address.
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync * @param pvBuf What the guest is reading/writing.
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync * @param cbBuf How much it's reading/writing.
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync * @param enmAccessType The access type.
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync * @param pvUser User argument.
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsyncstatic DECLCALLBACK(int) vmsvgaR3GMRAccessHandler(PVM pVM, RTGCPHYS GCPhys, void *pvPhys, void *pvBuf, size_t cbBuf, PGMACCESSTYPE enmAccessType, void *pvUser)
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync PVMSVGASTATE pSVGAState = (PVMSVGASTATE)pThis->svga.pSVGAState;
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync Log(("vmsvgaR3GMRAccessHandler: GMR access to page %RGp\n", GCPhys));
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync for (uint32_t i = 0; i < RT_ELEMENTS(pSVGAState->aGMR); i++)
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync for (uint32_t j = 0; j < pGMR->numDescriptors; j++)
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync && GCPhys < pGMR->paDesc[j].GCPhys + pGMR->paDesc[j].numPages * PAGE_SIZE)
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync * Turn off the write handler for this particular page and make it R/W.
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync * Then return telling the caller to restart the guest instruction.
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync int rc = PGMHandlerPhysicalPageTempOff(pVM, pGMR->paDesc[j].GCPhys, GCPhys);
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync/* Callback handler for VMR3ReqCallWait */
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsyncstatic DECLCALLBACK(int) vmsvgaRegisterGMR(PPDMDEVINS pDevIns, uint32_t gmrId)
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync PVGASTATE pThis = PDMINS_2_DATA(pDevIns, PVGASTATE);
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync PVMSVGASTATE pSVGAState = (PVMSVGASTATE)pThis->svga.pSVGAState;
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync for (uint32_t i = 0; i < pGMR->numDescriptors; i++)
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync rc = PGMR3HandlerPhysicalRegister(PDMDevHlpGetVM(pThis->pDevInsR3),
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync pGMR->paDesc[i].GCPhys, pGMR->paDesc[i].GCPhys + pGMR->paDesc[i].numPages * PAGE_SIZE - 1,
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync "VMSVGA GMR");
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync/* Callback handler for VMR3ReqCallWait */
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsyncstatic DECLCALLBACK(int) vmsvgaUnregisterGMR(PPDMDEVINS pDevIns, uint32_t gmrId)
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync PVGASTATE pThis = PDMINS_2_DATA(pDevIns, PVGASTATE);
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync PVMSVGASTATE pSVGAState = (PVMSVGASTATE)pThis->svga.pSVGAState;
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync for (uint32_t i = 0; i < pGMR->numDescriptors; i++)
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync int rc = PGMHandlerPhysicalDeregister(PDMDevHlpGetVM(pThis->pDevInsR3), pGMR->paDesc[i].GCPhys);
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync/* Callback handler for VMR3ReqCallWait */
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsyncstatic DECLCALLBACK(int) vmsvgaResetGMRHandlers(PVGASTATE pThis)
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync PVMSVGASTATE pSVGAState = (PVMSVGASTATE)pThis->svga.pSVGAState;
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync for (uint32_t i = 0; i < RT_ELEMENTS(pSVGAState->aGMR); i++)
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync for (uint32_t j = 0; j < pGMR->numDescriptors; j++)
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync int rc = PGMHandlerPhysicalReset(PDMDevHlpGetVM(pThis->pDevInsR3), pGMR->paDesc[j].GCPhys);
0802b726efeabba46f90cb2b285de4dadaac9507vboxsync# endif /* IN_RING3 */
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync#endif /* DEBUG_GMR_ACCESS */
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync/* -=-=-=-=-=- Ring 3 -=-=-=-=-=- */
36c3589d6411416bba897f2595f1812b9d9ff4b3vboxsync * Marks the FIFO non-busy, notifying any waiting EMTs.
36c3589d6411416bba897f2595f1812b9d9ff4b3vboxsync * @param pThis The VGA state.
36c3589d6411416bba897f2595f1812b9d9ff4b3vboxsync * @param pSVGAState Pointer to the ring-3 only SVGA state data.
36c3589d6411416bba897f2595f1812b9d9ff4b3vboxsync * @param offFifoMin The start byte offset of the command FIFO.
36c3589d6411416bba897f2595f1812b9d9ff4b3vboxsyncstatic void vmsvgaFifoSetNotBusy(PVGASTATE pThis, PVMSVGASTATE pSVGAState, uint32_t offFifoMin)
36c3589d6411416bba897f2595f1812b9d9ff4b3vboxsync ASMAtomicAndU32(&pThis->svga.fBusy, ~VMSVGA_BUSY_F_FIFO);
36c3589d6411416bba897f2595f1812b9d9ff4b3vboxsync if (VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_BUSY, offFifoMin))
36c3589d6411416bba897f2595f1812b9d9ff4b3vboxsync vmsvgaSafeFifoBusyRegUpdate(pThis, pThis->svga.fBusy != 0);
36c3589d6411416bba897f2595f1812b9d9ff4b3vboxsync /* Wake up any waiting EMTs. */
51163b26ef6e81898acf6db392f1ca751335f71bvboxsync VMCPUID idCpu = VMCpuSetFindLastPresentInternal(&pSVGAState->BusyDelayedEmts);
51163b26ef6e81898acf6db392f1ca751335f71bvboxsync while (idCpu-- > 0)
51163b26ef6e81898acf6db392f1ca751335f71bvboxsync if (VMCPUSET_IS_PRESENT(&pSVGAState->BusyDelayedEmts, idCpu))
36c3589d6411416bba897f2595f1812b9d9ff4b3vboxsync int rc2 = RTSemEventMultiSignal(pSVGAState->hBusyDelayedEmts);
c598affb4a1578b0e7be124835a70c4f08c5d2bdvboxsync * Reads (more) payload into the command buffer.
c598affb4a1578b0e7be124835a70c4f08c5d2bdvboxsync * @returns pbBounceBuf on success
c598affb4a1578b0e7be124835a70c4f08c5d2bdvboxsync * @retval (void *)1 if the thread was requested to stop.
c598affb4a1578b0e7be124835a70c4f08c5d2bdvboxsync * @retval NULL on FIFO error.
c598affb4a1578b0e7be124835a70c4f08c5d2bdvboxsync * @param cbPayloadReq The number of bytes of payload requested.
c598affb4a1578b0e7be124835a70c4f08c5d2bdvboxsync * @param pFIFO The FIFO.
c598affb4a1578b0e7be124835a70c4f08c5d2bdvboxsync * @param offCurrentCmd The FIFO byte offset of the current command.
c598affb4a1578b0e7be124835a70c4f08c5d2bdvboxsync * @param offFifoMin The start byte offset of the command FIFO.
c598affb4a1578b0e7be124835a70c4f08c5d2bdvboxsync * @param offFifoMax The end byte offset of the command FIFO.
c598affb4a1578b0e7be124835a70c4f08c5d2bdvboxsync * @param pbBounceBuf The bounch buffer. Same size as the entire FIFO, so
c598affb4a1578b0e7be124835a70c4f08c5d2bdvboxsync * always sufficient size.
c598affb4a1578b0e7be124835a70c4f08c5d2bdvboxsync * @param pcbAlreadyRead How much payload we've already read into the bounce
c598affb4a1578b0e7be124835a70c4f08c5d2bdvboxsync * buffer. (We will NEVER re-read anything.)
c66e448632d5ef48cf6b896f02e750440f5c6586vboxsync * @param pThread The calling PDM thread handle.
36c3589d6411416bba897f2595f1812b9d9ff4b3vboxsync * @param pThis The VGA state.
c66e448632d5ef48cf6b896f02e750440f5c6586vboxsync * @param pSVGAState Pointer to the ring-3 only SVGA state data. For
c66e448632d5ef48cf6b896f02e750440f5c6586vboxsync * statistics collection.
c66e448632d5ef48cf6b896f02e750440f5c6586vboxsyncstatic void *vmsvgaFIFOGetCmdPayload(uint32_t cbPayloadReq, uint32_t volatile *pFIFO,
c66e448632d5ef48cf6b896f02e750440f5c6586vboxsync uint32_t offCurrentCmd, uint32_t offFifoMin, uint32_t offFifoMax,
c66e448632d5ef48cf6b896f02e750440f5c6586vboxsync PPDMTHREAD pThread, PVGASTATE pThis, PVMSVGASTATE pSVGAState)
c598affb4a1578b0e7be124835a70c4f08c5d2bdvboxsync Assert(offCurrentCmd >= offFifoMin && offCurrentCmd < offFifoMax);
c598affb4a1578b0e7be124835a70c4f08c5d2bdvboxsync * Check if the requested payload size has already been satisfied .
c598affb4a1578b0e7be124835a70c4f08c5d2bdvboxsync * When called to read more, the caller is responsible for making sure the .
c598affb4a1578b0e7be124835a70c4f08c5d2bdvboxsync * new command size (cbRequsted) never is smaller than what has already .
c598affb4a1578b0e7be124835a70c4f08c5d2bdvboxsync * been read.
c598affb4a1578b0e7be124835a70c4f08c5d2bdvboxsync AssertLogRelReturn(cbPayloadReq == cbAlreadyRead, NULL);
c598affb4a1578b0e7be124835a70c4f08c5d2bdvboxsync * Commands bigger than the fifo buffer are invalid.
c598affb4a1578b0e7be124835a70c4f08c5d2bdvboxsync uint32_t const cbFifoCmd = offFifoMax - offFifoMin;
c66e448632d5ef48cf6b896f02e750440f5c6586vboxsync AssertMsgReturnStmt(cbPayloadReq <= cbFifoCmd, ("cbPayloadReq=%#x cbFifoCmd=%#x\n", cbPayloadReq, cbFifoCmd),
c598affb4a1578b0e7be124835a70c4f08c5d2bdvboxsync * Move offCurrentCmd past the command dword.
c598affb4a1578b0e7be124835a70c4f08c5d2bdvboxsync * Do we have sufficient payload data available already?
c598affb4a1578b0e7be124835a70c4f08c5d2bdvboxsync LogRelMax(16, ("vmsvgaFIFOGetCmdPayload: Invalid offNextCmd=%#x (offFifoMin=%#x offFifoMax=%#x)\n",
c598affb4a1578b0e7be124835a70c4f08c5d2bdvboxsync LogRelMax(16, ("vmsvgaFIFOGetCmdPayload: Invalid offNextCmd=%#x (offFifoMin=%#x offFifoMax=%#x)\n",
c598affb4a1578b0e7be124835a70c4f08c5d2bdvboxsync * Insufficient, must wait for it to arrive.
c66e448632d5ef48cf6b896f02e750440f5c6586vboxsync STAM_REL_PROFILE_START(&pSVGAState->StatFifoStalls, Stall);
c66e448632d5ef48cf6b896f02e750440f5c6586vboxsync for (uint32_t i = 0;; i++)
c66e448632d5ef48cf6b896f02e750440f5c6586vboxsync STAM_REL_PROFILE_STOP(&pSVGAState->StatFifoStalls, Stall);
c66e448632d5ef48cf6b896f02e750440f5c6586vboxsync Log(("Guest still copying (%x vs %x) current %x next %x stop %x loop %u; sleep a bit\n",
c66e448632d5ef48cf6b896f02e750440f5c6586vboxsync cbPayloadReq, cbAfter + cbBefore, offCurrentCmd, offNextCmd, pFIFO[SVGA_FIFO_STOP], i));
c66e448632d5ef48cf6b896f02e750440f5c6586vboxsync SUPSemEventWaitNoResume(pThis->svga.pSupDrvSession, pThis->svga.FIFORequestSem, i < 16 ? 1 : 2);
c598affb4a1578b0e7be124835a70c4f08c5d2bdvboxsync cbAfter = RT_MIN(offNextCmd, offFifoMax) - offCurrentCmd;
c598affb4a1578b0e7be124835a70c4f08c5d2bdvboxsync cbBefore = RT_MAX(offNextCmd, offFifoMin) - offFifoMin;
c66e448632d5ef48cf6b896f02e750440f5c6586vboxsync STAM_REL_PROFILE_STOP(&pSVGAState->StatFifoStalls, Stall);
c598affb4a1578b0e7be124835a70c4f08c5d2bdvboxsync * Copy out the memory and update what pcbAlreadyRead points to.
c598affb4a1578b0e7be124835a70c4f08c5d2bdvboxsync LogFlow(("Split data buffer at %x (%u-%u)\n", offCurrentCmd, cbAfter, cbBefore));
c598affb4a1578b0e7be124835a70c4f08c5d2bdvboxsync (uint8_t *)pFIFO + offFifoMin + cbAlreadyRead - cbAfter,
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync/* The async FIFO handling thread. */
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsyncstatic DECLCALLBACK(int) vmsvgaFIFOLoop(PPDMDEVINS pDevIns, PPDMTHREAD pThread)
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync PVMSVGASTATE pSVGAState = (PVMSVGASTATE)pThis->svga.pSVGAState;
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync if (pThread->enmState == PDMTHREADSTATE_INITIALIZING)
c66e448632d5ef48cf6b896f02e750440f5c6586vboxsync * Signal the semaphore to make sure we don't wait for 250 after a
c66e448632d5ef48cf6b896f02e750440f5c6586vboxsync * suspend & resume scenario (see vmsvgaFIFOGetCmdPayload).
c66e448632d5ef48cf6b896f02e750440f5c6586vboxsync SUPSemEventSignal(pThis->svga.pSupDrvSession, pThis->svga.FIFORequestSem);
c598affb4a1578b0e7be124835a70c4f08c5d2bdvboxsync * Allocate a bounce buffer for command we get from the FIFO.
c598affb4a1578b0e7be124835a70c4f08c5d2bdvboxsync * (All code must return via the end of the function to free this buffer.)
c598affb4a1578b0e7be124835a70c4f08c5d2bdvboxsync uint8_t *pbBounceBuf = (uint8_t *)RTMemAllocZ(VMSVGA_FIFO_SIZE);
c598affb4a1578b0e7be124835a70c4f08c5d2bdvboxsync uint32_t volatile * const pFIFO = pThis->svga.pFIFOR3;
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync while (pThread->enmState == PDMTHREADSTATE_RUNNING)
36c3589d6411416bba897f2595f1812b9d9ff4b3vboxsync * Wait for at most 250 ms to start polling.
cb39011e69667689c166f1cdf95247b46fff324dvboxsync rc = SUPSemEventWaitNoResume(pThis->svga.pSupDrvSession, pThis->svga.FIFORequestSem, 250);
cb39011e69667689c166f1cdf95247b46fff324dvboxsync AssertBreak(RT_SUCCESS(rc) || rc == VERR_TIMEOUT || rc == VERR_INTERRUPTED);
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync LogFlow(("vmsvgaFIFOLoop: thread state %x\n", pThread->enmState));
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync if (pFIFO[SVGA_FIFO_NEXT_CMD] == pFIFO[SVGA_FIFO_STOP])
c66e448632d5ef48cf6b896f02e750440f5c6586vboxsync STAM_REL_COUNTER_INC(&pSVGAState->StatFifoTodoTimeout);
c66e448632d5ef48cf6b896f02e750440f5c6586vboxsync else if (pFIFO[SVGA_FIFO_NEXT_CMD] != pFIFO[SVGA_FIFO_STOP])
c66e448632d5ef48cf6b896f02e750440f5c6586vboxsync STAM_REL_COUNTER_INC(&pSVGAState->StatFifoTodoWoken);
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync Log(("vmsvgaFIFOLoop: enabled=%d configured=%d busy=%d\n", pThis->svga.fEnabled, pThis->svga.fConfigured, pThis->svga.pFIFOR3[SVGA_FIFO_BUSY]));
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync Log(("vmsvgaFIFOLoop: min %x max %x\n", pFIFO[SVGA_FIFO_MIN], pFIFO[SVGA_FIFO_MAX]));
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync Log(("vmsvgaFIFOLoop: next %x stop %x\n", pFIFO[SVGA_FIFO_NEXT_CMD], pFIFO[SVGA_FIFO_STOP]));
36c3589d6411416bba897f2595f1812b9d9ff4b3vboxsync * Handle external commands.
3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync if (pThis->svga.u8FIFOExtCommand != VMSVGA_FIFO_EXTCMD_NONE)
3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync /* The 3d subsystem must be reset from the fifo thread. */
3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync Log(("vmsvgaFIFOLoop: terminate the fifo thread.\n"));
3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync /* The 3d subsystem must be shut down from the fifo thread. */
3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync Log(("vmsvgaFIFOLoop: VMSVGA_FIFO_EXTCMD_SAVESTATE.\n"));
3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync vmsvga3dSaveExec(pThis, (PSSMHANDLE)pThis->svga.pFIFOExtCmdParam);
3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync Log(("vmsvgaFIFOLoop: VMSVGA_FIFO_EXTCMD_LOADSTATE.\n"));
3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync PVMSVGA_STATE_LOAD pLoadState = (PVMSVGA_STATE_LOAD)pThis->svga.pFIFOExtCmdParam;
3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync vmsvga3dLoadExec(pThis, pLoadState->pSSM, pLoadState->uVersion, pLoadState->uPass);
3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync pThis->svga.u8FIFOExtCommand = VMSVGA_FIFO_EXTCMD_NONE;
3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync /* Signal the end of the external command. */
36c3589d6411416bba897f2595f1812b9d9ff4b3vboxsync vmsvgaFifoSetNotBusy(pThis, pSVGAState, pFIFO[SVGA_FIFO_MIN]);
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync continue; /* device not enabled. */
c598affb4a1578b0e7be124835a70c4f08c5d2bdvboxsync * Get and check the min/max values. We ASSUME that they will remain
c598affb4a1578b0e7be124835a70c4f08c5d2bdvboxsync * unchanged while we process requests. A further ASSUMPTION is that
c598affb4a1578b0e7be124835a70c4f08c5d2bdvboxsync * the guest won't mess with SVGA_FIFO_NEXT_CMD while we're busy, so
c598affb4a1578b0e7be124835a70c4f08c5d2bdvboxsync * we don't read it back while in the loop.
c598affb4a1578b0e7be124835a70c4f08c5d2bdvboxsync if (RT_UNLIKELY( !VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_STOP, offFifoMin)
36c3589d6411416bba897f2595f1812b9d9ff4b3vboxsync LogRelMax(8, ("vmsvgaFIFOLoop: Bad fifo: min=%#x stop=%#x max=%#x\n", offFifoMin, offCurrentCmd, offFifoMax));
36c3589d6411416bba897f2595f1812b9d9ff4b3vboxsync vmsvgaFifoSetNotBusy(pThis, pSVGAState, offFifoMin);
c598affb4a1578b0e7be124835a70c4f08c5d2bdvboxsync LogRelMax(8, ("vmsvgaFIFOLoop: Misaligned offCurrentCmd=%#x?\n", offCurrentCmd));
c598affb4a1578b0e7be124835a70c4f08c5d2bdvboxsync * Macro for shortening calls to vmsvgaFIFOGetCmdPayload.
c598affb4a1578b0e7be124835a70c4f08c5d2bdvboxsync * Will break out of the switch on failure.
c598affb4a1578b0e7be124835a70c4f08c5d2bdvboxsync * Will restart and quit the loop if the thread was requested to stop.
c598affb4a1578b0e7be124835a70c4f08c5d2bdvboxsync * @param a_cbPayloadReq How much payload to fetch.
c598affb4a1578b0e7be124835a70c4f08c5d2bdvboxsync * @remarks Access a bunch of variables in the current scope!
c598affb4a1578b0e7be124835a70c4f08c5d2bdvboxsync# define VMSVGAFIFO_GET_CMD_BUFFER_BREAK(a_PtrVar, a_Type, a_cbPayloadReq) \
c66e448632d5ef48cf6b896f02e750440f5c6586vboxsync (a_PtrVar) = (a_Type *)vmsvgaFIFOGetCmdPayload((a_cbPayloadReq), pFIFO, offCurrentCmd, offFifoMin, offFifoMax, \
c66e448632d5ef48cf6b896f02e750440f5c6586vboxsync pbBounceBuf, &cbPayload, pThread, pThis, pSVGAState); \
c598affb4a1578b0e7be124835a70c4f08c5d2bdvboxsync if (RT_UNLIKELY((uintptr_t)(a_PtrVar) < 2)) { if ((uintptr_t)(a_PtrVar) == 1) continue; break; } \
c598affb4a1578b0e7be124835a70c4f08c5d2bdvboxsync } else do {} while (0)
c598affb4a1578b0e7be124835a70c4f08c5d2bdvboxsync * Macro for shortening calls to vmsvgaFIFOGetCmdPayload for refetching the
c598affb4a1578b0e7be124835a70c4f08c5d2bdvboxsync * buffer after figuring out the actual command size.
c598affb4a1578b0e7be124835a70c4f08c5d2bdvboxsync * Will break out of the switch on failure.
c598affb4a1578b0e7be124835a70c4f08c5d2bdvboxsync * @param a_cbPayloadReq How much payload to fetch.
c598affb4a1578b0e7be124835a70c4f08c5d2bdvboxsync * @remarks Access a bunch of variables in the current scope!
c598affb4a1578b0e7be124835a70c4f08c5d2bdvboxsync# define VMSVGAFIFO_GET_MORE_CMD_BUFFER_BREAK(a_PtrVar, a_Type, a_cbPayloadReq) \
c598affb4a1578b0e7be124835a70c4f08c5d2bdvboxsync VMSVGAFIFO_GET_CMD_BUFFER_BREAK(a_PtrVar, a_Type, a_cbPayloadReq); \
c598affb4a1578b0e7be124835a70c4f08c5d2bdvboxsync } else do {} while (0)
c598affb4a1578b0e7be124835a70c4f08c5d2bdvboxsync * Mark the FIFO as busy.
36c3589d6411416bba897f2595f1812b9d9ff4b3vboxsync ASMAtomicWriteU32(&pThis->svga.fBusy, VMSVGA_BUSY_F_FIFO);
c598affb4a1578b0e7be124835a70c4f08c5d2bdvboxsync if (VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_BUSY, offFifoMin))
c598affb4a1578b0e7be124835a70c4f08c5d2bdvboxsync * Execute all queued FIFO commands.
c598affb4a1578b0e7be124835a70c4f08c5d2bdvboxsync * Quit if pending external command or changes in the thread state.
c598affb4a1578b0e7be124835a70c4f08c5d2bdvboxsync while ( !(fDone = pFIFO[SVGA_FIFO_NEXT_CMD] == offCurrentCmd)
c598affb4a1578b0e7be124835a70c4f08c5d2bdvboxsync Assert(offCurrentCmd < offFifoMax && offCurrentCmd >= offFifoMin);
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync /* First check any pending actions. */
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync if (ASMBitTestAndClear(&pThis->svga.u32ActionFlags, VMSVGA_ACTION_CHANGEMODE_BIT))
0802b726efeabba46f90cb2b285de4dadaac9507vboxsync {/*nothing*/}
3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync /* Check for pending external commands. */
3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync if (pThis->svga.u8FIFOExtCommand != VMSVGA_FIFO_EXTCMD_NONE)
c598affb4a1578b0e7be124835a70c4f08c5d2bdvboxsync * Process the command.
c598affb4a1578b0e7be124835a70c4f08c5d2bdvboxsync SVGAFifoCmdId const enmCmdId = (SVGAFifoCmdId)pFIFO[offCurrentCmd / sizeof(uint32_t)];
c598affb4a1578b0e7be124835a70c4f08c5d2bdvboxsync LogFlow(("vmsvgaFIFOLoop: FIFO command (iCmd=0x%x) %s 0x%x\n",
c598affb4a1578b0e7be124835a70c4f08c5d2bdvboxsync offCurrentCmd / sizeof(uint32_t), vmsvgaFIFOCmdToString(enmCmdId), enmCmdId));
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync /* Nothing to do. */
c598affb4a1578b0e7be124835a70c4f08c5d2bdvboxsync VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmdFence, SVGAFifoCmdFence, sizeof(*pCmdFence));
c598affb4a1578b0e7be124835a70c4f08c5d2bdvboxsync if (VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_FENCE, offFifoMin))
c598affb4a1578b0e7be124835a70c4f08c5d2bdvboxsync Log(("vmsvgaFIFOLoop: SVGA_CMD_FENCE %x\n", pCmdFence->fence));
c598affb4a1578b0e7be124835a70c4f08c5d2bdvboxsync if (pThis->svga.u32IrqMask & SVGA_IRQFLAG_ANY_FENCE)
c598affb4a1578b0e7be124835a70c4f08c5d2bdvboxsync if ( VMSVGA_IS_VALID_FIFO_REG(SVGA_FIFO_FENCE_GOAL, offFifoMin)
c598affb4a1578b0e7be124835a70c4f08c5d2bdvboxsync && (pThis->svga.u32IrqMask & SVGA_IRQFLAG_FENCE_GOAL)
c598affb4a1578b0e7be124835a70c4f08c5d2bdvboxsync && pFIFO[SVGA_FIFO_FENCE_GOAL] == pCmdFence->fence)
c598affb4a1578b0e7be124835a70c4f08c5d2bdvboxsync Log(("vmsvgaFIFOLoop: fence goal reached irq (fence=%x)\n", pCmdFence->fence));
c598affb4a1578b0e7be124835a70c4f08c5d2bdvboxsync Log(("SVGA_CMD_FENCE is bogus when offFifoMin is %#x!\n", offFifoMin));
c598affb4a1578b0e7be124835a70c4f08c5d2bdvboxsync VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pUpdate, SVGAFifoCmdUpdate, sizeof(*pUpdate));
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync Log(("vmsvgaFIFOLoop: UPDATE (%d,%d)(%d,%d)\n", pUpdate->x, pUpdate->y, pUpdate->width, pUpdate->height));
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync vgaR3UpdateDisplay(pThis, pUpdate->x, pUpdate->y, pUpdate->width, pUpdate->height);
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync /* Followed by bitmap data. */
c598affb4a1578b0e7be124835a70c4f08c5d2bdvboxsync VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCursor, SVGAFifoCmdDefineCursor, sizeof(*pCursor));
c598affb4a1578b0e7be124835a70c4f08c5d2bdvboxsync AssertFailed(); /** @todo implement when necessary. */
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync /* Followed by bitmap data. */
c598affb4a1578b0e7be124835a70c4f08c5d2bdvboxsync VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCursor, SVGAFifoCmdDefineAlphaCursor, sizeof(*pCursor));
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync Log(("vmsvgaFIFOLoop: ALPHA_CURSOR id=%d size (%d,%d) hotspot (%d,%d)\n", pCursor->id, pCursor->width, pCursor->height, pCursor->hotspotX, pCursor->hotspotY));
3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync /* Check against a reasonable upper limit to prevent integer overflows in the sanity checks below. */
c598affb4a1578b0e7be124835a70c4f08c5d2bdvboxsync AssertBreak(pCursor->height < 2048 && pCursor->width < 2048);
c598affb4a1578b0e7be124835a70c4f08c5d2bdvboxsync /* Refetch the bitmap data as well. */
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync cbCmd = sizeof(SVGAFifoCmdDefineAlphaCursor) + pCursor->width * pCursor->height * sizeof(uint32_t) /* 32-bit BRGA format */;
c598affb4a1578b0e7be124835a70c4f08c5d2bdvboxsync VMSVGAFIFO_GET_MORE_CMD_BUFFER_BREAK(pCursor, SVGAFifoCmdDefineAlphaCursor, cbCmd);
c598affb4a1578b0e7be124835a70c4f08c5d2bdvboxsync /** @todo Would be more efficient to copy the data straight into pCursorCopy (memcpy below). */
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync /* The mouse pointer interface always expects an AND mask followed by the color data (XOR mask). */
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync cbAndMask = (pCursor->width + 7) / 8 * pCursor->height; /* size of the AND mask */
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync cbAndMask = ((cbAndMask + 3) & ~3); /* + gap for alignment */
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync cbCursorShape = cbAndMask + pCursor->width * sizeof(uint32_t) * pCursor->height; /* + size of the XOR mask (32-bit BRGA format) */
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync pCursorCopy = (uint8_t *)RTMemAlloc(cbCursorShape);
c6ade8a5a12fad69394e7223b7ea170bd729f0f4vboxsync Log2(("Cursor data:\n%.*Rhxd\n", pCursor->width * pCursor->height * sizeof(uint32_t), pCursor+1));
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync /* Transparency is defined by the alpha bytes, so make the whole bitmap visible. */
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync /* Colour data */
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync memcpy(pCursorCopy + cbAndMask, (pCursor + 1), pCursor->width * pCursor->height * sizeof(uint32_t));
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync rc = pThis->pDrv->pfnVBVAMousePointerShape (pThis->pDrv,
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync /* Followed by nsize bytes of data. */
c598affb4a1578b0e7be124835a70c4f08c5d2bdvboxsync VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pEscape, SVGAFifoCmdEscape, sizeof(*pEscape));
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync /* Refetch the command buffer with the variable data; undo size increase (ugly) */
c598affb4a1578b0e7be124835a70c4f08c5d2bdvboxsync uint32_t cbCmd = sizeof(SVGAFifoCmdEscape) + pEscape->size;
c598affb4a1578b0e7be124835a70c4f08c5d2bdvboxsync VMSVGAFIFO_GET_MORE_CMD_BUFFER_BREAK(pEscape, SVGAFifoCmdEscape, cbCmd);
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync Log(("vmsvgaFIFOLoop: ESCAPE (%x %x) VMWARE cmd=%x\n", pEscape->nsid, pEscape->size, cmd));
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync SVGAEscapeVideoSetRegs *pVideoCmd = (SVGAEscapeVideoSetRegs *)(pEscape + 1);
c598affb4a1578b0e7be124835a70c4f08c5d2bdvboxsync AssertBreak(pEscape->size >= sizeof(pVideoCmd->header));
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync uint32_t cRegs = (pEscape->size - sizeof(pVideoCmd->header)) / sizeof(pVideoCmd->items[0]);
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync Log(("SVGA_ESCAPE_VMWARE_VIDEO_SET_REGS: stream %x\n", pVideoCmd->header.streamId));
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync Log(("SVGA_ESCAPE_VMWARE_VIDEO_SET_REGS: reg %x val %x\n", pVideoCmd->items[iReg].registerId, pVideoCmd->items[iReg].value));
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync SVGAEscapeVideoFlush *pVideoCmd = (SVGAEscapeVideoFlush *)(pEscape + 1);
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync Log(("SVGA_ESCAPE_VMWARE_VIDEO_FLUSH: stream %x\n", pVideoCmd->streamId));
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync Log(("vmsvgaFIFOLoop: ESCAPE %x %x\n", pEscape->nsid, pEscape->size));
c598affb4a1578b0e7be124835a70c4f08c5d2bdvboxsync VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdDefineGMR2, sizeof(*pCmd));
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync Log(("vmsvgaFIFOLoop: SVGA_CMD_DEFINE_GMR2 id=%x %x pages\n", pCmd->gmrId, pCmd->numPages));
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync /* Validate current GMR id. */
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync AssertBreak(pCmd->numPages <= VMSVGA_MAX_GMR_PAGES);
3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync /* everything done in remap */
c598affb4a1578b0e7be124835a70c4f08c5d2bdvboxsync /* Followed by page descriptors or guest ptr. */
c598affb4a1578b0e7be124835a70c4f08c5d2bdvboxsync VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdRemapGMR2, sizeof(*pCmd));
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync uint32_t cbPageDesc = (pCmd->flags & SVGA_REMAP_GMR2_PPN64) ? sizeof(uint64_t) : sizeof(uint32_t);
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync Log(("vmsvgaFIFOLoop: SVGA_CMD_REMAP_GMR2 id=%x flags=%x offset=%x npages=%x\n", pCmd->gmrId, pCmd->flags, pCmd->offsetPages, pCmd->numPages));
c598affb4a1578b0e7be124835a70c4f08c5d2bdvboxsync /* Calculate the size of what comes after next and fetch it. */
c598affb4a1578b0e7be124835a70c4f08c5d2bdvboxsync VMSVGAFIFO_GET_MORE_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdRemapGMR2, cbCmd);
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync /* Validate current GMR id. */
3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync AssertBreak(pCmd->offsetPages + pCmd->numPages <= pGMR->cMaxPages);
c66e448632d5ef48cf6b896f02e750440f5c6586vboxsync AssertBreak(!pCmd->offsetPages || pGMR->paDesc); /** @todo */
3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync /* Save the old page descriptors as an array of page addresses (>> PAGE_SHIFT) */
3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync paNewPage64 = (uint64_t *)RTMemAllocZ(pGMR->cMaxPages * sizeof(uint64_t));
3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync for (uint32_t i = 0; i < pGMR->numDescriptors; i++)
3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync for (uint32_t j = 0; j < pGMR->paDesc[i].numPages; j++)
3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync paNewPage64[idxPage++] = (pGMR->paDesc[i].GCPhys + j * PAGE_SIZE) >> PAGE_SHIFT;
3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync AssertBreak(idxPage == pGMR->cbTotal >> PAGE_SHIFT);
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync /* Free the old GMR if present. */
3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync /* Allocate the maximum amount possible (everything non-continuous) */
3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync pGMR->paDesc = (PVMSVGAGMRDESCRIPTOR)RTMemAllocZ(pGMR->cMaxPages * sizeof(VMSVGAGMRDESCRIPTOR));
0802b726efeabba46f90cb2b285de4dadaac9507vboxsync /** @todo */
3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync bool fGCPhys64 = !!(pCmd->flags & SVGA_REMAP_GMR2_PPN64);
3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync /* Overwrite the old page array with the new page values. */
3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync for (uint32_t i = pCmd->offsetPages; i < pCmd->offsetPages + pCmd->numPages; i++)
3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync /* Use the updated page array instead of the command data. */
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync GCPhys = (pPage64[0] << PAGE_SHIFT) & 0x00000FFFFFFFFFFFULL; /* seeing rubbish in the top bits with certain linux guests*/
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync GCPhys = (pPage64[i] << PAGE_SHIFT) & 0x00000FFFFFFFFFFFULL; /* seeing rubbish in the top bits with certain linux guests*/
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync /* Continuous physical memory? */
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync if (GCPhys == pGMR->paDesc[iDescriptor].GCPhys + pGMR->paDesc[iDescriptor].numPages * PAGE_SIZE)
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync LogFlow(("Page %x GCPhys=%RGp successor\n", i, GCPhys));
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync LogFlow(("Page %x GCPhys=%RGp\n", i, pGMR->paDesc[iDescriptor].GCPhys));
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync LogFlow(("Nr of descriptors %x\n", iDescriptor + 1));
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync VMR3ReqCallWait(PDMDevHlpGetVM(pThis->pDevInsR3), VMCPUID_ANY, (PFNRT)vmsvgaRegisterGMR, 2, pThis->pDevInsR3, pCmd->gmrId);
0802b726efeabba46f90cb2b285de4dadaac9507vboxsync# endif // VBOX_WITH_VMSVGA3D
c598affb4a1578b0e7be124835a70c4f08c5d2bdvboxsync /* Note! The size of this command is specified by the guest and depends on capabilities. */
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync Assert(!(pThis->svga.pFIFOR3[SVGA_FIFO_CAPABILITIES] & SVGA_FIFO_CAP_SCREEN_OBJECT));
c598affb4a1578b0e7be124835a70c4f08c5d2bdvboxsync VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdDefineScreen, sizeof(pCmd->screen.structSize));
c598affb4a1578b0e7be124835a70c4f08c5d2bdvboxsync RT_BZERO(&pCmd->screen.id, sizeof(*pCmd) - RT_OFFSETOF(SVGAFifoCmdDefineScreen, screen.structSize));
c598affb4a1578b0e7be124835a70c4f08c5d2bdvboxsync VMSVGAFIFO_GET_MORE_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdDefineScreen, RT_MAX(sizeof(pCmd->screen.structSize), pCmd->screen.structSize));
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync Log(("vmsvgaFIFOLoop: SVGA_CMD_DEFINE_SCREEN id=%x flags=%x size=(%d,%d) root=(%d,%d)\n", pCmd->screen.id, pCmd->screen.flags, pCmd->screen.size.width, pCmd->screen.size.height, pCmd->screen.root.x, pCmd->screen.root.y));
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync Log(("vmsvgaFIFOLoop: SVGA_CMD_DEFINE_SCREEN flags SVGA_SCREEN_HAS_ROOT\n"));
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync Log(("vmsvgaFIFOLoop: SVGA_CMD_DEFINE_SCREEN flags SVGA_SCREEN_IS_PRIMARY\n"));
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync if (pCmd->screen.flags & SVGA_SCREEN_FULLSCREEN_HINT)
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync Log(("vmsvgaFIFOLoop: SVGA_CMD_DEFINE_SCREEN flags SVGA_SCREEN_FULLSCREEN_HINT\n"));
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync Log(("vmsvgaFIFOLoop: SVGA_CMD_DEFINE_SCREEN flags SVGA_SCREEN_DEACTIVATE \n"));
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync Log(("vmsvgaFIFOLoop: SVGA_CMD_DEFINE_SCREEN flags SVGA_SCREEN_BLANKING\n"));
c598affb4a1578b0e7be124835a70c4f08c5d2bdvboxsync /** @todo multi monitor support and screen object capabilities. */
c598affb4a1578b0e7be124835a70c4f08c5d2bdvboxsync VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdDestroyScreen, sizeof(*pCmd));
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync Log(("vmsvgaFIFOLoop: SVGA_CMD_DESTROY_SCREEN id=%x\n", pCmd->screenId));
c598affb4a1578b0e7be124835a70c4f08c5d2bdvboxsync VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdDefineGMRFB, sizeof(*pCmd));
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync Log(("vmsvgaFIFOLoop: SVGA_CMD_DEFINE_GMRFB gmr=%x offset=%x bytesPerLine=%x bpp=%d color depth=%d\n", pCmd->ptr.gmrId, pCmd->ptr.offset, pCmd->bytesPerLine, pCmd->format.s.bitsPerPixel, pCmd->format.s.colorDepth));
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync pSVGAState->GMRFB.bytesPerLine = pCmd->bytesPerLine;
c598affb4a1578b0e7be124835a70c4f08c5d2bdvboxsync VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdBlitGMRFBToScreen, sizeof(*pCmd));
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync Log(("vmsvgaFIFOLoop: SVGA_CMD_BLIT_GMRFB_TO_SCREEN src=(%d,%d) dest id=%d (%d,%d)(%d,%d)\n", pCmd->srcOrigin.x, pCmd->srcOrigin.y, pCmd->destScreenId, pCmd->destRect.left, pCmd->destRect.top, pCmd->destRect.right, pCmd->destRect.bottom));
c598affb4a1578b0e7be124835a70c4f08c5d2bdvboxsync /** @todo Support GMRFB.format.s.bitsPerPixel != pThis->svga.uBpp */
3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync AssertBreak(pSVGAState->GMRFB.format.s.bitsPerPixel == pThis->svga.uBpp);
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync width = pCmd->destRect.right - pCmd->destRect.left;
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync height = pCmd->destRect.bottom - pCmd->destRect.top;
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync break; /* Nothing to do. */
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync /* Clip to screen dimensions. */
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync unsigned offsetSource = (pCmd->srcOrigin.x * pSVGAState->GMRFB.format.s.bitsPerPixel) / 8 + pSVGAState->GMRFB.bytesPerLine * pCmd->srcOrigin.y;
3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync unsigned offsetDest = (pCmd->destRect.left * RT_ALIGN(pThis->svga.uBpp, 8)) / 8 + pThis->svga.cbScanline * pCmd->destRect.top;
3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync unsigned cbCopyWidth = (width * RT_ALIGN(pThis->svga.uBpp, 8)) / 8;
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync rc = vmsvgaGMRTransfer(pThis, SVGA3D_WRITE_HOST_VRAM, pThis->CTX_SUFF(vram_ptr) + offsetDest, pThis->svga.cbScanline, pSVGAState->GMRFB.ptr, offsetSource, pSVGAState->GMRFB.bytesPerLine, cbCopyWidth, height);
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync vgaR3UpdateDisplay(pThis, pCmd->destRect.left, pCmd->destRect.top, pCmd->destRect.right - pCmd->destRect.left, pCmd->destRect.bottom - pCmd->destRect.top);
c598affb4a1578b0e7be124835a70c4f08c5d2bdvboxsync VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdBlitScreenToGMRFB, sizeof(*pCmd));
c598affb4a1578b0e7be124835a70c4f08c5d2bdvboxsync /* Note! This can fetch 3d render results as well!! */
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync Log(("vmsvgaFIFOLoop: SVGA_CMD_BLIT_SCREEN_TO_GMRFB dest=(%d,%d) src id=%d (%d,%d)(%d,%d)\n", pCmd->destOrigin.x, pCmd->destOrigin.y, pCmd->srcScreenId, pCmd->srcRect.left, pCmd->srcRect.top, pCmd->srcRect.right, pCmd->srcRect.bottom));
0802b726efeabba46f90cb2b285de4dadaac9507vboxsync# endif // VBOX_WITH_VMSVGA3D
c598affb4a1578b0e7be124835a70c4f08c5d2bdvboxsync VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdAnnotationFill, sizeof(*pCmd));
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync Log(("vmsvgaFIFOLoop: SVGA_CMD_ANNOTATION_FILL red=%x green=%x blue=%x\n", pCmd->color.s.r, pCmd->color.s.g, pCmd->color.s.b));
c598affb4a1578b0e7be124835a70c4f08c5d2bdvboxsync VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pCmd, SVGAFifoCmdAnnotationCopy, sizeof(*pCmd));
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync Log(("vmsvgaFIFOLoop: SVGA_CMD_ANNOTATION_COPY\n"));
c66e448632d5ef48cf6b896f02e750440f5c6586vboxsync /** @todo SVGA_CMD_RECT_COPY - see with ubuntu */
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync /* All 3d commands start with a common header, which defines the size of the command. */
c598affb4a1578b0e7be124835a70c4f08c5d2bdvboxsync VMSVGAFIFO_GET_CMD_BUFFER_BREAK(pHdr, SVGA3dCmdHeader, sizeof(*pHdr));
c598affb4a1578b0e7be124835a70c4f08c5d2bdvboxsync uint32_t cbCmd = sizeof(SVGA3dCmdHeader) + pHdr->size;
c598affb4a1578b0e7be124835a70c4f08c5d2bdvboxsync VMSVGAFIFO_GET_MORE_CMD_BUFFER_BREAK(pHdr, SVGA3dCmdHeader, cbCmd);
c598affb4a1578b0e7be124835a70c4f08c5d2bdvboxsync * Check that the 3D command has at least a_cbMin of payload bytes after the
c598affb4a1578b0e7be124835a70c4f08c5d2bdvboxsync * header. Will break out of the switch if it doesn't.
c598affb4a1578b0e7be124835a70c4f08c5d2bdvboxsync# define VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(a_cbMin) \
c598affb4a1578b0e7be124835a70c4f08c5d2bdvboxsync AssertMsgBreak((a_cbMin) <= pHdr->size, ("size=%#x a_cbMin=%#zx\n", pHdr->size, (size_t)(a_cbMin)))
534b08d8ec6f569f90e80fd5eb49021993da0745vboxsync switch ((int)enmCmdId)
c598affb4a1578b0e7be124835a70c4f08c5d2bdvboxsync SVGA3dCmdDefineSurface *pCmd = (SVGA3dCmdDefineSurface *)(pHdr + 1);
c598affb4a1578b0e7be124835a70c4f08c5d2bdvboxsync VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync cMipLevels = (pHdr->size - sizeof(*pCmd)) / sizeof(SVGA3dSize);
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync rc = vmsvga3dSurfaceDefine(pThis, pCmd->sid, (uint32_t)pCmd->surfaceFlags, pCmd->format, pCmd->face, 0, SVGA3D_TEX_FILTER_NONE, cMipLevels, (SVGA3dSize *)(pCmd + 1));
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync VMR3ReqCallWait(PDMDevHlpGetVM(pThis->pDevInsR3), VMCPUID_ANY, (PFNRT)vmsvgaResetGMRHandlers, 1, pThis);
c598affb4a1578b0e7be124835a70c4f08c5d2bdvboxsync SVGA3dCmdDefineSurface_v2 *pCmd = (SVGA3dCmdDefineSurface_v2 *)(pHdr + 1);
c598affb4a1578b0e7be124835a70c4f08c5d2bdvboxsync VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync cMipLevels = (pHdr->size - sizeof(*pCmd)) / sizeof(SVGA3dSize);
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync rc = vmsvga3dSurfaceDefine(pThis, pCmd->sid, pCmd->surfaceFlags, pCmd->format, pCmd->face, pCmd->multisampleCount, pCmd->autogenFilter, cMipLevels, (SVGA3dSize *)(pCmd + 1));
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync SVGA3dCmdDestroySurface *pCmd = (SVGA3dCmdDestroySurface *)(pHdr + 1);
c598affb4a1578b0e7be124835a70c4f08c5d2bdvboxsync VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
c598affb4a1578b0e7be124835a70c4f08c5d2bdvboxsync SVGA3dCmdSurfaceCopy *pCmd = (SVGA3dCmdSurfaceCopy *)(pHdr + 1);
c598affb4a1578b0e7be124835a70c4f08c5d2bdvboxsync VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync cCopyBoxes = (pHdr->size - sizeof(pCmd)) / sizeof(SVGA3dCopyBox);
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync rc = vmsvga3dSurfaceCopy(pThis, pCmd->dest, pCmd->src, cCopyBoxes, (SVGA3dCopyBox *)(pCmd + 1));
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync SVGA3dCmdSurfaceStretchBlt *pCmd = (SVGA3dCmdSurfaceStretchBlt *)(pHdr + 1);
c598affb4a1578b0e7be124835a70c4f08c5d2bdvboxsync VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync rc = vmsvga3dSurfaceStretchBlt(pThis, pCmd->dest, pCmd->boxDest, pCmd->src, pCmd->boxSrc, pCmd->mode);
c598affb4a1578b0e7be124835a70c4f08c5d2bdvboxsync SVGA3dCmdSurfaceDMA *pCmd = (SVGA3dCmdSurfaceDMA *)(pHdr + 1);
c598affb4a1578b0e7be124835a70c4f08c5d2bdvboxsync VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync cCopyBoxes = (pHdr->size - sizeof(*pCmd)) / sizeof(SVGA3dCopyBox);
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync STAM_PROFILE_START(&pSVGAState->StatR3CmdSurfaceDMA, a);
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync rc = vmsvga3dSurfaceDMA(pThis, pCmd->guest, pCmd->host, pCmd->transfer, cCopyBoxes, (SVGA3dCopyBox *)(pCmd + 1));
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync STAM_PROFILE_STOP(&pSVGAState->StatR3CmdSurfaceDMA, a);
c598affb4a1578b0e7be124835a70c4f08c5d2bdvboxsync SVGA3dCmdBlitSurfaceToScreen *pCmd = (SVGA3dCmdBlitSurfaceToScreen *)(pHdr + 1);
c598affb4a1578b0e7be124835a70c4f08c5d2bdvboxsync VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync cRects = (pHdr->size - sizeof(*pCmd)) / sizeof(SVGASignedRect);
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync rc = vmsvga3dSurfaceBlitToScreen(pThis, pCmd->destScreenId, pCmd->destRect, pCmd->srcImage, pCmd->srcRect, cRects, (SVGASignedRect *)(pCmd + 1));
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync SVGA3dCmdDefineContext *pCmd = (SVGA3dCmdDefineContext *)(pHdr + 1);
c598affb4a1578b0e7be124835a70c4f08c5d2bdvboxsync VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync SVGA3dCmdDestroyContext *pCmd = (SVGA3dCmdDestroyContext *)(pHdr + 1);
c598affb4a1578b0e7be124835a70c4f08c5d2bdvboxsync VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync SVGA3dCmdSetTransform *pCmd = (SVGA3dCmdSetTransform *)(pHdr + 1);
c598affb4a1578b0e7be124835a70c4f08c5d2bdvboxsync VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync rc = vmsvga3dSetTransform(pThis, pCmd->cid, pCmd->type, pCmd->matrix);
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync SVGA3dCmdSetZRange *pCmd = (SVGA3dCmdSetZRange *)(pHdr + 1);
c598affb4a1578b0e7be124835a70c4f08c5d2bdvboxsync VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync rc = vmsvga3dSetZRange(pThis, pCmd->cid, pCmd->zRange);
c598affb4a1578b0e7be124835a70c4f08c5d2bdvboxsync SVGA3dCmdSetRenderState *pCmd = (SVGA3dCmdSetRenderState *)(pHdr + 1);
c598affb4a1578b0e7be124835a70c4f08c5d2bdvboxsync VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync cRenderStates = (pHdr->size - sizeof(*pCmd)) / sizeof(SVGA3dRenderState);
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync rc = vmsvga3dSetRenderState(pThis, pCmd->cid, cRenderStates, (SVGA3dRenderState *)(pCmd + 1));
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync SVGA3dCmdSetRenderTarget *pCmd = (SVGA3dCmdSetRenderTarget *)(pHdr + 1);
c598affb4a1578b0e7be124835a70c4f08c5d2bdvboxsync VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync rc = vmsvga3dSetRenderTarget(pThis, pCmd->cid, pCmd->type, pCmd->target);
c598affb4a1578b0e7be124835a70c4f08c5d2bdvboxsync SVGA3dCmdSetTextureState *pCmd = (SVGA3dCmdSetTextureState *)(pHdr + 1);
c598affb4a1578b0e7be124835a70c4f08c5d2bdvboxsync VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync cTextureStates = (pHdr->size - sizeof(*pCmd)) / sizeof(SVGA3dTextureState);
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync rc = vmsvga3dSetTextureState(pThis, pCmd->cid, cTextureStates, (SVGA3dTextureState *)(pCmd + 1));
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync SVGA3dCmdSetMaterial *pCmd = (SVGA3dCmdSetMaterial *)(pHdr + 1);
c598affb4a1578b0e7be124835a70c4f08c5d2bdvboxsync VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync rc = vmsvga3dSetMaterial(pThis, pCmd->cid, pCmd->face, &pCmd->material);
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync SVGA3dCmdSetLightData *pCmd = (SVGA3dCmdSetLightData *)(pHdr + 1);
c598affb4a1578b0e7be124835a70c4f08c5d2bdvboxsync VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync rc = vmsvga3dSetLightData(pThis, pCmd->cid, pCmd->index, &pCmd->data);
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync SVGA3dCmdSetLightEnabled *pCmd = (SVGA3dCmdSetLightEnabled *)(pHdr + 1);
c598affb4a1578b0e7be124835a70c4f08c5d2bdvboxsync VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync rc = vmsvga3dSetLightEnabled(pThis, pCmd->cid, pCmd->index, pCmd->enabled);
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync SVGA3dCmdSetViewport *pCmd = (SVGA3dCmdSetViewport *)(pHdr + 1);
c598affb4a1578b0e7be124835a70c4f08c5d2bdvboxsync VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync rc = vmsvga3dSetViewPort(pThis, pCmd->cid, &pCmd->rect);
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync SVGA3dCmdSetClipPlane *pCmd = (SVGA3dCmdSetClipPlane *)(pHdr + 1);
c598affb4a1578b0e7be124835a70c4f08c5d2bdvboxsync VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync rc = vmsvga3dSetClipPlane(pThis, pCmd->cid, pCmd->index, pCmd->plane);
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync SVGA3dCmdClear *pCmd = (SVGA3dCmdClear *)(pHdr + 1);
c598affb4a1578b0e7be124835a70c4f08c5d2bdvboxsync VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync cRects = (pHdr->size - sizeof(*pCmd)) / sizeof(SVGA3dRect);
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync rc = vmsvga3dCommandClear(pThis, pCmd->cid, pCmd->clearFlag, pCmd->color, pCmd->depth, pCmd->stencil, cRects, (SVGA3dRect *)(pCmd + 1));
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync SVGA3dCmdPresent *pCmd = (SVGA3dCmdPresent *)(pHdr + 1);
c598affb4a1578b0e7be124835a70c4f08c5d2bdvboxsync VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync cRects = (pHdr->size - sizeof(*pCmd)) / sizeof(SVGA3dCopyRect);
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync STAM_PROFILE_START(&pSVGAState->StatR3CmdPresent, a);
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync rc = vmsvga3dCommandPresent(pThis, pCmd->sid, cRects, (SVGA3dCopyRect *)(pCmd + 1));
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync STAM_PROFILE_STOP(&pSVGAState->StatR3CmdPresent, a);
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync SVGA3dCmdDefineShader *pCmd = (SVGA3dCmdDefineShader *)(pHdr + 1);
c598affb4a1578b0e7be124835a70c4f08c5d2bdvboxsync VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync rc = vmsvga3dShaderDefine(pThis, pCmd->cid, pCmd->shid, pCmd->type, cbData, (uint32_t *)(pCmd + 1));
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync SVGA3dCmdDestroyShader *pCmd = (SVGA3dCmdDestroyShader *)(pHdr + 1);
c598affb4a1578b0e7be124835a70c4f08c5d2bdvboxsync VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync rc = vmsvga3dShaderDestroy(pThis, pCmd->cid, pCmd->shid, pCmd->type);
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync SVGA3dCmdSetShader *pCmd = (SVGA3dCmdSetShader *)(pHdr + 1);
c598affb4a1578b0e7be124835a70c4f08c5d2bdvboxsync VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync rc = vmsvga3dShaderSet(pThis, pCmd->cid, pCmd->type, pCmd->shid);
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync SVGA3dCmdSetShaderConst *pCmd = (SVGA3dCmdSetShaderConst *)(pHdr + 1);
c598affb4a1578b0e7be124835a70c4f08c5d2bdvboxsync VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync uint32_t cRegisters = (pHdr->size - sizeof(*pCmd)) / sizeof(pCmd->values) + 1;
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync rc = vmsvga3dShaderSetConst(pThis, pCmd->cid, pCmd->reg, pCmd->type, pCmd->ctype, cRegisters, pCmd->values);
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync SVGA3dCmdDrawPrimitives *pCmd = (SVGA3dCmdDrawPrimitives *)(pHdr + 1);
c598affb4a1578b0e7be124835a70c4f08c5d2bdvboxsync VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync cVertexDivisor = (pHdr->size - sizeof(*pCmd) - sizeof(SVGA3dVertexDecl) * pCmd->numVertexDecls - sizeof(SVGA3dPrimitiveRange) * pCmd->numRanges);
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync Assert(pCmd->numRanges <= SVGA3D_MAX_DRAW_PRIMITIVE_RANGES);
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync Assert(pCmd->numVertexDecls <= SVGA3D_MAX_VERTEX_ARRAYS);
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync Assert(!cVertexDivisor || cVertexDivisor == pCmd->numVertexDecls);
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync SVGA3dVertexDecl *pVertexDecl = (SVGA3dVertexDecl *)(pCmd + 1);
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync SVGA3dPrimitiveRange *pNumRange = (SVGA3dPrimitiveRange *) (&pVertexDecl[pCmd->numVertexDecls]);
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync SVGA3dVertexDivisor *pVertexDivisor = (cVertexDivisor) ? (SVGA3dVertexDivisor *)(&pNumRange[pCmd->numRanges]) : NULL;
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync STAM_PROFILE_START(&pSVGAState->StatR3CmdDrawPrimitive, a);
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync rc = vmsvga3dDrawPrimitives(pThis, pCmd->cid, pCmd->numVertexDecls, pVertexDecl, pCmd->numRanges, pNumRange, cVertexDivisor, pVertexDivisor);
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync STAM_PROFILE_STOP(&pSVGAState->StatR3CmdDrawPrimitive, a);
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync SVGA3dCmdSetScissorRect *pCmd = (SVGA3dCmdSetScissorRect *)(pHdr + 1);
c598affb4a1578b0e7be124835a70c4f08c5d2bdvboxsync VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync rc = vmsvga3dSetScissorRect(pThis, pCmd->cid, &pCmd->rect);
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync SVGA3dCmdBeginQuery *pCmd = (SVGA3dCmdBeginQuery *)(pHdr + 1);
c598affb4a1578b0e7be124835a70c4f08c5d2bdvboxsync VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync rc = vmsvga3dQueryBegin(pThis, pCmd->cid, pCmd->type);
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync SVGA3dCmdEndQuery *pCmd = (SVGA3dCmdEndQuery *)(pHdr + 1);
c598affb4a1578b0e7be124835a70c4f08c5d2bdvboxsync VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync rc = vmsvga3dQueryEnd(pThis, pCmd->cid, pCmd->type, pCmd->guestResult);
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync SVGA3dCmdWaitForQuery *pCmd = (SVGA3dCmdWaitForQuery *)(pHdr + 1);
c598affb4a1578b0e7be124835a70c4f08c5d2bdvboxsync VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync rc = vmsvga3dQueryWait(pThis, pCmd->cid, pCmd->type, pCmd->guestResult);
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync SVGA3dCmdGenerateMipmaps *pCmd = (SVGA3dCmdGenerateMipmaps *)(pHdr + 1);
c598affb4a1578b0e7be124835a70c4f08c5d2bdvboxsync VMSVGAFIFO_CHECK_3D_CMD_MIN_SIZE_BREAK(sizeof(*pCmd));
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync rc = vmsvga3dGenerateMipmaps(pThis, pCmd->sid, pCmd->filter);
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync /* context id + surface id? */
c66e448632d5ef48cf6b896f02e750440f5c6586vboxsync STAM_REL_COUNTER_INC(&pSVGAState->StatFifoUnkCmds);
0802b726efeabba46f90cb2b285de4dadaac9507vboxsync# endif // VBOX_WITH_VMSVGA3D
c66e448632d5ef48cf6b896f02e750440f5c6586vboxsync STAM_REL_COUNTER_INC(&pSVGAState->StatFifoUnkCmds);
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync /* Go to the next slot */
c598affb4a1578b0e7be124835a70c4f08c5d2bdvboxsync Assert(cbPayload + sizeof(uint32_t) <= offFifoMax - offFifoMin);
c598affb4a1578b0e7be124835a70c4f08c5d2bdvboxsync offCurrentCmd += RT_ALIGN_32(cbPayload + sizeof(uint32_t), sizeof(uint32_t));
c598affb4a1578b0e7be124835a70c4f08c5d2bdvboxsync ASMAtomicWriteU32(&pFIFO[SVGA_FIFO_STOP], offCurrentCmd);
c66e448632d5ef48cf6b896f02e750440f5c6586vboxsync STAM_REL_COUNTER_INC(&pSVGAState->StatFifoCommands);
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync /* FIFO progress might trigger an interrupt. */
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync if (pThis->svga.u32IrqMask & SVGA_IRQFLAG_FIFO_PROGRESS)
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync /* Irq pending? */
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync Log(("vmsvgaFIFOLoop: Trigger interrupt with status %x\n", u32IrqStatus));
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync ASMAtomicOrU32(&pThis->svga.u32IrqStatus, u32IrqStatus);
c598affb4a1578b0e7be124835a70c4f08c5d2bdvboxsync /* If really done, clear the busy flag. */
c598affb4a1578b0e7be124835a70c4f08c5d2bdvboxsync Log(("vmsvgaFIFOLoop: emptied the FIFO next=%x stop=%x\n", pFIFO[SVGA_FIFO_NEXT_CMD], offCurrentCmd));
36c3589d6411416bba897f2595f1812b9d9ff4b3vboxsync vmsvgaFifoSetNotBusy(pThis, pSVGAState, offFifoMin);
c598affb4a1578b0e7be124835a70c4f08c5d2bdvboxsync * Free the bounce buffer. (There are no returns above!)
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync * Free the specified GMR
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync * @param pThis VGA device instance data.
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync * @param idGMR GMR id
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync PVMSVGASTATE pSVGAState = (PVMSVGASTATE)pThis->svga.pSVGAState;
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync /* Free the old descriptor if present. */
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync VMR3ReqCallWait(PDMDevHlpGetVM(pThis->pDevInsR3), VMCPUID_ANY, (PFNRT)vmsvgaUnregisterGMR, 2, pThis->pDevInsR3, idGMR);
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync * Copy from a GMR to host memory or vice versa
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync * @returns VBox status code.
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync * @param pThis VGA device instance data.
c049162517778158b3507c0389358a7342622b99vboxsync * @param enmTransferType Transfer type (read/write)
c049162517778158b3507c0389358a7342622b99vboxsync * @param pbDst Host destination pointer
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync * @param cbDestPitch Destination buffer pitch
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync * @param src GMR description
c049162517778158b3507c0389358a7342622b99vboxsync * @param offSrc Source buffer offset
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync * @param cbSrcPitch Source buffer pitch
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync * @param cbWidth Source width in bytes
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync * @param cHeight Source height
c049162517778158b3507c0389358a7342622b99vboxsyncint vmsvgaGMRTransfer(PVGASTATE pThis, const SVGA3dTransferType enmTransferType, uint8_t *pbDst, int32_t cbDestPitch,
c049162517778158b3507c0389358a7342622b99vboxsync SVGAGuestPtr src, uint32_t offSrc, int32_t cbSrcPitch, uint32_t cbWidth, uint32_t cHeight)
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync PVMSVGASTATE pSVGAState = (PVMSVGASTATE)pThis->svga.pSVGAState;
c049162517778158b3507c0389358a7342622b99vboxsync Log(("vmsvgaGMRTransfer: gmr=%x offset=%x pitch=%d cbWidth=%d cHeight=%d; src offset=%d src pitch=%d\n",
c049162517778158b3507c0389358a7342622b99vboxsync src.gmrId, src.offset, cbDestPitch, cbWidth, cHeight, offSrc, cbSrcPitch));
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync /* Shortcut for the framebuffer. */
c049162517778158b3507c0389358a7342622b99vboxsync ("src.offset=%#x offSrc=%#x cbSrcPitch=%#x cHeight=%#x cbWidth=%#x cbTotal=%#x vram_size=%#x\n",
c049162517778158b3507c0389358a7342622b99vboxsync src.offset, offSrc, cbSrcPitch, cHeight, cbWidth, pThis->vram_size),
c049162517778158b3507c0389358a7342622b99vboxsync AssertMsgReturn(offSrc + cbSrcPitch * (cHeight - 1) + cbWidth <= pThis->vram_size,
c049162517778158b3507c0389358a7342622b99vboxsync ("src.offset=%#x offSrc=%#x cbSrcPitch=%#x cHeight=%#x cbWidth=%#x cbTotal=%#x vram_size=%#x\n",
c049162517778158b3507c0389358a7342622b99vboxsync src.offset, offSrc, cbSrcPitch, cHeight, cbWidth, pThis->vram_size),
c049162517778158b3507c0389358a7342622b99vboxsync uint8_t *pSrc = pThis->CTX_SUFF(vram_ptr) + offSrc;
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync /* switch src & dest */
36c3589d6411416bba897f2595f1812b9d9ff4b3vboxsync if ( pThis->svga.cbScanline == (uint32_t)cbDestPitch
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync AssertReturn(src.gmrId < VMSVGA_MAX_GMR_IDS, VERR_INVALID_PARAMETER);
c049162517778158b3507c0389358a7342622b99vboxsync ("src.gmrId=%#x src.offset=%#x offSrc=%#x cbSrcPitch=%#x cHeight=%#x cbWidth=%#x cbTotal=%#x\n",
c049162517778158b3507c0389358a7342622b99vboxsync src.gmrId, src.offset, offSrc, cbSrcPitch, cHeight, cbWidth, pGMR->cbTotal),
c049162517778158b3507c0389358a7342622b99vboxsync AssertMsgReturn(offSrc + cbSrcPitch * (cHeight - 1) + cbWidth <= pGMR->cbTotal,
c049162517778158b3507c0389358a7342622b99vboxsync ("src.gmrId=%#x src.offset=%#x offSrc=%#x cbSrcPitch=%#x cHeight=%#x cbWidth=%#x cbTotal=%#x\n",
c049162517778158b3507c0389358a7342622b99vboxsync src.gmrId, src.offset, offSrc, cbSrcPitch, cHeight, cbWidth, pGMR->cbTotal),
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync /* Find the right descriptor */
c049162517778158b3507c0389358a7342622b99vboxsync while (offDesc + pDesc->numPages * PAGE_SIZE <= offCurrent)
c049162517778158b3507c0389358a7342622b99vboxsync AssertReturn(offDesc < pGMR->cbTotal, VERR_INTERNAL_ERROR); /* overflow protection */
c049162517778158b3507c0389358a7342622b99vboxsync if (offCurrent + cbCurrentWidth <= offDesc + pDesc->numPages * PAGE_SIZE)
c049162517778158b3507c0389358a7342622b99vboxsync cbToCopy = (offDesc + pDesc->numPages * PAGE_SIZE - offCurrent);
3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync AssertReturn(cbToCopy <= cbCurrentWidth, VERR_INVALID_PARAMETER);
c049162517778158b3507c0389358a7342622b99vboxsync LogFlow(("vmsvgaGMRTransfer: %s phys=%RGp\n", (enmTransferType == SVGA3D_WRITE_HOST_VRAM) ? "READ" : "WRITE", pDesc->GCPhys + offCurrent - offDesc));
c049162517778158b3507c0389358a7342622b99vboxsync rc = PDMDevHlpPhysRead(pThis->CTX_SUFF(pDevIns), pDesc->GCPhys + offCurrent - offDesc, pCurrentDest, cbToCopy);
c049162517778158b3507c0389358a7342622b99vboxsync rc = PDMDevHlpPhysWrite(pThis->CTX_SUFF(pDevIns), pDesc->GCPhys + offCurrent - offDesc, pCurrentDest, cbToCopy);
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync /* Go to the next descriptor if there's anything left. */
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync * Unblock the FIFO I/O thread so it can respond to a state change.
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync * @returns VBox status code.
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync * @param pDevIns The VGA device instance.
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync * @param pThread The send thread.
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsyncstatic DECLCALLBACK(int) vmsvgaFIFOLoopWakeUp(PPDMDEVINS pDevIns, PPDMTHREAD pThread)
cb39011e69667689c166f1cdf95247b46fff324dvboxsync return SUPSemEventSignal(pThis->svga.pSupDrvSession, pThis->svga.FIFORequestSem);
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync * Enables or disables dirty page tracking for the framebuffer
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync * @param pThis VGA device instance data.
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync * @param fTraces Enable/disable traces
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsyncstatic void vmsvgaSetTraces(PVGASTATE pThis, bool fTraces)
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync if ( (!pThis->svga.fConfigured || !pThis->svga.fEnabled)
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync //Assert(pThis->svga.fTraces);
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync Log(("vmsvgaSetTraces: *not* allowed to disable dirty page tracking when the device is in legacy mode.\n"));
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync Log(("vmsvgaSetTraces: enable dirty page handling for the frame buffer only (%x bytes)\n", 0));
3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync if (pThis->svga.uHeight != VMSVGA_VAL_UNINITIALIZED)
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync /* Hardware enabled; return real framebuffer size .*/
3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync cbFrameBuffer = (uint32_t)pThis->svga.uHeight * pThis->svga.cbScanline;
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync cbFrameBuffer = RT_ALIGN(cbFrameBuffer, PAGE_SIZE);
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync Log(("vmsvgaSetTraces: enable frame buffer dirty page tracking. (%x bytes; vram %x)\n", cbFrameBuffer, pThis->vram_size));
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync Log(("vmsvgaSetTraces: disable frame buffer dirty page tracking\n"));
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync * Callback function for mapping a PCI I/O region.
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync * @return VBox status code.
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync * @param pPciDev Pointer to PCI device.
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync * Use pPciDev->pDevIns to get the device instance.
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync * @param iRegion The region number.
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync * @param GCPhysAddress Physical address of the region.
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync * If iType is PCI_ADDRESS_SPACE_IO, this is an
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync * I/O port, else it's a physical address.
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync * This address is *NOT* relative
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync * to pci_mem_base like earlier!
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync * @param enmType One of the PCI_ADDRESS_SPACE_* values.
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsyncDECLCALLBACK(int) vmsvgaR3IORegionMap(PPCIDEVICE pPciDev, int iRegion, RTGCPHYS GCPhysAddress, uint32_t cb, PCIADDRESSSPACE enmType)
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync PVGASTATE pThis = PDMINS_2_DATA(pDevIns, PVGASTATE);
3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync Log(("vgasvgaR3IORegionMap: iRegion=%d GCPhysAddress=%RGp cb=%#x enmType=%d\n", iRegion, GCPhysAddress, cb, enmType));
cb39011e69667689c166f1cdf95247b46fff324dvboxsync rc = PDMDevHlpIOPortRegister(pDevIns, (RTIOPORT)GCPhysAddress, cb, 0,
cb39011e69667689c166f1cdf95247b46fff324dvboxsync vmsvgaIOWrite, vmsvgaIORead, NULL /* OutStr */, NULL /* InStr */, "VMSVGA");
cb39011e69667689c166f1cdf95247b46fff324dvboxsync rc = PDMDevHlpIOPortRegisterR0(pDevIns, (RTIOPORT)GCPhysAddress, cb, 0,
cb39011e69667689c166f1cdf95247b46fff324dvboxsync "vmsvgaIOWrite", "vmsvgaIORead", NULL, NULL, "VMSVGA");
cb39011e69667689c166f1cdf95247b46fff324dvboxsync rc = PDMDevHlpIOPortRegisterRC(pDevIns, (RTIOPORT)GCPhysAddress, cb, 0,
cb39011e69667689c166f1cdf95247b46fff324dvboxsync "vmsvgaIOWrite", "vmsvgaIORead", NULL, NULL, "VMSVGA");
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync Log(("vmsvgaR3IORegionMap: base port = %x\n", pThis->svga.BasePort));
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync AssertReturn(iRegion == 2 && enmType == PCI_ADDRESS_SPACE_MEM, VERR_INTERNAL_ERROR);
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync * Mapping the FIFO RAM.
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync rc = PDMDevHlpMMIO2Map(pDevIns, iRegion, GCPhysAddress);
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync rc = PGMR3HandlerPhysicalRegister(PDMDevHlpGetVM(pDevIns),
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync GCPhysAddress, GCPhysAddress + (VMSVGA_FIFO_SIZE - 1),
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync "VMSVGA FIFO");
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync Log(("vmsvgaR3IORegionMap: FIFO address = %RGp\n", GCPhysAddress));
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync rc = PGMHandlerPhysicalDeregister(PDMDevHlpGetVM(pDevIns), pThis->svga.GCPhysFIFO);
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync * @copydoc FNSSMDEVLOADEXEC
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsyncint vmsvgaLoadExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync PVGASTATE pThis = PDMINS_2_DATA(pDevIns, PVGASTATE);
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync PVMSVGASTATE pSVGAState = (PVMSVGASTATE)pThis->svga.pSVGAState;
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync /* Load our part of the VGAState */
3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync rc = SSMR3GetStructEx(pSSM, &pThis->svga, sizeof(pThis->svga), 0, g_aVGAStateSVGAFields, NULL);
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync /* Load the framebuffer backup. */
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync rc = SSMR3GetMem(pSSM, pThis->svga.pFrameBufferBackup, VMSVGA_FRAMEBUFFER_BACKUP_SIZE);
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync /* Load the VMSVGA state. */
3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync rc = SSMR3GetStructEx(pSSM, pSVGAState, sizeof(*pSVGAState), 0, g_aVMSVGASTATEFields, NULL);
3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync /* Load the active cursor bitmaps. */
3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync pSVGAState->Cursor.pData = RTMemAlloc(pSVGAState->Cursor.cbData);
3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync AssertReturn(pSVGAState->Cursor.pData, VERR_NO_MEMORY);
3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync rc = SSMR3GetMem(pSSM, pSVGAState->Cursor.pData, pSVGAState->Cursor.cbData);
3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync /* Load the GMR state */
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync for (uint32_t i = 0; i < RT_ELEMENTS(pSVGAState->aGMR); i++)
3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync rc = SSMR3GetStructEx(pSSM, pGMR, sizeof(*pGMR), 0, g_aGMRFields, NULL);
3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync /* Allocate the maximum amount possible (everything non-continuous) */
3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync pGMR->paDesc = (PVMSVGAGMRDESCRIPTOR)RTMemAllocZ((pGMR->cMaxPages) ? pGMR->cMaxPages : (pGMR->cbTotal >> PAGE_SHIFT) * sizeof(VMSVGAGMRDESCRIPTOR));
3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync for (uint32_t j = 0; j < pGMR->numDescriptors; j++)
3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync rc = SSMR3GetStructEx(pSSM, &pGMR->paDesc[j], sizeof(pGMR->paDesc[j]), 0, g_aVMSVGAGMRDESCRIPTORFields, NULL);
3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync /* Save the 3d state in the FIFO thread. */
3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync pThis->svga.u8FIFOExtCommand = VMSVGA_FIFO_EXTCMD_LOADSTATE;
2b114c590cf5a19f8047cd7bde9c7e5ae00aa22bvboxsync /* Hack alert: resume the IO thread as it has been suspended before the destruct callback.
3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync * The PowerOff notification isn't working, so not an option in this case.
cb39011e69667689c166f1cdf95247b46fff324dvboxsync SUPSemEventSignal(pThis->svga.pSupDrvSession, pThis->svga.FIFORequestSem);
3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync /* Wait for the end of the command. */
3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync rc = RTSemEventWait(pThis->svga.FIFOExtCmdSem, RT_INDEFINITE_WAIT);
3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync * Reinit the video mode after the state has been loaded.
3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync PVGASTATE pThis = PDMINS_2_DATA(pDevIns, PVGASTATE);
3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync PVMSVGASTATE pSVGAState = (PVMSVGASTATE)pThis->svga.pSVGAState;
3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync pThis->last_bpp = VMSVGA_VAL_UNINITIALIZED; /* force mode reset */
3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync /* Set the active cursor. */
3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync rc = pThis->pDrv->pfnVBVAMousePointerShape (pThis->pDrv,
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync * @copydoc FNSSMDEVSAVEEXEC
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsyncint vmsvgaSaveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync PVGASTATE pThis = PDMINS_2_DATA(pDevIns, PVGASTATE);
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync PVMSVGASTATE pSVGAState = (PVMSVGASTATE)pThis->svga.pSVGAState;
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync /* Save our part of the VGAState */
3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync rc = SSMR3PutStructEx(pSSM, &pThis->svga, sizeof(pThis->svga), 0, g_aVGAStateSVGAFields, NULL);
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync /* Save the framebuffer backup. */
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync rc = SSMR3PutMem(pSSM, pThis->svga.pFrameBufferBackup, VMSVGA_FRAMEBUFFER_BACKUP_SIZE);
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync /* Save the VMSVGA state. */
3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync rc = SSMR3PutStructEx(pSSM, pSVGAState, sizeof(*pSVGAState), 0, g_aVMSVGASTATEFields, NULL);
3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync /* Save the active cursor bitmaps. */
3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync rc = SSMR3PutMem(pSSM, pSVGAState->Cursor.pData, pSVGAState->Cursor.cbData);
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync /* Save the GMR state */
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync for (uint32_t i = 0; i < RT_ELEMENTS(pSVGAState->aGMR); i++)
3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync rc = SSMR3PutStructEx(pSSM, &pSVGAState->aGMR[i], sizeof(pSVGAState->aGMR[i]), 0, g_aGMRFields, NULL);
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync for (uint32_t j = 0; j < pSVGAState->aGMR[i].numDescriptors; j++)
3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync rc = SSMR3PutStructEx(pSSM, &pSVGAState->aGMR[i].paDesc[j], sizeof(pSVGAState->aGMR[i].paDesc[j]), 0, g_aVMSVGAGMRDESCRIPTORFields, NULL);
3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync /* Save the 3d state in the FIFO thread. */
3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync pThis->svga.u8FIFOExtCommand = VMSVGA_FIFO_EXTCMD_SAVESTATE;
2b114c590cf5a19f8047cd7bde9c7e5ae00aa22bvboxsync /* Hack alert: resume the IO thread as it has been suspended before the destruct callback.
3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync * The PowerOff notification isn't working, so not an option in this case.
cb39011e69667689c166f1cdf95247b46fff324dvboxsync SUPSemEventSignal(pThis->svga.pSupDrvSession, pThis->svga.FIFORequestSem);
3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync /* Wait for the end of the external command. */
3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync rc = RTSemEventWait(pThis->svga.FIFOExtCmdSem, RT_INDEFINITE_WAIT);
3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync * Resets the SVGA hardware state
3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync * @returns VBox status code.
3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync * @param pDevIns The device instance.
3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync PVGASTATE pThis = PDMINS_2_DATA(pDevIns, PVGASTATE);
3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync PVMSVGASTATE pSVGAState = (PVMSVGASTATE)pThis->svga.pSVGAState;
3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync /* Reset before init? */
3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync pThis->svga.pFIFOR3[SVGA_FIFO_NEXT_CMD] = pThis->svga.pFIFOR3[SVGA_FIFO_STOP] = 0;
3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync /* Reset the FIFO thread. */
3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync pThis->svga.u8FIFOExtCommand = VMSVGA_FIFO_EXTCMD_RESET;
cb39011e69667689c166f1cdf95247b46fff324dvboxsync SUPSemEventSignal(pThis->svga.pSupDrvSession, pThis->svga.FIFORequestSem);
3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync /* Wait for the end of the termination sequence. */
3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync int rc = RTSemEventWait(pThis->svga.FIFOExtCmdSem, 10000);
3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync memset(pThis->svga.au32ScratchRegion, 0, sizeof(pThis->svga.au32ScratchRegion));
3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync memset(pThis->svga.pSVGAState, 0, sizeof(VMSVGASTATE));
3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync memset(pThis->svga.pFrameBufferBackup, 0, VMSVGA_FRAMEBUFFER_BACKUP_SIZE);
3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync /* Register caps. */
3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync pThis->svga.u32RegCaps = SVGA_CAP_GMR | SVGA_CAP_GMR2 | SVGA_CAP_CURSOR | SVGA_CAP_CURSOR_BYPASS_2 | SVGA_CAP_EXTENDED_FIFO | SVGA_CAP_IRQMASK | SVGA_CAP_PITCHLOCK | SVGA_CAP_TRACES | SVGA_CAP_SCREEN_OBJECT_2 | SVGA_CAP_ALPHA_CURSOR;
3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync /* Setup FIFO capabilities. */
3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync pThis->svga.pFIFOR3[SVGA_FIFO_CAPABILITIES] = SVGA_FIFO_CAP_FENCE | SVGA_FIFO_CAP_CURSOR_BYPASS_3 | SVGA_FIFO_CAP_GMR2 | SVGA_FIFO_CAP_3D_HWVERSION_REVISED | SVGA_FIFO_CAP_SCREEN_OBJECT_2;
3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync /* Valid with SVGA_FIFO_CAP_SCREEN_OBJECT_2 */
3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync pThis->svga.pFIFOR3[SVGA_FIFO_CURSOR_SCREEN_ID] = SVGA_ID_INVALID;
3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync /* VRAM tracking is enabled by default during bootup. */
3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync /* Invalidate current settings. */
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync * Cleans up the SVGA hardware state
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync * @returns VBox status code.
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync * @param pDevIns The device instance.
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync PVGASTATE pThis = PDMINS_2_DATA(pDevIns, PVGASTATE);
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync PVMSVGASTATE pSVGAState = (PVMSVGASTATE)pThis->svga.pSVGAState;
3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync /* Stop the FIFO thread. */
3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync pThis->svga.u8FIFOExtCommand = VMSVGA_FIFO_EXTCMD_TERMINATE;
2b114c590cf5a19f8047cd7bde9c7e5ae00aa22bvboxsync /* Hack alert: resume the IO thread as it has been suspended before the destruct callback.
3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync * The PowerOff notification isn't working, so not an option in this case.
cb39011e69667689c166f1cdf95247b46fff324dvboxsync SUPSemEventSignal(pThis->svga.pSupDrvSession, pThis->svga.FIFORequestSem);
3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync /* Wait for the end of the termination sequence. */
3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync rc = RTSemEventWait(pThis->svga.FIFOExtCmdSem, 10000);
36c3589d6411416bba897f2595f1812b9d9ff4b3vboxsync if (pSVGAState->hBusyDelayedEmts != NIL_RTSEMEVENTMULTI)
36c3589d6411416bba897f2595f1812b9d9ff4b3vboxsync RTSemEventMultiDestroy(pSVGAState->hBusyDelayedEmts);
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync for (unsigned i = 0; i < RT_ELEMENTS(pSVGAState->aGMR); i++)
cb39011e69667689c166f1cdf95247b46fff324dvboxsync SUPSemEventClose(pThis->svga.pSupDrvSession, pThis->svga.FIFORequestSem);
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync * Initialize the SVGA hardware state
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync * @returns VBox status code.
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync * @param pDevIns The device instance.
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync PVGASTATE pThis = PDMINS_2_DATA(pDevIns, PVGASTATE);
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync memset(pThis->svga.au32ScratchRegion, 0, sizeof(pThis->svga.au32ScratchRegion));
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync pThis->svga.pSVGAState = RTMemAllocZ(sizeof(VMSVGASTATE));
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync AssertReturn(pThis->svga.pSVGAState, VERR_NO_MEMORY);
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync /* Necessary for creating a backup of the text mode frame buffer when switching into svga mode. */
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync pThis->svga.pFrameBufferBackup = RTMemAllocZ(VMSVGA_FRAMEBUFFER_BACKUP_SIZE);
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync AssertReturn(pThis->svga.pFrameBufferBackup, VERR_NO_MEMORY);
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync /* Create event semaphore. */
cb39011e69667689c166f1cdf95247b46fff324dvboxsync pThis->svga.pSupDrvSession = PDMDevHlpGetSupDrvSession(pDevIns);
cb39011e69667689c166f1cdf95247b46fff324dvboxsync rc = SUPSemEventCreate(pThis->svga.pSupDrvSession, &pThis->svga.FIFORequestSem);
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync Log(("%s: Failed to create event semaphore for FIFO handling.\n", __FUNCTION__));
3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync /* Create event semaphore. */
3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync Log(("%s: Failed to create event semaphore for external fifo cmd handling.\n", __FUNCTION__));
36c3589d6411416bba897f2595f1812b9d9ff4b3vboxsync /* Create semaphore for delaying EMTs wait for the FIFO to stop being busy. */
36c3589d6411416bba897f2595f1812b9d9ff4b3vboxsync rc = RTSemEventMultiCreate(&pSVGAState->hBusyDelayedEmts);
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync /* Register caps. */
3194da424708abdd288b28d96892b3a5f3f7df0bvboxsync pThis->svga.u32RegCaps = SVGA_CAP_GMR | SVGA_CAP_GMR2 | SVGA_CAP_CURSOR | SVGA_CAP_CURSOR_BYPASS_2 | SVGA_CAP_EXTENDED_FIFO | SVGA_CAP_IRQMASK | SVGA_CAP_PITCHLOCK | SVGA_CAP_TRACES | SVGA_CAP_SCREEN_OBJECT_2 | SVGA_CAP_ALPHA_CURSOR;
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync /* Setup FIFO capabilities. */
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync pThis->svga.pFIFOR3[SVGA_FIFO_CAPABILITIES] = SVGA_FIFO_CAP_FENCE | SVGA_FIFO_CAP_CURSOR_BYPASS_3 | SVGA_FIFO_CAP_GMR2 | SVGA_FIFO_CAP_3D_HWVERSION_REVISED | SVGA_FIFO_CAP_SCREEN_OBJECT_2;
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync /* Valid with SVGA_FIFO_CAP_SCREEN_OBJECT_2 */
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync pThis->svga.pFIFOR3[SVGA_FIFO_CURSOR_SCREEN_ID] = SVGA_ID_INVALID;
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync pThis->svga.pFIFOR3[SVGA_FIFO_3D_HWVERSION] = pThis->svga.pFIFOR3[SVGA_FIFO_3D_HWVERSION_REVISED] = 0; /* no 3d available. */
9a379ef11a4bb232c8e41c12b82ec94c8e10d9a0vboxsync LogRel(("VMSVGA3d: 3D support disabled! (vmsvga3dInit -> %Rrc)\n", rc));
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync /* VRAM tracking is enabled by default during bootup. */
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync /* Invalidate current settings. */
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync while (pThis->svga.u32MaxWidth * pThis->svga.u32MaxHeight * 4 /* 32 bpp */ > pThis->vram_size)
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync Log(("VMSVGA: Maximum size (%d,%d)\n", pThis->svga.u32MaxWidth, pThis->svga.u32MaxHeight));
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync /* Create the async IO thread. */
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync rc = PDMDevHlpThreadCreate(pDevIns, &pThis->svga.pFIFOIOThread, pThis, vmsvgaFIFOLoop, vmsvgaFIFOLoopWakeUp, 0,
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync AssertMsgFailed(("%s: Async IO Thread creation for FIFO handling failed rc=%d\n", __FUNCTION__, rc));
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync * Statistics.
c66e448632d5ef48cf6b896f02e750440f5c6586vboxsync STAM_REG(pVM, &pSVGAState->StatR3CmdPresent, STAMTYPE_PROFILE, "/Devices/VMSVGA/3d/Cmd/Present", STAMUNIT_TICKS_PER_CALL, "Profiling of Present.");
c66e448632d5ef48cf6b896f02e750440f5c6586vboxsync STAM_REG(pVM, &pSVGAState->StatR3CmdDrawPrimitive, STAMTYPE_PROFILE, "/Devices/VMSVGA/3d/Cmd/DrawPrimitive", STAMUNIT_TICKS_PER_CALL, "Profiling of DrawPrimitive.");
c66e448632d5ef48cf6b896f02e750440f5c6586vboxsync STAM_REG(pVM, &pSVGAState->StatR3CmdSurfaceDMA, STAMTYPE_PROFILE, "/Devices/VMSVGA/3d/Cmd/SurfaceDMA", STAMUNIT_TICKS_PER_CALL, "Profiling of SurfaceDMA.");
36c3589d6411416bba897f2595f1812b9d9ff4b3vboxsync STAM_REL_REG(pVM, &pSVGAState->StatBusyDelayEmts, STAMTYPE_PROFILE, "/Devices/VMSVGA/EmtDelayOnBusyFifo", STAMUNIT_TICKS_PER_CALL, "Time we've delayed EMTs because of busy FIFO thread.");
c66e448632d5ef48cf6b896f02e750440f5c6586vboxsync STAM_REL_REG(pVM, &pSVGAState->StatFifoCommands, STAMTYPE_COUNTER, "/Devices/VMSVGA/FifoCommands", STAMUNIT_OCCURENCES, "FIFO command counter.");
c66e448632d5ef48cf6b896f02e750440f5c6586vboxsync STAM_REL_REG(pVM, &pSVGAState->StatFifoErrors, STAMTYPE_COUNTER, "/Devices/VMSVGA/FifoErrors", STAMUNIT_OCCURENCES, "FIFO error counter.");
c66e448632d5ef48cf6b896f02e750440f5c6586vboxsync STAM_REL_REG(pVM, &pSVGAState->StatFifoUnkCmds, STAMTYPE_COUNTER, "/Devices/VMSVGA/FifoUnknownCommands", STAMUNIT_OCCURENCES, "FIFO unknown command counter.");
c66e448632d5ef48cf6b896f02e750440f5c6586vboxsync STAM_REL_REG(pVM, &pSVGAState->StatFifoTodoTimeout, STAMTYPE_COUNTER, "/Devices/VMSVGA/FifoTodoTimeout", STAMUNIT_OCCURENCES, "Number of times we discovered pending work after a wait timeout.");
c66e448632d5ef48cf6b896f02e750440f5c6586vboxsync STAM_REL_REG(pVM, &pSVGAState->StatFifoTodoWoken, STAMTYPE_COUNTER, "/Devices/VMSVGA/FifoTodoWoken", STAMUNIT_OCCURENCES, "Number of times we discovered pending work after being woken up.");
c66e448632d5ef48cf6b896f02e750440f5c6586vboxsync STAM_REL_REG(pVM, &pSVGAState->StatFifoStalls, STAMTYPE_PROFILE, "/Devices/VMSVGA/FifoStalls", STAMUNIT_TICKS_PER_CALL, "Profiling of FIFO stalls (waiting for guest to finish copying data).");
69ff5c7ce4fe075b219c21370a979908bf6f9f41vboxsync/** Names for the vmsvga 3d capabilities, prefixed with format type hint char. */
69ff5c7ce4fe075b219c21370a979908bf6f9f41vboxsyncstatic const char * const g_apszVmSvgaDevCapNames[] =
69ff5c7ce4fe075b219c21370a979908bf6f9f41vboxsync "xMAX_LIGHTS",
69ff5c7ce4fe075b219c21370a979908bf6f9f41vboxsync "xMAX_TEXTURES",
69ff5c7ce4fe075b219c21370a979908bf6f9f41vboxsync "xMAX_CLIP_PLANES",
69ff5c7ce4fe075b219c21370a979908bf6f9f41vboxsync "xVERTEX_SHADER_VERSION",
69ff5c7ce4fe075b219c21370a979908bf6f9f41vboxsync "xVERTEX_SHADER",
69ff5c7ce4fe075b219c21370a979908bf6f9f41vboxsync "xFRAGMENT_SHADER_VERSION",
69ff5c7ce4fe075b219c21370a979908bf6f9f41vboxsync "xFRAGMENT_SHADER",
69ff5c7ce4fe075b219c21370a979908bf6f9f41vboxsync "xMAX_RENDER_TARGETS",
69ff5c7ce4fe075b219c21370a979908bf6f9f41vboxsync "xS23E8_TEXTURES",
69ff5c7ce4fe075b219c21370a979908bf6f9f41vboxsync "xS10E5_TEXTURES",
69ff5c7ce4fe075b219c21370a979908bf6f9f41vboxsync "xMAX_FIXED_VERTEXBLEND",
69ff5c7ce4fe075b219c21370a979908bf6f9f41vboxsync "xD16_BUFFER_FORMAT",
69ff5c7ce4fe075b219c21370a979908bf6f9f41vboxsync "xD24S8_BUFFER_FORMAT",
69ff5c7ce4fe075b219c21370a979908bf6f9f41vboxsync "xD24X8_BUFFER_FORMAT",
69ff5c7ce4fe075b219c21370a979908bf6f9f41vboxsync "xQUERY_TYPES",
69ff5c7ce4fe075b219c21370a979908bf6f9f41vboxsync "xTEXTURE_GRADIENT_SAMPLING",
69ff5c7ce4fe075b219c21370a979908bf6f9f41vboxsync "rMAX_POINT_SIZE",
69ff5c7ce4fe075b219c21370a979908bf6f9f41vboxsync "xMAX_SHADER_TEXTURES",
69ff5c7ce4fe075b219c21370a979908bf6f9f41vboxsync "xMAX_TEXTURE_WIDTH",
69ff5c7ce4fe075b219c21370a979908bf6f9f41vboxsync "xMAX_TEXTURE_HEIGHT",
69ff5c7ce4fe075b219c21370a979908bf6f9f41vboxsync "xMAX_VOLUME_EXTENT",
69ff5c7ce4fe075b219c21370a979908bf6f9f41vboxsync "xMAX_TEXTURE_REPEAT",
69ff5c7ce4fe075b219c21370a979908bf6f9f41vboxsync "xMAX_TEXTURE_ASPECT_RATIO",
69ff5c7ce4fe075b219c21370a979908bf6f9f41vboxsync "xMAX_TEXTURE_ANISOTROPY",
69ff5c7ce4fe075b219c21370a979908bf6f9f41vboxsync "xMAX_PRIMITIVE_COUNT",
69ff5c7ce4fe075b219c21370a979908bf6f9f41vboxsync "xMAX_VERTEX_INDEX",
69ff5c7ce4fe075b219c21370a979908bf6f9f41vboxsync "xMAX_VERTEX_SHADER_INSTRUCTIONS",
69ff5c7ce4fe075b219c21370a979908bf6f9f41vboxsync "xMAX_FRAGMENT_SHADER_INSTRUCTIONS",
69ff5c7ce4fe075b219c21370a979908bf6f9f41vboxsync "xMAX_VERTEX_SHADER_TEMPS",
69ff5c7ce4fe075b219c21370a979908bf6f9f41vboxsync "xMAX_FRAGMENT_SHADER_TEMPS",
69ff5c7ce4fe075b219c21370a979908bf6f9f41vboxsync "xTEXTURE_OPS",
69ff5c7ce4fe075b219c21370a979908bf6f9f41vboxsync "xSURFACEFMT_X8R8G8B8",
69ff5c7ce4fe075b219c21370a979908bf6f9f41vboxsync "xSURFACEFMT_A8R8G8B8",
69ff5c7ce4fe075b219c21370a979908bf6f9f41vboxsync "xSURFACEFMT_A2R10G10B10",
69ff5c7ce4fe075b219c21370a979908bf6f9f41vboxsync "xSURFACEFMT_X1R5G5B5",
69ff5c7ce4fe075b219c21370a979908bf6f9f41vboxsync "xSURFACEFMT_A1R5G5B5",
69ff5c7ce4fe075b219c21370a979908bf6f9f41vboxsync "xSURFACEFMT_A4R4G4B4",
69ff5c7ce4fe075b219c21370a979908bf6f9f41vboxsync "xSURFACEFMT_R5G6B5",
69ff5c7ce4fe075b219c21370a979908bf6f9f41vboxsync "xSURFACEFMT_LUMINANCE16",
69ff5c7ce4fe075b219c21370a979908bf6f9f41vboxsync "xSURFACEFMT_LUMINANCE8_ALPHA8",
69ff5c7ce4fe075b219c21370a979908bf6f9f41vboxsync "xSURFACEFMT_ALPHA8",
69ff5c7ce4fe075b219c21370a979908bf6f9f41vboxsync "xSURFACEFMT_LUMINANCE8",
69ff5c7ce4fe075b219c21370a979908bf6f9f41vboxsync "xSURFACEFMT_Z_D16",
69ff5c7ce4fe075b219c21370a979908bf6f9f41vboxsync "xSURFACEFMT_Z_D24S8",
69ff5c7ce4fe075b219c21370a979908bf6f9f41vboxsync "xSURFACEFMT_Z_D24X8",
69ff5c7ce4fe075b219c21370a979908bf6f9f41vboxsync "xSURFACEFMT_DXT1",
69ff5c7ce4fe075b219c21370a979908bf6f9f41vboxsync "xSURFACEFMT_DXT2",
69ff5c7ce4fe075b219c21370a979908bf6f9f41vboxsync "xSURFACEFMT_DXT3",
69ff5c7ce4fe075b219c21370a979908bf6f9f41vboxsync "xSURFACEFMT_DXT4",
69ff5c7ce4fe075b219c21370a979908bf6f9f41vboxsync "xSURFACEFMT_DXT5",
69ff5c7ce4fe075b219c21370a979908bf6f9f41vboxsync "xSURFACEFMT_BUMPX8L8V8U8",
69ff5c7ce4fe075b219c21370a979908bf6f9f41vboxsync "xSURFACEFMT_A2W10V10U10",
69ff5c7ce4fe075b219c21370a979908bf6f9f41vboxsync "xSURFACEFMT_BUMPU8V8",
69ff5c7ce4fe075b219c21370a979908bf6f9f41vboxsync "xSURFACEFMT_Q8W8V8U8",
69ff5c7ce4fe075b219c21370a979908bf6f9f41vboxsync "xSURFACEFMT_CxV8U8",
69ff5c7ce4fe075b219c21370a979908bf6f9f41vboxsync "xSURFACEFMT_R_S10E5",
69ff5c7ce4fe075b219c21370a979908bf6f9f41vboxsync "xSURFACEFMT_R_S23E8",
69ff5c7ce4fe075b219c21370a979908bf6f9f41vboxsync "xSURFACEFMT_RG_S10E5",
69ff5c7ce4fe075b219c21370a979908bf6f9f41vboxsync "xSURFACEFMT_RG_S23E8",
69ff5c7ce4fe075b219c21370a979908bf6f9f41vboxsync "xSURFACEFMT_ARGB_S10E5",
69ff5c7ce4fe075b219c21370a979908bf6f9f41vboxsync "xSURFACEFMT_ARGB_S23E8",
69ff5c7ce4fe075b219c21370a979908bf6f9f41vboxsync "xMISSING62",
69ff5c7ce4fe075b219c21370a979908bf6f9f41vboxsync "xMAX_VERTEX_SHADER_TEXTURES",
69ff5c7ce4fe075b219c21370a979908bf6f9f41vboxsync "xMAX_SIMULTANEOUS_RENDER_TARGETS",
69ff5c7ce4fe075b219c21370a979908bf6f9f41vboxsync "xSURFACEFMT_V16U16",
69ff5c7ce4fe075b219c21370a979908bf6f9f41vboxsync "xSURFACEFMT_G16R16",
69ff5c7ce4fe075b219c21370a979908bf6f9f41vboxsync "xSURFACEFMT_A16B16G16R16",
69ff5c7ce4fe075b219c21370a979908bf6f9f41vboxsync "xSURFACEFMT_UYVY",
69ff5c7ce4fe075b219c21370a979908bf6f9f41vboxsync "xSURFACEFMT_YUY2",
69ff5c7ce4fe075b219c21370a979908bf6f9f41vboxsync "xMULTISAMPLE_NONMASKABLESAMPLES",
69ff5c7ce4fe075b219c21370a979908bf6f9f41vboxsync "xMULTISAMPLE_MASKABLESAMPLES",
69ff5c7ce4fe075b219c21370a979908bf6f9f41vboxsync "xALPHATOCOVERAGE",
69ff5c7ce4fe075b219c21370a979908bf6f9f41vboxsync "xSUPERSAMPLE",
69ff5c7ce4fe075b219c21370a979908bf6f9f41vboxsync "xAUTOGENMIPMAPS",
69ff5c7ce4fe075b219c21370a979908bf6f9f41vboxsync "xSURFACEFMT_NV12",
69ff5c7ce4fe075b219c21370a979908bf6f9f41vboxsync "xSURFACEFMT_AYUV",
69ff5c7ce4fe075b219c21370a979908bf6f9f41vboxsync "xMAX_CONTEXT_IDS",
69ff5c7ce4fe075b219c21370a979908bf6f9f41vboxsync "xMAX_SURFACE_IDS",
69ff5c7ce4fe075b219c21370a979908bf6f9f41vboxsync "xSURFACEFMT_Z_DF16",
69ff5c7ce4fe075b219c21370a979908bf6f9f41vboxsync "xSURFACEFMT_Z_DF24",
69ff5c7ce4fe075b219c21370a979908bf6f9f41vboxsync "xSURFACEFMT_Z_D24S8_INT",
69ff5c7ce4fe075b219c21370a979908bf6f9f41vboxsync "xSURFACEFMT_BC4_UNORM",
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync * Power On notification.
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync * @returns VBox status.
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync * @param pDevIns The device instance data.
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync * @remarks Caller enters the device critical section.
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsyncDECLCALLBACK(void) vmsvgaR3PowerOn(PPDMDEVINS pDevIns)
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync PVGASTATE pThis = PDMINS_2_DATA(pDevIns, PVGASTATE);
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync /* 3d hardware version; latest and greatest */
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync pThis->svga.pFIFOR3[SVGA_FIFO_3D_HWVERSION_REVISED] = SVGA3D_HWVERSION_CURRENT;
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync pThis->svga.pFIFOR3[SVGA_FIFO_3D_HWVERSION] = SVGA3D_HWVERSION_CURRENT;
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync pCaps = (SVGA3dCapsRecord *)&pThis->svga.pFIFOR3[SVGA_FIFO_3D_CAPS];
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync /* Fill out all 3d capabilities. */
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync for (unsigned i = 0; i < SVGA3D_DEVCAP_MAX; i++)
69ff5c7ce4fe075b219c21370a979908bf6f9f41vboxsync LogRel(("VMSVGA3d: cap[%u]=%#010x {%s}\n", i, val, &g_apszVmSvgaDevCapNames[i][1]));
97748042650c3cb2b0cb62a801ba9ebc0652e0f8vboxsync LogRel(("VMSVGA3d: cap[%u]=%d.%04u {%s}\n", i, (int)*(float *)&val, (unsigned)(*(float *)&val * 10000) % 10000,
69ff5c7ce4fe075b219c21370a979908bf6f9f41vboxsync LogRel(("VMSVGA3d: cap[%u]=failed rc=%Rrc! {%s}\n", i, rc, &g_apszVmSvgaDevCapNames[i][1]));
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync pCaps->header.length = (sizeof(pCaps->header) + idxCap * sizeof(SVGA3dCapPair)) / sizeof(uint32_t);
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync pCaps = (SVGA3dCapsRecord *)((uint32_t *)pCaps + pCaps->header.length);
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync /* Mark end of record array. */
0802b726efeabba46f90cb2b285de4dadaac9507vboxsync# endif // VBOX_WITH_VMSVGA3D
ae94ad7e769e467419ab99cab5403bdb39bc544fvboxsync#endif /* IN_RING3 */