Flat32ToFlat64.asm revision 4fd606d1f5abe38e1f42c38de1d2e895166bd0f4
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync;------------------------------------------------------------------------------
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync; Transition from 32 bit flat protected mode into 64 bit flat protected mode
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync; Copyright (c) 2008 - 2009, Intel Corporation. All rights reserved.<BR>
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync; This program and the accompanying materials
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync; are licensed and made available under the terms and conditions of the BSD License
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync; which accompanies this distribution. The full text of the license may be found at
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync;------------------------------------------------------------------------------
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync ; Macro for filling in page table entries with EAX as base content.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync ; @param %1 What to increment EAX with for each iteration.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync ; @param %2 Start address.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync ; @param %3 End address (exclusive).
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync ; @uses EAX, EBX, EFLAGS
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync %macro FILL_ENTRIES 3
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync mov ebx, %2
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync mov [ebx], eax
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync mov dword [ebx + 4], 0
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync add eax, %1
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync cmp ebx, %3
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync jb %%myloop
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync ; Macro for filling in page table entries with zeros.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync ; @param %1 Start address.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync ; @param %2 End address (exclusive).
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync ; @uses EAX, EBX, EFLAGS
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync %macro ZERO_ENTRIES 2
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync mov ebx, %1
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync xor eax, eax
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync mov [ebx], eax
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync mov dword [ebx + 4], eax
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync cmp ebx, %2
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync jb %%myloop
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync ; The address of the page tables.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync %define VBOX_PDPT_ADDR (0x00800000 - 0x6000)
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync %define VBOX_PDPTR_ADDR (0x00800000 - 0x2000)
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync %define VBOX_PML4_ADDR (0x00800000 - 0x1000)
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync%endif ; VBOX
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync%ifndef VBOX
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync; Modified: EAX
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync; Modified: EAX, EBX
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsyncTransition32FlatTo64Flat:
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync%ifndef VBOX
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync mov eax, ((ADDR_OF_START_OF_RESET_CODE & ~0xfff) - 0x1000)
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync%else ; !VBOX
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync ; Produce our own page table that does not reside in ROM, since the PGM
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync ; pool code cannot quite cope with write monitoring ROM pages.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync ; First, set up page directories with 2MB pages for the first 4GB.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync mov eax, ( X86_PDE4M_P | X86_PDE4M_A | X86_PDE4M_PS | X86_PDE4M_PCD | X86_PDE4M_RW | X86_PDE4M_D )
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync FILL_ENTRIES X86_PAGE_2M_SIZE, VBOX_PDPT_ADDR, VBOX_PDPT_ADDR + 0x4000
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync ; Second, set up page a directory pointer table with 4 entries pointing to
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync ; the PTPDs we created above and the remainder as zeros.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync mov eax, ( X86_PDPE_P | X86_PDPE_RW | X86_PDPE_A | X86_PDPE_PCD ) + VBOX_PDPT_ADDR
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync FILL_ENTRIES X86_PAGE_4K_SIZE, VBOX_PDPTR_ADDR, VBOX_PDPTR_ADDR + 4*8
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync ZERO_ENTRIES VBOX_PDPTR_ADDR + 4*8, VBOX_PDPTR_ADDR + 0x1000
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync ; Third, set up a PML4 with the first entry pointing to the previous table.
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync mov dword [VBOX_PML4_ADDR], ( X86_PML4E_P | X86_PML4E_PCD | X86_PML4E_A | X86_PML4E_RW ) + VBOX_PDPTR_ADDR
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync mov dword [VBOX_PML4_ADDR + 4], 0
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync ZERO_ENTRIES VBOX_PML4_ADDR + 1*8, VBOX_PML4_ADDR + 0x1000
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync mov eax, VBOX_PML4_ADDR
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync mov cr3, eax
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync mov eax, cr4
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync bts eax, 5 ; enable PAE
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync mov cr4, eax
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync mov ecx, 0xc0000080
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync bts eax, 8 ; set LME
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync mov eax, cr0
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync bts eax, 31 ; set PG
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync mov cr0, eax ; enable paging
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync jmp LINEAR_CODE64_SEL:ADDR_OF(jumpTo64BitAndLandHere)
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsyncjumpTo64BitAndLandHere:
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync debugShowPostCode POSTCODE_64BIT_MODE
4fd606d1f5abe38e1f42c38de1d2e895166bd0f4vboxsync OneTimeCallRet Transition32FlatTo64Flat